<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jul 20, 2016 at 11:11 AM, Michael Kuperstein <span dir="ltr"><<a href="mailto:mkuper@google.com" target="_blank">mkuper@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">So, to be honest, this is more of an irrational fear of things I don't fully understand than a concrete example I have in mind. :-)<div><br>cmpl 0x0,%eax<br>setne %al<br>movzbl %al, %eax<br><br>Is probably fine as is - the setne has a a read dependency on the high lanes of %eax, but so does the cmpl that feeds it with flags, so if I understand this correctly, we should not have a stall.</div><div><br></div><div>This is more complicated:</div><div>cmpb 0x0,%al<br>setne %al<br>movzbl %al, %eax<br></div><div><br></div><div>Here, we do have an additional dependence that we can't get rid of - but I'm not sure whether there can actually be a stall here or not. (that would depend on how %al is def'd previously, and it's possible all cases are ok, but I'm not sure).</div><div><br></div><div>Regardless, I actually tend to agree with you that we want to eventually do this in post-RA. This was a first stab at this, to fix the most common issue, but what we probably really want to do is to integrate this with ExecutionDepsFix to handle longer chains of 8-bit operations, like PR28442.</div><div><br></div></div></blockquote><div><br></div><div>SGTM</div><div><br></div><div>-- Sean Silva</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jul 20, 2016 at 10:27 AM, Sean Silva <span dir="ltr"><<a href="mailto:chisophugis@gmail.com" target="_blank">chisophugis@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Jul 14, 2016 at 7:51 PM, Michael Kuperstein <span dir="ltr"><<a href="mailto:mkuper@google.com" target="_blank">mkuper@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div class="gmail_extra">Thanks for looking into this.</div><div class="gmail_extra">I've also started looking into the miscompile, and it seems like it may be a regalloc bug, but I'm not entirely sure yet.</div><div class="gmail_extra"><br></div><div class="gmail_extra">Regarding the spills - a slight increase in register pressure is expected. If before we generated something like:</div><div class="gmail_extra"><br></div><div class="gmail_extra">cmpl 0x0,%eax</div><div class="gmail_extra">setne %al</div><div class="gmail_extra">movzbl %al, %eax</div><div class="gmail_extra"><br></div><div class="gmail_extra">Where there were no other free registers, then using the xor idiom will necessarily cause a spill, since an extra register is required. One way to handle this would be to run the pass post-RA, and give up when the register that's def'd by the setcc is alive before the instruction that defs eflags, but I'm afraid that may cause us to miss opportunities.</div></div></blockquote><div><br></div><div>Do you have any examples where doing it post-RA would miss opportunities? I think it would make sense to do this post-RA because then you can be sure it will be a win. </div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div class="gmail_extra"><br></div><div class="gmail_extra">Is the spilling you've seen consistent with that, or is it something worse?</div></div></blockquote><div><br></div><div>Yeah, I think that was all that was happening.</div><div><br></div><div>-- Sean Silva</div><div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div class="gmail_extra"><br></div><div class="gmail_extra">Michael</div><div class="gmail_extra"><br></div><div class="gmail_extra"><div class="gmail_quote">On Jul 14, 2016 17:54, "Sean Silva" <<a href="mailto:chisophugis@gmail.com" target="_blank">chisophugis@gmail.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr">Btw, while staring at the side-by-side assembly both with and without this patch when debugging the micompile, it definitely seemed like this patch was causing quite a few spills.<div><br></div><div>Of course, we only looked at one particular TU, but you may want to look a bit more closely at the register pressure implications of this pass.<div><br></div><div><div><div>-- Sean Silva</div></div></div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Jul 14, 2016 at 2:25 PM, Michael Kuperstein <span dir="ltr"><<a href="mailto:mkuper@google.com" target="_blank">mkuper@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr">Thanks, looking into it!</div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Jul 14, 2016 at 2:25 PM, Jake VanAdrighem <span dir="ltr"><<a href="mailto:jvanadrighem@gmail.com" target="_blank">jvanadrighem@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr">Okay, progress was made! Just posted <a href="https://llvm.org/bugs/show_bug.cgi?id=28557" target="_blank">https://llvm.org/bugs/show_bug.cgi?id=28557</a>.<div><br></div><div>Jake</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jul 13, 2016 at 5:18 PM, Michael Kuperstein <span dir="ltr"><<a href="mailto:mkuper@google.com" target="_blank">mkuper@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr">Yes, this definitely looks like something's gone wrong.<div>Unfortunately, I don't see how I can debug and fix this without a reproducer - in either source or IR form.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jul 13, 2016 at 4:33 PM, Jake VanAdrighem <span dir="ltr"><<a href="mailto:jvanadrighem@gmail.com" target="_blank">jvanadrighem@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr">Here's a vimdiff of the build with/without this commit. Something seems to have gone wrong here. Let me know if more is needed to properly identify the bug. Looks like the xorl is above the place we need it and some garbage value ends up somewhere in memory. Let me know if I'm not seeing something correctly here.<div><br></div><div><img src="cid:ii_155e69546b095223" alt="Inline image 1" width="562" height="215"><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jul 13, 2016 at 10:04 AM, Michael Kuperstein <span dir="ltr"><<a href="mailto:mkuper@google.com" target="_blank">mkuper@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr">Ok, please let me know when you have a reproducer. Sorry for the breakage.<div><br></div><div>Michael</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jul 12, 2016 at 8:51 PM, Jake VanAdrighem <span dir="ltr"><<a href="mailto:jvanadrighem@gmail.com" target="_blank">jvanadrighem@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jul 12, 2016 at 8:44 PM, Michael Kuperstein <span dir="ltr"><<a href="mailto:mkuper@google.com" target="_blank">mkuper@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><p dir="ltr">Thanks, Jake!</p>
<p dir="ltr">Is this with -O0 or in an optimized build? I've since disabled the pass for -O0 - it should have never run in the first place, and exposed a fast regalloc bug.</p>
<p dir="ltr">Michael</p></blockquote><div>An optimized build, -O2 per TU. No LTO.</div><div><br></div><div>Jake</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><p dir="ltr"> </p>
<div class="gmail_extra"><br><div class="gmail_quote">On Jul 12, 2016 20:25, "Jake VanAdrighem" <<a href="mailto:jvanadrighem@gmail.com" target="_blank">jvanadrighem@gmail.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr">By the way, I've bisected this commit as the cause of a miscompile. Unfortunately, I don't have a self-contained reproducer yet but I just wanted to get the word out.<div><br></div><div>Jake</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Jul 7, 2016 at 3:50 PM, Michael Kuperstein via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex">Author: mkuper<br>
Date: Thu Jul 7 17:50:23 2016<br>
New Revision: 274802<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=274802&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=274802&view=rev</a><br>
Log:<br>
Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setcc<br>
<br>
xorl + setcc is generally the preferred sequence due to the partial register<br>
stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller.<br>
This fixes PR28146.<br>
<br>
The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD)<br>
which was not appreciated by fast regalloc on 32-bit.<br>
<br>
<br>
Added:<br>
llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp<br>
- copied, changed from r274770, llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp<br>
Modified:<br>
llvm/trunk/lib/Target/X86/CMakeLists.txt<br>
llvm/trunk/lib/Target/X86/X86.h<br>
llvm/trunk/lib/Target/X86/X86TargetMachine.cpp<br>
llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll<br>
llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll<br>
llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll<br>
llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-cmp.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll<br>
llvm/trunk/test/CodeGen/X86/bmi.ll<br>
llvm/trunk/test/CodeGen/X86/cmov.ll<br>
llvm/trunk/test/CodeGen/X86/cmp.ll<br>
llvm/trunk/test/CodeGen/X86/cmpxchg-i1.ll<br>
llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll<br>
llvm/trunk/test/CodeGen/X86/ctpop-combine.ll<br>
llvm/trunk/test/CodeGen/X86/fp128-cast.ll<br>
llvm/trunk/test/CodeGen/X86/fp128-compare.ll<br>
llvm/trunk/test/CodeGen/X86/mcinst-lowering.ll<br>
llvm/trunk/test/CodeGen/X86/return-ext.ll<br>
llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll<br>
llvm/trunk/test/CodeGen/X86/setcc.ll<br>
llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll<br>
llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll<br>
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll<br>
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll<br>
llvm/trunk/test/CodeGen/X86/sse41-intrinsics-fast-isel.ll<br>
llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86.ll<br>
llvm/trunk/test/CodeGen/X86/sse41.ll<br>
llvm/trunk/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll<br>
llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/Target/X86/CMakeLists.txt Thu Jul 7 17:50:23 2016<br>
@@ -19,6 +19,7 @@ set(sources<br>
X86FastISel.cpp<br>
X86FixupBWInsts.cpp<br>
X86FixupLEAs.cpp<br>
+ X86FixupSetCC.cpp<br>
X86FloatingPoint.cpp<br>
X86FrameLowering.cpp<br>
X86ISelDAGToDAG.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86.h Thu Jul 7 17:50:23 2016<br>
@@ -59,6 +59,9 @@ FunctionPass *createX86FixupLEAs();<br>
/// recalculations.<br>
FunctionPass *createX86OptimizeLEAs();<br>
<br>
+/// Return a pass that transforms setcc + movzx pairs into xor + setcc.<br>
+FunctionPass *createX86FixupSetCC();<br>
+<br>
/// Return a pass that expands WinAlloca pseudo-instructions.<br>
FunctionPass *createX86WinAllocaExpander();<br>
<br>
<br>
Copied: llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp (from r274770, llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp)<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp?p2=llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp&p1=llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp&r1=274770&r2=274802&rev=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp?p2=llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp&p1=llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp&r1=274770&r2=274802&rev=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86FixupSetCC.cpp Thu Jul 7 17:50:23 2016<br>
@@ -156,7 +156,10 @@ bool X86FixupSetCCPass::runOnMachineFunc<br>
++NumSubstZexts;<br>
Changed = true;<br>
<br>
- auto *RC = MRI->getRegClass(ZExt->getOperand(0).getReg());<br>
+ // On 32-bit, we need to be careful to force an ABCD register.<br>
+ const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()<br>
+ ? &X86::GR32RegClass<br>
+ : &X86::GR32_ABCDRegClass;<br>
unsigned ZeroReg = MRI->createVirtualRegister(RC);<br>
unsigned InsertReg = MRI->createVirtualRegister(RC);<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Jul 7 17:50:23 2016<br>
@@ -285,7 +285,6 @@ bool X86PassConfig::addInstSelector() {<br>
addPass(createCleanupLocalDynamicTLSPass());<br>
<br>
addPass(createX86GlobalBaseRegPass());<br>
-<br>
return false;<br>
}<br>
<br>
@@ -305,6 +304,8 @@ bool X86PassConfig::addPreISel() {<br>
}<br>
<br>
void X86PassConfig::addPreRegAlloc() {<br>
+ addPass(createX86FixupSetCC());<br>
+<br>
if (getOptLevel() != CodeGenOpt::None)<br>
addPass(createX86OptimizeLEAs());<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll Thu Jul 7 17:50:23 2016<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movzbl<br>
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep xorl<br>
<br>
define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind {<br>
entry:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll Thu Jul 7 17:50:23 2016<br>
@@ -10,9 +10,9 @@ entry:<br>
; SOURCE-SCHED: subl<br>
; SOURCE-SCHED: movl<br>
; SOURCE-SCHED: sarl<br>
+; SOURCE-SCHED: xorl<br>
; SOURCE-SCHED: cmpl<br>
; SOURCE-SCHED: setg<br>
-; SOURCE-SCHED: movzbl<br>
; SOURCE-SCHED: movb<br>
; SOURCE-SCHED: xorl<br>
; SOURCE-SCHED: subl<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll Thu Jul 7 17:50:23 2016<br>
@@ -3384,16 +3384,16 @@ declare i32 @llvm.x86.avx.ptestc.256(<4<br>
define i32 @test_mm_testnzc_pd(<2 x double> %a0, <2 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm_testnzc_pd:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: vtestpd %xmm1, %xmm0<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_testnzc_pd:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: vtestpd %xmm1, %xmm0<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x double> %a1)<br>
ret i32 %res<br>
@@ -3403,17 +3403,17 @@ declare i32 @llvm.x86.avx.vtestnzc.pd(<2<br>
define i32 @test_mm256_testnzc_pd(<4 x double> %a0, <4 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm256_testnzc_pd:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: vtestpd %ymm1, %ymm0<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: vzeroupper<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm256_testnzc_pd:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: vtestpd %ymm1, %ymm0<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: vzeroupper<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0, <4 x double> %a1)<br>
@@ -3424,16 +3424,16 @@ declare i32 @llvm.x86.avx.vtestnzc.pd.25<br>
define i32 @test_mm_testnzc_ps(<4 x float> %a0, <4 x float> %a1) nounwind {<br>
; X32-LABEL: test_mm_testnzc_ps:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: vtestps %xmm1, %xmm0<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_testnzc_ps:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: vtestps %xmm1, %xmm0<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.avx.vtestnzc.ps" rel="noreferrer" target="_blank">llvm.x86.avx.vtestnzc.ps</a>(<4 x float> %a0, <4 x float> %a1)<br>
ret i32 %res<br>
@@ -3443,17 +3443,17 @@ declare i32 @<a href="http://llvm.x86.avx.vtestnzc.ps" rel="noreferrer" target="_blank">llvm.x86.avx.vtestnzc.ps</a>(<4<br>
define i32 @test_mm256_testnzc_ps(<8 x float> %a0, <8 x float> %a1) nounwind {<br>
; X32-LABEL: test_mm256_testnzc_ps:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: vtestps %ymm1, %ymm0<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: vzeroupper<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm256_testnzc_ps:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: vtestps %ymm1, %ymm0<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: vzeroupper<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0, <8 x float> %a1)<br>
@@ -3464,17 +3464,17 @@ declare i32 @llvm.x86.avx.vtestnzc.ps.25<br>
define i32 @test_mm256_testnzc_si256(<4 x i64> %a0, <4 x i64> %a1) nounwind {<br>
; X32-LABEL: test_mm256_testnzc_si256:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: vptest %ymm1, %ymm0<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: vzeroupper<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm256_testnzc_si256:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: vptest %ymm1, %ymm0<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: vzeroupper<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x i64> %a1)<br>
@@ -3485,16 +3485,16 @@ declare i32 @llvm.x86.avx.ptestnzc.256(<<br>
define i32 @test_mm_testz_pd(<2 x double> %a0, <2 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm_testz_pd:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: vtestpd %xmm1, %xmm0<br>
; X32-NEXT: sete %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_testz_pd:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: vtestpd %xmm1, %xmm0<br>
; X64-NEXT: sete %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x double> %a1)<br>
ret i32 %res<br>
@@ -3504,17 +3504,17 @@ declare i32 @llvm.x86.avx.vtestz.pd(<2 x<br>
define i32 @test_mm256_testz_pd(<4 x double> %a0, <4 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm256_testz_pd:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: vtestpd %ymm1, %ymm0<br>
; X32-NEXT: sete %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: vzeroupper<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm256_testz_pd:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: vtestpd %ymm1, %ymm0<br>
; X64-NEXT: sete %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: vzeroupper<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4 x double> %a1)<br>
@@ -3525,16 +3525,16 @@ declare i32 @llvm.x86.avx.vtestz.pd.256(<br>
define i32 @test_mm_testz_ps(<4 x float> %a0, <4 x float> %a1) nounwind {<br>
; X32-LABEL: test_mm_testz_ps:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: vtestps %xmm1, %xmm0<br>
; X32-NEXT: sete %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_testz_ps:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: vtestps %xmm1, %xmm0<br>
; X64-NEXT: sete %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.avx.vtestz.ps" rel="noreferrer" target="_blank">llvm.x86.avx.vtestz.ps</a>(<4 x float> %a0, <4 x float> %a1)<br>
ret i32 %res<br>
@@ -3544,17 +3544,17 @@ declare i32 @<a href="http://llvm.x86.avx.vtestz.ps" rel="noreferrer" target="_blank">llvm.x86.avx.vtestz.ps</a>(<4 x<br>
define i32 @test_mm256_testz_ps(<8 x float> %a0, <8 x float> %a1) nounwind {<br>
; X32-LABEL: test_mm256_testz_ps:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: vtestps %ymm1, %ymm0<br>
; X32-NEXT: sete %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: vzeroupper<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm256_testz_ps:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: vtestps %ymm1, %ymm0<br>
; X64-NEXT: sete %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: vzeroupper<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8 x float> %a1)<br>
@@ -3565,17 +3565,17 @@ declare i32 @llvm.x86.avx.vtestz.ps.256(<br>
define i32 @test_mm256_testz_si256(<4 x i64> %a0, <4 x i64> %a1) nounwind {<br>
; X32-LABEL: test_mm256_testz_si256:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: vptest %ymm1, %ymm0<br>
; X32-NEXT: sete %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: vzeroupper<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm256_testz_si256:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: vptest %ymm1, %ymm0<br>
; X64-NEXT: sete %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: vzeroupper<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x i64> %a1)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Thu Jul 7 17:50:23 2016<br>
@@ -173,16 +173,16 @@ declare i32 @<a href="http://llvm.x86.sse2.comieq.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comieq.sd</a>(<2<br>
define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; AVX-LABEL: test_x86_sse2_comige_sd:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vcomisd %xmm1, %xmm0<br>
; AVX-NEXT: setae %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse2_comige_sd:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vcomisd %xmm1, %xmm0<br>
; AVX512VL-NEXT: setae %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comige.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comige.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -193,16 +193,16 @@ declare i32 @<a href="http://llvm.x86.sse2.comige.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comige.sd</a>(<2<br>
define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; AVX-LABEL: test_x86_sse2_comigt_sd:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vcomisd %xmm1, %xmm0<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse2_comigt_sd:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vcomisd %xmm1, %xmm0<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comigt.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comigt.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -213,16 +213,16 @@ declare i32 @<a href="http://llvm.x86.sse2.comigt.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comigt.sd</a>(<2<br>
define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; AVX-LABEL: test_x86_sse2_comile_sd:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vcomisd %xmm0, %xmm1<br>
; AVX-NEXT: setae %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse2_comile_sd:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vcomisd %xmm0, %xmm1<br>
; AVX512VL-NEXT: setae %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comile.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comile.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -233,16 +233,16 @@ declare i32 @<a href="http://llvm.x86.sse2.comile.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comile.sd</a>(<2<br>
define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; AVX-LABEL: test_x86_sse2_comilt_sd:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vcomisd %xmm0, %xmm1<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse2_comilt_sd:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vcomisd %xmm0, %xmm1<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comilt.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comilt.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1264,16 +1264,16 @@ declare i32 @<a href="http://llvm.x86.sse2.ucomieq.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomieq.sd</a>(<2<br>
define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; AVX-LABEL: test_x86_sse2_ucomige_sd:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vucomisd %xmm1, %xmm0<br>
; AVX-NEXT: setae %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse2_ucomige_sd:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vucomisd %xmm1, %xmm0<br>
; AVX512VL-NEXT: setae %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomige.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomige.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1284,16 +1284,16 @@ declare i32 @<a href="http://llvm.x86.sse2.ucomige.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomige.sd</a>(<2<br>
define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; AVX-LABEL: test_x86_sse2_ucomigt_sd:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vucomisd %xmm1, %xmm0<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse2_ucomigt_sd:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vucomisd %xmm1, %xmm0<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomigt.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomigt.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1304,16 +1304,16 @@ declare i32 @<a href="http://llvm.x86.sse2.ucomigt.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomigt.sd</a>(<2<br>
define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; AVX-LABEL: test_x86_sse2_ucomile_sd:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vucomisd %xmm0, %xmm1<br>
; AVX-NEXT: setae %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse2_ucomile_sd:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vucomisd %xmm0, %xmm1<br>
; AVX512VL-NEXT: setae %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomile.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomile.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1324,16 +1324,16 @@ declare i32 @<a href="http://llvm.x86.sse2.ucomile.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomile.sd</a>(<2<br>
define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; AVX-LABEL: test_x86_sse2_ucomilt_sd:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vucomisd %xmm0, %xmm1<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse2_ucomilt_sd:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vucomisd %xmm0, %xmm1<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomilt.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomilt.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1791,16 +1791,16 @@ declare i32 @llvm.x86.sse41.ptestc(<2 x<br>
define i32 @test_x86_sse41_ptestnzc(<2 x i64> %a0, <2 x i64> %a1) {<br>
; AVX-LABEL: test_x86_sse41_ptestnzc:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vptest %xmm1, %xmm0<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse41_ptestnzc:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vptest %xmm1, %xmm0<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1811,16 +1811,16 @@ declare i32 @llvm.x86.sse41.ptestnzc(<2<br>
define i32 @test_x86_sse41_ptestz(<2 x i64> %a0, <2 x i64> %a1) {<br>
; AVX-LABEL: test_x86_sse41_ptestz:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vptest %xmm1, %xmm0<br>
; AVX-NEXT: sete %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse41_ptestz:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vptest %xmm1, %xmm0<br>
; AVX512VL-NEXT: sete %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1943,23 +1943,29 @@ define i32 @test_x86_sse42_pcmpestri128_<br>
}<br>
<br>
<br>
-define i32 @test_x86_sse42_pcmpestria128(<16 x i8> %a0, <16 x i8> %a2) {<br>
+define i32 @test_x86_sse42_pcmpestria128(<16 x i8> %a0, <16 x i8> %a2) nounwind {<br>
; AVX-LABEL: test_x86_sse42_pcmpestria128:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: pushl %ebx<br>
; AVX-NEXT: movl $7, %eax<br>
; AVX-NEXT: movl $7, %edx<br>
+; AVX-NEXT: xorl %ebx, %ebx<br>
; AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0<br>
-; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
+; AVX-NEXT: seta %bl<br>
+; AVX-NEXT: movl %ebx, %eax<br>
+; AVX-NEXT: popl %ebx<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse42_pcmpestria128:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: pushl %ebx<br>
; AVX512VL-NEXT: movl $7, %eax<br>
; AVX512VL-NEXT: movl $7, %edx<br>
+; AVX512VL-NEXT: xorl %ebx, %ebx<br>
; AVX512VL-NEXT: vpcmpestri $7, %xmm1, %xmm0<br>
-; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
+; AVX512VL-NEXT: seta %bl<br>
+; AVX512VL-NEXT: movl %ebx, %eax<br>
+; AVX512VL-NEXT: popl %ebx<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse42.pcmpestria128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1991,23 +1997,29 @@ define i32 @test_x86_sse42_pcmpestric128<br>
declare i32 @llvm.x86.sse42.pcmpestric128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone<br>
<br>
<br>
-define i32 @test_x86_sse42_pcmpestrio128(<16 x i8> %a0, <16 x i8> %a2) {<br>
+define i32 @test_x86_sse42_pcmpestrio128(<16 x i8> %a0, <16 x i8> %a2) nounwind {<br>
; AVX-LABEL: test_x86_sse42_pcmpestrio128:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: pushl %ebx<br>
; AVX-NEXT: movl $7, %eax<br>
; AVX-NEXT: movl $7, %edx<br>
+; AVX-NEXT: xorl %ebx, %ebx<br>
; AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0<br>
-; AVX-NEXT: seto %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
+; AVX-NEXT: seto %bl<br>
+; AVX-NEXT: movl %ebx, %eax<br>
+; AVX-NEXT: popl %ebx<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse42_pcmpestrio128:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: pushl %ebx<br>
; AVX512VL-NEXT: movl $7, %eax<br>
; AVX512VL-NEXT: movl $7, %edx<br>
+; AVX512VL-NEXT: xorl %ebx, %ebx<br>
; AVX512VL-NEXT: vpcmpestri $7, %xmm1, %xmm0<br>
-; AVX512VL-NEXT: seto %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
+; AVX512VL-NEXT: seto %bl<br>
+; AVX512VL-NEXT: movl %ebx, %eax<br>
+; AVX512VL-NEXT: popl %ebx<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2015,23 +2027,29 @@ define i32 @test_x86_sse42_pcmpestrio128<br>
declare i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone<br>
<br>
<br>
-define i32 @test_x86_sse42_pcmpestris128(<16 x i8> %a0, <16 x i8> %a2) {<br>
+define i32 @test_x86_sse42_pcmpestris128(<16 x i8> %a0, <16 x i8> %a2) nounwind {<br>
; AVX-LABEL: test_x86_sse42_pcmpestris128:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: pushl %ebx<br>
; AVX-NEXT: movl $7, %eax<br>
; AVX-NEXT: movl $7, %edx<br>
+; AVX-NEXT: xorl %ebx, %ebx<br>
; AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0<br>
-; AVX-NEXT: sets %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
+; AVX-NEXT: sets %bl<br>
+; AVX-NEXT: movl %ebx, %eax<br>
+; AVX-NEXT: popl %ebx<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse42_pcmpestris128:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: pushl %ebx<br>
; AVX512VL-NEXT: movl $7, %eax<br>
; AVX512VL-NEXT: movl $7, %edx<br>
+; AVX512VL-NEXT: xorl %ebx, %ebx<br>
; AVX512VL-NEXT: vpcmpestri $7, %xmm1, %xmm0<br>
-; AVX512VL-NEXT: sets %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
+; AVX512VL-NEXT: sets %bl<br>
+; AVX512VL-NEXT: movl %ebx, %eax<br>
+; AVX512VL-NEXT: popl %ebx<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse42.pcmpestris128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2039,23 +2057,29 @@ define i32 @test_x86_sse42_pcmpestris128<br>
declare i32 @llvm.x86.sse42.pcmpestris128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone<br>
<br>
<br>
-define i32 @test_x86_sse42_pcmpestriz128(<16 x i8> %a0, <16 x i8> %a2) {<br>
+define i32 @test_x86_sse42_pcmpestriz128(<16 x i8> %a0, <16 x i8> %a2) nounwind {<br>
; AVX-LABEL: test_x86_sse42_pcmpestriz128:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: pushl %ebx<br>
; AVX-NEXT: movl $7, %eax<br>
; AVX-NEXT: movl $7, %edx<br>
+; AVX-NEXT: xorl %ebx, %ebx<br>
; AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0<br>
-; AVX-NEXT: sete %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
+; AVX-NEXT: sete %bl<br>
+; AVX-NEXT: movl %ebx, %eax<br>
+; AVX-NEXT: popl %ebx<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse42_pcmpestriz128:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: pushl %ebx<br>
; AVX512VL-NEXT: movl $7, %eax<br>
; AVX512VL-NEXT: movl $7, %edx<br>
+; AVX512VL-NEXT: xorl %ebx, %ebx<br>
; AVX512VL-NEXT: vpcmpestri $7, %xmm1, %xmm0<br>
-; AVX512VL-NEXT: sete %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
+; AVX512VL-NEXT: sete %bl<br>
+; AVX512VL-NEXT: movl %ebx, %eax<br>
+; AVX512VL-NEXT: popl %ebx<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2151,16 +2175,16 @@ define i32 @test_x86_sse42_pcmpistri128_<br>
define i32 @test_x86_sse42_pcmpistria128(<16 x i8> %a0, <16 x i8> %a1) {<br>
; AVX-LABEL: test_x86_sse42_pcmpistria128:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse42_pcmpistria128:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vpcmpistri $7, %xmm1, %xmm0<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse42.pcmpistria128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2191,16 +2215,16 @@ declare i32 @llvm.x86.sse42.pcmpistric12<br>
define i32 @test_x86_sse42_pcmpistrio128(<16 x i8> %a0, <16 x i8> %a1) {<br>
; AVX-LABEL: test_x86_sse42_pcmpistrio128:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0<br>
; AVX-NEXT: seto %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse42_pcmpistrio128:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vpcmpistri $7, %xmm1, %xmm0<br>
; AVX512VL-NEXT: seto %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse42.pcmpistrio128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2211,16 +2235,16 @@ declare i32 @llvm.x86.sse42.pcmpistrio12<br>
define i32 @test_x86_sse42_pcmpistris128(<16 x i8> %a0, <16 x i8> %a1) {<br>
; AVX-LABEL: test_x86_sse42_pcmpistris128:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0<br>
; AVX-NEXT: sets %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse42_pcmpistris128:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vpcmpistri $7, %xmm1, %xmm0<br>
; AVX512VL-NEXT: sets %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse42.pcmpistris128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2231,16 +2255,16 @@ declare i32 @llvm.x86.sse42.pcmpistris12<br>
define i32 @test_x86_sse42_pcmpistriz128(<16 x i8> %a0, <16 x i8> %a1) {<br>
; AVX-LABEL: test_x86_sse42_pcmpistriz128:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0<br>
; AVX-NEXT: sete %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse42_pcmpistriz128:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vpcmpistri $7, %xmm1, %xmm0<br>
; AVX512VL-NEXT: sete %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2357,16 +2381,16 @@ declare i32 @llvm.x86.sse.comieq.ss(<4 x<br>
define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; AVX-LABEL: test_x86_sse_comige_ss:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vcomiss %xmm1, %xmm0<br>
; AVX-NEXT: setae %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse_comige_ss:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vcomiss %xmm1, %xmm0<br>
; AVX512VL-NEXT: setae %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2377,16 +2401,16 @@ declare i32 @llvm.x86.sse.comige.ss(<4 x<br>
define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; AVX-LABEL: test_x86_sse_comigt_ss:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vcomiss %xmm1, %xmm0<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse_comigt_ss:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vcomiss %xmm1, %xmm0<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2397,16 +2421,16 @@ declare i32 @llvm.x86.sse.comigt.ss(<4 x<br>
define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; AVX-LABEL: test_x86_sse_comile_ss:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vcomiss %xmm0, %xmm1<br>
; AVX-NEXT: setae %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse_comile_ss:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vcomiss %xmm0, %xmm1<br>
; AVX512VL-NEXT: setae %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2417,16 +2441,16 @@ declare i32 @llvm.x86.sse.comile.ss(<4 x<br>
define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; AVX-LABEL: test_x86_sse_comilt_ss:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vcomiss %xmm0, %xmm1<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse_comilt_ss:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vcomiss %xmm0, %xmm1<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2797,16 +2821,16 @@ declare i32 @llvm.x86.sse.ucomieq.ss(<4<br>
define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; AVX-LABEL: test_x86_sse_ucomige_ss:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vucomiss %xmm1, %xmm0<br>
; AVX-NEXT: setae %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse_ucomige_ss:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vucomiss %xmm1, %xmm0<br>
; AVX512VL-NEXT: setae %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2817,16 +2841,16 @@ declare i32 @llvm.x86.sse.ucomige.ss(<4<br>
define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; AVX-LABEL: test_x86_sse_ucomigt_ss:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vucomiss %xmm1, %xmm0<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse_ucomigt_ss:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vucomiss %xmm1, %xmm0<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2837,16 +2861,16 @@ declare i32 @llvm.x86.sse.ucomigt.ss(<4<br>
define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; AVX-LABEL: test_x86_sse_ucomile_ss:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vucomiss %xmm0, %xmm1<br>
; AVX-NEXT: setae %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse_ucomile_ss:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vucomiss %xmm0, %xmm1<br>
; AVX512VL-NEXT: setae %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2857,16 +2881,16 @@ declare i32 @llvm.x86.sse.ucomile.ss(<4<br>
define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; AVX-LABEL: test_x86_sse_ucomilt_ss:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vucomiss %xmm0, %xmm1<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_sse_ucomilt_ss:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vucomiss %xmm0, %xmm1<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -3778,17 +3802,17 @@ declare i32 @llvm.x86.avx.ptestc.256(<4<br>
define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64> %a1) {<br>
; AVX-LABEL: test_x86_avx_ptestnzc_256:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vptest %ymm1, %ymm0<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: vzeroupper<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_ptestnzc_256:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vptest %ymm1, %ymm0<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -3799,17 +3823,17 @@ declare i32 @llvm.x86.avx.ptestnzc.256(<<br>
define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) {<br>
; AVX-LABEL: test_x86_avx_ptestz_256:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vptest %ymm1, %ymm0<br>
; AVX-NEXT: sete %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: vzeroupper<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_ptestz_256:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vptest %ymm1, %ymm0<br>
; AVX512VL-NEXT: sete %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -4175,16 +4199,16 @@ declare i32 @llvm.x86.avx.vtestc.ps.256(<br>
define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x double> %a1) {<br>
; AVX-LABEL: test_x86_avx_vtestnzc_pd:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vtestpd %xmm1, %xmm0<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_vtestnzc_pd:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vtestpd %xmm1, %xmm0<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -4195,17 +4219,17 @@ declare i32 @llvm.x86.avx.vtestnzc.pd(<2<br>
define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x double> %a1) {<br>
; AVX-LABEL: test_x86_avx_vtestnzc_pd_256:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vtestpd %ymm1, %ymm0<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: vzeroupper<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_vtestnzc_pd_256:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vtestpd %ymm1, %ymm0<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -4216,16 +4240,16 @@ declare i32 @llvm.x86.avx.vtestnzc.pd.25<br>
define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float> %a1) {<br>
; AVX-LABEL: test_x86_avx_vtestnzc_ps:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vtestps %xmm1, %xmm0<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_vtestnzc_ps:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vtestps %xmm1, %xmm0<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.avx.vtestnzc.ps" rel="noreferrer" target="_blank">llvm.x86.avx.vtestnzc.ps</a>(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -4236,17 +4260,17 @@ declare i32 @<a href="http://llvm.x86.avx.vtestnzc.ps" rel="noreferrer" target="_blank">llvm.x86.avx.vtestnzc.ps</a>(<4<br>
define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x float> %a1) {<br>
; AVX-LABEL: test_x86_avx_vtestnzc_ps_256:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vtestps %ymm1, %ymm0<br>
; AVX-NEXT: seta %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: vzeroupper<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_vtestnzc_ps_256:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vtestps %ymm1, %ymm0<br>
; AVX512VL-NEXT: seta %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -4257,16 +4281,16 @@ declare i32 @llvm.x86.avx.vtestnzc.ps.25<br>
define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double> %a1) {<br>
; AVX-LABEL: test_x86_avx_vtestz_pd:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vtestpd %xmm1, %xmm0<br>
; AVX-NEXT: sete %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_vtestz_pd:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vtestpd %xmm1, %xmm0<br>
; AVX512VL-NEXT: sete %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -4277,17 +4301,17 @@ declare i32 @llvm.x86.avx.vtestz.pd(<2 x<br>
define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x double> %a1) {<br>
; AVX-LABEL: test_x86_avx_vtestz_pd_256:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vtestpd %ymm1, %ymm0<br>
; AVX-NEXT: sete %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: vzeroupper<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_vtestz_pd_256:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vtestpd %ymm1, %ymm0<br>
; AVX512VL-NEXT: sete %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -4298,16 +4322,16 @@ declare i32 @llvm.x86.avx.vtestz.pd.256(<br>
define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float> %a1) {<br>
; AVX-LABEL: test_x86_avx_vtestz_ps:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vtestps %xmm1, %xmm0<br>
; AVX-NEXT: sete %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_vtestz_ps:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vtestps %xmm1, %xmm0<br>
; AVX512VL-NEXT: sete %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.avx.vtestz.ps" rel="noreferrer" target="_blank">llvm.x86.avx.vtestz.ps</a>(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -4318,17 +4342,17 @@ declare i32 @<a href="http://llvm.x86.avx.vtestz.ps" rel="noreferrer" target="_blank">llvm.x86.avx.vtestz.ps</a>(<4 x<br>
define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x float> %a1) {<br>
; AVX-LABEL: test_x86_avx_vtestz_ps_256:<br>
; AVX: ## BB#0:<br>
+; AVX-NEXT: xorl %eax, %eax<br>
; AVX-NEXT: vtestps %ymm1, %ymm0<br>
; AVX-NEXT: sete %al<br>
-; AVX-NEXT: movzbl %al, %eax<br>
; AVX-NEXT: vzeroupper<br>
; AVX-NEXT: retl<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_vtestz_ps_256:<br>
; AVX512VL: ## BB#0:<br>
+; AVX512VL-NEXT: xorl %eax, %eax<br>
; AVX512VL-NEXT: vtestps %ymm1, %ymm0<br>
; AVX512VL-NEXT: sete %al<br>
-; AVX512VL-NEXT: movzbl %al, %eax<br>
; AVX512VL-NEXT: retl<br>
%res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-cmp.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-cmp.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-cmp.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-cmp.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-cmp.ll Thu Jul 7 17:50:23 2016<br>
@@ -94,9 +94,9 @@ return:<br>
define i32 @test6(i32 %a, i32 %b) {<br>
; ALL-LABEL: test6:<br>
; ALL: ## BB#0:<br>
+; ALL-NEXT: xorl %eax, %eax<br>
; ALL-NEXT: cmpl %esi, %edi<br>
; ALL-NEXT: sete %al<br>
-; ALL-NEXT: movzbl %al, %eax<br>
; ALL-NEXT: retq<br>
%cmp = icmp eq i32 %a, %b<br>
%res = zext i1 %cmp to i32<br>
@@ -106,9 +106,9 @@ define i32 @test6(i32 %a, i32 %b) {<br>
define i32 @test7(double %x, double %y) #2 {<br>
; ALL-LABEL: test7:<br>
; ALL: ## BB#0: ## %entry<br>
+; ALL-NEXT: xorl %eax, %eax<br>
; ALL-NEXT: vucomisd %xmm1, %xmm0<br>
; ALL-NEXT: setne %al<br>
-; ALL-NEXT: movzbl %al, %eax<br>
; ALL-NEXT: retq<br>
entry:<br>
%0 = fcmp one double %x, %y<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll Thu Jul 7 17:50:23 2016<br>
@@ -7,9 +7,9 @@ define i32 @test_kortestz(i16 %a0, i16 %<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: kmovw %esi, %k0<br>
; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: xorl %eax, %eax<br>
; CHECK-NEXT: kortestw %k0, %k1<br>
; CHECK-NEXT: sete %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: retq<br>
%res = call i32 @llvm.x86.avx512.kortestz.w(i16 %a0, i16 %a1)<br>
ret i32 %res<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll Thu Jul 7 17:50:23 2016<br>
@@ -571,9 +571,9 @@ define <64 x i8> @test17(i64 %x, i32 %y,<br>
; KNL-NEXT: vpbroadcastd %eax, %zmm1 {%k1} {z}<br>
; KNL-NEXT: vpmovdb %zmm1, %xmm1<br>
; KNL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1<br>
+; KNL-NEXT: xorl %ecx, %ecx<br>
; KNL-NEXT: cmpl %edx, %esi<br>
; KNL-NEXT: setg %cl<br>
-; KNL-NEXT: movzbl %cl, %ecx<br>
; KNL-NEXT: vpinsrb $5, %ecx, %xmm0, %xmm0<br>
; KNL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]<br>
; KNL-NEXT: vpsllw $7, %ymm0, %ymm0<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/bmi.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/bmi.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/bmi.ll Thu Jul 7 17:50:23 2016<br>
@@ -201,7 +201,6 @@ define i1 @and_cmp_const_power_of_two(i3<br>
; CHECK-NEXT: btl %esi, %edi<br>
; CHECK-NEXT: setae %al<br>
; CHECK-NEXT: retq<br>
-;<br>
%shl = shl i32 1, %y<br>
%and = and i32 %x, %shl<br>
%cmp = icmp ne i32 %and, %shl<br>
@@ -213,12 +212,11 @@ define i32 @and_cmp_not_one_use(i32 %x)<br>
; CHECK-LABEL: and_cmp_not_one_use:<br>
; CHECK: # BB#0:<br>
; CHECK-NEXT: andl $37, %edi<br>
+; CHECK-NEXT: xorl %eax, %eax<br>
; CHECK-NEXT: cmpl $37, %edi<br>
; CHECK-NEXT: sete %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: addl %edi, %eax<br>
; CHECK-NEXT: retq<br>
-;<br>
%and = and i32 %x, 37<br>
%cmp = icmp eq i32 %and, 37<br>
%ext = zext i1 %cmp to i32<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/cmov.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmov.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmov.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/cmov.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/cmov.ll Thu Jul 7 17:50:23 2016<br>
@@ -120,8 +120,8 @@ declare i32 @printf(i8* nocapture, ...)<br>
define i32 @test5(i32* nocapture %P) nounwind readonly {<br>
entry:<br>
; CHECK-LABEL: test5:<br>
+; CHECK: xorl %eax, %eax<br>
; CHECK: setg %al<br>
-; CHECK: movzbl %al, %eax<br>
; CHECK: orl $-2, %eax<br>
; CHECK: ret<br>
<br>
@@ -134,8 +134,8 @@ entry:<br>
define i32 @test6(i32* nocapture %P) nounwind readonly {<br>
entry:<br>
; CHECK-LABEL: test6:<br>
+; CHECK: xorl %eax, %eax<br>
; CHECK: setl %al<br>
-; CHECK: movzbl %al, %eax<br>
; CHECK: leal 4(%rax,%rax,8), %eax<br>
; CHECK: ret<br>
%0 = load i32, i32* %P, align 4 ; <i32> [#uses=1]<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/cmp.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmp.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmp.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/cmp.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/cmp.ll Thu Jul 7 17:50:23 2016<br>
@@ -49,9 +49,9 @@ define i64 @test3(i64 %x) nounwind {<br>
%r = zext i1 %t to i64<br>
ret i64 %r<br>
; CHECK-LABEL: test3:<br>
+; CHECK: xorl %eax, %eax<br>
; CHECK: testq %rdi, %rdi<br>
; CHECK: sete %al<br>
-; CHECK: movzbl %al, %eax<br>
; CHECK: ret<br>
}<br>
<br>
@@ -60,9 +60,9 @@ define i64 @test4(i64 %x) nounwind {<br>
%r = zext i1 %t to i64<br>
ret i64 %r<br>
; CHECK-LABEL: test4:<br>
+; CHECK: xorl %eax, %eax<br>
; CHECK: testq %rdi, %rdi<br>
; CHECK: setle %al<br>
-; CHECK: movzbl %al, %eax<br>
; CHECK: ret<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/cmpxchg-i1.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmpxchg-i1.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmpxchg-i1.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/cmpxchg-i1.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/cmpxchg-i1.ll Thu Jul 7 17:50:23 2016<br>
@@ -34,7 +34,7 @@ define i64 @cmpxchg_sext(i32* %addr, i32<br>
; CHECK-LABEL: cmpxchg_sext:<br>
; CHECK-DAG: cmpxchgl<br>
; CHECK-NOT: cmpl<br>
-; CHECK: sete %al<br>
+; CHECK: sete %cl<br>
; CHECK: retq<br>
%pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst<br>
%success = extractvalue { i32, i1 } %pair, 1<br>
@@ -44,10 +44,10 @@ define i64 @cmpxchg_sext(i32* %addr, i32<br>
<br>
define i32 @cmpxchg_zext(i32* %addr, i32 %desired, i32 %new) {<br>
; CHECK-LABEL: cmpxchg_zext:<br>
+; CHECK: xorl %e[[R:[a-z]]]x<br>
; CHECK: cmpxchgl<br>
; CHECK-NOT: cmp<br>
-; CHECK: sete [[BYTE:%[a-z0-9]+]]<br>
-; CHECK: movzbl [[BYTE]], %eax<br>
+; CHECK: sete %[[R]]l<br>
%pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst<br>
%success = extractvalue { i32, i1 } %pair, 1<br>
%mask = zext i1 %success to i32<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll Thu Jul 7 17:50:23 2016<br>
@@ -44,10 +44,10 @@ define i1 @cmpxchg_arithcmp(i128* %addr,<br>
<br>
define i128 @cmpxchg_zext(i128* %addr, i128 %desired, i128 %new) {<br>
; CHECK-LABEL: cmpxchg_zext:<br>
+; CHECK: xorl<br>
; CHECK: cmpxchg16b<br>
; CHECK-NOT: cmpq<br>
-; CHECK: sete [[BYTE:%[a-z0-9]+]]<br>
-; CHECK: movzbl [[BYTE]], %eax<br>
+; CHECK: sete<br>
%pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst<br>
%success = extractvalue { i128, i1 } %pair, 1<br>
%mask = zext i1 %success to i128<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/ctpop-combine.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ctpop-combine.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ctpop-combine.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/ctpop-combine.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/ctpop-combine.ll Thu Jul 7 17:50:23 2016<br>
@@ -6,10 +6,10 @@ declare i64 @llvm.ctpop.i64(i64) nounwin<br>
define i32 @test1(i64 %x) nounwind readnone {<br>
; CHECK-LABEL: test1:<br>
; CHECK: # BB#0:<br>
-; CHECK-NEXT: leaq -1(%rdi), %rax<br>
-; CHECK-NEXT: testq %rax, %rdi<br>
+; CHECK-NEXT: leaq -1(%rdi), %rcx<br>
+; CHECK-NEXT: xorl %eax, %eax<br>
+; CHECK-NEXT: testq %rcx, %rdi<br>
; CHECK-NEXT: setne %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: retq<br>
%count = tail call i64 @llvm.ctpop.i64(i64 %x)<br>
%cast = trunc i64 %count to i32<br>
@@ -22,10 +22,10 @@ define i32 @test1(i64 %x) nounwind readn<br>
define i32 @test2(i64 %x) nounwind readnone {<br>
; CHECK-LABEL: test2:<br>
; CHECK: # BB#0:<br>
-; CHECK-NEXT: leaq -1(%rdi), %rax<br>
-; CHECK-NEXT: testq %rax, %rdi<br>
+; CHECK-NEXT: leaq -1(%rdi), %rcx<br>
+; CHECK-NEXT: xorl %eax, %eax<br>
+; CHECK-NEXT: testq %rcx, %rdi<br>
; CHECK-NEXT: sete %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: retq<br>
%count = tail call i64 @llvm.ctpop.i64(i64 %x)<br>
%cmp = icmp ult i64 %count, 2<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/fp128-cast.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp128-cast.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp128-cast.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/fp128-cast.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/fp128-cast.ll Thu Jul 7 17:50:23 2016<br>
@@ -238,6 +238,7 @@ entry:<br>
; X64-LABEL: TestConst128:<br>
; X64: movaps {{.*}}, %xmm1<br>
; X64-NEXT: callq __gttf2<br>
+; X64-NEXT: xorl<br>
; X64-NEXT: test<br>
; X64: retq<br>
}<br>
@@ -277,9 +278,9 @@ entry:<br>
; X64-NEXT: movq (%rsp),<br>
; X64-NEXT: movq %<br>
; X64-NEXT: shrq $32,<br>
-; X64: orl<br>
+; X64: xorl %eax, %eax<br>
+; X64-NEXT: orl<br>
; X64-NEXT: sete %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64: retq<br>
;<br>
; If TestBits128 fails due to any llvm or clang change,<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/fp128-compare.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp128-compare.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp128-compare.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/fp128-compare.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/fp128-compare.ll Thu Jul 7 17:50:23 2016<br>
@@ -8,8 +8,9 @@ entry:<br>
ret i32 %conv<br>
; CHECK-LABEL: TestComp128GT:<br>
; CHECK: callq __gttf2<br>
-; CHECK: setg %al<br>
-; CHECK: movzbl %al, %eax<br>
+; CHECK: xorl %ecx, %ecx<br>
+; CHECK: setg %cl<br>
+; CHECK: movl %ecx, %eax<br>
; CHECK: retq<br>
}<br>
<br>
@@ -20,9 +21,10 @@ entry:<br>
ret i32 %conv<br>
; CHECK-LABEL: TestComp128GE:<br>
; CHECK: callq __getf2<br>
+; CHECK: xorl %ecx, %ecx<br>
; CHECK: testl %eax, %eax<br>
-; CHECK: setns %al<br>
-; CHECK: movzbl %al, %eax<br>
+; CHECK: setns %cl<br>
+; CHECK: movl %ecx, %eax<br>
; CHECK: retq<br>
}<br>
<br>
@@ -48,9 +50,10 @@ entry:<br>
ret i32 %conv<br>
; CHECK-LABEL: TestComp128LE:<br>
; CHECK: callq __letf2<br>
-; CHECK-NEXT: testl %eax, %eax<br>
-; CHECK: setle %al<br>
-; CHECK: movzbl %al, %eax<br>
+; CHECK: xorl %ecx, %ecx<br>
+; CHECK: testl %eax, %eax<br>
+; CHECK: setle %cl<br>
+; CHECK: movl %ecx, %eax<br>
; CHECK: retq<br>
}<br>
<br>
@@ -61,9 +64,10 @@ entry:<br>
ret i32 %conv<br>
; CHECK-LABEL: TestComp128EQ:<br>
; CHECK: callq __eqtf2<br>
-; CHECK-NEXT: testl %eax, %eax<br>
-; CHECK: sete %al<br>
-; CHECK: movzbl %al, %eax<br>
+; CHECK: xorl %ecx, %ecx<br>
+; CHECK: testl %eax, %eax<br>
+; CHECK: sete %cl<br>
+; CHECK: movl %ecx, %eax<br>
; CHECK: retq<br>
}<br>
<br>
@@ -74,9 +78,10 @@ entry:<br>
ret i32 %conv<br>
; CHECK-LABEL: TestComp128NE:<br>
; CHECK: callq __netf2<br>
-; CHECK-NEXT: testl %eax, %eax<br>
-; CHECK: setne %al<br>
-; CHECK: movzbl %al, %eax<br>
+; CHECK: xorl %ecx, %ecx<br>
+; CHECK: testl %eax, %eax<br>
+; CHECK: setne %cl<br>
+; CHECK: movl %ecx, %eax<br>
; CHECK: retq<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/mcinst-lowering.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mcinst-lowering.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mcinst-lowering.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/mcinst-lowering.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/mcinst-lowering.ll Thu Jul 7 17:50:23 2016<br>
@@ -3,26 +3,17 @@<br>
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"<br>
target triple = "x86_64-apple-darwin10.0.0"<br>
<br>
+declare i32 @foo();<br>
+<br>
define i32 @f0(i32* nocapture %x) nounwind readonly ssp {<br>
entry:<br>
- %tmp1 = load i32, i32* %x ; <i32> [#uses=2]<br>
- %tobool = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1]<br>
- br i1 %tobool, label %if.end, label %return<br>
-<br>
-if.end: ; preds = %entry<br>
-<br>
-; Check that we lower to the short form of cmpl, which has a fixed %eax<br>
-; register.<br>
-;<br>
+ %tmp1 = call i32 @foo()<br>
; CHECK: cmpl $16777216, %eax<br>
; CHECK: # encoding: [0x3d,0x00,0x00,0x00,0x01]<br>
%cmp = icmp eq i32 %tmp1, 16777216 ; <i1> [#uses=1]<br>
<br>
%conv = zext i1 %cmp to i32 ; <i32> [#uses=1]<br>
ret i32 %conv<br>
-<br>
-return: ; preds = %entry<br>
- ret i32 0<br>
}<br>
<br>
define i32 @f1() nounwind {<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/return-ext.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/return-ext.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/return-ext.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/return-ext.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/return-ext.ll Thu Jul 7 17:50:23 2016<br>
@@ -42,9 +42,9 @@ entry:<br>
<br>
; Except on Darwin, for legacy reasons.<br>
; DARWIN-LABEL: unsigned_i8:<br>
-; DARWIN: cmp<br>
+; DARWIN: xorl<br>
+; DARWIN-NEXT: cmp<br>
; DARWIN-NEXT: sete<br>
-; DARWIN-NEXT: movzbl<br>
; DARWIN-NEXT: ret<br>
}<br>
<br>
@@ -63,9 +63,9 @@ entry:<br>
<br>
; Except on Darwin, for legacy reasons.<br>
; DARWIN-LABEL: signed_i8:<br>
-; DARWIN: cmp<br>
+; DARWIN: xorl<br>
+; DARWIN-NEXT: cmp<br>
; DARWIN-NEXT: sete<br>
-; DARWIN-NEXT: movzbl<br>
; DARWIN-NEXT: ret<br>
}<br>
<br>
@@ -85,7 +85,7 @@ entry:<br>
; CHECK-NEXT: addw<br>
; CHECK-NEXT: ret<br>
<br>
-; Except on Darwin, for legay reasons.<br>
+; Except on Darwin, for legacy reasons.<br>
; DARWIN-LABEL: unsigned_i16:<br>
; DARWIN-BWOFF: movw<br>
; DARWIN-BWON: movzwl<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll Thu Jul 7 17:50:23 2016<br>
@@ -6,9 +6,9 @@<br>
define i32 @t1() nounwind ssp {<br>
entry:<br>
; CHECK-LABEL: t1:<br>
-; CHECK: cmpl $0, _t1.global<br>
+; CHECK: xorl %eax, %eax<br>
+; CHECK-NEXT: cmpl $0, _t1.global<br>
; CHECK-NEXT: setne %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: ret<br>
%0 = load i64, i64* @t1.global, align 8<br>
%and = and i64 4294967295, %0<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/setcc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setcc.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setcc.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/setcc.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/setcc.ll Thu Jul 7 17:50:23 2016<br>
@@ -7,8 +7,8 @@<br>
define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {<br>
entry:<br>
; CHECK-LABEL: t1:<br>
+; CHECK: xorl %eax, %eax<br>
; CHECK: seta %al<br>
-; CHECK: movzbl %al, %eax<br>
; CHECK: shll $5, %eax<br>
%0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1]<br>
%iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll Thu Jul 7 17:50:23 2016<br>
@@ -593,16 +593,16 @@ declare i32 @llvm.x86.sse.comieq.ss(<4 x<br>
define i32 @test_mm_comige_ss(<4 x float> %a0, <4 x float> %a1) nounwind {<br>
; X32-LABEL: test_mm_comige_ss:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: comiss %xmm1, %xmm0<br>
; X32-NEXT: setae %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_comige_ss:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: comiss %xmm1, %xmm0<br>
; X64-NEXT: setae %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1)<br>
ret i32 %res<br>
@@ -612,16 +612,16 @@ declare i32 @llvm.x86.sse.comige.ss(<4 x<br>
define i32 @test_mm_comigt_ss(<4 x float> %a0, <4 x float> %a1) nounwind {<br>
; X32-LABEL: test_mm_comigt_ss:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: comiss %xmm1, %xmm0<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_comigt_ss:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: comiss %xmm1, %xmm0<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1)<br>
ret i32 %res<br>
@@ -631,16 +631,16 @@ declare i32 @llvm.x86.sse.comigt.ss(<4 x<br>
define i32 @test_mm_comile_ss(<4 x float> %a0, <4 x float> %a1) nounwind {<br>
; X32-LABEL: test_mm_comile_ss:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: comiss %xmm0, %xmm1<br>
; X32-NEXT: setae %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_comile_ss:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: comiss %xmm0, %xmm1<br>
; X64-NEXT: setae %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1)<br>
ret i32 %res<br>
@@ -650,16 +650,16 @@ declare i32 @llvm.x86.sse.comile.ss(<4 x<br>
define i32 @test_mm_comilt_ss(<4 x float> %a0, <4 x float> %a1) nounwind {<br>
; X32-LABEL: test_mm_comilt_ss:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: comiss %xmm0, %xmm1<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_comilt_ss:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: comiss %xmm0, %xmm1<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1)<br>
ret i32 %res<br>
@@ -2094,16 +2094,16 @@ declare i32 @llvm.x86.sse.ucomieq.ss(<4<br>
define i32 @test_mm_ucomige_ss(<4 x float> %a0, <4 x float> %a1) nounwind {<br>
; X32-LABEL: test_mm_ucomige_ss:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: ucomiss %xmm1, %xmm0<br>
; X32-NEXT: setae %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_ucomige_ss:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: ucomiss %xmm1, %xmm0<br>
; X64-NEXT: setae %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1)<br>
ret i32 %res<br>
@@ -2113,16 +2113,16 @@ declare i32 @llvm.x86.sse.ucomige.ss(<4<br>
define i32 @test_mm_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) nounwind {<br>
; X32-LABEL: test_mm_ucomigt_ss:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: ucomiss %xmm1, %xmm0<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_ucomigt_ss:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: ucomiss %xmm1, %xmm0<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1)<br>
ret i32 %res<br>
@@ -2132,16 +2132,16 @@ declare i32 @llvm.x86.sse.ucomigt.ss(<4<br>
define i32 @test_mm_ucomile_ss(<4 x float> %a0, <4 x float> %a1) nounwind {<br>
; X32-LABEL: test_mm_ucomile_ss:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: ucomiss %xmm0, %xmm1<br>
; X32-NEXT: setae %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_ucomile_ss:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: ucomiss %xmm0, %xmm1<br>
; X64-NEXT: setae %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1)<br>
ret i32 %res<br>
@@ -2151,16 +2151,16 @@ declare i32 @llvm.x86.sse.ucomile.ss(<4<br>
define i32 @test_mm_ucomilt_ss(<4 x float> %a0, <4 x float> %a1) nounwind {<br>
; X32-LABEL: test_mm_ucomilt_ss:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: ucomiss %xmm0, %xmm1<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_ucomilt_ss:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: ucomiss %xmm0, %xmm1<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1)<br>
ret i32 %res<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll Thu Jul 7 17:50:23 2016<br>
@@ -77,16 +77,16 @@ declare i32 @llvm.x86.sse.comieq.ss(<4 x<br>
define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; SSE-LABEL: test_x86_sse_comige_ss:<br>
; SSE: ## BB#0:<br>
+; SSE-NEXT: xorl %eax, %eax<br>
; SSE-NEXT: comiss %xmm1, %xmm0<br>
; SSE-NEXT: setae %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_comige_ss:<br>
; KNL: ## BB#0:<br>
+; KNL-NEXT: xorl %eax, %eax<br>
; KNL-NEXT: vcomiss %xmm1, %xmm0<br>
; KNL-NEXT: setae %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -97,16 +97,16 @@ declare i32 @llvm.x86.sse.comige.ss(<4 x<br>
define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; SSE-LABEL: test_x86_sse_comigt_ss:<br>
; SSE: ## BB#0:<br>
+; SSE-NEXT: xorl %eax, %eax<br>
; SSE-NEXT: comiss %xmm1, %xmm0<br>
; SSE-NEXT: seta %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_comigt_ss:<br>
; KNL: ## BB#0:<br>
+; KNL-NEXT: xorl %eax, %eax<br>
; KNL-NEXT: vcomiss %xmm1, %xmm0<br>
; KNL-NEXT: seta %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -117,16 +117,16 @@ declare i32 @llvm.x86.sse.comigt.ss(<4 x<br>
define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; SSE-LABEL: test_x86_sse_comile_ss:<br>
; SSE: ## BB#0:<br>
+; SSE-NEXT: xorl %eax, %eax<br>
; SSE-NEXT: comiss %xmm0, %xmm1<br>
; SSE-NEXT: setae %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_comile_ss:<br>
; KNL: ## BB#0:<br>
+; KNL-NEXT: xorl %eax, %eax<br>
; KNL-NEXT: vcomiss %xmm0, %xmm1<br>
; KNL-NEXT: setae %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -137,16 +137,16 @@ declare i32 @llvm.x86.sse.comile.ss(<4 x<br>
define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; SSE-LABEL: test_x86_sse_comilt_ss:<br>
; SSE: ## BB#0:<br>
+; SSE-NEXT: xorl %eax, %eax<br>
; SSE-NEXT: comiss %xmm0, %xmm1<br>
; SSE-NEXT: seta %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_comilt_ss:<br>
; KNL: ## BB#0:<br>
+; KNL-NEXT: xorl %eax, %eax<br>
; KNL-NEXT: vcomiss %xmm0, %xmm1<br>
; KNL-NEXT: seta %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -517,16 +517,16 @@ declare i32 @llvm.x86.sse.ucomieq.ss(<4<br>
define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; SSE-LABEL: test_x86_sse_ucomige_ss:<br>
; SSE: ## BB#0:<br>
+; SSE-NEXT: xorl %eax, %eax<br>
; SSE-NEXT: ucomiss %xmm1, %xmm0<br>
; SSE-NEXT: setae %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_ucomige_ss:<br>
; KNL: ## BB#0:<br>
+; KNL-NEXT: xorl %eax, %eax<br>
; KNL-NEXT: vucomiss %xmm1, %xmm0<br>
; KNL-NEXT: setae %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -537,16 +537,16 @@ declare i32 @llvm.x86.sse.ucomige.ss(<4<br>
define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; SSE-LABEL: test_x86_sse_ucomigt_ss:<br>
; SSE: ## BB#0:<br>
+; SSE-NEXT: xorl %eax, %eax<br>
; SSE-NEXT: ucomiss %xmm1, %xmm0<br>
; SSE-NEXT: seta %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_ucomigt_ss:<br>
; KNL: ## BB#0:<br>
+; KNL-NEXT: xorl %eax, %eax<br>
; KNL-NEXT: vucomiss %xmm1, %xmm0<br>
; KNL-NEXT: seta %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -557,16 +557,16 @@ declare i32 @llvm.x86.sse.ucomigt.ss(<4<br>
define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; SSE-LABEL: test_x86_sse_ucomile_ss:<br>
; SSE: ## BB#0:<br>
+; SSE-NEXT: xorl %eax, %eax<br>
; SSE-NEXT: ucomiss %xmm0, %xmm1<br>
; SSE-NEXT: setae %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_ucomile_ss:<br>
; KNL: ## BB#0:<br>
+; KNL-NEXT: xorl %eax, %eax<br>
; KNL-NEXT: vucomiss %xmm0, %xmm1<br>
; KNL-NEXT: setae %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -577,16 +577,16 @@ declare i32 @llvm.x86.sse.ucomile.ss(<4<br>
define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; SSE-LABEL: test_x86_sse_ucomilt_ss:<br>
; SSE: ## BB#0:<br>
+; SSE-NEXT: xorl %eax, %eax<br>
; SSE-NEXT: ucomiss %xmm0, %xmm1<br>
; SSE-NEXT: seta %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_ucomilt_ss:<br>
; KNL: ## BB#0:<br>
+; KNL-NEXT: xorl %eax, %eax<br>
; KNL-NEXT: vucomiss %xmm0, %xmm1<br>
; KNL-NEXT: seta %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll Thu Jul 7 17:50:23 2016<br>
@@ -983,16 +983,16 @@ declare i32 @<a href="http://llvm.x86.sse2.comieq.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comieq.sd</a>(<2<br>
define i32 @test_mm_comige_sd(<2 x double> %a0, <2 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm_comige_sd:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: comisd %xmm1, %xmm0<br>
; X32-NEXT: setae %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_comige_sd:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: comisd %xmm1, %xmm0<br>
; X64-NEXT: setae %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comige.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comige.sd</a>(<2 x double> %a0, <2 x double> %a1)<br>
ret i32 %res<br>
@@ -1002,16 +1002,16 @@ declare i32 @<a href="http://llvm.x86.sse2.comige.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comige.sd</a>(<2<br>
define i32 @test_mm_comigt_sd(<2 x double> %a0, <2 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm_comigt_sd:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: comisd %xmm1, %xmm0<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_comigt_sd:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: comisd %xmm1, %xmm0<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comigt.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comigt.sd</a>(<2 x double> %a0, <2 x double> %a1)<br>
ret i32 %res<br>
@@ -1021,16 +1021,16 @@ declare i32 @<a href="http://llvm.x86.sse2.comigt.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comigt.sd</a>(<2<br>
define i32 @test_mm_comile_sd(<2 x double> %a0, <2 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm_comile_sd:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: comisd %xmm0, %xmm1<br>
; X32-NEXT: setae %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_comile_sd:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: comisd %xmm0, %xmm1<br>
; X64-NEXT: setae %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comile.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comile.sd</a>(<2 x double> %a0, <2 x double> %a1)<br>
ret i32 %res<br>
@@ -1040,16 +1040,16 @@ declare i32 @<a href="http://llvm.x86.sse2.comile.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comile.sd</a>(<2<br>
define i32 @test_mm_comilt_sd(<2 x double> %a0, <2 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm_comilt_sd:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: comisd %xmm0, %xmm1<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_comilt_sd:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: comisd %xmm0, %xmm1<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comilt.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comilt.sd</a>(<2 x double> %a0, <2 x double> %a1)<br>
ret i32 %res<br>
@@ -3538,16 +3538,16 @@ declare i32 @<a href="http://llvm.x86.sse2.ucomieq.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomieq.sd</a>(<2<br>
define i32 @test_mm_ucomige_sd(<2 x double> %a0, <2 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm_ucomige_sd:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: ucomisd %xmm1, %xmm0<br>
; X32-NEXT: setae %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_ucomige_sd:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: ucomisd %xmm1, %xmm0<br>
; X64-NEXT: setae %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomige.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomige.sd</a>(<2 x double> %a0, <2 x double> %a1)<br>
ret i32 %res<br>
@@ -3557,16 +3557,16 @@ declare i32 @<a href="http://llvm.x86.sse2.ucomige.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomige.sd</a>(<2<br>
define i32 @test_mm_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm_ucomigt_sd:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: ucomisd %xmm1, %xmm0<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_ucomigt_sd:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: ucomisd %xmm1, %xmm0<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomigt.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomigt.sd</a>(<2 x double> %a0, <2 x double> %a1)<br>
ret i32 %res<br>
@@ -3576,16 +3576,16 @@ declare i32 @<a href="http://llvm.x86.sse2.ucomigt.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomigt.sd</a>(<2<br>
define i32 @test_mm_ucomile_sd(<2 x double> %a0, <2 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm_ucomile_sd:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: ucomisd %xmm0, %xmm1<br>
; X32-NEXT: setae %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_ucomile_sd:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: ucomisd %xmm0, %xmm1<br>
; X64-NEXT: setae %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomile.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomile.sd</a>(<2 x double> %a0, <2 x double> %a1)<br>
ret i32 %res<br>
@@ -3595,16 +3595,16 @@ declare i32 @<a href="http://llvm.x86.sse2.ucomile.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomile.sd</a>(<2<br>
define i32 @test_mm_ucomilt_sd(<2 x double> %a0, <2 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm_ucomilt_sd:<br>
; X32: # BB#0:<br>
+; X32-NEXT: xorl %eax, %eax<br>
; X32-NEXT: ucomisd %xmm0, %xmm1<br>
; X32-NEXT: seta %al<br>
-; X32-NEXT: movzbl %al, %eax<br>
; X32-NEXT: retl<br>
;<br>
; X64-LABEL: test_mm_ucomilt_sd:<br>
; X64: # BB#0:<br>
+; X64-NEXT: xorl %eax, %eax<br>
; X64-NEXT: ucomisd %xmm0, %xmm1<br>
; X64-NEXT: seta %al<br>
-; X64-NEXT: movzbl %al, %eax<br>
; X64-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomilt.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.ucomilt.sd</a>(<2 x double> %a0, <2 x double> %a1)<br>
ret i32 %res<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=274802&r1=274801&r2=274802&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=274802&r1=274801&r2=274802&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll Thu Jul 7 17:50:23 2016<br>
@@ -77,16 +77,16 @@ declare i32 @<a href="http://llvm.x86.sse2.comieq.sd" rel="noreferrer" target="_blank">llvm.x86.sse2.comieq.sd</a>(<2<br>
define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; SSE-LABEL: test_x86_sse2_comige_sd:<br>
; SSE: ## BB#0:<br>
+; SSE-NEXT: xorl %eax, %eax<br>
; SSE-NEXT: comisd %xmm1, %xmm0<br>
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