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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">I think it's worth it. Most backend tests currently mutate the default target triple (often the host triple) and converting all of those to fully specify a target triple
using –triple/-mtriple is a big task that isn't a pre-requisite of fixing the N32 vs N64 problem.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Rafael Espíndola [mailto:rafael.espindola@gmail.com]
<br>
<b>Sent:</b> 11 July 2016 16:52<br>
<b>To:</b> reviews+D21465+public+92eb7897bc2cfded@reviews.llvm.org<br>
<b>Cc:</b> Daniel Sanders; nemanja.i.ibm@gmail.com; amara.emerson@arm.com; tberghammer@google.com; danalbert@google.com; srhines@google.com; llvm-commits@lists.llvm.org; t.p.northover@gmail.com; filcab+llvm.phabricator@gmail.com<br>
<b>Subject:</b> Re: [PATCH] D21465: [llc+llvm-mc] Replace the hidden -target-abi option with a -mabi thats visible in --help.<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Given that we agreed on using triples to differentiate n32 and n64, is this worth it? A followup patch would just delete the option and use the triple, no?<br>
<br>
On Monday, 11 July 2016, Daniel Sanders <<a href="mailto:daniel.sanders@imgtec.com">daniel.sanders@imgtec.com</a>> wrote:<o:p></o:p></p>
<p class="MsoNormal" style="margin-bottom:12.0pt">dsanders updated this revision to Diff 63489.<br>
dsanders added a comment.<br>
<br>
Refresh patch. This patch is unaffected by the recent discussion on llvm-dev.<br>
<br>
<br>
<a href="http://reviews.llvm.org/D21465" target="_blank">http://reviews.llvm.org/D21465</a><br>
<br>
Files:<br>
include/llvm/MC/MCTargetOptionsCommandFlags.h<br>
test/CodeGen/ARM/arm-abi-attr.ll<br>
test/CodeGen/ARM/atomic-64bit.ll<br>
test/CodeGen/ARM/dagcombine-concatvector.ll<br>
test/CodeGen/ARM/emit-big-cst.ll<br>
test/CodeGen/ARM/tail-call.ll<br>
test/CodeGen/Mips/2008-08-01-AsmInline.ll<br>
test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll<br>
test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll<br>
test/CodeGen/Mips/abiflags32.ll<br>
test/CodeGen/Mips/adjust-callstack-sp.ll<br>
test/CodeGen/Mips/atomicCmpSwapPW.ll<br>
test/CodeGen/Mips/blockaddr.ll<br>
test/CodeGen/Mips/cconv/arguments-float.ll<br>
test/CodeGen/Mips/cconv/arguments-fp128.ll<br>
test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll<br>
test/CodeGen/Mips/cconv/arguments-hard-float.ll<br>
test/CodeGen/Mips/cconv/arguments-hard-fp128.ll<br>
test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll<br>
test/CodeGen/Mips/cconv/arguments-struct.ll<br>
test/CodeGen/Mips/cconv/arguments-varargs.ll<br>
test/CodeGen/Mips/cconv/arguments.ll<br>
test/CodeGen/Mips/cconv/callee-saved-float.ll<br>
test/CodeGen/Mips/cconv/callee-saved.ll<br>
test/CodeGen/Mips/cconv/memory-layout.ll<br>
test/CodeGen/Mips/cconv/reserved-space.ll<br>
test/CodeGen/Mips/cconv/return-float.ll<br>
test/CodeGen/Mips/cconv/return-hard-float.ll<br>
test/CodeGen/Mips/cconv/return-hard-fp128.ll<br>
test/CodeGen/Mips/cconv/return-hard-struct-f128.ll<br>
test/CodeGen/Mips/cconv/return-struct.ll<br>
test/CodeGen/Mips/cconv/return.ll<br>
test/CodeGen/Mips/cconv/roundl-call.ll<br>
test/CodeGen/Mips/cconv/stack-alignment.ll<br>
test/CodeGen/Mips/compactbranches/compact-branches.ll<br>
test/CodeGen/Mips/cstmaterialization/stack.ll<br>
test/CodeGen/Mips/dynamic-stack-realignment.ll<br>
test/CodeGen/Mips/ehframe-indirect.ll<br>
test/CodeGen/Mips/elf_eflags.ll<br>
test/CodeGen/Mips/fcopysign-f32-f64.ll<br>
test/CodeGen/Mips/fcopysign.ll<br>
test/CodeGen/Mips/fmadd1.ll<br>
test/CodeGen/Mips/fp-indexed-ls.ll<br>
test/CodeGen/Mips/fpxx.ll<br>
test/CodeGen/Mips/global-address.ll<br>
test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll<br>
test/CodeGen/Mips/inlineasm64.ll<br>
test/CodeGen/Mips/interrupt-attr-64-error.ll<br>
test/CodeGen/Mips/largeimmprinting.ll<br>
test/CodeGen/Mips/llvm-ir/add.ll<br>
test/CodeGen/Mips/llvm-ir/and.ll<br>
test/CodeGen/Mips/llvm-ir/lh_lhu.ll<br>
test/CodeGen/Mips/llvm-ir/mul.ll<br>
test/CodeGen/Mips/llvm-ir/not.ll<br>
test/CodeGen/Mips/llvm-ir/or.ll<br>
test/CodeGen/Mips/llvm-ir/sdiv.ll<br>
test/CodeGen/Mips/llvm-ir/srem.ll<br>
test/CodeGen/Mips/llvm-ir/udiv.ll<br>
test/CodeGen/Mips/llvm-ir/urem.ll<br>
test/CodeGen/Mips/llvm-ir/xor.ll<br>
test/CodeGen/Mips/load-store-left-right.ll<br>
test/CodeGen/Mips/longbranch.ll<br>
test/CodeGen/Mips/madd-msub.ll<br>
test/CodeGen/Mips/micromips-lwc1-swc1.ll<br>
test/CodeGen/Mips/mips64-sret.ll<br>
test/CodeGen/Mips/mips64directive.ll<br>
test/CodeGen/Mips/mips64ext.ll<br>
test/CodeGen/Mips/mips64extins.ll<br>
test/CodeGen/Mips/mips64fpimm0.ll<br>
test/CodeGen/Mips/mips64fpldst.ll<br>
test/CodeGen/Mips/mips64intldst.ll<br>
test/CodeGen/Mips/mips64r6/compatibility.ll<br>
test/CodeGen/Mips/msa/basic_operations.ll<br>
test/CodeGen/Mips/msa/basic_operations_float.ll<br>
test/CodeGen/Mips/named-register-n32.ll<br>
test/CodeGen/Mips/remat-immed-load.ll<br>
test/CodeGen/Mips/start-asm-file.ll<br>
test/CodeGen/Mips/zeroreg.ll<br>
test/CodeGen/PowerPC/ppc64-elf-abi.ll<br>
test/MC/Mips/cpload.s<br>
test/MC/Mips/cprestore-noreorder-noat.s<br>
test/MC/Mips/cprestore-noreorder.s<br>
test/MC/Mips/cprestore-reorder.s<br>
test/MC/Mips/cpsetup.s<br>
test/MC/Mips/do_switch3.s<br>
test/MC/Mips/elf_eflags.s<br>
test/MC/Mips/elf_reginfo.s<br>
test/MC/Mips/expansion-jal-sym-pic.s<br>
test/MC/Mips/macro-la-bad.s<br>
test/MC/Mips/macro-la.s<br>
test/MC/Mips/macro-li-bad.s<br>
test/MC/Mips/mips-expansions-bad.s<br>
test/MC/Mips/mips-reginfo-fp64.s<br>
test/MC/Mips/mips64-register-names-n32-n64.s<br>
test/MC/Mips/mips64-register-names-o32.s<br>
test/MC/Mips/mips64/abiflags.s<br>
test/MC/Mips/mips64extins.s<br>
test/MC/Mips/mips64r2/abi-bad.s<br>
test/MC/Mips/mips64r2/abiflags.s<br>
test/MC/Mips/mips64r3/abi-bad.s<br>
test/MC/Mips/mips64r3/abiflags.s<br>
test/MC/Mips/mips64r5/abi-bad.s<br>
test/MC/Mips/mips64r5/abiflags.s<br>
test/MC/Mips/mips_abi_flags_xx.s<br>
test/MC/Mips/nabi-regs.s<br>
test/MC/Mips/nooddspreg-cmdarg.s<br>
test/MC/Mips/nooddspreg.s<br>
test/MC/Mips/oddspreg.s<br>
test/MC/Mips/reloc-directive-bad.s<br>
test/MC/Mips/reloc-directive-negative.s<br>
test/MC/Mips/reloc-directive.s<br>
tools/llc/llc.cpp<br>
tools/llvm-mc/llvm-mc.cpp<o:p></o:p></p>
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