<div dir="ltr">Hi Craig,<div><br></div><div>I'm seeing a buildbot failure, <a href="http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/2074/">http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/2074/</a> , that looks like it might be related to this. Could you check it out? </div><div><br></div><div>- Lang.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Jul 7, 2016 at 11:14 PM, Craig Topper via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ctopper<br>
Date: Fri Jul 8 01:14:47 2016<br>
New Revision: 274827<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=274827&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=274827&view=rev</a><br>
Log:<br>
[AVX512] Remove and autoupgrade a duplicate set of 512-bit masked shift intrinsics.<br>
<br>
I'm not sure if clang ever used these builtin names or not.<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
llvm/trunk/lib/IR/AutoUpgrade.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h<br>
llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll<br>
<br>
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=274827&r1=274826&r2=274827&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=274827&r1=274826&r2=274827&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)<br>
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Fri Jul 8 01:14:47 2016<br>
@@ -2040,25 +2040,6 @@ let TargetPrefix = "x86" in { // All in<br>
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,<br>
llvm_i32_ty], [IntrNoMem]>;<br>
<br>
- def int_x86_avx512_mask_pslli_d : GCCBuiltin<"__builtin_ia32_pslldi512">,<br>
- Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,<br>
- llvm_i32_ty, llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;<br>
- def int_x86_avx512_mask_pslli_q : GCCBuiltin<"__builtin_ia32_psllqi512">,<br>
- Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,<br>
- llvm_i32_ty, llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;<br>
- def int_x86_avx512_mask_psrli_d : GCCBuiltin<"__builtin_ia32_psrldi512">,<br>
- Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,<br>
- llvm_i32_ty, llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;<br>
- def int_x86_avx512_mask_psrli_q : GCCBuiltin<"__builtin_ia32_psrlqi512">,<br>
- Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,<br>
- llvm_i32_ty, llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;<br>
- def int_x86_avx512_mask_psrai_d : GCCBuiltin<"__builtin_ia32_psradi512">,<br>
- Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,<br>
- llvm_i32_ty, llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;<br>
- def int_x86_avx512_mask_psrai_q : GCCBuiltin<"__builtin_ia32_psraqi512">,<br>
- Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,<br>
- llvm_i32_ty, llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;<br>
-<br>
def int_x86_avx512_mask_psrl_w_128 : GCCBuiltin<"__builtin_ia32_psrlw128_mask">,<br>
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,<br>
llvm_v8i16_ty, llvm_v8i16_ty, llvm_i8_ty], [IntrNoMem]>;<br>
<br>
Modified: llvm/trunk/lib/IR/AutoUpgrade.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=274827&r1=274826&r2=274827&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=274827&r1=274826&r2=274827&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/IR/AutoUpgrade.cpp (original)<br>
+++ llvm/trunk/lib/IR/AutoUpgrade.cpp Fri Jul 8 01:14:47 2016<br>
@@ -342,6 +342,23 @@ static bool UpgradeIntrinsicFunction1(Fu<br>
Intrinsic::x86_xop_vfrcz_sd);<br>
return true;<br>
}<br>
+ if (IsX86 && (Name.startswith("avx512.mask.pslli.") ||<br>
+ Name.startswith("avx512.mask.psrai.") ||<br>
+ Name.startswith("avx512.mask.psrli."))) {<br>
+ F->setName("llvm.x86." + Name + ".old");<br>
+ Intrinsic::ID ShiftID;<br>
+ if (Name.slice(12, 16) == "psll")<br>
+ ShiftID = Name[18] == 'd' ? Intrinsic::x86_avx512_mask_psll_di_512<br>
+ : Intrinsic::x86_avx512_mask_psll_qi_512;<br>
+ else if (Name.slice(12, 16) == "psra")<br>
+ ShiftID = Name[18] == 'd' ? Intrinsic::x86_avx512_mask_psra_di_512<br>
+ : Intrinsic::x86_avx512_mask_psra_qi_512;<br>
+ else<br>
+ ShiftID = Name[18] == 'd' ? Intrinsic::x86_avx512_mask_psrl_di_512<br>
+ : Intrinsic::x86_avx512_mask_psrl_qi_512;<br>
+ NewFn = Intrinsic::getDeclaration(F->getParent(), ShiftID);<br>
+ return true;<br>
+ }<br>
// Fix the FMA4 intrinsics to remove the 4<br>
if (IsX86 && Name.startswith("fma4.")) {<br>
F->setName("llvm.x86.fma" + Name.substr(5));<br>
@@ -353,7 +370,7 @@ static bool UpgradeIntrinsicFunction1(Fu<br>
auto Params = F->getFunctionType()->params();<br>
auto Idx = Params[2];<br>
if (Idx->getScalarType()->isFloatingPointTy()) {<br>
- F->setName(Name + ".old");<br>
+ F->setName("llvm.x86." + Name + ".old");<br>
unsigned IdxSize = Idx->getPrimitiveSizeInBits();<br>
unsigned EltSize = Idx->getScalarSizeInBits();<br>
Intrinsic::ID Permil2ID;<br>
@@ -1179,6 +1196,12 @@ void llvm::UpgradeIntrinsicCall(CallInst<br>
default:<br>
llvm_unreachable("Unknown function for CallInst upgrade.");<br>
<br>
+ case Intrinsic::x86_avx512_mask_psll_di_512:<br>
+ case Intrinsic::x86_avx512_mask_psra_di_512:<br>
+ case Intrinsic::x86_avx512_mask_psrl_di_512:<br>
+ case Intrinsic::x86_avx512_mask_psll_qi_512:<br>
+ case Intrinsic::x86_avx512_mask_psra_qi_512:<br>
+ case Intrinsic::x86_avx512_mask_psrl_qi_512:<br>
case Intrinsic::arm_neon_vld1:<br>
case Intrinsic::arm_neon_vld2:<br>
case Intrinsic::arm_neon_vld3:<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=274827&r1=274826&r2=274827&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=274827&r1=274826&r2=274827&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jul 8 01:14:47 2016<br>
@@ -17796,13 +17796,6 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
case VSHIFT:<br>
return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),<br>
Op.getOperand(1), Op.getOperand(2), DAG);<br>
- case VSHIFT_MASK:<br>
- return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,<br>
- Op.getSimpleValueType(),<br>
- Op.getOperand(1),<br>
- Op.getOperand(2), DAG),<br>
- Op.getOperand(4), Op.getOperand(3), Subtarget,<br>
- DAG);<br>
case COMPRESS_EXPAND_IN_REG: {<br>
SDValue Mask = Op.getOperand(3);<br>
SDValue DataToCompress = Op.getOperand(1);<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h?rev=274827&r1=274826&r2=274827&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h?rev=274827&r1=274826&r2=274827&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h Fri Jul 8 01:14:47 2016<br>
@@ -23,7 +23,7 @@ enum IntrinsicType : uint16_t {<br>
INTR_NO_TYPE,<br>
GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST, ADX, FPCLASS, FPCLASSS,<br>
INTR_TYPE_1OP, INTR_TYPE_2OP, INTR_TYPE_2OP_IMM8, INTR_TYPE_3OP, INTR_TYPE_4OP,<br>
- CMP_MASK, CMP_MASK_CC,CMP_MASK_SCALAR_CC, VSHIFT, VSHIFT_MASK, COMI, COMI_RM,<br>
+ CMP_MASK, CMP_MASK_CC,CMP_MASK_SCALAR_CC, VSHIFT, COMI, COMI_RM,<br>
INTR_TYPE_1OP_MASK, INTR_TYPE_1OP_MASK_RM,<br>
INTR_TYPE_2OP_MASK, INTR_TYPE_2OP_MASK_RM, INTR_TYPE_2OP_IMM8_MASK,<br>
INTR_TYPE_3OP_MASK, INTR_TYPE_3OP_MASK_RM, INTR_TYPE_3OP_IMM8_MASK,<br>
@@ -1278,8 +1278,6 @@ static const IntrinsicData IntrinsicsWi<br>
X86_INTRINSIC_DATA(avx512_mask_psll_wi_128, INTR_TYPE_2OP_IMM8_MASK, X86ISD::VSHLI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psll_wi_256, INTR_TYPE_2OP_IMM8_MASK, X86ISD::VSHLI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psll_wi_512, INTR_TYPE_2OP_IMM8_MASK, X86ISD::VSHLI, 0),<br>
- X86_INTRINSIC_DATA(avx512_mask_pslli_d, VSHIFT_MASK, X86ISD::VSHLI, 0),<br>
- X86_INTRINSIC_DATA(avx512_mask_pslli_q, VSHIFT_MASK, X86ISD::VSHLI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psllv_d, INTR_TYPE_2OP_MASK, ISD::SHL, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psllv_q, INTR_TYPE_2OP_MASK, ISD::SHL, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psllv16_hi, INTR_TYPE_2OP_MASK, ISD::SHL, 0),<br>
@@ -1307,8 +1305,6 @@ static const IntrinsicData IntrinsicsWi<br>
X86_INTRINSIC_DATA(avx512_mask_psra_wi_128, INTR_TYPE_2OP_IMM8_MASK, X86ISD::VSRAI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psra_wi_256, INTR_TYPE_2OP_IMM8_MASK, X86ISD::VSRAI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psra_wi_512, INTR_TYPE_2OP_IMM8_MASK, X86ISD::VSRAI, 0),<br>
- X86_INTRINSIC_DATA(avx512_mask_psrai_d, VSHIFT_MASK, X86ISD::VSRAI, 0),<br>
- X86_INTRINSIC_DATA(avx512_mask_psrai_q, VSHIFT_MASK, X86ISD::VSRAI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psrav_d, INTR_TYPE_2OP_MASK, X86ISD::VSRAV, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psrav_q, INTR_TYPE_2OP_MASK, X86ISD::VSRAV, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psrav_q_128, INTR_TYPE_2OP_MASK, X86ISD::VSRAV, 0),<br>
@@ -1336,8 +1332,6 @@ static const IntrinsicData IntrinsicsWi<br>
X86_INTRINSIC_DATA(avx512_mask_psrl_wi_128, INTR_TYPE_2OP_IMM8_MASK, X86ISD::VSRLI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psrl_wi_256, INTR_TYPE_2OP_IMM8_MASK, X86ISD::VSRLI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psrl_wi_512, INTR_TYPE_2OP_IMM8_MASK, X86ISD::VSRLI, 0),<br>
- X86_INTRINSIC_DATA(avx512_mask_psrli_d, VSHIFT_MASK, X86ISD::VSRLI, 0),<br>
- X86_INTRINSIC_DATA(avx512_mask_psrli_q, VSHIFT_MASK, X86ISD::VSRLI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psrlv_d, INTR_TYPE_2OP_MASK, ISD::SRL, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psrlv_q, INTR_TYPE_2OP_MASK, ISD::SRL, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psrlv16_hi, INTR_TYPE_2OP_MASK, ISD::SRL, 0),<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll?rev=274827&r1=274826&r2=274827&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll?rev=274827&r1=274826&r2=274827&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll Fri Jul 8 01:14:47 2016<br>
@@ -723,3 +723,195 @@ define <16 x i32>@test_int_x86_avx512_ma<br>
ret <16 x i32> %res2<br>
}<br>
<br>
+define <16 x i32> @test_x86_avx512_pslli_d(<16 x i32> %a0) {<br>
+; CHECK-LABEL: test_x86_avx512_pslli_d:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: vpslld $7, %zmm0, %zmm0<br>
+; CHECK-NEXT: retq<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 -1)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+define <16 x i32> @test_x86_avx512_mask_pslli_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {<br>
+; CHECK-LABEL: test_x86_avx512_mask_pslli_d:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: vpslld $7, %zmm0, %zmm1 {%k1}<br>
+; CHECK-NEXT: vmovaps %zmm1, %zmm0<br>
+; CHECK-NEXT: retq<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+define <16 x i32> @test_x86_avx512_maskz_pslli_d(<16 x i32> %a0, i16 %mask) {<br>
+; CHECK-LABEL: test_x86_avx512_maskz_pslli_d:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: vpslld $7, %zmm0, %zmm0 {%k1} {z}<br>
+; CHECK-NEXT: retq<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 %mask)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+declare <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32>, i32, <16 x i32>, i16) nounwind readnone<br>
+<br>
+define <8 x i64> @test_x86_avx512_pslli_q(<8 x i64> %a0) {<br>
+; CHECK-LABEL: test_x86_avx512_pslli_q:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: vpsllq $7, %zmm0, %zmm0<br>
+; CHECK-NEXT: retq<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+define <8 x i64> @test_x86_avx512_mask_pslli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {<br>
+; CHECK-LABEL: test_x86_avx512_mask_pslli_q:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: vpsllq $7, %zmm0, %zmm1 {%k1}<br>
+; CHECK-NEXT: vmovaps %zmm1, %zmm0<br>
+; CHECK-NEXT: retq<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+define <8 x i64> @test_x86_avx512_maskz_pslli_q(<8 x i64> %a0, i8 %mask) {<br>
+; CHECK-LABEL: test_x86_avx512_maskz_pslli_q:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: vpsllq $7, %zmm0, %zmm0 {%k1} {z}<br>
+; CHECK-NEXT: retq<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+declare <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone<br>
+<br>
+define <16 x i32> @test_x86_avx512_psrli_d(<16 x i32> %a0) {<br>
+; CHECK-LABEL: test_x86_avx512_psrli_d:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: vpsrld $7, %zmm0, %zmm0<br>
+; CHECK-NEXT: retq<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 -1)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+define <16 x i32> @test_x86_avx512_mask_psrli_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {<br>
+; CHECK-LABEL: test_x86_avx512_mask_psrli_d:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: vpsrld $7, %zmm0, %zmm1 {%k1}<br>
+; CHECK-NEXT: vmovaps %zmm1, %zmm0<br>
+; CHECK-NEXT: retq<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+define <16 x i32> @test_x86_avx512_maskz_psrli_d(<16 x i32> %a0, i16 %mask) {<br>
+; CHECK-LABEL: test_x86_avx512_maskz_psrli_d:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: vpsrld $7, %zmm0, %zmm0 {%k1} {z}<br>
+; CHECK-NEXT: retq<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 %mask)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+declare <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32>, i32, <16 x i32>, i16) nounwind readnone<br>
+<br>
+define <8 x i64> @test_x86_avx512_psrli_q(<8 x i64> %a0) {<br>
+; CHECK-LABEL: test_x86_avx512_psrli_q:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: vpsrlq $7, %zmm0, %zmm0<br>
+; CHECK-NEXT: retq<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+define <8 x i64> @test_x86_avx512_mask_psrli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {<br>
+; CHECK-LABEL: test_x86_avx512_mask_psrli_q:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: vpsrlq $7, %zmm0, %zmm1 {%k1}<br>
+; CHECK-NEXT: vmovaps %zmm1, %zmm0<br>
+; CHECK-NEXT: retq<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+define <8 x i64> @test_x86_avx512_maskz_psrli_q(<8 x i64> %a0, i8 %mask) {<br>
+; CHECK-LABEL: test_x86_avx512_maskz_psrli_q:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: vpsrlq $7, %zmm0, %zmm0 {%k1} {z}<br>
+; CHECK-NEXT: retq<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+declare <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone<br>
+<br>
+define <16 x i32> @test_x86_avx512_psrai_d(<16 x i32> %a0) {<br>
+; CHECK-LABEL: test_x86_avx512_psrai_d:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: vpsrad $7, %zmm0, %zmm0<br>
+; CHECK-NEXT: retq<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 -1)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+define <16 x i32> @test_x86_avx512_mask_psrai_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {<br>
+; CHECK-LABEL: test_x86_avx512_mask_psrai_d:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: vpsrad $7, %zmm0, %zmm1 {%k1}<br>
+; CHECK-NEXT: vmovaps %zmm1, %zmm0<br>
+; CHECK-NEXT: retq<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+define <16 x i32> @test_x86_avx512_maskz_psrai_d(<16 x i32> %a0, i16 %mask) {<br>
+; CHECK-LABEL: test_x86_avx512_maskz_psrai_d:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: vpsrad $7, %zmm0, %zmm0 {%k1} {z}<br>
+; CHECK-NEXT: retq<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 %mask)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+declare <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32>, i32, <16 x i32>, i16) nounwind readnone<br>
+<br>
+define <8 x i64> @test_x86_avx512_psrai_q(<8 x i64> %a0) {<br>
+; CHECK-LABEL: test_x86_avx512_psrai_q:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: vpsraq $7, %zmm0, %zmm0<br>
+; CHECK-NEXT: retq<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+define <8 x i64> @test_x86_avx512_mask_psrai_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {<br>
+; CHECK-LABEL: test_x86_avx512_mask_psrai_q:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: vpsraq $7, %zmm0, %zmm1 {%k1}<br>
+; CHECK-NEXT: vmovaps %zmm1, %zmm0<br>
+; CHECK-NEXT: retq<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+define <8 x i64> @test_x86_avx512_maskz_psrai_q(<8 x i64> %a0, i8 %mask) {<br>
+; CHECK-LABEL: test_x86_avx512_maskz_psrai_q:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: kmovw %edi, %k1<br>
+; CHECK-NEXT: vpsraq $7, %zmm0, %zmm0 {%k1} {z}<br>
+; CHECK-NEXT: retq<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+declare <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone<br>
+<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=274827&r1=274826&r2=274827&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=274827&r1=274826&r2=274827&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll Fri Jul 8 01:14:47 2016<br>
@@ -1323,198 +1323,6 @@ define <4 x double> @test_vextractf64x4(<br>
<br>
declare <4 x double> @llvm.x86.avx512.mask.vextractf64x4.512(<8 x double>, i32, <4 x double>, i8)<br>
<br>
-define <16 x i32> @test_x86_avx512_pslli_d(<16 x i32> %a0) {<br>
-; CHECK-LABEL: test_x86_avx512_pslli_d:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vpslld $7, %zmm0, %zmm0<br>
-; CHECK-NEXT: retq<br>
- %res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 -1)<br>
- ret <16 x i32> %res<br>
-}<br>
-<br>
-define <16 x i32> @test_x86_avx512_mask_pslli_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {<br>
-; CHECK-LABEL: test_x86_avx512_mask_pslli_d:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: kmovw %edi, %k1<br>
-; CHECK-NEXT: vpslld $7, %zmm0, %zmm1 {%k1}<br>
-; CHECK-NEXT: vmovaps %zmm1, %zmm0<br>
-; CHECK-NEXT: retq<br>
- %res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)<br>
- ret <16 x i32> %res<br>
-}<br>
-<br>
-define <16 x i32> @test_x86_avx512_maskz_pslli_d(<16 x i32> %a0, i16 %mask) {<br>
-; CHECK-LABEL: test_x86_avx512_maskz_pslli_d:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: kmovw %edi, %k1<br>
-; CHECK-NEXT: vpslld $7, %zmm0, %zmm0 {%k1} {z}<br>
-; CHECK-NEXT: retq<br>
- %res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 %mask)<br>
- ret <16 x i32> %res<br>
-}<br>
-<br>
-declare <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32>, i32, <16 x i32>, i16) nounwind readnone<br>
-<br>
-define <8 x i64> @test_x86_avx512_pslli_q(<8 x i64> %a0) {<br>
-; CHECK-LABEL: test_x86_avx512_pslli_q:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vpsllq $7, %zmm0, %zmm0<br>
-; CHECK-NEXT: retq<br>
- %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)<br>
- ret <8 x i64> %res<br>
-}<br>
-<br>
-define <8 x i64> @test_x86_avx512_mask_pslli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {<br>
-; CHECK-LABEL: test_x86_avx512_mask_pslli_q:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: kmovw %edi, %k1<br>
-; CHECK-NEXT: vpsllq $7, %zmm0, %zmm1 {%k1}<br>
-; CHECK-NEXT: vmovaps %zmm1, %zmm0<br>
-; CHECK-NEXT: retq<br>
- %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)<br>
- ret <8 x i64> %res<br>
-}<br>
-<br>
-define <8 x i64> @test_x86_avx512_maskz_pslli_q(<8 x i64> %a0, i8 %mask) {<br>
-; CHECK-LABEL: test_x86_avx512_maskz_pslli_q:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: kmovw %edi, %k1<br>
-; CHECK-NEXT: vpsllq $7, %zmm0, %zmm0 {%k1} {z}<br>
-; CHECK-NEXT: retq<br>
- %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)<br>
- ret <8 x i64> %res<br>
-}<br>
-<br>
-declare <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone<br>
-<br>
-define <16 x i32> @test_x86_avx512_psrli_d(<16 x i32> %a0) {<br>
-; CHECK-LABEL: test_x86_avx512_psrli_d:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vpsrld $7, %zmm0, %zmm0<br>
-; CHECK-NEXT: retq<br>
- %res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 -1)<br>
- ret <16 x i32> %res<br>
-}<br>
-<br>
-define <16 x i32> @test_x86_avx512_mask_psrli_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {<br>
-; CHECK-LABEL: test_x86_avx512_mask_psrli_d:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: kmovw %edi, %k1<br>
-; CHECK-NEXT: vpsrld $7, %zmm0, %zmm1 {%k1}<br>
-; CHECK-NEXT: vmovaps %zmm1, %zmm0<br>
-; CHECK-NEXT: retq<br>
- %res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)<br>
- ret <16 x i32> %res<br>
-}<br>
-<br>
-define <16 x i32> @test_x86_avx512_maskz_psrli_d(<16 x i32> %a0, i16 %mask) {<br>
-; CHECK-LABEL: test_x86_avx512_maskz_psrli_d:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: kmovw %edi, %k1<br>
-; CHECK-NEXT: vpsrld $7, %zmm0, %zmm0 {%k1} {z}<br>
-; CHECK-NEXT: retq<br>
- %res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 %mask)<br>
- ret <16 x i32> %res<br>
-}<br>
-<br>
-declare <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32>, i32, <16 x i32>, i16) nounwind readnone<br>
-<br>
-define <8 x i64> @test_x86_avx512_psrli_q(<8 x i64> %a0) {<br>
-; CHECK-LABEL: test_x86_avx512_psrli_q:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vpsrlq $7, %zmm0, %zmm0<br>
-; CHECK-NEXT: retq<br>
- %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)<br>
- ret <8 x i64> %res<br>
-}<br>
-<br>
-define <8 x i64> @test_x86_avx512_mask_psrli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {<br>
-; CHECK-LABEL: test_x86_avx512_mask_psrli_q:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: kmovw %edi, %k1<br>
-; CHECK-NEXT: vpsrlq $7, %zmm0, %zmm1 {%k1}<br>
-; CHECK-NEXT: vmovaps %zmm1, %zmm0<br>
-; CHECK-NEXT: retq<br>
- %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)<br>
- ret <8 x i64> %res<br>
-}<br>
-<br>
-define <8 x i64> @test_x86_avx512_maskz_psrli_q(<8 x i64> %a0, i8 %mask) {<br>
-; CHECK-LABEL: test_x86_avx512_maskz_psrli_q:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: kmovw %edi, %k1<br>
-; CHECK-NEXT: vpsrlq $7, %zmm0, %zmm0 {%k1} {z}<br>
-; CHECK-NEXT: retq<br>
- %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)<br>
- ret <8 x i64> %res<br>
-}<br>
-<br>
-declare <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone<br>
-<br>
-define <16 x i32> @test_x86_avx512_psrai_d(<16 x i32> %a0) {<br>
-; CHECK-LABEL: test_x86_avx512_psrai_d:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vpsrad $7, %zmm0, %zmm0<br>
-; CHECK-NEXT: retq<br>
- %res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 -1)<br>
- ret <16 x i32> %res<br>
-}<br>
-<br>
-define <16 x i32> @test_x86_avx512_mask_psrai_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {<br>
-; CHECK-LABEL: test_x86_avx512_mask_psrai_d:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: kmovw %edi, %k1<br>
-; CHECK-NEXT: vpsrad $7, %zmm0, %zmm1 {%k1}<br>
-; CHECK-NEXT: vmovaps %zmm1, %zmm0<br>
-; CHECK-NEXT: retq<br>
- %res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)<br>
- ret <16 x i32> %res<br>
-}<br>
-<br>
-define <16 x i32> @test_x86_avx512_maskz_psrai_d(<16 x i32> %a0, i16 %mask) {<br>
-; CHECK-LABEL: test_x86_avx512_maskz_psrai_d:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: kmovw %edi, %k1<br>
-; CHECK-NEXT: vpsrad $7, %zmm0, %zmm0 {%k1} {z}<br>
-; CHECK-NEXT: retq<br>
- %res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 %mask)<br>
- ret <16 x i32> %res<br>
-}<br>
-<br>
-declare <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32>, i32, <16 x i32>, i16) nounwind readnone<br>
-<br>
-define <8 x i64> @test_x86_avx512_psrai_q(<8 x i64> %a0) {<br>
-; CHECK-LABEL: test_x86_avx512_psrai_q:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vpsraq $7, %zmm0, %zmm0<br>
-; CHECK-NEXT: retq<br>
- %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)<br>
- ret <8 x i64> %res<br>
-}<br>
-<br>
-define <8 x i64> @test_x86_avx512_mask_psrai_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {<br>
-; CHECK-LABEL: test_x86_avx512_mask_psrai_q:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: kmovw %edi, %k1<br>
-; CHECK-NEXT: vpsraq $7, %zmm0, %zmm1 {%k1}<br>
-; CHECK-NEXT: vmovaps %zmm1, %zmm0<br>
-; CHECK-NEXT: retq<br>
- %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)<br>
- ret <8 x i64> %res<br>
-}<br>
-<br>
-define <8 x i64> @test_x86_avx512_maskz_psrai_q(<8 x i64> %a0, i8 %mask) {<br>
-; CHECK-LABEL: test_x86_avx512_maskz_psrai_q:<br>
-; CHECK: ## BB#0:<br>
-; CHECK-NEXT: kmovw %edi, %k1<br>
-; CHECK-NEXT: vpsraq $7, %zmm0, %zmm0 {%k1} {z}<br>
-; CHECK-NEXT: retq<br>
- %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)<br>
- ret <8 x i64> %res<br>
-}<br>
-<br>
-declare <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone<br>
-<br>
define <16 x i32> @test_x86_avx512_psll_d(<16 x i32> %a0, <4 x i32> %a1) {<br>
; CHECK-LABEL: test_x86_avx512_psll_d:<br>
; CHECK: ## BB#0:<br>
<br>
<br>
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</blockquote></div><br></div>