<div dir="ltr"><div>Sorry this review comment is a little late... but doesn't LangRef say "If the
value won’t fit in the integer type, the results are undefined."?<br><br></div>-Eli<br><div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Jun 2, 2016 at 3:55 AM, Simon Pilgrim via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rksimon<br>
Date: Thu Jun 2 05:55:21 2016<br>
New Revision: 271510<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=271510&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=271510&view=rev</a><br>
Log:<br>
[X86][SSE] Replace (V)CVTTPS2DQ and VCVTTPD2DQ truncating (round to zero) f32/f64 to i32 with generic IR (llvm)<br>
<br>
This patch removes the llvm intrinsics (V)CVTTPS2DQ and VCVTTPD2DQ truncation (round to zero) conversions and auto-upgrades to FP_TO_SINT calls instead.<br>
<br>
Note: I looked at updating CVTTPD2DQ as well but this still requires a lot more work to correctly lower.<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D20860" rel="noreferrer" target="_blank">http://reviews.llvm.org/D20860</a><br>
<br>
Modified:<br>
llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
llvm/trunk/lib/IR/AutoUpgrade.cpp<br>
llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll<br>
llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll<br>
llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll<br>
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll<br>
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll<br>
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll<br>
<br>
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=271510&r1=271509&r2=271510&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=271510&r1=271509&r2=271510&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)<br>
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Thu Jun 2 05:55:21 2016<br>
@@ -488,8 +488,6 @@ let TargetPrefix = "x86" in { // All in<br>
Intrinsic<[llvm_v4f32_ty], [llvm_v2f64_ty], [IntrNoMem]>;<br>
def int_x86_sse2_cvtps2dq : GCCBuiltin<"__builtin_ia32_cvtps2dq">,<br>
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;<br>
- def int_x86_sse2_cvttps2dq : GCCBuiltin<"__builtin_ia32_cvttps2dq">,<br>
- Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;<br>
def int_x86_sse2_cvtsd2si : GCCBuiltin<"__builtin_ia32_cvtsd2si">,<br>
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;<br>
def int_x86_sse2_cvtsd2si64 : GCCBuiltin<"__builtin_ia32_cvtsd2si64">,<br>
@@ -1725,12 +1723,8 @@ let TargetPrefix = "x86" in { // All in<br>
Intrinsic<[llvm_v4f32_ty], [llvm_v4f64_ty], [IntrNoMem]>;<br>
def int_x86_avx_cvt_ps2dq_256 : GCCBuiltin<"__builtin_ia32_cvtps2dq256">,<br>
Intrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty], [IntrNoMem]>;<br>
- def int_x86_avx_cvtt_pd2dq_256 : GCCBuiltin<"__builtin_ia32_cvttpd2dq256">,<br>
- Intrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty], [IntrNoMem]>;<br>
def int_x86_avx_cvt_pd2dq_256 : GCCBuiltin<"__builtin_ia32_cvtpd2dq256">,<br>
Intrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty], [IntrNoMem]>;<br>
- def int_x86_avx_cvtt_ps2dq_256 : GCCBuiltin<"__builtin_ia32_cvttps2dq256">,<br>
- Intrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty], [IntrNoMem]>;<br>
}<br>
<br>
// Vector bit test<br>
<br>
Modified: llvm/trunk/lib/IR/AutoUpgrade.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=271510&r1=271509&r2=271510&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=271510&r1=271509&r2=271510&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/IR/AutoUpgrade.cpp (original)<br>
+++ llvm/trunk/lib/IR/AutoUpgrade.cpp Thu Jun 2 05:55:21 2016<br>
@@ -185,6 +185,8 @@ static bool UpgradeIntrinsicFunction1(Fu<br>
Name == "x86.sse2.cvtps2pd" ||<br>
Name == "x86.avx.cvtdq2.pd.256" ||<br>
Name == "x86.avx.cvt.ps2.pd.256" ||<br>
+ Name == "x86.sse2.cvttps2dq" ||<br>
+ Name.startswith("x86.avx.cvtt.") ||<br>
Name.startswith("x86.avx.vinsertf128.") ||<br>
Name == "x86.avx2.vinserti128" ||<br>
Name.startswith("x86.avx.vextractf128.") ||<br>
@@ -498,6 +500,12 @@ void llvm::UpgradeIntrinsicCall(CallInst<br>
Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd");<br>
else<br>
Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd");<br>
+ } else if (Name == "llvm.x86.sse2.cvttps2dq" ||<br>
+ Name.startswith("llvm.x86.avx.cvtt.")) {<br>
+ // Truncation (round to zero) float/double to i32 vector conversion.<br>
+ Value *Src = CI->getArgOperand(0);<br>
+ VectorType *DstTy = cast<VectorType>(CI->getType());<br>
+ Rep = Builder.CreateFPToSI(Src, DstTy, "cvtt");<br>
} else if (Name.startswith("llvm.x86.avx.movnt.")) {<br>
Module *M = F->getParent();<br>
SmallVector<Metadata *, 1> Elts;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=271510&r1=271509&r2=271510&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=271510&r1=271509&r2=271510&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Jun 2 05:55:21 2016<br>
@@ -2013,35 +2013,24 @@ def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (<br>
// SSE2 packed instructions with XS prefix<br>
def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),<br>
"cvttps2dq\t{$src, $dst|$dst, $src}",<br>
- [(set VR128:$dst,<br>
- (int_x86_sse2_cvttps2dq VR128:$src))],<br>
- IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;<br>
+ [], IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;<br>
def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),<br>
"cvttps2dq\t{$src, $dst|$dst, $src}",<br>
- [(set VR128:$dst, (int_x86_sse2_cvttps2dq<br>
- (loadv4f32 addr:$src)))],<br>
- IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;<br>
+ [], IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;<br>
def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),<br>
"cvttps2dq\t{$src, $dst|$dst, $src}",<br>
- [(set VR256:$dst,<br>
- (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],<br>
- IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;<br>
+ [], IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;<br>
def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),<br>
"cvttps2dq\t{$src, $dst|$dst, $src}",<br>
- [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256<br>
- (loadv8f32 addr:$src)))],<br>
- IIC_SSE_CVT_PS_RM>, VEX, VEX_L,<br>
+ [], IIC_SSE_CVT_PS_RM>, VEX, VEX_L,<br>
Sched<[WriteCvtF2ILd]>;<br>
<br>
def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),<br>
"cvttps2dq\t{$src, $dst|$dst, $src}",<br>
- [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],<br>
- IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;<br>
+ [], IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;<br>
def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),<br>
"cvttps2dq\t{$src, $dst|$dst, $src}",<br>
- [(set VR128:$dst,<br>
- (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],<br>
- IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;<br>
+ [], IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;<br>
<br>
let Predicates = [HasAVX] in {<br>
def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),<br>
@@ -2111,14 +2100,10 @@ def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem<br>
// YMM only<br>
def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),<br>
"cvttpd2dq{y}\t{$src, $dst|$dst, $src}",<br>
- [(set VR128:$dst,<br>
- (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],<br>
- IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;<br>
+ [], IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;<br>
def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),<br>
"cvttpd2dq{y}\t{$src, $dst|$dst, $src}",<br>
- [(set VR128:$dst,<br>
- (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],<br>
- IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;<br>
+ [], IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;<br>
def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",<br>
(VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll?rev=271510&r1=271509&r2=271510&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll?rev=271510&r1=271509&r2=271510&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll Thu Jun 2 05:55:21 2016<br>
@@ -675,11 +675,10 @@ define <2 x i64> @test_mm256_cvttpd_epi3<br>
; X64-NEXT: vcvttpd2dqy %ymm0, %xmm0<br>
; X64-NEXT: vzeroupper<br>
; X64-NEXT: retq<br>
- %cvt = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0)<br>
+ %cvt = fptosi <4 x double> %a0 to <4 x i32><br>
%res = bitcast <4 x i32> %cvt to <2 x i64><br>
ret <2 x i64> %res<br>
}<br>
-declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind readnone<br>
<br>
define <4 x i64> @test_mm256_cvttps_epi32(<8 x float> %a0) nounwind {<br>
; X32-LABEL: test_mm256_cvttps_epi32:<br>
@@ -691,11 +690,10 @@ define <4 x i64> @test_mm256_cvttps_epi3<br>
; X64: # BB#0:<br>
; X64-NEXT: vcvttps2dq %ymm0, %ymm0<br>
; X64-NEXT: retq<br>
- %cvt = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0)<br>
+ %cvt = fptosi <8 x float> %a0 to <8 x i32><br>
%res = bitcast <8 x i32> %cvt to <4 x i64><br>
ret <4 x i64> %res<br>
}<br>
-declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind readnone<br>
<br>
define <4 x double> @test_mm256_div_pd(<4 x double> %a0, <4 x double> %a1) nounwind {<br>
; X32-LABEL: test_mm256_div_pd:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll?rev=271510&r1=271509&r2=271510&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll?rev=271510&r1=271509&r2=271510&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll Thu Jun 2 05:55:21 2016<br>
@@ -357,12 +357,35 @@ define <4 x double> @test_x86_avx_cvt_ps<br>
declare <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float>) nounwind readnone<br>
<br>
<br>
+define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) {<br>
+; CHECK-LABEL: test_x86_avx_cvtt_pd2dq_256:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: vcvttpd2dqy %ymm0, %xmm0<br>
+; CHECK-NEXT: vzeroupper<br>
+; CHECK-NEXT: retl<br>
+ %res = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1]<br>
+ ret <4 x i32> %res<br>
+}<br>
+declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind readnone<br>
+<br>
+<br>
+define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) {<br>
+; CHECK-LABEL: test_x86_avx_cvtt_ps2dq_256:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0<br>
+; CHECK-NEXT: retl<br>
+ %res = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1]<br>
+ ret <8 x i32> %res<br>
+}<br>
+declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind readnone<br>
+<br>
+<br>
define void @test_x86_sse2_storeu_dq(i8* %a0, <16 x i8> %a1) {<br>
; add operation forces the execution domain.<br>
; CHECK-LABEL: test_x86_sse2_storeu_dq:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
-; CHECK-NEXT: vpaddb LCPI32_0, %xmm0, %xmm0<br>
+; CHECK-NEXT: vpaddb LCPI34_0, %xmm0, %xmm0<br>
; CHECK-NEXT: vmovdqu %xmm0, (%eax)<br>
; CHECK-NEXT: retl<br>
%a2 = add <16 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1><br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=271510&r1=271509&r2=271510&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=271510&r1=271509&r2=271510&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Thu Jun 2 05:55:21 2016<br>
@@ -3407,39 +3407,6 @@ define <8 x float> @test_x86_avx_cvtdq2_<br>
declare <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32>) nounwind readnone<br>
<br>
<br>
-define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) {<br>
-; AVX-LABEL: test_x86_avx_cvtt_pd2dq_256:<br>
-; AVX: ## BB#0:<br>
-; AVX-NEXT: vcvttpd2dqy %ymm0, %xmm0<br>
-; AVX-NEXT: vzeroupper<br>
-; AVX-NEXT: retl<br>
-;<br>
-; AVX512VL-LABEL: test_x86_avx_cvtt_pd2dq_256:<br>
-; AVX512VL: ## BB#0:<br>
-; AVX512VL-NEXT: vcvttpd2dqy %ymm0, %xmm0<br>
-; AVX512VL-NEXT: retl<br>
- %res = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1]<br>
- ret <4 x i32> %res<br>
-}<br>
-declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind readnone<br>
-<br>
-<br>
-define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) {<br>
-; AVX-LABEL: test_x86_avx_cvtt_ps2dq_256:<br>
-; AVX: ## BB#0:<br>
-; AVX-NEXT: vcvttps2dq %ymm0, %ymm0<br>
-; AVX-NEXT: retl<br>
-;<br>
-; AVX512VL-LABEL: test_x86_avx_cvtt_ps2dq_256:<br>
-; AVX512VL: ## BB#0:<br>
-; AVX512VL-NEXT: vcvttps2dq %ymm0, %ymm0<br>
-; AVX512VL-NEXT: retl<br>
- %res = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1]<br>
- ret <8 x i32> %res<br>
-}<br>
-declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind readnone<br>
-<br>
-<br>
define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) {<br>
; AVX-LABEL: test_x86_avx_dp_ps_256:<br>
; AVX: ## BB#0:<br>
@@ -4133,7 +4100,7 @@ define <4 x double> @test_x86_avx_vpermi<br>
;<br>
; AVX512VL-LABEL: test_x86_avx_vpermilvar_pd_256_2:<br>
; AVX512VL: ## BB#0:<br>
-; AVX512VL-NEXT: vpermilpd LCPI233_0, %ymm0, %ymm0<br>
+; AVX512VL-NEXT: vpermilpd LCPI231_0, %ymm0, %ymm0<br>
; AVX512VL-NEXT: retl<br>
%res = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 2, i64 0, i64 0, i64 2>) ; <<4 x double>> [#uses=1]<br>
ret <4 x double> %res<br>
@@ -4625,7 +4592,7 @@ define void @movnt_dq(i8* %p, <2 x i64><br>
; AVX-LABEL: movnt_dq:<br>
; AVX: ## BB#0:<br>
; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
-; AVX-NEXT: vpaddq LCPI260_0, %xmm0, %xmm0<br>
+; AVX-NEXT: vpaddq LCPI258_0, %xmm0, %xmm0<br>
; AVX-NEXT: vmovntdq %ymm0, (%eax)<br>
; AVX-NEXT: vzeroupper<br>
; AVX-NEXT: retl<br>
@@ -4633,7 +4600,7 @@ define void @movnt_dq(i8* %p, <2 x i64><br>
; AVX512VL-LABEL: movnt_dq:<br>
; AVX512VL: ## BB#0:<br>
; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
-; AVX512VL-NEXT: vpaddq LCPI260_0, %xmm0, %xmm0<br>
+; AVX512VL-NEXT: vpaddq LCPI258_0, %xmm0, %xmm0<br>
; AVX512VL-NEXT: vmovntdq %ymm0, (%eax)<br>
; AVX512VL-NEXT: retl<br>
%a2 = add <2 x i64> %a1, <i64 1, i64 1><br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll?rev=271510&r1=271509&r2=271510&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll?rev=271510&r1=271509&r2=271510&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll Thu Jun 2 05:55:21 2016<br>
@@ -1280,11 +1280,10 @@ define <2 x i64> @test_mm_cvttps_epi32(<<br>
; X64: # BB#0:<br>
; X64-NEXT: cvttps2dq %xmm0, %xmm0<br>
; X64-NEXT: retq<br>
- %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0)<br>
+ %res = fptosi <4 x float> %a0 to <4 x i32><br>
%bc = bitcast <4 x i32> %res to <2 x i64><br>
ret <2 x i64> %bc<br>
}<br>
-declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone<br>
<br>
define i32 @test_mm_cvttsd_si32(<2 x double> %a0) nounwind {<br>
; X32-LABEL: test_mm_cvttsd_si32:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll?rev=271510&r1=271509&r2=271510&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll?rev=271510&r1=271509&r2=271510&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll Thu Jun 2 05:55:21 2016<br>
@@ -84,6 +84,17 @@ define <2 x double> @test_x86_sse2_cvtps<br>
declare <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float>) nounwind readnone<br>
<br>
<br>
+define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) {<br>
+; CHECK-LABEL: test_x86_sse2_cvttps2dq:<br>
+; CHECK: ## BB#0:<br>
+; CHECK-NEXT: cvttps2dq %xmm0, %xmm0<br>
+; CHECK-NEXT: retl<br>
+ %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]<br>
+ ret <4 x i32> %res<br>
+}<br>
+declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone<br>
+<br>
+<br>
define void @test_x86_sse2_storel_dq(i8* %a0, <4 x i32> %a1) {<br>
; CHECK-LABEL: test_x86_sse2_storel_dq:<br>
; CHECK: ## BB#0:<br>
@@ -101,7 +112,7 @@ define void @test_x86_sse2_storeu_dq(i8*<br>
; CHECK-LABEL: test_x86_sse2_storeu_dq:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
-; CHECK-NEXT: paddb LCPI7_0, %xmm0<br>
+; CHECK-NEXT: paddb LCPI8_0, %xmm0<br>
; CHECK-NEXT: movdqu %xmm0, (%eax)<br>
; CHECK-NEXT: retl<br>
%a2 = add <16 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1><br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=271510&r1=271509&r2=271510&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=271510&r1=271509&r2=271510&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll Thu Jun 2 05:55:21 2016<br>
@@ -322,22 +322,6 @@ define <4 x i32> @test_x86_sse2_cvttpd2d<br>
declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>) nounwind readnone<br>
<br>
<br>
-define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) {<br>
-; SSE-LABEL: test_x86_sse2_cvttps2dq:<br>
-; SSE: ## BB#0:<br>
-; SSE-NEXT: cvttps2dq %xmm0, %xmm0<br>
-; SSE-NEXT: retl<br>
-;<br>
-; KNL-LABEL: test_x86_sse2_cvttps2dq:<br>
-; KNL: ## BB#0:<br>
-; KNL-NEXT: vcvttps2dq %xmm0, %xmm0<br>
-; KNL-NEXT: retl<br>
- %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]<br>
- ret <4 x i32> %res<br>
-}<br>
-declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone<br>
-<br>
-<br>
define i32 @test_x86_sse2_cvttsd2si(<2 x double> %a0) {<br>
; SSE-LABEL: test_x86_sse2_cvttsd2si:<br>
; SSE: ## BB#0:<br>
<br>
<br>
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</blockquote></div><br></div></div></div>