<div dir="ltr">The bot is still failing, not sure if it is caused by your change.<div><a href="http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-globalisel_check/2618/">http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-globalisel_check/2618/</a></div><div><br></div><div>Can you take a look?</div><div><br></div><div>Thanks,</div><div>Manman</div><div><br><div><span style="color:rgb(51,51,51);font-family:monospace;font-size:13px;white-space:pre-wrap">FAIL: LLVM :: CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll (13900 of 34098)
</span><a id="7995210528254eaf0-7326-4999-85b0-388101f2d404" style="word-wrap:break-word;color:rgb(51,51,51);font-family:monospace;font-size:13px;white-space:pre-wrap;display:block"></a><span title="Regression test failed" style="font-family:monospace;font-size:13px;white-space:pre-wrap;color:white;background-color:red">******************** TEST 'LLVM :: CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll' FAILED ********************
</span><span style="color:rgb(51,51,51);font-family:monospace;font-size:13px;white-space:pre-wrap">Script:
--
/Users/buildslave/jenkins/sharedspace/clang-stage1-cmake-RA_workspace/clang-build/./bin/llc -march=amdgcn -mcpu=fiji -O0 -stop-after=irtranslator -global-isel /Users/buildslave/jenkins/sharedspace/clang-stage1-cmake-RA_workspace/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll -o - 2>&1 | /Users/buildslave/jenkins/sharedspace/clang-stage1-cmake-RA_workspace/clang-build/./bin/FileCheck /Users/buildslave/jenkins/sharedspace/clang-stage1-cmake-RA_workspace/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
--
Exit Code: 1
Command Output (stderr):
--
</span><a id="59070779949ba4694-19c4-4d7e-bec5-911270d8a58c" style="word-wrap:break-word;color:rgb(51,51,51);font-family:monospace;font-size:13px;white-space:pre-wrap;display:block"></a><span title="Compile Error" style="font-family:monospace;font-size:13px;white-space:pre-wrap;color:white;background-color:red">/Users/buildslave/jenkins/sharedspace/clang-stage1-cmake-RA_workspace/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll:7:10: error: expected string not found in input
</span><span style="color:rgb(51,51,51);font-family:monospace;font-size:13px;white-space:pre-wrap">; CHECK: name: addi32
^
<stdin>:1:1: note: scanning from here
Stack dump:
^
<stdin>:4:40: note: possible intended match here
2. Running pass 'IRTranslator' on function '@addi32'</span><br></div><div><br></div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jun 27, 2016 at 5:18 PM, Matt Arsenault via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="HOEnZb"><div class="h5">On 06/27/2016 04:28 PM, Manman Ren wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Seems to break a bot: <a href="http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-globalisel_build/2648/" rel="noreferrer" target="_blank">http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-globalisel_build/2648/</a><br>
<br>
FAILED: /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/c++ -DGTEST_HAS_RTTI=0 -DLLVM_BUILD_GLOBAL_ISEL -D_DEBUG -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Ilib/Target/AMDGPU -I/Users/buildslave/jenkins/sharedspace/clang-stage1-cmake-RA_workspace/llvm/lib/Target/AMDGPU -Iinclude -I/Users/buildslave/jenkins/sharedspace/clang-stage1-cmake-RA_workspace/llvm/include -fPIC -fvisibility-inlines-hidden -Wall -W -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wcovered-switch-default -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Werror=date-time -std=c++11 -fcolor-diagnostics -O3 -UNDEBUG -fno-exceptions -fno-rtti -MMD -MT lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o -MF lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o.d -o lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o -c /Users/buildslave/jenkins/sharedspace/clang-stage1-cmake-RA_workspace/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp<br>
<br>
/Users/buildslave/jenkins/sharedspace/clang-stage1-cmake-RA_workspace/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp:222:5: error: unknown type name 'SIGISelActualAccessor'<br>
<br>
SIGISelActualAccessor *GISel = new SIGISelActualAccessor();<br>
^<br>
/Users/buildslave/jenkins/sharedspace/clang-stage1-cmake-RA_workspace/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp:222:40: error: unknown type name 'SIGISelActualAccessor'<br>
SIGISelActualAccessor *GISel = new SIGISelActualAccessor();<br>
^<br>
2 errors generated.<br>
<br>
Can you take a look?<br>
<br>
Thanks,<br>
Manman<br>
<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
On Jun 27, 2016, at 1:32 PM, Matt Arsenault via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br>
<br>
Author: arsenm<br>
Date: Mon Jun 27 15:32:13 2016<br>
New Revision: 273937<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=273937&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=273937&view=rev</a><br>
Log:<br>
AMDGPU: Move subtarget feature checks into passes<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPU.td<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp<br>
llvm/trunk/test/CodeGen/AMDGPU/captured-frame-index.ll<br>
llvm/trunk/test/CodeGen/AMDGPU/cgp-addressing-modes.ll<br>
llvm/trunk/test/CodeGen/AMDGPU/extload-private.ll<br>
llvm/trunk/test/CodeGen/AMDGPU/parallelandifcollapse.ll<br>
llvm/trunk/test/CodeGen/AMDGPU/structurize1.ll<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPU.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPU.td?rev=273937&r1=273936&r2=273937&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPU.td?rev=273937&r1=273936&r2=273937&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPU.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.td Mon Jun 27 15:32:13 2016<br>
@@ -241,12 +241,6 @@ def FeatureEnableUnsafeDSOffsetFolding :<br>
"Force using DS instruction immediate offsets on SI"<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
;<br>
</blockquote>
-def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",<br>
- "EnableIfCvt",<br>
- "false",<br>
- "Disable the if conversion pass"<br>
->;<br>
-<br>
def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",<br>
"EnableSIScheduler",<br>
"true",<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp?rev=273937&r1=273936&r2=273937&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp?rev=273937&r1=273936&r2=273937&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp Mon Jun 27 15:32:13 2016<br>
@@ -124,6 +124,10 @@ bool AMDGPUPromoteAlloca::runOnFunction(<br>
if (!TM || skipFunction(F))<br>
return false;<br>
<br>
+ const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(F);<br>
+ if (!ST.isPromoteAllocaEnabled())<br>
+ return false;<br>
+<br>
FunctionType *FTy = F.getFunctionType();<br>
<br>
// If the function has any arguments in the local address space, then it's<br>
@@ -139,8 +143,6 @@ bool AMDGPUPromoteAlloca::runOnFunction(<br>
}<br>
}<br>
<br>
- const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(F);<br>
-<br>
LocalMemLimit = ST.getLocalMemorySize();<br>
if (LocalMemLimit == 0)<br>
return false;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=273937&r1=273936&r2=273937&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=273937&r1=273936&r2=273937&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Mon Jun 27 15:32:13 2016<br>
@@ -105,7 +105,6 @@ AMDGPUSubtarget::AMDGPUSubtarget(const T<br>
<br>
EnableVGPRSpilling(false),<br>
EnablePromoteAlloca(false),<br>
- EnableIfCvt(true),<br>
EnableLoadStoreOpt(false),<br>
EnableUnsafeDSOffsetFolding(false),<br>
EnableSIScheduler(false),<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=273937&r1=273936&r2=273937&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=273937&r1=273936&r2=273937&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h Mon Jun 27 15:32:13 2016<br>
@@ -82,7 +82,6 @@ protected:<br>
// Used as options.<br>
bool EnableVGPRSpilling;<br>
bool EnablePromoteAlloca;<br>
- bool EnableIfCvt;<br>
bool EnableLoadStoreOpt;<br>
bool EnableUnsafeDSOffsetFolding;<br>
bool EnableSIScheduler;<br>
@@ -222,10 +221,6 @@ public:<br>
return EnablePromoteAlloca;<br>
}<br>
<br>
- bool isIfCvtEnabled() const {<br>
- return EnableIfCvt;<br>
- }<br>
-<br>
bool unsafeDSOffsetFoldingEnabled() const {<br>
return EnableUnsafeDSOffsetFolding;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=273937&r1=273936&r2=273937&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=273937&r1=273936&r2=273937&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Mon Jun 27 15:32:13 2016<br>
@@ -45,6 +45,18 @@ static cl::opt<bool> EnableR600Structuri<br>
cl::desc("Use StructurizeCFG IR pass"),<br>
cl::init(true));<br>
<br>
+static cl::opt<bool> EnableSROA(<br>
+ "amdgpu-sroa",<br>
+ cl::desc("Run SROA after promote alloca pass"),<br>
+ cl::ReallyHidden,<br>
+ cl::init(true));<br>
+<br>
+static cl::opt<bool> EnableR600IfConvert(<br>
+ "r600-if-convert",<br>
+ cl::desc("Use if conversion pass"),<br>
+ cl::ReallyHidden,<br>
+ cl::init(true));<br>
+<br>
extern "C" void LLVMInitializeAMDGPUTarget() {<br>
// Register the target<br>
RegisterTargetMachine<R600TargetMachine> X(TheAMDGPUTarget);<br>
@@ -212,12 +224,7 @@ public:<br>
}<br>
<br>
ScheduleDAGInstrs *<br>
- createMachineScheduler(MachineSchedContext *C) const override {<br>
- const SISubtarget *ST = getGCNTargetMachine().getSubtargetImpl();<br>
- if (ST->enableSIScheduler())<br>
- return createSIMachineScheduler(C);<br>
- return nullptr;<br>
- }<br>
+ createMachineScheduler(MachineSchedContext *C) const override;<br>
<br>
bool addPreISel() override;<br>
void addMachineSSAOptimization() override;<br>
@@ -285,10 +292,11 @@ void AMDGPUPassConfig::addIRPasses() {<br>
addPass(createAMDGPUOpenCLImageTypeLoweringPass());<br>
<br>
const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();<br>
- const AMDGPUSubtarget &ST = *TM.getSubtargetImpl();<br>
- if (TM.getOptLevel() > CodeGenOpt::None && ST.isPromoteAllocaEnabled()) {<br>
+ if (TM.getOptLevel() > CodeGenOpt::None) {<br>
addPass(createAMDGPUPromoteAlloca(&TM));<br>
- addPass(createSROAPass());<br>
+<br>
+ if (EnableSROA)<br>
+ addPass(createSROAPass());<br>
}<br>
<br>
addStraightLineScalarOptimizationPasses();<br>
@@ -344,9 +352,8 @@ void R600PassConfig::addPreRegAlloc() {<br>
}<br>
<br>
void R600PassConfig::addPreSched2() {<br>
- const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();<br>
addPass(createR600EmitClauseMarkers(), false);<br>
- if (ST.isIfCvtEnabled())<br>
+ if (EnableR600IfConvert)<br>
addPass(&IfConverterID, false);<br>
addPass(createR600ClauseMergePass(*TM), false);<br>
}<br>
@@ -367,6 +374,14 @@ TargetPassConfig *R600TargetMachine::cre<br>
// GCN Pass Setup<br>
//===----------------------------------------------------------------------===//<br>
<br>
+ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(<br>
+ MachineSchedContext *C) const {<br>
+ const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();<br>
+ if (ST.enableSIScheduler())<br>
+ return createSIMachineScheduler(C);<br>
+ return nullptr;<br>
+}<br>
+<br>
bool GCNPassConfig::addPreISel() {<br>
AMDGPUPassConfig::addPreISel();<br>
<br>
@@ -415,8 +430,6 @@ bool GCNPassConfig::addRegBankSelect() {<br>
#endif<br>
<br>
void GCNPassConfig::addPreRegAlloc() {<br>
- const SISubtarget &ST = *getGCNTargetMachine().getSubtargetImpl();<br>
-<br>
// This needs to be run directly before register allocation because<br>
// earlier passes might recompute live intervals.<br>
// TODO: handle CodeGenOpt::None; fast RA ignores spill weights set by the pass<br>
@@ -424,15 +437,18 @@ void GCNPassConfig::addPreRegAlloc() {<br>
insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);<br>
}<br>
<br>
- if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {<br>
+ if (getOptLevel() > CodeGenOpt::None) {<br>
// Don't do this with no optimizations since it throws away debug info by<br>
// merging nonadjacent loads.<br>
<br>
// This should be run after scheduling, but before register allocation. It<br>
// also need extra copies to the address operand to be eliminated.<br>
+<br>
+ // FIXME: Move pre-RA and remove extra reg coalescer run.<br>
insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);<br>
insertPass(&MachineSchedulerID, &RegisterCoalescerID);<br>
}<br>
+<br>
addPass(createSIShrinkInstructionsPass());<br>
addPass(createSIWholeQuadModePass());<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp?rev=273937&r1=273936&r2=273937&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp?rev=273937&r1=273936&r2=273937&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp Mon Jun 27 15:32:13 2016<br>
@@ -412,6 +412,9 @@ bool SILoadStoreOptimizer::runOnMachineF<br>
return false;<br>
<br>
const SISubtarget &STM = MF.getSubtarget<SISubtarget>();<br>
+ if (!STM.loadStoreOptEnabled())<br>
+ return false;<br>
+<br>
TII = STM.getInstrInfo();<br>
TRI = &TII->getRegisterInfo();<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/captured-frame-index.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/captured-frame-index.ll?rev=273937&r1=273936&r2=273937&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/captured-frame-index.ll?rev=273937&r1=273936&r2=273937&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/captured-frame-index.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/captured-frame-index.ll Mon Jun 27 15:32:13 2016<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc -march=amdgcn -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s<br>
+; RUN: llc -march=amdgcn -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s<br>
<br>
; GCN-LABEL: {{^}}stored_fi_to_lds:<br>
; GCN: s_load_dword [[LDSPTR:s[0-9]+]]<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/cgp-addressing-modes.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/cgp-addressing-modes.ll?rev=273937&r1=273936&r2=273937&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/cgp-addressing-modes.ll?rev=273937&r1=273936&r2=273937&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/cgp-addressing-modes.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/cgp-addressing-modes.ll Mon Jun 27 15:32:13 2016<br>
@@ -1,9 +1,9 @@<br>
; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tahiti < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-SI %s<br>
; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI %s<br>
; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tonga < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI %s<br>
-; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s<br>
-; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s<br>
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s<br>
+; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s<br>
+; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s<br>
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s<br>
<br>
; OPT-LABEL: @test_sink_global_small_offset_i32(<br>
; OPT-CI-NOT: getelementptr i32, i32 addrspace(1)* %in<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/extload-private.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/extload-private.ll?rev=273937&r1=273936&r2=273937&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/extload-private.ll?rev=273937&r1=273936&r2=273937&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/extload-private.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/extload-private.ll Mon Jun 27 15:32:13 2016<br>
@@ -1,5 +1,5 @@<br>
-; RUN: llc < %s -march=amdgcn -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s<br>
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s<br>
+; RUN: llc -march=amdgcn -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s<br>
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s<br>
<br>
; FUNC-LABEL: {{^}}load_i8_sext_private:<br>
; SI: buffer_load_sbyte v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen<br>
@@ -39,7 +39,7 @@ entry:<br>
define void @load_i16_zext_private(i32 addrspace(1)* %out) {<br>
entry:<br>
%tmp0 = alloca i16<br>
- %tmp1 = load i16, i16* %tmp0<br>
+ %tmp1 = load volatile i16, i16* %tmp0<br>
%tmp2 = zext i16 %tmp1 to i32<br>
store i32 %tmp2, i32 addrspace(1)* %out<br>
ret void<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/parallelandifcollapse.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/parallelandifcollapse.ll?rev=273937&r1=273936&r2=273937&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/parallelandifcollapse.ll?rev=273937&r1=273936&r2=273937&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/parallelandifcollapse.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/parallelandifcollapse.ll Mon Jun 27 15:32:13 2016<br>
@@ -1,5 +1,4 @@<br>
-; Function Attrs: nounwind<br>
-; RUN: llc -march=r600 -mcpu=redwood -mattr=-promote-alloca < %s | FileCheck %s<br>
+; RUN: llc -march=r600 -mcpu=redwood -mattr=-promote-alloca -amdgpu-sroa=0 < %s | FileCheck %s<br>
;<br>
; CFG flattening should use parallel-and mode to generate branch conditions and<br>
; then merge if-regions with the same bodies.<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/structurize1.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/structurize1.ll?rev=273937&r1=273936&r2=273937&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/structurize1.ll?rev=273937&r1=273936&r2=273937&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/structurize1.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/structurize1.ll Mon Jun 27 15:32:13 2016<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc < %s -march=r600 -mattr=disable-ifcvt -mcpu=redwood | FileCheck %s<br>
+; RUN: llc -march=r600 -mcpu=redwood -r600-if-convert=0 < %s | FileCheck %s<br>
<br>
; This tests for abug where the AMDILCFGStructurizer was crashing on loops<br>
; like this:<br>
<br>
<br>
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</blockquote></blockquote></div></div>
Fixed by r273964<div class="HOEnZb"><div class="h5"><br>
<br>
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