<div dir="ltr">Should be fixed in r273242. I'm sorry about the breakage.</div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jun 21, 2016 at 2:06 PM, Rui Ueyama <span dir="ltr"><<a href="mailto:ruiu@google.com" target="_blank">ruiu@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">On it.</div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jun 21, 2016 at 1:55 PM, Sean Silva <span dir="ltr"><<a href="mailto:chisophugis@gmail.com" target="_blank">chisophugis@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">I think this broke the bots: <a href="http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/15038/steps/build/logs/stdio" target="_blank">http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/15038/steps/build/logs/stdio</a><div><br></div><div><br></div></div><div><div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jun 20, 2016 at 8:42 PM, Rui Ueyama via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ruiu<br>
Date: Mon Jun 20 22:42:32 2016<br>
New Revision: 273238<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=273238&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=273238&view=rev</a><br>
Log:<br>
Refactor X86_64TargetInfo::relaxTlsIeToLe.<br>
<br>
This patch is to rewrite the function with a table-lookup-ish approach<br>
so that it can read as a series of "convert this pattern to this" pattern.<br>
<br>
Modified:<br>
lld/trunk/ELF/Target.cpp<br>
lld/trunk/test/ELF/tls-opt.s<br>
<br>
Modified: lld/trunk/ELF/Target.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/lld/trunk/ELF/Target.cpp?rev=273238&r1=273237&r2=273238&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/lld/trunk/ELF/Target.cpp?rev=273238&r1=273237&r2=273238&view=diff</a><br>
==============================================================================<br>
--- lld/trunk/ELF/Target.cpp (original)<br>
+++ lld/trunk/ELF/Target.cpp Mon Jun 20 22:42:32 2016<br>
@@ -677,34 +677,40 @@ void X86_64TargetInfo::relaxTlsGdToIe(ui<br>
// R_X86_64_TPOFF32 so that it does not use GOT.<br>
void X86_64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,<br>
uint64_t Val) const {<br>
- // Ulrich's document section 6.5 says that @gottpoff(%rip) must be<br>
- // used in MOVQ or ADDQ instructions only.<br>
- // "MOVQ foo@GOTTPOFF(%RIP), %REG" is transformed to "MOVQ $foo, %REG".<br>
- // "ADDQ foo@GOTTPOFF(%RIP), %REG" is transformed to "LEAQ foo(%REG), %REG"<br>
- // (if the register is not RSP/R12) or "ADDQ $foo, %RSP".<br>
- // Opcodes info can be found at <a href="http://ref.x86asm.net/coder64.html#x48" rel="noreferrer" target="_blank">http://ref.x86asm.net/coder64.html#x48</a>.<br>
- uint8_t *Prefix = Loc - 3;<br>
- uint8_t *Inst = Loc - 2;<br>
- uint8_t *RegSlot = Loc - 1;<br>
+ uint8_t *Inst = Loc - 3;<br>
uint8_t Reg = Loc[-1] >> 3;<br>
- bool IsMov = *Inst == 0x8b;<br>
- bool RspAdd = !IsMov && Reg == 4;<br>
+ uint8_t RegSlot = Loc - 1;<br>
<br>
- // r12 and rsp registers requires special handling.<br>
- // Problem is that for other registers, for example leaq 0xXXXXXXXX(%r11),%r11<br>
- // result out is 7 bytes: 4d 8d 9b XX XX XX XX,<br>
- // but leaq 0xXXXXXXXX(%r12),%r12 is 8 bytes: 4d 8d a4 24 XX XX XX XX.<br>
- // The same true for rsp. So we convert to addq for them, saving 1 byte that<br>
- // we dont have.<br>
- if (RspAdd)<br>
- *Inst = 0x81;<br>
- else<br>
- *Inst = IsMov ? 0xc7 : 0x8d;<br>
- if (*Prefix == 0x4c)<br>
- *Prefix = (IsMov || RspAdd) ? 0x49 : 0x4d;<br>
- *RegSlot = (IsMov || RspAdd) ? (0xc0 | Reg) : (0x80 | Reg | (Reg << 3));<br>
- // The original code used a pc relative relocation and so we have to<br>
- // compensate for the -4 in had in the addend.<br>
+ // Note that LEA with RSP or R12 is converted to ADD instead of LEA<br>
+ // because LEA with these registers needs 4 bytes to encode and thus<br>
+ // wouldn't fit the space.<br>
+<br>
+ if (memcmp(Inst, "\x48\x03\x25", 3) == 0) {<br>
+ // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp"<br>
+ memcpy(Inst, "\x48\x81\xc4", 3);<br>
+ } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) {<br>
+ // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12"<br>
+ memcpy(Inst, "\x49\x81\xc4", 3);<br>
+ } else if (memcmp(Inst, "\x4c\x03", 2) == 0) {<br>
+ // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]"<br>
+ memcpy(Inst, "\x4d\x8d", 2);<br>
+ *RegSlot = 0x80 | (Reg << 3) | Reg;<br>
+ } else if (memcmp(Inst, "\x48\x03", 2) == 0) {<br>
+ // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg"<br>
+ memcpy(Inst, "\x48\x8d", 2);<br>
+ *RegSlot = 0x80 | (Reg << 3) | Reg;<br>
+ } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) {<br>
+ // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]"<br>
+ memcpy(Inst, "\x49\xc7", 2);<br>
+ *RegSlot = 0xc0 | Reg;<br>
+ } else if (memcmp(Inst, "\x48\x8b", 2) == 0) {<br>
+ // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg"<br>
+ memcpy(Inst, "\x48\xc7", 2);<br>
+ *RegSlot = 0xc0 | Reg;<br>
+ }<br>
+<br>
+ // The original code used a PC relative relocation.<br>
+ // Need to compensate for the -4 it had in the addend.<br>
relocateOne(Loc, R_X86_64_TPOFF32, Val + 4);<br>
}<br>
<br>
<br>
Modified: lld/trunk/test/ELF/tls-opt.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/lld/trunk/test/ELF/tls-opt.s?rev=273238&r1=273237&r2=273238&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/lld/trunk/test/ELF/tls-opt.s?rev=273238&r1=273237&r2=273238&view=diff</a><br>
==============================================================================<br>
--- lld/trunk/test/ELF/tls-opt.s (original)<br>
+++ lld/trunk/test/ELF/tls-opt.s Mon Jun 20 22:42:32 2016<br>
@@ -20,11 +20,9 @@<br>
// DISASM-NEXT: 1103f: 4d 8d bf fc ff ff ff leaq -4(%r15), %r15<br>
// DISASM-NEXT: 11046: 48 81 c4 fc ff ff ff addq $-4, %rsp<br>
// DISASM-NEXT: 1104d: 49 81 c4 fc ff ff ff addq $-4, %r12<br>
-// Corrupred output:<br>
-// DISASM-NEXT: 11054: 48 8d 80 f8 ff ff ff leaq -8(%rax), %rax<br>
-// DISASM-NEXT: 1105b: 48 d1 81 c4 fc ff ff rolq -828(%rcx)<br>
-// DISASM-NEXT: 11062: ff 48 d1 decl -47(%rax)<br>
-// DISASM-NEXT: 11065: 81 c4 fc ff ff ff addl $4294967292, %esp<br>
+// DISASM-NEXT: 11054: 48 87 05 f8 ff ff ff xchgq %rax, -8(%rip)<br>
+// DISASM-NEXT: 1105b: 48 d1 24 25 fc ff ff ff shlq -4<br>
+// DISASM-NEXT: 11063: 48 d1 04 25 fc ff ff ff rolq -4<br>
// LD to LE:<br>
// DISASM-NEXT: 1106b: 66 66 66 64 48 8b 04 25 00 00 00 00 movq %fs:0, %rax<br>
// DISASM-NEXT: 11077: 48 8d 88 f8 ff ff ff leaq -8(%rax), %rcx<br>
<br>
<br>
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