<p dir="ltr">Lgtm, but I have a question:</p>
<p dir="ltr">Will SCRATCH_RSRC_DWORD also need special  treatment in the linker? If so we should have special relocations for it to avoid using names in the linker. This is similar to how the got position is accessed: magical name for the assembler, different relocation for the linker.</p>
<p dir="ltr">Cheers,<br>
Rafael</p>
<div class="gmail_quote">On Jun 17, 2016 10:19 PM, "Tom Stellard" <<a href="mailto:thomas.stellard@amd.com">thomas.stellard@amd.com</a>> wrote:<br type="attribution"><blockquote class="quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">tstellarAMD updated this revision to Diff 61153.<br>
tstellarAMD added a comment.<br>
<br>
Split the test case in to to avoid using llc -filetype=obj<br>
<div class="quoted-text"><br>
<br>
<a href="http://reviews.llvm.org/D21400" rel="noreferrer" target="_blank">http://reviews.llvm.org/D21400</a><br>
<br>
Files:<br>
  lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp<br>
  test/CodeGen/AMDGPU/large-alloca-compute.ll<br>
</div>  test/MC/AMDGPU/reloc.s<br>
<br>
Index: test/MC/AMDGPU/reloc.s<br>
===================================================================<br>
--- /dev/null<br>
+++ test/MC/AMDGPU/reloc.s<br>
@@ -0,0 +1,12 @@<br>
+// RUN: llvm-mc -filetype=obj -triple amdgcn-- -mcpu=kaveri -show-encoding %s | llvm-readobj -relocations | FileCheck %s<br>
+<br>
+// CHECK: Relocations [<br>
+// CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0<br>
+// CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0<br>
+// CHECK: ]<br>
+<br>
+kernel:<br>
+  s_mov_b32 s0, SCRATCH_RSRC_DWORD0<br>
+  s_mov_b32 s1, SCRATCH_RSRC_DWORD1<br>
+<br>
+.globl SCRATCH_RSRC_DWORD0<br>
<div class="quoted-text">Index: test/CodeGen/AMDGPU/large-alloca-compute.ll<br>
===================================================================<br>
--- test/CodeGen/AMDGPU/large-alloca-compute.ll<br>
+++ test/CodeGen/AMDGPU/large-alloca-compute.ll<br>
</div>@@ -8,9 +8,9 @@<br>
<div class="quoted-text"> ; ALL-LABEL: {{^}}large_alloca_compute_shader:<br>
<br>
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0<br>
</div>-; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0, kind: FK_Data_4<br>
+; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0<br>
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1<br>
-; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1, kind: FK_Data_4<br>
+; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1<br>
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1<br>
 ; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe8f000<br>
 ; VI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe80000<br>
<div class="quoted-text">Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp<br>
===================================================================<br>
--- lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp<br>
+++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp<br>
@@ -21,10 +21,7 @@<br>
   AMDGPUELFObjectWriter(bool Is64Bit, bool HasRelocationAddend);<br>
 protected:<br>
   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,<br>
-                        const MCFixup &Fixup, bool IsPCRel) const override {<br>
-    return Fixup.getKind();<br>
-  }<br>
-<br>
+                        const MCFixup &Fixup, bool IsPCRel) const override;<br>
 };<br>
<br>
<br>
</div>@@ -37,6 +34,20 @@<br>
<div class="quoted-text">                             ELF::EM_AMDGPU,<br>
                             HasRelocationAddend) { }<br>
<br>
+unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,<br>
+                                             const MCValue &Target,<br>
+                                             const MCFixup &Fixup,<br>
+                                             bool IsPCRel) const {<br>
</div><div class="elided-text">+  // SCRATCH_RSRC_DWORD[01] is a special global variable that represents<br>
+  // the scratch buffer.<br>
+  if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD0")<br>
+    return ELF::R_AMDGPU_ABS32_LO;<br>
+  if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD1")<br>
+    return ELF::R_AMDGPU_ABS32_HI;<br>
+<br>
+  llvm_unreachable("unhandled relocation type");<br>
+}<br>
+<br>
<br>
 MCObjectWriter *llvm::createAMDGPUELFObjectWriter(bool Is64Bit,<br>
                                                   bool HasRelocationAddend,<br>
<br>
<br>
</div></blockquote></div>