<div dir="ltr">Awesome dogfooding this!</div><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Jun 12, 2016 at 10:30 AM, Benjamin Kramer via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: d0k<br>
Date: Sun Jun 12 12:30:47 2016<br>
New Revision: 272516<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=272516&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=272516&view=rev</a><br>
Log:<br>
Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.<br>
<br>
No functionality change intended.<br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp<br>
llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp<br>
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp<br>
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp<br>
llvm/trunk/tools/llvm-mc/llvm-mc.cpp<br>
llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp<br>
llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Sun Jun 12 12:30:47 2016<br>
@@ -998,7 +998,7 @@ void DwarfDebug::beginInstruction(const<br>
<br>
// Check if source location changes, but ignore DBG_VALUE locations.<br>
if (!MI->isDebugValue()) {<br>
- DebugLoc DL = MI->getDebugLoc();<br>
+ const DebugLoc &DL = MI->getDebugLoc();<br>
if (DL != PrevInstLoc) {<br>
if (DL) {<br>
unsigned Flags = 0;<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Sun Jun 12 12:30:47 2016<br>
@@ -1139,7 +1139,7 @@ bool HexagonAsmParser::parseOperand(Oper<br>
static char const *RParen = ")";<br>
Operands.push_back(HexagonOperand::CreateToken(LParen, Begin));<br>
Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));<br>
- AsmToken MaybeDotNew = Lexer.getTok();<br>
+ const AsmToken &MaybeDotNew = Lexer.getTok();<br>
if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&<br>
MaybeDotNew.getString().equals_lower(".new"))<br>
splitIdentifier(Operands);<br>
@@ -1155,7 +1155,7 @@ bool HexagonAsmParser::parseOperand(Oper<br>
Operands.insert(Operands.end () - 1,<br>
HexagonOperand::CreateToken(LParen, Begin));<br>
Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));<br>
- AsmToken MaybeDotNew = Lexer.getTok();<br>
+ const AsmToken &MaybeDotNew = Lexer.getTok();<br>
if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&<br>
MaybeDotNew.getString().equals_lower(".new"))<br>
splitIdentifier(Operands);<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp Sun Jun 12 12:30:47 2016<br>
@@ -1302,7 +1302,7 @@ bool RedundantInstrElimination::processB<br>
continue;<br>
<br>
// If found, replace the instruction with a COPY.<br>
- DebugLoc DL = MI->getDebugLoc();<br>
+ const DebugLoc &DL = MI->getDebugLoc();<br>
const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI);<br>
unsigned NewR = MRI.createVirtualRegister(FRC);<br>
BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp Sun Jun 12 12:30:47 2016<br>
@@ -960,7 +960,7 @@ void HexagonEarlyIfConversion::eliminate<br>
// MRI.replaceVregUsesWith does not allow to update the subregister,<br>
// so instead of doing the use-iteration here, create a copy into a<br>
// "non-subregistered" register.<br>
- DebugLoc DL = PN->getDebugLoc();<br>
+ const DebugLoc &DL = PN->getDebugLoc();<br>
const TargetRegisterClass *RC = MRI->getRegClass(DefR);<br>
NewR = MRI->createVirtualRegister(RC);<br>
NonPHI = BuildMI(*B, NonPHI, DL, TII->get(TargetOpcode::COPY), NewR)<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp Sun Jun 12 12:30:47 2016<br>
@@ -616,7 +616,7 @@ MachineInstr *HexagonExpandCondsets::gen<br>
bool PredSense, bool ReadUndef, bool ImpUse) {<br>
MachineInstr *MI = SrcOp.getParent();<br>
MachineBasicBlock &B = *At->getParent();<br>
- DebugLoc DL = MI->getDebugLoc();<br>
+ const DebugLoc &DL = MI->getDebugLoc();<br>
<br>
// Don't avoid identity copies here (i.e. if the source and the destination<br>
// are the same registers). It is actually better to generate them here,<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp Sun Jun 12 12:30:47 2016<br>
@@ -2120,7 +2120,7 @@ void HexagonFrameLowering::optimizeSpill<br>
MachineBasicBlock::iterator StartIt = SI, NextIt;<br>
MachineInstr *CopyIn = nullptr;<br>
if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) {<br>
- DebugLoc DL = SI->getDebugLoc();<br>
+ const DebugLoc &DL = SI->getDebugLoc();<br>
CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)<br>
.addOperand(SrcOp);<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp Sun Jun 12 12:30:47 2016<br>
@@ -196,7 +196,7 @@ void HexagonRegisterInfo::eliminateFrame<br>
// register and use it with offset 0.<br>
auto &MRI = MF.getRegInfo();<br>
unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);<br>
- DebugLoc DL = MI.getDebugLoc();<br>
+ const DebugLoc &DL = MI.getDebugLoc();<br>
BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)<br>
.addReg(BP)<br>
.addImm(RealOffset);<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Sun Jun 12 12:30:47 2016<br>
@@ -1191,7 +1191,7 @@ MachineBasicBlock *MipsTargetLowering::e<br>
MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,<br>
unsigned SrcReg) const {<br>
const TargetInstrInfo *TII = Subtarget.getInstrInfo();<br>
- DebugLoc DL = MI->getDebugLoc();<br>
+ const DebugLoc &DL = MI->getDebugLoc();<br>
<br>
if (Subtarget.hasMips32r2() && Size == 1) {<br>
BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Sun Jun 12 12:30:47 2016<br>
@@ -1830,7 +1830,7 @@ eliminateCallFramePseudoInstr(MachineFun<br>
unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;<br>
unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;<br>
MachineInstr *MI = I;<br>
- DebugLoc dl = MI->getDebugLoc();<br>
+ const DebugLoc &dl = MI->getDebugLoc();<br>
<br>
if (isInt<16>(CalleeAmt)) {<br>
BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Sun Jun 12 12:30:47 2016<br>
@@ -786,7 +786,7 @@ static const TableEntry PopTable[] = {<br>
///<br>
void FPS::popStackAfter(MachineBasicBlock::iterator &I) {<br>
MachineInstr* MI = I;<br>
- DebugLoc dl = MI->getDebugLoc();<br>
+ const DebugLoc &dl = MI->getDebugLoc();<br>
ASSERT_SORTED(PopTable);<br>
if (StackTop == 0)<br>
report_fatal_error("Cannot pop empty stack!");<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sun Jun 12 12:30:47 2016<br>
@@ -2504,7 +2504,7 @@ void X86InstrInfo::reMaterialize(Machine<br>
llvm_unreachable("Unexpected instruction!");<br>
}<br>
<br>
- DebugLoc DL = Orig->getDebugLoc();<br>
+ const DebugLoc &DL = Orig->getDebugLoc();<br>
BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))<br>
.addImm(Value);<br>
} else {<br>
<br>
Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Sun Jun 12 12:30:47 2016<br>
@@ -1302,7 +1302,7 @@ updateInlinedAtInfo(const DebugLoc &DL,<br>
/// to encode location where these instructions are inlined.<br>
static void fixupLineNumbers(Function *Fn, Function::iterator FI,<br>
Instruction *TheCall) {<br>
- DebugLoc TheCallDL = TheCall->getDebugLoc();<br>
+ const DebugLoc &TheCallDL = TheCall->getDebugLoc();<br>
if (!TheCallDL)<br>
return;<br>
<br>
<br>
Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)<br>
+++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Sun Jun 12 12:30:47 2016<br>
@@ -250,7 +250,7 @@ static int AsLexInput(SourceMgr &SrcMgr,<br>
<br>
bool Error = false;<br>
while (Lexer.Lex().isNot(AsmToken::Eof)) {<br>
- AsmToken Tok = Lexer.getTok();<br>
+ const AsmToken &Tok = Lexer.getTok();<br>
<br>
switch (Tok.getKind()) {<br>
default:<br>
<br>
Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Sun Jun 12 12:30:47 2016<br>
@@ -576,7 +576,7 @@ void AsmWriterEmitter::EmitGetRegisterNa<br>
O << " switch(AltIdx) {\n"<br>
<< " default: llvm_unreachable(\"Invalid register alt name index!\");\n";<br>
for (const Record *R : AltNameIndices) {<br>
- std::string AltName(R->getName());<br>
+ const std::string &AltName = R->getName();<br>
std::string Prefix = !Namespace.empty() ? Namespace + "::" : "";<br>
O << " case " << Prefix << AltName << ":\n"<br>
<< " assert(*(AsmStrs" << AltName << "+RegAsmOffset"<br>
<br>
Modified: llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp?rev=272516&r1=272515&r2=272516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp?rev=272516&r1=272515&r2=272516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp Sun Jun 12 12:30:47 2016<br>
@@ -709,7 +709,7 @@ int DFAPacketizerEmitter::collectAllComb<br>
Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc");<br>
const std::vector<Record*> &FuncList =<br>
FuncData->getValueAsListOfDefs("FuncList");<br>
- std::string ComboFuncName = ComboFunc->getName();<br>
+ const std::string &ComboFuncName = ComboFunc->getName();<br>
unsigned ComboBit = FUNameToBitsMap[ComboFuncName];<br>
unsigned ComboResources = ComboBit;<br>
DEBUG(dbgs() << " combo: " << ComboFuncName<br>
<br>
<br>
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</blockquote></div><br></div>