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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>The transformation that helps my case is applicable during LegalizeDAG. It will try to construct a ccmp sequence when it sees And i32/i64, Or i32/i64 with setcc leafs. If the result is feedback into condition input of a node like BRCOND or CSEL it will pessimize the codegen. Since LegalizeDAG works in reverse topological order, the only way my transformation is applicable is when we previously had a zext i1->i32 or if we failed to construct ccmp sequence at SELECT_CC nodes because </span><span style='font-size:10.0pt;font-family:"Segoe UI",sans-serif;color:black;background:white'>isConjunctionDisjunctionTree </span><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>was not satisfied. If I want to move the transform to PerformDAGCombine and still keep using the utilities </span><span style='font-size:10.0pt;font-family:"Segoe UI",sans-serif;color:black;background:white'>isConjunctionDisjunctionTree </span><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>and</span><span style='font-size:10.0pt;font-family:"Segoe UI",sans-serif;color:black;background:white'> emitConditionalComparison </span><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>I will have to do before LegalizeOps phase, but since LowerSELECT_CC is not yet called I will have to additionally check if the result of AND/OR is feedback into BRCOND or CSEL and bail out conservatively. This will miss some opportunities where we would have transformed if it failed to construct a ccmp sequence at SELECT_CC nodes. If we want to catch all the opportunities, we need to do the transform afterLegalizeVectorOps phase, but now the setcc and cmp nodes are all lowered into AArch64 specific DAG nodes and the utilities </span><span style='font-size:10.0pt;font-family:"Segoe UI",sans-serif;color:black;background:white'>isConjunctionDisjunctionTree </span><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>and</span><span style='font-size:10.0pt;font-family:"Segoe UI",sans-serif;color:black;background:white'> emitConditionalComparison </span><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>will fail to match the pattern. So I don’t see an easy way to do this without a lot of refactoring.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>-Balaram <o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'> qcolombet@apple.com [mailto:qcolombet@apple.com] <br><b>Sent:</b> Wednesday, June 08, 2016 6:32 PM<br><b>To:</b> Balaram Makam <bmakam@codeaurora.org><br><b>Cc:</b> llvm-commits@lists.llvm.org<br><b>Subject:</b> Re: [llvm] r259387 - AArch64: Implement missed conditional compare sequences.<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Hi Balaram,<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><p class=MsoNormal>On Jun 8, 2016, at 2:10 PM, Balaram Makam <<a href="mailto:bmakam@codeaurora.org">bmakam@codeaurora.org</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Hi Quentin,</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'> </span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>I don’t see an easy way to achieve the same combine in PerformDAGCombine because it depends on the utilities emitConditionalComparison and isConjunctionDisjunctionTree that will now fail to match the AArch64 specific DAG nodes.</span><o:p></o:p></p></div></div></blockquote><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>I am not sure I get why this is a problem. You should be able to use those within PerformDAGCombine, shouldn’t you?<o:p></o:p></p></div><p class=MsoNormal><br><br><o:p></o:p></p><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Is there any other way we could do the custom lowering with just the isLegal part of the check?</span><o:p></o:p></p></div></div></blockquote><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>No, there is not at legalization time.<o:p></o:p></p></div><div><p class=MsoNormal>When does the combine, that help in your case, apply?<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal>Cheers,<o:p></o:p></p></div><div><p class=MsoNormal>-Quentin<br><br><o:p></o:p></p><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'> </span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Regards,</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Balaram</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'> </span><o:p></o:p></p></div><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><div><p class=MsoNormal><b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span class=apple-converted-space><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'> </span></span><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>Quentin Colombet [</span><a href="mailto:qcolombet@apple.com"><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>mailto:qcolombet@apple.com</span></a><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>]<span class=apple-converted-space> </span><br><b>Sent:</b><span class=apple-converted-space> </span>Monday, June 06, 2016 7:34 PM<br><b>To:</b><span class=apple-converted-space> </span>Balaram Makam <</span><a href="mailto:bmakam@codeaurora.org"><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>bmakam@codeaurora.org</span></a><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>><br><b>Cc:</b><span class=apple-converted-space> </span></span><a href="mailto:llvm-commits@lists.llvm.org"><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>llvm-commits@lists.llvm.org</span></a><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'><br><b>Subject:</b><span class=apple-converted-space> </span>Re: [llvm] r259387 - AArch64: Implement missed conditional compare sequences.</span><o:p></o:p></p></div></div></div><div><p class=MsoNormal> <o:p></o:p></p></div><div><div><p class=MsoNormal>Hi Balaram,<o:p></o:p></p></div></div><div><p class=MsoNormal> <o:p></o:p></p></div><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><p class=MsoNormal>On Jun 6, 2016, at 2:43 PM, Balaram Makam <<a href="mailto:bmakam@codeaurora.org"><span style='color:purple'>bmakam@codeaurora.org</span></a>> wrote:<o:p></o:p></p></div></div><div><p class=MsoNormal> <o:p></o:p></p></div><div><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Hi Quentin,</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>I will take another look at this. I believe the problem is seen only on the internal branch. Do you have a test case to reproduce the issue?</span><o:p></o:p></p></div></div></div></blockquote><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>Unfortunately, no, I do not have a test case for you.<o:p></o:p></p></div></div><div><div><p class=MsoNormal>Basically, this patch generates illegal code after legalization, and the problem is only the fact that we use Custom here to check legality.<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>You should be able to achieve the same combine in the AArch64 backend with just the isLegal part of the check.<o:p></o:p></p></div></div><div><div><p class=MsoNormal>There are a bunch of hooks during the lowering of SDAG and I am pretty sure you could find another way to do your custom lowering (I know I’ve already been in that situation :)). The "perform dag combine” that I mentioned should be one of them, but you have others.<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>Cheers,<o:p></o:p></p></div></div><div><div><p class=MsoNormal>-Quentin<o:p></o:p></p></div></div><div><p class=MsoNormal><br><br><br><o:p></o:p></p></div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Thanks,</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Balaram</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'> </span><o:p></o:p></p></div></div><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><div><div><p class=MsoNormal><b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span class=apple-converted-space><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'> </span></span><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>Quentin Colombet [</span><a href="mailto:qcolombet@apple.com"><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:purple'>mailto:qcolombet@apple.com</span></a><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>]<span class=apple-converted-space> </span><br><b>Sent:</b><span class=apple-converted-space> </span>Monday, June 06, 2016 5:30 PM<br><b>To:</b><span class=apple-converted-space> </span>Balaram Makam <</span><a href="mailto:bmakam@codeaurora.org"><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:purple'>bmakam@codeaurora.org</span></a><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>><br><b>Cc:</b><span class=apple-converted-space> </span></span><a href="mailto:llvm-commits@lists.llvm.org"><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:purple'>llvm-commits@lists.llvm.org</span></a><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'><br><b>Subject:</b><span class=apple-converted-space> </span>Re: [llvm] r259387 - AArch64: Implement missed conditional compare sequences.</span><o:p></o:p></p></div></div></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><div><p class=MsoNormal>Hi Balaram,<o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal>Sorry for the late reply, but I am seeing this commit is causing problem internally.<o:p></o:p></p></div></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><div><p class=MsoNormal>On Feb 1, 2016, at 11:13 AM, Balaram Makam via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org"><span style='color:purple'>llvm-commits@lists.llvm.org</span></a>> wrote:<o:p></o:p></p></div></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><div><div><p class=MsoNormal>Author: bmakam<br>Date: Mon Feb 1 13:13:07 2016<br>New Revision: 259387<br><br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project?rev=259387&view=rev"><span style='color:purple'>http://llvm.org/viewvc/llvm-project?rev=259387&view=rev</span></a><br>Log:<br>AArch64: Implement missed conditional compare sequences.<br><br>Summary:<br>This is an extension to the existing implementation of r242436 which<br>restricts to only select inputs. This version fixes missed opportunities<br>in pr26084 by attempting to lower conditional compare sequences of<br>and/or trees with setcc leafs. This will additionaly handle the case<br>when a tree with select input is not a conjunction-disjunction tree<br>but some of the sub trees are conjunction-disjunction trees.<br><br>Reviewers: jmolloy, t.p.northover, mcrosier, MatzeB<br><br>Subscribers: mcrosier, llvm-commits, junbuml, haicheng, mssimpso, gberry<br><br>Differential Revision:<span class=apple-converted-space> </span><a href="http://reviews.llvm.org/D16291"><span style='color:purple'>http://reviews.llvm.org/D16291</span></a><br><br>Modified:<br> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h<br> llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll<br><br>Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=259387&r1=259386&r2=259387&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=259387&r1=259386&r2=259387&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Feb 1 13:13:07 2016<br>@@ -1721,7 +1721,7 @@ SDValue DAGCombiner::visitADD(SDNode *N)<br> return SDValue(N, 0);<br><br> // fold (a+b) -> (a|b) iff a and b share no bits.<br>- if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&<br>+ if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::OR, VT)) &&<o:p></o:p></p></div></div></div></div></blockquote><div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal>This is wrong. Custom does not imply that the operation is Legal!<o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal>You said in the review that without custom, one of the lit test case was failing. I believe you can fix that by making the Custom lowering as part of the combine process (<span style='font-size:8.5pt'>PerformDAGCombine</span>.)<o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal>Anyhow, this line is generally not correct.<o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal>Cheers,<o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal>-Quentin<o:p></o:p></p></div></div></div><div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div></div><div><div><p class=MsoNormal><br><br><br><br><o:p></o:p></p></div></div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><div><div><div><p class=MsoNormal> VT.isInteger() && !VT.isVector() && DAG.haveNoCommonBitsSet(N0, N1))<br> return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);<br><br>@@ -6363,7 +6363,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SD<br> isa<LoadSDNode>(N0.getOperand(0)) &&<br> N0.getOperand(1).getOpcode() == ISD::Constant &&<br> TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()) &&<br>- (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {<br>+ (!LegalOperations && TLI.isOperationLegalOrCustom(N0.getOpcode(), VT))) {<br> LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));<br> if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {<br> bool DoXform = true;<br><br>Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=259387&r1=259386&r2=259387&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=259387&r1=259386&r2=259387&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)<br>+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Mon Feb 1 13:13:07 2016<br>@@ -144,6 +144,16 @@ AArch64TargetLowering::AArch64TargetLowe<br> setOperationAction(ISD::XOR, MVT::i32, Custom);<br> setOperationAction(ISD::XOR, MVT::i64, Custom);<br><br>+ // Custom lowering hooks are needed for OR<br>+ // to fold it into CCMP.<br>+ setOperationAction(ISD::OR, MVT::i32, Custom);<br>+ setOperationAction(ISD::OR, MVT::i64, Custom);<br>+<br>+ // Custom lowering hooks are needed for AND<br>+ // to fold it into CCMP.<br>+ setOperationAction(ISD::AND, MVT::i32, Custom);<br>+ setOperationAction(ISD::AND, MVT::i64, Custom);<br>+<br> // Virtually no operation on f128 is legal, but LLVM can't expand them when<br> // there's a valid register class, so we need custom operations in most cases.<br> setOperationAction(ISD::FABS, MVT::f128, Expand);<br>@@ -1597,6 +1607,27 @@ static SDValue getAArch64Cmp(SDValue LHS<br> return Cmp;<br>}<br><br>+// Attempt to form conditional compare sequences for and/or trees<br>+// with setcc leafs.<br>+static SDValue tryLowerToAArch64Cmp(SDValue Op, SelectionDAG &DAG) {<br>+ SDValue LHS = Op.getOperand(0);<br>+ SDValue RHS = Op.getOperand(1);<br>+ if ((LHS.getOpcode() != ISD::SETCC) || (RHS.getOpcode() != ISD::SETCC))<br>+ return Op;<br>+<br>+ bool CanNegate;<br>+ if (!isConjunctionDisjunctionTree(Op, CanNegate))<br>+ return SDValue();<br>+<br>+ EVT VT = Op.getValueType();<br>+ SDLoc DL(Op);<br>+ SDValue TVal = DAG.getConstant(1, DL, VT);<br>+ SDValue FVal = DAG.getConstant(0, DL, VT);<br>+ SDValue CCVal;<br>+ SDValue Cmp = getAArch64Cmp(Op, FVal, ISD::SETEQ, CCVal, DAG, DL);<br>+ return DAG.getNode(AArch64ISD::CSEL, DL, VT, FVal, TVal, CCVal, Cmp);<br>+}<br>+<br>static std::pair<SDValue, SDValue><br>getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {<br> assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&<br>@@ -1718,6 +1749,18 @@ SDValue AArch64TargetLowering::LowerF128<br> return makeLibCall(DAG, Call, MVT::f128, Ops, false, SDLoc(Op)).first;<br>}<br><br>+SDValue AArch64TargetLowering::LowerAND(SDValue Op, SelectionDAG &DAG) const {<br>+ if (Op.getValueType().isVector())<br>+ return LowerVectorAND(Op, DAG);<br>+ return tryLowerToAArch64Cmp(Op, DAG);<br>+}<br>+<br>+SDValue AArch64TargetLowering::LowerOR(SDValue Op, SelectionDAG &DAG) const {<br>+ if (Op.getValueType().isVector())<br>+ return LowerVectorOR(Op, DAG);<br>+ return tryLowerToAArch64Cmp(Op, DAG);<br>+}<br>+<br>static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {<br> SDValue Sel = Op.getOperand(0);<br> SDValue Other = Op.getOperand(1);<br>@@ -2372,9 +2415,9 @@ SDValue AArch64TargetLowering::LowerOper<br> case ISD::FCOPYSIGN:<br> return LowerFCOPYSIGN(Op, DAG);<br> case ISD::AND:<br>- return LowerVectorAND(Op, DAG);<br>+ return LowerAND(Op, DAG);<br> case ISD::OR:<br>- return LowerVectorOR(Op, DAG);<br>+ return LowerOR(Op, DAG);<br> case ISD::XOR:<br> return LowerXOR(Op, DAG);<br> case ISD::PREFETCH:<br><br>Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=259387&r1=259386&r2=259387&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=259387&r1=259386&r2=259387&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h (original)<br>+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h Mon Feb 1 13:13:07 2016<br>@@ -488,6 +488,8 @@ private:<br> SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;<br> SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,<br> RTLIB::Libcall Call) const;<br>+ SDValue LowerAND(SDValue Op, SelectionDAG &DAG) const;<br>+ SDValue LowerOR(SDValue Op, SelectionDAG &DAG) const;<br> SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;<br> SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;<br> SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll<br>URL:<span class=apple-converted-space> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll?rev=259387&r1=259386&r2=259387&view=diff"><span style='color:purple'>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll?rev=259387&r1=259386&r2=259387&view=diff</span></a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll Mon Feb 1 13:13:07 2016<br>@@ -371,21 +371,76 @@ define i32 @select_andor(i32 %v1, i32 %v<br> ret i32 %sel<br>}<br><br>-; CHECK-LABEL: select_noccmp1<br>-define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {<br>-; CHECK: cmp x0, #0<br>-; CHECK-NEXT: cset [[REG0:w[0-9]+]], lt<br>-; CHECK-NEXT: cmp x0, #13<br>-; CHECK-NOT: ccmp<br>+; CHECK-LABEL: single_noselect<br>+define i32 @single_noselect(i32 %A, i32 %B) #0 {<br>+; CHECK: cmp w1, #1<br>+; CHECK-NEXT: ccmp w0, #1, #8, ge<br>+; CHECK-NEXT: cset w0, lt<br>+; CHECK-NEXT: ret<br>+ %notlhs = icmp slt i32 %A, 1<br>+ %notrhs = icmp slt i32 %B, 1<br>+ %lnot = or i1 %notlhs, %notrhs<br>+ %conv = zext i1 %lnot to i32<br>+ ret i32 %conv<br>+}<br>+<br>+; CHECK-LABEL: single_and_ext<br>+define i32 @single_and_ext(i32 %A, i32 %B, i32 %C) #0 {<br>+; CHECK: cmp w1, #2<br>+; CHECK-NEXT: ccmp w0, #4, #0, lt<br>+; CHECK-NEXT: cinc w0, w2, lt<br>+; CHECK-NEXT: ret<br>+ %cmp = icmp slt i32 %A, 4<br>+ %cmp1 = icmp slt i32 %B, 2<br>+ %and1 = and i1 %cmp, %cmp1<br>+ %conv = zext i1 %and1 to i32<br>+ %add = add nsw i32 %conv, %C<br>+ ret i32 %add<br>+}<br>+<br>+; CHECK-LABEL: single_noselect_phi<br>+define i32 @single_noselect_phi(i32 %A, i32 %B, i32 %C) #0 {<br>+; CHECK: cmp w1, #0<br>+; CHECK-NEXT: ccmp w0, #0, #4, gt<br>; CHECK-NEXT: cset [[REG1:w[0-9]+]], gt<br>-; CHECK-NEXT: cmp x2, #2<br>+; CHECK-NEXT: cmp w1, #2<br>+; CHECK-NEXT: ccmp w0, #4, #8, ge<br>; CHECK-NEXT: cset [[REG2:w[0-9]+]], lt<br>+; CHECK-NEXT: cmp w2, #0<br>+; CHECK-NEXT: csel w0, [[REG1]], [[REG2]], eq<br>+; CHECK-NEXT: ret<br>+entry:<br>+ %tobool = icmp eq i32 %C, 0<br>+ br i1 %tobool, label %if.else, label %if.then<br>+<br>+if.then: ; preds = %entry<br>+ %cmp = icmp slt i32 %A, 4<br>+ %cmp1 = icmp slt i32 %B, 2<br>+ %0 = or i1 %cmp, %cmp1<br>+ br label %if.end<br>+<br>+if.else: ; preds = %entry<br>+ %cmp2 = icmp sgt i32 %A, 0<br>+ %cmp3 = icmp sgt i32 %B, 0<br>+ %1 = and i1 %cmp2, %cmp3<br>+ br label %if.end<br>+<br>+if.end: ; preds = %if.else, %if.then<br>+ %<a href="http://b.0.in">b.0.in</a> = phi i1 [ %0, %if.then ], [ %1, %if.else ]<br>+ %conv = zext i1 %<a href="http://b.0.in">b.0.in</a> to i32<br>+ ret i32 %conv<br>+}<br>+<br>+; CHECK-LABEL: select_noccmp1<br>+define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {<br>+; CHECK: cmp x0, #13<br>+; CHECK-NEXT: ccmp x0, #0, #0, gt<br>+; CHECK-NEXT: cset [[REG1:w[0-9]+]], lt<br>; CHECK-NEXT: cmp x2, #4<br>-; CHECK-NEXT: cset [[REG3:w[0-9]+]], gt<br>-; CHECK-NEXT: and [[REG4:w[0-9]+]], [[REG0]], [[REG1]]<br>-; CHECK-NEXT: and [[REG5:w[0-9]+]], [[REG2]], [[REG3]]<br>-; CHECK-NEXT: orr [[REG6:w[0-9]+]], [[REG4]], [[REG5]]<br>-; CHECK-NEXT: cmp [[REG6]], #0<br>+; CHECK-NEXT: ccmp x2, #2, #0, gt<br>+; CHECK-NEXT: cset [[REG2:w[0-9]+]], lt<br>+; CHECK-NEXT: orr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]<br>+; CHECK-NEXT: cmp [[REG3]], #0<br>; CHECK-NEXT: csel x0, xzr, x3, ne<br>; CHECK-NEXT: ret<br> %c0 = icmp slt i64 %v1, 0<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@lists.llvm.org"><span style='color:purple'>llvm-commits@lists.llvm.org</span></a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits"><span style='color:purple'>http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</span></a><o:p></o:p></p></div></div></div></div></blockquote></div></div></blockquote></div></div></blockquote></div><p class=MsoNormal><o:p> </o:p></p></div></div></body></html>