<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><div class="">Hi Balaram,</div><div class=""><br class=""></div><div class="">Sorry for the late reply, but I am seeing this commit is causing problem internally.</div><br class=""><div><blockquote type="cite" class=""><div class="">On Feb 1, 2016, at 11:13 AM, Balaram Makam via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">Author: bmakam<br class="">Date: Mon Feb 1 13:13:07 2016<br class="">New Revision: 259387<br class=""><br class="">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=259387&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=259387&view=rev</a><br class="">Log:<br class="">AArch64: Implement missed conditional compare sequences.<br class=""><br class="">Summary:<br class="">This is an extension to the existing implementation of r242436 which<br class="">restricts to only select inputs. This version fixes missed opportunities<br class="">in pr26084 by attempting to lower conditional compare sequences of<br class="">and/or trees with setcc leafs. This will additionaly handle the case<br class="">when a tree with select input is not a conjunction-disjunction tree<br class="">but some of the sub trees are conjunction-disjunction trees.<br class=""><br class="">Reviewers: jmolloy, t.p.northover, mcrosier, MatzeB<br class=""><br class="">Subscribers: mcrosier, llvm-commits, junbuml, haicheng, mssimpso, gberry<br class=""><br class="">Differential Revision: <a href="http://reviews.llvm.org/D16291" class="">http://reviews.llvm.org/D16291</a><br class=""><br class="">Modified:<br class=""> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br class=""> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br class=""> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h<br class=""> llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=259387&r1=259386&r2=259387&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=259387&r1=259386&r2=259387&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Feb 1 13:13:07 2016<br class="">@@ -1721,7 +1721,7 @@ SDValue DAGCombiner::visitADD(SDNode *N)<br class=""> return SDValue(N, 0);<br class=""><br class=""> // fold (a+b) -> (a|b) iff a and b share no bits.<br class="">- if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&<br class="">+ if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::OR, VT)) &&<br class=""></div></div></blockquote><div><br class=""></div><div>This is wrong. Custom does not imply that the operation is Legal!</div><div><br class=""></div><div>You said in the review that without custom, one of the lit test case was failing. I believe you can fix that by making the Custom lowering as part of the combine process (<span style="font-family: Menlo; font-size: 11px;" class="">PerformDAGCombine</span>.)</div><div><br class=""></div><div>Anyhow, this line is generally not correct.</div><div><br class=""></div><div>Cheers,</div><div>-Quentin</div><div><br class=""></div><br class=""><blockquote type="cite" class=""><div class=""><div class=""> VT.isInteger() && !VT.isVector() && DAG.haveNoCommonBitsSet(N0, N1))<br class=""> return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);<br class=""><br class="">@@ -6363,7 +6363,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SD<br class=""> isa<LoadSDNode>(N0.getOperand(0)) &&<br class=""> N0.getOperand(1).getOpcode() == ISD::Constant &&<br class=""> TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()) &&<br class="">- (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {<br class="">+ (!LegalOperations && TLI.isOperationLegalOrCustom(N0.getOpcode(), VT))) {<br class=""> LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));<br class=""> if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {<br class=""> bool DoXform = true;<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=259387&r1=259386&r2=259387&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=259387&r1=259386&r2=259387&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Mon Feb 1 13:13:07 2016<br class="">@@ -144,6 +144,16 @@ AArch64TargetLowering::AArch64TargetLowe<br class=""> setOperationAction(ISD::XOR, MVT::i32, Custom);<br class=""> setOperationAction(ISD::XOR, MVT::i64, Custom);<br class=""><br class="">+ // Custom lowering hooks are needed for OR<br class="">+ // to fold it into CCMP.<br class="">+ setOperationAction(ISD::OR, MVT::i32, Custom);<br class="">+ setOperationAction(ISD::OR, MVT::i64, Custom);<br class="">+<br class="">+ // Custom lowering hooks are needed for AND<br class="">+ // to fold it into CCMP.<br class="">+ setOperationAction(ISD::AND, MVT::i32, Custom);<br class="">+ setOperationAction(ISD::AND, MVT::i64, Custom);<br class="">+<br class=""> // Virtually no operation on f128 is legal, but LLVM can't expand them when<br class=""> // there's a valid register class, so we need custom operations in most cases.<br class=""> setOperationAction(ISD::FABS, MVT::f128, Expand);<br class="">@@ -1597,6 +1607,27 @@ static SDValue getAArch64Cmp(SDValue LHS<br class=""> return Cmp;<br class=""> }<br class=""><br class="">+// Attempt to form conditional compare sequences for and/or trees<br class="">+// with setcc leafs.<br class="">+static SDValue tryLowerToAArch64Cmp(SDValue Op, SelectionDAG &DAG) {<br class="">+ SDValue LHS = Op.getOperand(0);<br class="">+ SDValue RHS = Op.getOperand(1);<br class="">+ if ((LHS.getOpcode() != ISD::SETCC) || (RHS.getOpcode() != ISD::SETCC))<br class="">+ return Op;<br class="">+<br class="">+ bool CanNegate;<br class="">+ if (!isConjunctionDisjunctionTree(Op, CanNegate))<br class="">+ return SDValue();<br class="">+<br class="">+ EVT VT = Op.getValueType();<br class="">+ SDLoc DL(Op);<br class="">+ SDValue TVal = DAG.getConstant(1, DL, VT);<br class="">+ SDValue FVal = DAG.getConstant(0, DL, VT);<br class="">+ SDValue CCVal;<br class="">+ SDValue Cmp = getAArch64Cmp(Op, FVal, ISD::SETEQ, CCVal, DAG, DL);<br class="">+ return DAG.getNode(AArch64ISD::CSEL, DL, VT, FVal, TVal, CCVal, Cmp);<br class="">+}<br class="">+<br class=""> static std::pair<SDValue, SDValue><br class=""> getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {<br class=""> assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&<br class="">@@ -1718,6 +1749,18 @@ SDValue AArch64TargetLowering::LowerF128<br class=""> return makeLibCall(DAG, Call, MVT::f128, Ops, false, SDLoc(Op)).first;<br class=""> }<br class=""><br class="">+SDValue AArch64TargetLowering::LowerAND(SDValue Op, SelectionDAG &DAG) const {<br class="">+ if (Op.getValueType().isVector())<br class="">+ return LowerVectorAND(Op, DAG);<br class="">+ return tryLowerToAArch64Cmp(Op, DAG);<br class="">+}<br class="">+<br class="">+SDValue AArch64TargetLowering::LowerOR(SDValue Op, SelectionDAG &DAG) const {<br class="">+ if (Op.getValueType().isVector())<br class="">+ return LowerVectorOR(Op, DAG);<br class="">+ return tryLowerToAArch64Cmp(Op, DAG);<br class="">+}<br class="">+<br class=""> static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {<br class=""> SDValue Sel = Op.getOperand(0);<br class=""> SDValue Other = Op.getOperand(1);<br class="">@@ -2372,9 +2415,9 @@ SDValue AArch64TargetLowering::LowerOper<br class=""> case ISD::FCOPYSIGN:<br class=""> return LowerFCOPYSIGN(Op, DAG);<br class=""> case ISD::AND:<br class="">- return LowerVectorAND(Op, DAG);<br class="">+ return LowerAND(Op, DAG);<br class=""> case ISD::OR:<br class="">- return LowerVectorOR(Op, DAG);<br class="">+ return LowerOR(Op, DAG);<br class=""> case ISD::XOR:<br class=""> return LowerXOR(Op, DAG);<br class=""> case ISD::PREFETCH:<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=259387&r1=259386&r2=259387&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=259387&r1=259386&r2=259387&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h Mon Feb 1 13:13:07 2016<br class="">@@ -488,6 +488,8 @@ private:<br class=""> SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;<br class=""> SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,<br class=""> RTLIB::Libcall Call) const;<br class="">+ SDValue LowerAND(SDValue Op, SelectionDAG &DAG) const;<br class="">+ SDValue LowerOR(SDValue Op, SelectionDAG &DAG) const;<br class=""> SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;<br class=""> SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;<br class=""> SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll?rev=259387&r1=259386&r2=259387&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll?rev=259387&r1=259386&r2=259387&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll Mon Feb 1 13:13:07 2016<br class="">@@ -371,21 +371,76 @@ define i32 @select_andor(i32 %v1, i32 %v<br class=""> ret i32 %sel<br class=""> }<br class=""><br class="">-; CHECK-LABEL: select_noccmp1<br class="">-define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {<br class="">-; CHECK: cmp x0, #0<br class="">-; CHECK-NEXT: cset [[REG0:w[0-9]+]], lt<br class="">-; CHECK-NEXT: cmp x0, #13<br class="">-; CHECK-NOT: ccmp<br class="">+; CHECK-LABEL: single_noselect<br class="">+define i32 @single_noselect(i32 %A, i32 %B) #0 {<br class="">+; CHECK: cmp w1, #1<br class="">+; CHECK-NEXT: ccmp w0, #1, #8, ge<br class="">+; CHECK-NEXT: cset w0, lt<br class="">+; CHECK-NEXT: ret<br class="">+ %notlhs = icmp slt i32 %A, 1<br class="">+ %notrhs = icmp slt i32 %B, 1<br class="">+ %lnot = or i1 %notlhs, %notrhs<br class="">+ %conv = zext i1 %lnot to i32<br class="">+ ret i32 %conv<br class="">+}<br class="">+<br class="">+; CHECK-LABEL: single_and_ext<br class="">+define i32 @single_and_ext(i32 %A, i32 %B, i32 %C) #0 {<br class="">+; CHECK: cmp w1, #2<br class="">+; CHECK-NEXT: ccmp w0, #4, #0, lt<br class="">+; CHECK-NEXT: cinc w0, w2, lt<br class="">+; CHECK-NEXT: ret<br class="">+ %cmp = icmp slt i32 %A, 4<br class="">+ %cmp1 = icmp slt i32 %B, 2<br class="">+ %and1 = and i1 %cmp, %cmp1<br class="">+ %conv = zext i1 %and1 to i32<br class="">+ %add = add nsw i32 %conv, %C<br class="">+ ret i32 %add<br class="">+}<br class="">+<br class="">+; CHECK-LABEL: single_noselect_phi<br class="">+define i32 @single_noselect_phi(i32 %A, i32 %B, i32 %C) #0 {<br class="">+; CHECK: cmp w1, #0<br class="">+; CHECK-NEXT: ccmp w0, #0, #4, gt<br class=""> ; CHECK-NEXT: cset [[REG1:w[0-9]+]], gt<br class="">-; CHECK-NEXT: cmp x2, #2<br class="">+; CHECK-NEXT: cmp w1, #2<br class="">+; CHECK-NEXT: ccmp w0, #4, #8, ge<br class=""> ; CHECK-NEXT: cset [[REG2:w[0-9]+]], lt<br class="">+; CHECK-NEXT: cmp w2, #0<br class="">+; CHECK-NEXT: csel w0, [[REG1]], [[REG2]], eq<br class="">+; CHECK-NEXT: ret<br class="">+entry:<br class="">+ %tobool = icmp eq i32 %C, 0<br class="">+ br i1 %tobool, label %if.else, label %if.then<br class="">+<br class="">+if.then: ; preds = %entry<br class="">+ %cmp = icmp slt i32 %A, 4<br class="">+ %cmp1 = icmp slt i32 %B, 2<br class="">+ %0 = or i1 %cmp, %cmp1<br class="">+ br label %if.end<br class="">+<br class="">+if.else: ; preds = %entry<br class="">+ %cmp2 = icmp sgt i32 %A, 0<br class="">+ %cmp3 = icmp sgt i32 %B, 0<br class="">+ %1 = and i1 %cmp2, %cmp3<br class="">+ br label %if.end<br class="">+<br class="">+if.end: ; preds = %if.else, %if.then<br class="">+ %b.0.in = phi i1 [ %0, %if.then ], [ %1, %if.else ]<br class="">+ %conv = zext i1 %b.0.in to i32<br class="">+ ret i32 %conv<br class="">+}<br class="">+<br class="">+; CHECK-LABEL: select_noccmp1<br class="">+define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {<br class="">+; CHECK: cmp x0, #13<br class="">+; CHECK-NEXT: ccmp x0, #0, #0, gt<br class="">+; CHECK-NEXT: cset [[REG1:w[0-9]+]], lt<br class=""> ; CHECK-NEXT: cmp x2, #4<br class="">-; CHECK-NEXT: cset [[REG3:w[0-9]+]], gt<br class="">-; CHECK-NEXT: and [[REG4:w[0-9]+]], [[REG0]], [[REG1]]<br class="">-; CHECK-NEXT: and [[REG5:w[0-9]+]], [[REG2]], [[REG3]]<br class="">-; CHECK-NEXT: orr [[REG6:w[0-9]+]], [[REG4]], [[REG5]]<br class="">-; CHECK-NEXT: cmp [[REG6]], #0<br class="">+; CHECK-NEXT: ccmp x2, #2, #0, gt<br class="">+; CHECK-NEXT: cset [[REG2:w[0-9]+]], lt<br class="">+; CHECK-NEXT: orr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]<br class="">+; CHECK-NEXT: cmp [[REG3]], #0<br class=""> ; CHECK-NEXT: csel x0, xzr, x3, ne<br class=""> ; CHECK-NEXT: ret<br class=""> %c0 = icmp slt i64 %v1, 0<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br class=""></div></div></blockquote></div><br class=""></body></html>