<div dir="ltr">Why do we need this? We already have generic intrinsics:<br><a href="http://llvm.org/docs/LangRef.html#llvm-cttz-intrinsic">http://llvm.org/docs/LangRef.html#llvm-cttz-intrinsic</a><div><a href="http://llvm.org/docs/LangRef.html#llvm-ctlz-intrinsic">http://llvm.org/docs/LangRef.html#llvm-ctlz-intrinsic</a><br><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jun 1, 2016 at 5:20 AM, Michael Zuckerman via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex">Author: mzuckerm<br>
Date: Wed Jun  1 07:02:37 2016<br>
New Revision: 271386<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=271386&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=271386&view=rev</a><br>
Log:<br>
Adding back-end support to two bit scanning intrinsics<br>
<br>
Adding LLVM back-end support to two intrinsics dealing with bit scan: _bit_scan_forward and _bit_scan_reverse.<br>
Their functionality is as described in Intel intrinsics guide:<br>
<a href="https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370" rel="noreferrer" target="_blank">https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370</a><br>
<a href="https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370" rel="noreferrer" target="_blank">https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370</a><br>
<br>
Commit on behalf of Omer Paparo Bivas<br>
<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D19915" rel="noreferrer" target="_blank">http://reviews.llvm.org/D19915</a><br>
<br>
<br>
Added:<br>
    llvm/trunk/test/CodeGen/X86/bitscan.ll<br>
Modified:<br>
    llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
    llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h<br>
<br>
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=271386&r1=271385&r2=271386&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=271386&r1=271385&r2=271386&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)<br>
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Wed Jun  1 07:02:37 2016<br>
@@ -8442,3 +8442,13 @@ let TargetPrefix = "x86" in {<br>
       : GCCBuiltin<"__builtin_ia32_mwaitx">,<br>
         Intrinsic<[], [ llvm_i32_ty, llvm_i32_ty, llvm_i32_ty ], []>;<br>
 }<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// Bit Scan intrinsics<br>
+let TargetPrefix = "x86" in {<br>
+  def int_x86_bit_scan_forward_32 : GCCBuiltin<"__builtin_ia32_bit_scan_forward">,<br>
+      Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+<br>
+  def int_x86_bit_scan_reverse_32 : GCCBuiltin<"__builtin_ia32_bit_scan_reverse">,<br>
+      Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; </blockquote><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex">
+}<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h?rev=271386&r1=271385&r2=271386&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h?rev=271386&r1=271385&r2=271386&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h Wed Jun  1 07:02:37 2016<br>
@@ -2133,6 +2133,8 @@ static const IntrinsicData  IntrinsicsWi<br>
                      X86ISD::SCALAR_FP_TO_UINT_RND, 0),<br>
   X86_INTRINSIC_DATA(avx512_vcvtss2usi64, INTR_TYPE_2OP,<br>
                      X86ISD::SCALAR_FP_TO_UINT_RND, 0),<br>
+  X86_INTRINSIC_DATA(bit_scan_forward_32,  INTR_TYPE_1OP, X86ISD::BSF, 0),<br>
+  X86_INTRINSIC_DATA(bit_scan_reverse_32,  INTR_TYPE_1OP, X86ISD::BSR, 0),<br>
   X86_INTRINSIC_DATA(fma_vfmadd_pd,        INTR_TYPE_3OP, X86ISD::FMADD, 0),<br>
   X86_INTRINSIC_DATA(fma_vfmadd_pd_256,    INTR_TYPE_3OP, X86ISD::FMADD, 0),<br>
   X86_INTRINSIC_DATA(fma_vfmadd_ps,        INTR_TYPE_3OP, X86ISD::FMADD, 0),<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/bitscan.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitscan.ll?rev=271386&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitscan.ll?rev=271386&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/bitscan.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/bitscan.ll Wed Jun  1 07:02:37 2016<br>
@@ -0,0 +1,23 @@<br>
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7 | FileCheck %s --check-prefix=ALL --check-prefix=64-BIT<br>
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=corei7 | FileCheck %s --check-prefix=ALL --check-prefix=32-BIT<br>
+declare i32 @llvm.x86.bit.scan.forward.32(i32 %val)<br>
+declare i32 @llvm.x86.bit.scan.reverse.32(i32 %val)<br>
+<br>
+define i32 @test_bsf(i32 %val) {<br>
+  %call = call i32 @llvm.x86.bit.scan.forward.32(i32 %val)<br>
+  ret i32 %call<br>
+<br>
+; ALL-LABEL: test_bsf:<br>
+; 64-BIT:    bsfl %edi, %eax<br>
+; 32-BIT:    bsfl 4(%esp), %eax<br>
+}<br>
+<br>
+define i32 @test_bsr(i32 %val) {<br>
+  %call = call i32 @llvm.x86.bit.scan.reverse.32(i32 %val)<br>
+  ret i32 %call<br>
+<br>
+; ALL-LABEL: test_bsr:<br>
+; 64-BIT:    bsrl %edi, %eax<br>
+; 32-BIT:    bsrl 4(%esp), %eax<br>
+}<br>
+<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br>
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote></div><br></div></div></div>