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<div>Thanks Andrew,</div>
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<div>I'll revert and work out what's going on. </div>
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<div>Cheers,</div>
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<div>James </div>
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On 9 May 2016, at 22:35, Andrew Adams <<a href="mailto:andrew.b.adams@gmail.com">andrew.b.adams@gmail.com</a>> wrote:<br>
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<div dir="ltr">It's possible this commit broke something. I'm seeing incorrect truncations in the loop vectorizer now:
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<div><a href="https://llvm.org/bugs/show_bug.cgi?id=27690">https://llvm.org/bugs/show_bug.cgi?id=27690</a><br>
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<div class="gmail_extra"><br>
<div class="gmail_quote">On Mon, May 9, 2016 at 7:32 AM, James Molloy via llvm-commits
<span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: jamesm<br>
Date: Mon May 9 09:32:30 2016<br>
New Revision: 268921<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=268921&view=rev" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=268921&view=rev</a><br>
Log:<br>
[VectorUtils] Query number of sign bits to allow more truncations<br>
<br>
When deciding if a vector calculation can be done in a smaller bitwidth, use sign bit information from ValueTracking to add more information and allow more truncations.<br>
<br>
Modified:<br>
llvm/trunk/lib/Analysis/VectorUtils.cpp<br>
llvm/trunk/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll<br>
<br>
Modified: llvm/trunk/lib/Analysis/VectorUtils.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/VectorUtils.cpp?rev=268921&r1=268920&r2=268921&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/VectorUtils.cpp?rev=268921&r1=268920&r2=268921&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Analysis/VectorUtils.cpp (original)<br>
+++ llvm/trunk/lib/Analysis/VectorUtils.cpp Mon May 9 09:32:30 2016<br>
@@ -320,6 +320,9 @@ llvm::computeMinimumValueSizes(ArrayRef<<br>
SmallPtrSet<Instruction *, 4> InstructionSet;<br>
MapVector<Instruction *, uint64_t> MinBWs;<br>
<br>
+ assert(Blocks.size() > 0 && "Must have at least one block!");<br>
+ const DataLayout &DL = Blocks[0]->getModule()->getDataLayout();<br>
+<br>
// Determine the roots. We work bottom-up, from truncs or icmps.<br>
bool SeenExtFromIllegalType = false;<br>
for (auto *BB : Blocks)<br>
@@ -363,12 +366,19 @@ llvm::computeMinimumValueSizes(ArrayRef<<br>
<br>
// If we encounter a type that is larger than 64 bits, we can't represent<br>
// it so bail out.<br>
- if (DB.getDemandedBits(I).getBitWidth() > 64)<br>
+ APInt NeededBits = DB.getDemandedBits(I);<br>
+ unsigned BW = NeededBits.getBitWidth();<br>
+ if (BW > 64)<br>
return MapVector<Instruction *, uint64_t>();<br>
<br>
- uint64_t V = DB.getDemandedBits(I).getZExtValue();<br>
- DBits[Leader] |= V;<br>
- DBits[I] = V;<br>
+ auto NSB = ComputeNumSignBits(I, DL);<br>
+<br>
+ // Query demanded bits for the bits required by the instruction. Remove<br>
+ // any bits that are equal to the sign bit, because we can truncate the<br>
+ // instruction without changing their value.<br>
+ NeededBits &= APInt::getLowBitsSet(BW, BW - NSB);<br>
+ DBits[Leader] |= NeededBits.getZExtValue();<br>
+ DBits[I] |= NeededBits.getZExtValue();<br>
<br>
// Casts, loads and instructions outside of our range terminate a chain<br>
// successfully.<br>
<br>
Modified: llvm/trunk/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll?rev=268921&r1=268920&r2=268921&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll?rev=268921&r1=268920&r2=268921&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll (original)<br>
+++ llvm/trunk/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll Mon May 9 09:32:30 2016<br>
@@ -263,5 +263,41 @@ for.body:<br>
br i1 %exitcond, label %for.cond.cleanup, label %for.body<br>
}<br>
<br>
+; CHECK-LABEL: @add_g<br>
+; CHECK: load <16 x i8><br>
+; CHECK: xor <16 x i8><br>
+; CHECK: icmp ult <16 x i8><br>
+; CHECK: select <16 x i1> {{.*}}, <16 x i8><br>
+; CHECK: store <16 x i8><br>
+define void @add_g(i8* noalias nocapture readonly %p, i8* noalias nocapture readonly %q, i8* noalias nocapture<br>
+%r, i8 %arg1, i32 %len) #0 {<br>
+ %1 = icmp sgt i32 %len, 0<br>
+ br i1 %1, label %.<a href="http://lr.ph" rel="noreferrer" target="_blank">lr.ph</a>, label %._crit_edge<br>
+<br>
+.<a href="http://lr.ph" rel="noreferrer" target="_blank">lr.ph</a>: ; preds = %0<br>
+ %2 = sext i8 %arg1 to i64<br>
+ br label %3<br>
+<br>
+._crit_edge: ; preds = %3, %0<br>
+ ret void<br>
+<br>
+; <label>:3 ; preds = %3, %.<a href="http://lr.ph" rel="noreferrer" target="_blank">lr.ph</a><br>
+ %indvars.iv = phi i64 [ 0, %.<a href="http://lr.ph" rel="noreferrer" target="_blank">lr.ph</a> ], [ %indvars.iv.next, %3 ]<br>
+ %x4 = getelementptr inbounds i8, i8* %p, i64 %indvars.iv<br>
+ %x5 = load i8, i8* %x4<br>
+ %x7 = getelementptr inbounds i8, i8* %q, i64 %indvars.iv<br>
+ %x8 = load i8, i8* %x7<br>
+ %x9 = zext i8 %x5 to i32<br>
+ %x10 = xor i32 %x9, 255<br>
+ %x11 = icmp ult i32 %x10, 24<br>
+ %x12 = select i1 %x11, i32 %x10, i32 24<br>
+ %x13 = trunc i32 %x12 to i8<br>
+ store i8 %x13, i8* %x4<br>
+ %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1<br>
+ %lftr.wideiv = trunc i64 %indvars.iv.next to i32<br>
+ %exitcond = icmp eq i32 %lftr.wideiv, %len<br>
+ br i1 %exitcond, label %._crit_edge, label %3<br>
+}<br>
+<br>
attributes #0 = { nounwind }<br>
<br>
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