<div dir="ltr">Thanks - confirmed fixed on my machine.<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, May 6, 2016 at 11:19 AM, Geoff Berry <span dir="ltr"><<a href="mailto:gberry@codeaurora.org" target="_blank">gberry@codeaurora.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div bgcolor="#FFFFFF" text="#000000">
<p>Sorry about that. Should be fixed by r268752<br>
</p><div><div class="h5">
<div>On 5/6/2016 1:08 PM, Sanjay Patel
wrote:<br>
</div>
<blockquote type="cite">
<div dir="ltr">I'm getting a make check failure on OSX after this
commit:<br>
<br>
$ ./llvm-lit
../../llvm/test/CodeGen/AArch64/arm64-virtual_base.ll -v<br>
-- Testing: 1 tests, 1 threads --<br>
FAIL: LLVM :: CodeGen/AArch64/arm64-virtual_base.ll (1 of 1)<br>
******************** TEST 'LLVM ::
CodeGen/AArch64/arm64-virtual_base.ll' FAILED
********************<br>
Script:<br>
--<br>
llc <
/Users/spatel/myllvm/llvm/test/CodeGen/AArch64/arm64-virtual_base.ll
-O3 -march arm64 | FileCheck
/Users/spatel/myllvm/llvm/test/CodeGen/AArch64/arm64-virtual_base.ll<br>
--<br>
Exit Code: 1<br>
<br>
Command Output (stderr):<br>
--<br>
/Users/spatel/myllvm/llvm/test/CodeGen/AArch64/arm64-virtual_base.ll:37:15:
error: CHECK-NEXT: is not on the line after the previous match<br>
; CHECK-NEXT: str [[VAL]], [sp, #232]<br>
^<br>
<stdin>:18:2: note: 'next' match was here<br>
str x8, [sp, #232]<br>
^<br>
<stdin>:16:20: note: previous match ended here<br>
ldr x8, [x0, #288]<br>
^<br>
<stdin>:17:1: note: non-matching line after previous match
is here<br>
ldp x28, x27, [sp, #384] ; 8-byte Folded Reload<br>
^<br>
<br>
--<br>
<br>
********************<br>
Testing Time: 0.47s<br>
********************<br>
Failing Tests (1):<br>
LLVM :: CodeGen/AArch64/arm64-virtual_base.ll<br>
<br>
Unexpected Failures: 1<br>
<br>
</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Fri, May 6, 2016 at 10:35 AM, Geoff
Berry via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank"></a><a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author:
gberry<br>
Date: Fri May 6 11:34:59 2016<br>
New Revision: 268746<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=268746&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=268746&view=rev</a><br>
Log:<br>
[AArch64] Combine callee-save and local stack SP adjustment
instructions.<br>
<br>
Summary:<br>
If a function needs to allocate both callee-save stack
memory and local<br>
stack memory, we currently decrement/increment the SP in two
steps:<br>
first for the callee-save area, and then for the local stack
area. This<br>
changes the code to allocate them both at once at the very
beginning/end<br>
of the function. This has two benefits:<br>
<br>
1) there is one fewer sub/add micro-op in the
prologue/epilogue<br>
<br>
2) the stack adjustment instructions act as a scheduling
barrier, so<br>
moving them to the very beginning/end of the function
increases post-RA<br>
scheduler's ability to move instructions (that only depend
on argument<br>
registers) before any of the callee-save stores<br>
<br>
This change can cause an increase in instructions if the
original local<br>
stack SP decrement could be folded into the first store to
the stack.<br>
This occurs when the first local stack store is to stack
offset 0. In<br>
this case we are trading off one more sub instruction for
one fewer sub<br>
micro-op (along with benefits (2) and (3) above).<br>
<br>
Reviewers: t.p.northover<br>
<br>
Subscribers: aemerson, rengolin, mcrosier, llvm-commits<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D18619" rel="noreferrer" target="_blank">http://reviews.llvm.org/D18619</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.h<br>
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp<br>
llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-aapcs-be.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-join-reserved.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-shrink-wrapping.ll<br>
llvm/trunk/test/CodeGen/AArch64/fastcc.ll<br>
llvm/trunk/test/CodeGen/AArch64/func-calls.ll<br>
llvm/trunk/test/CodeGen/AArch64/tailcall-implicit-sret.ll<br>
llvm/trunk/test/DebugInfo/AArch64/prologue_end.ll<br>
<br>
Modified:
llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
(original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
Fri May 6 11:34:59 2016<br>
@@ -283,6 +283,127 @@ bool
AArch64FrameLowering::canUseAsProlo<br>
return findScratchNonCalleeSaveRegister(TmpMBB) !=
AArch64::NoRegister;<br>
}<br>
<br>
+bool AArch64FrameLowering::shouldCombineCSRLocalStackBump(<br>
+ MachineFunction &MF, unsigned StackBumpBytes) const
{<br>
+ AArch64FunctionInfo *AFI =
MF.getInfo<AArch64FunctionInfo>();<br>
+ const MachineFrameInfo *MFI = MF.getFrameInfo();<br>
+ const AArch64Subtarget &Subtarget =
MF.getSubtarget<AArch64Subtarget>();<br>
+ const AArch64RegisterInfo *RegInfo =
Subtarget.getRegisterInfo();<br>
+<br>
+ if (AFI->getLocalStackSize() == 0)<br>
+ return false;<br>
+<br>
+ // 512 is the maximum immediate for stp/ldp that will be
used for<br>
+ // callee-save save/restores<br>
+ if (StackBumpBytes >= 512)<br>
+ return false;<br>
+<br>
+ if (MFI->hasVarSizedObjects())<br>
+ return false;<br>
+<br>
+ if (RegInfo->needsStackRealignment(MF))<br>
+ return false;<br>
+<br>
+ // This isn't strictly necessary, but it simplifies
things a bit since the<br>
+ // current RedZone handling code assumes the SP is
adjusted by the<br>
+ // callee-save save/restore code.<br>
+ if (canUseRedZone(MF))<br>
+ return false;<br>
+<br>
+ return true;<br>
+}<br>
+<br>
+// Convert callee-save register save/restore instruction to
do stack pointer<br>
+// decrement/increment to allocate/deallocate the
callee-save stack area by<br>
+// converting store/load to use pre/post increment version.<br>
+static MachineBasicBlock::iterator
convertCalleeSaveRestoreToSPPrePostIncDec(<br>
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator
MBBI, DebugLoc DL,<br>
+ const TargetInstrInfo *TII, int CSStackSizeInc) {<br>
+<br>
+ unsigned NewOpc;<br>
+ bool NewIsUnscaled = false;<br>
+ switch (MBBI->getOpcode()) {<br>
+ default:<br>
+ llvm_unreachable("Unexpected callee-save save/restore
opcode!");<br>
+ case AArch64::STPXi:<br>
+ NewOpc = AArch64::STPXpre;<br>
+ break;<br>
+ case AArch64::STPDi:<br>
+ NewOpc = AArch64::STPDpre;<br>
+ break;<br>
+ case AArch64::STRXui:<br>
+ NewOpc = AArch64::STRXpre;<br>
+ NewIsUnscaled = true;<br>
+ break;<br>
+ case AArch64::STRDui:<br>
+ NewOpc = AArch64::STRDpre;<br>
+ NewIsUnscaled = true;<br>
+ break;<br>
+ case AArch64::LDPXi:<br>
+ NewOpc = AArch64::LDPXpost;<br>
+ break;<br>
+ case AArch64::LDPDi:<br>
+ NewOpc = AArch64::LDPDpost;<br>
+ break;<br>
+ case AArch64::LDRXui:<br>
+ NewOpc = AArch64::LDRXpost;<br>
+ NewIsUnscaled = true;<br>
+ break;<br>
+ case AArch64::LDRDui:<br>
+ NewOpc = AArch64::LDRDpost;<br>
+ NewIsUnscaled = true;<br>
+ break;<br>
+ }<br>
+<br>
+ MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL,
TII->get(NewOpc));<br>
+ MIB.addReg(AArch64::SP, RegState::Define);<br>
+<br>
+ // Copy all operands other than the immediate offset.<br>
+ unsigned OpndIdx = 0;<br>
+ for (unsigned OpndEnd = MBBI->getNumOperands() - 1;
OpndIdx < OpndEnd;<br>
+ ++OpndIdx)<br>
+ MIB.addOperand(MBBI->getOperand(OpndIdx));<br>
+<br>
+ assert(MBBI->getOperand(OpndIdx).getImm() == 0
&&<br>
+ "Unexpected immediate offset in first/last
callee-save save/restore "<br>
+ "instruction!");<br>
+ assert(MBBI->getOperand(OpndIdx - 1).getReg() ==
AArch64::SP &&<br>
+ "Unexpected base register in callee-save
save/restore instruction!");<br>
+ // Last operand is immediate offset that needs fixing.<br>
+ assert(CSStackSizeInc % 8 == 0);<br>
+ int64_t CSStackSizeIncImm = CSStackSizeInc;<br>
+ if (!NewIsUnscaled)<br>
+ CSStackSizeIncImm /= 8;<br>
+ MIB.addImm(CSStackSizeIncImm);<br>
+<br>
+ MIB.setMIFlags(MBBI->getFlags());<br>
+ MIB.setMemRefs(MBBI->memoperands_begin(),
MBBI->memoperands_end());<br>
+<br>
+ return std::prev(MBB.erase(MBBI));<br>
+}<br>
+<br>
+// Fixup callee-save register save/restore instructions to
take into account<br>
+// combined SP bump by adding the local stack size to the
stack offsets.<br>
+static void fixupCalleeSaveRestoreStackOffset(MachineInstr
*MI,<br>
+ unsigned
LocalStackSize) {<br>
+ unsigned Opc = MI->getOpcode();<br>
+ (void)Opc;<br>
+ assert((Opc == AArch64::STPXi || Opc == AArch64::STPDi ||<br>
+ Opc == AArch64::STRXui || Opc == AArch64::STRDui
||<br>
+ Opc == AArch64::LDPXi || Opc == AArch64::LDPDi ||<br>
+ Opc == AArch64::LDRXui || Opc == AArch64::LDRDui)
&&<br>
+ "Unexpected callee-save save/restore opcode!");<br>
+<br>
+ unsigned OffsetIdx = MI->getNumExplicitOperands() - 1;<br>
+ assert(MI->getOperand(OffsetIdx - 1).getReg() ==
AArch64::SP &&<br>
+ "Unexpected base register in callee-save
save/restore instruction!");<br>
+ // Last operand is immediate offset that needs fixing.<br>
+ MachineOperand &OffsetOpnd =
MI->getOperand(OffsetIdx);<br>
+ // All generated opcodes have scaled offsets.<br>
+ assert(LocalStackSize % 8 == 0);<br>
+ OffsetOpnd.setImm(OffsetOpnd.getImm() + LocalStackSize /
8);<br>
+}<br>
+<br>
void AArch64FrameLowering::emitPrologue(MachineFunction
&MF,<br>
MachineBasicBlock
&MBB) const {<br>
MachineBasicBlock::iterator MBBI = MBB.begin();<br>
@@ -334,18 +455,36 @@ void
AArch64FrameLowering::emitPrologue(<br>
return;<br>
}<br>
<br>
- NumBytes -= AFI->getCalleeSavedStackSize();<br>
- assert(NumBytes >= 0 && "Negative stack
allocation size!?");<br>
+ auto CSStackSize = AFI->getCalleeSavedStackSize();<br>
// All of the remaining stack allocations are for locals.<br>
- AFI->setLocalStackSize(NumBytes);<br>
+ AFI->setLocalStackSize(NumBytes - CSStackSize);<br>
+<br>
+ bool CombineSPBump = shouldCombineCSRLocalStackBump(MF,
NumBytes);<br>
+ if (CombineSPBump) {<br>
+ emitFrameOffset(MBB, MBBI, DL, AArch64::SP,
AArch64::SP, -NumBytes, TII,<br>
+ MachineInstr::FrameSetup);<br>
+ NumBytes = 0;<br>
+ } else if (CSStackSize != 0) {<br>
+ MBBI = convertCalleeSaveRestoreToSPPrePostIncDec(MBB,
MBBI, DL, TII,<br>
+
-CSStackSize);<br>
+ NumBytes -= CSStackSize;<br>
+ }<br>
+ assert(NumBytes >= 0 && "Negative stack
allocation size!?");<br>
<br>
- // Move past the saves of the callee-saved registers.<br>
+ // Move past the saves of the callee-saved registers,
fixing up the offsets<br>
+ // and pre-inc if we decided to combine the callee-save
and local stack<br>
+ // pointer bump above.<br>
MachineBasicBlock::iterator End = MBB.end();<br>
- while (MBBI != End &&
MBBI->getFlag(MachineInstr::FrameSetup))<br>
+ while (MBBI != End &&
MBBI->getFlag(MachineInstr::FrameSetup)) {<br>
+ if (CombineSPBump)<br>
+ fixupCalleeSaveRestoreStackOffset(MBBI,
AFI->getLocalStackSize());<br>
++MBBI;<br>
+ }<br>
if (HasFP) {<br>
// Only set up FP if we actually need to. Frame pointer
is fp = sp - 16.<br>
- int FPOffset = AFI->getCalleeSavedStackSize() - 16;<br>
+ int FPOffset = CSStackSize - 16;<br>
+ if (CombineSPBump)<br>
+ FPOffset += AFI->getLocalStackSize();<br>
<br>
// Issue sub fp, sp, FPOffset or<br>
// mov fp,sp when FPOffset is zero.<br>
@@ -569,6 +708,13 @@ void
AArch64FrameLowering::emitEpilogue(<br>
// AArch64TargetLowering::LowerCall figures out
ArgumentPopSize and keeps<br>
// it as the 2nd argument of AArch64ISD::TC_RETURN.<br>
<br>
+ auto CSStackSize = AFI->getCalleeSavedStackSize();<br>
+ bool CombineSPBump = shouldCombineCSRLocalStackBump(MF,
NumBytes);<br>
+<br>
+ if (!CombineSPBump && CSStackSize != 0)<br>
+ convertCalleeSaveRestoreToSPPrePostIncDec(<br>
+ MBB, std::prev(MBB.getFirstTerminator()), DL, TII,
CSStackSize);<br>
+<br>
// Move past the restores of the callee-saved registers.<br>
MachineBasicBlock::iterator LastPopI =
MBB.getFirstTerminator();<br>
MachineBasicBlock::iterator Begin = MBB.begin();<br>
@@ -577,9 +723,19 @@ void
AArch64FrameLowering::emitEpilogue(<br>
if (!LastPopI->getFlag(MachineInstr::FrameDestroy))
{<br>
++LastPopI;<br>
break;<br>
- }<br>
+ } else if (CombineSPBump)<br>
+ fixupCalleeSaveRestoreStackOffset(LastPopI,
AFI->getLocalStackSize());<br>
}<br>
- NumBytes -= AFI->getCalleeSavedStackSize();<br>
+<br>
+ // If there is a single SP update, insert it before the
ret and we're done.<br>
+ if (CombineSPBump) {<br>
+ emitFrameOffset(MBB, MBB.getFirstTerminator(), DL,
AArch64::SP, AArch64::SP,<br>
+ NumBytes + ArgumentPopSize, TII,<br>
+ MachineInstr::FrameDestroy);<br>
+ return;<br>
+ }<br>
+<br>
+ NumBytes -= CSStackSize;<br>
assert(NumBytes >= 0 && "Negative stack
allocation size!?");<br>
<br>
if (!hasFP(MF)) {<br>
@@ -589,7 +745,7 @@ void AArch64FrameLowering::emitEpilogue(<br>
if (RedZone && ArgumentPopSize == 0)<br>
return;<br>
<br>
- bool NoCalleeSaveRestore =
AFI->getCalleeSavedStackSize() == 0;<br>
+ bool NoCalleeSaveRestore = CSStackSize == 0;<br>
int StackRestoreBytes = RedZone ? 0 : NumBytes;<br>
if (NoCalleeSaveRestore)<br>
StackRestoreBytes += ArgumentPopSize;<br>
@@ -608,8 +764,7 @@ void AArch64FrameLowering::emitEpilogue(<br>
// be able to save any instructions.<br>
if (MFI->hasVarSizedObjects() ||
AFI->isStackRealigned())<br>
emitFrameOffset(MBB, LastPopI, DL, AArch64::SP,
AArch64::FP,<br>
- -AFI->getCalleeSavedStackSize() +
16, TII,<br>
- MachineInstr::FrameDestroy);<br>
+ -CSStackSize + 16, TII,
MachineInstr::FrameDestroy);<br>
else if (NumBytes)<br>
emitFrameOffset(MBB, LastPopI, DL, AArch64::SP,
AArch64::SP, NumBytes, TII,<br>
MachineInstr::FrameDestroy);<br>
@@ -799,14 +954,6 @@ static void
computeCalleeSaveRegisterPai<br>
if (RPI.isPaired())<br>
++i;<br>
}<br>
-<br>
- // Align first offset to even 16-byte boundary to avoid
additional SP<br>
- // adjustment instructions.<br>
- // Last pair offset is size of whole callee-save region
for SP<br>
- // pre-dec/post-inc.<br>
- RegPairInfo &LastPair = RegPairs.back();<br>
- assert(AFI->getCalleeSavedStackSize() % 8 == 0);<br>
- LastPair.Offset = AFI->getCalleeSavedStackSize() / 8;<br>
}<br>
<br>
bool AArch64FrameLowering::spillCalleeSavedRegisters(<br>
@@ -827,29 +974,20 @@ bool
AArch64FrameLowering::spillCalleeSa<br>
unsigned Reg2 = RPI.Reg2;<br>
unsigned StrOpc;<br>
<br>
- // Issue sequence of non-sp increment and pi sp spills
for cs regs. The<br>
- // first spill is a pre-increment that allocates the
stack.<br>
+ // Issue sequence of spills for cs regs. The first
spill may be converted<br>
+ // to a pre-decrement store later by emitPrologue if
the callee-save stack<br>
+ // area allocation can't be combined with the local
stack area allocation.<br>
// For example:<br>
- // stp x22, x21, [sp, #-48]! // addImm(-6)<br>
+ // stp x22, x21, [sp, #0] // addImm(+0)<br>
// stp x20, x19, [sp, #16] // addImm(+2)<br>
// stp fp, lr, [sp, #32] // addImm(+4)<br>
// Rationale: This sequence saves uop updates compared
to a sequence of<br>
// pre-increment spills like stp xi,xj,[sp,#-16]!<br>
// Note: Similar rationale and sequence for restores in
epilog.<br>
- bool BumpSP = RPII == RegPairs.rbegin();<br>
- if (RPI.IsGPR) {<br>
- // For first spill use pre-increment store.<br>
- if (BumpSP)<br>
- StrOpc = RPI.isPaired() ? AArch64::STPXpre :
AArch64::STRXpre;<br>
- else<br>
- StrOpc = RPI.isPaired() ? AArch64::STPXi :
AArch64::STRXui;<br>
- } else {<br>
- // For first spill use pre-increment store.<br>
- if (BumpSP)<br>
- StrOpc = RPI.isPaired() ? AArch64::STPDpre :
AArch64::STRDpre;<br>
- else<br>
- StrOpc = RPI.isPaired() ? AArch64::STPDi :
AArch64::STRDui;<br>
- }<br>
+ if (RPI.IsGPR)<br>
+ StrOpc = RPI.isPaired() ? AArch64::STPXi :
AArch64::STRXui;<br>
+ else<br>
+ StrOpc = RPI.isPaired() ? AArch64::STPDi :
AArch64::STRDui;<br>
DEBUG(dbgs() << "CSR spill: (" <<
TRI->getName(Reg1);<br>
if (RPI.isPaired())<br>
dbgs() << ", " <<
TRI->getName(Reg2);<br>
@@ -858,29 +996,19 @@ bool
AArch64FrameLowering::spillCalleeSa<br>
dbgs() << ", " << RPI.FrameIdx+1;<br>
dbgs() << ")\n");<br>
<br>
- const int Offset = BumpSP ? -RPI.Offset : RPI.Offset;<br>
MachineInstrBuilder MIB = BuildMI(MBB, MI, DL,
TII.get(StrOpc));<br>
- if (BumpSP)<br>
- MIB.addReg(AArch64::SP, RegState::Define);<br>
-<br>
+ MBB.addLiveIn(Reg1);<br>
if (RPI.isPaired()) {<br>
- MBB.addLiveIn(Reg1);<br>
MBB.addLiveIn(Reg2);<br>
- MIB.addReg(Reg2, getPrologueDeath(MF, Reg2))<br>
- .addReg(Reg1, getPrologueDeath(MF, Reg1))<br>
- .addReg(AArch64::SP)<br>
- .addImm(Offset) // [sp, #offset * 8], where factor
* 8 is implicit<br>
- .setMIFlag(MachineInstr::FrameSetup);<br>
+ MIB.addReg(Reg2, getPrologueDeath(MF, Reg2));<br>
MIB.addMemOperand(MF.getMachineMemOperand(<br>
MachinePointerInfo::getFixedStack(MF,
RPI.FrameIdx + 1),<br>
MachineMemOperand::MOStore, 8, 8));<br>
- } else {<br>
- MBB.addLiveIn(Reg1);<br>
- MIB.addReg(Reg1, getPrologueDeath(MF, Reg1))<br>
+ }<br>
+ MIB.addReg(Reg1, getPrologueDeath(MF, Reg1))<br>
.addReg(AArch64::SP)<br>
- .addImm(BumpSP ? Offset * 8 : Offset) // pre-inc
version is unscaled<br>
+ .addImm(RPI.Offset) // [sp, #offset*8], where
factor*8 is implicit<br>
.setMIFlag(MachineInstr::FrameSetup);<br>
- }<br>
MIB.addMemOperand(MF.getMachineMemOperand(<br>
MachinePointerInfo::getFixedStack(MF,
RPI.FrameIdx),<br>
MachineMemOperand::MOStore, 8, 8));<br>
@@ -908,26 +1036,19 @@ bool
AArch64FrameLowering::restoreCallee<br>
unsigned Reg1 = RPI.Reg1;<br>
unsigned Reg2 = RPI.Reg2;<br>
<br>
- // Issue sequence of non-sp increment and sp-pi
restores for cs regs. Only<br>
- // the last load is sp-pi post-increment and
de-allocates the stack:<br>
+ // Issue sequence of restores for cs regs. The last
restore may be converted<br>
+ // to a post-increment load later by emitEpilogue if
the callee-save stack<br>
+ // area allocation can't be combined with the local
stack area allocation.<br>
// For example:<br>
// ldp fp, lr, [sp, #32] // addImm(+4)<br>
// ldp x20, x19, [sp, #16] // addImm(+2)<br>
- // ldp x22, x21, [sp], #48 // addImm(+6)<br>
+ // ldp x22, x21, [sp, #0] // addImm(+0)<br>
// Note: see comment in spillCalleeSavedRegisters()<br>
unsigned LdrOpc;<br>
- bool BumpSP = RPII == std::prev(RegPairs.end());<br>
- if (RPI.IsGPR) {<br>
- if (BumpSP)<br>
- LdrOpc = RPI.isPaired() ? AArch64::LDPXpost :
AArch64::LDRXpost;<br>
- else<br>
- LdrOpc = RPI.isPaired() ? AArch64::LDPXi :
AArch64::LDRXui;<br>
- } else {<br>
- if (BumpSP)<br>
- LdrOpc = RPI.isPaired() ? AArch64::LDPDpost :
AArch64::LDRDpost;<br>
- else<br>
- LdrOpc = RPI.isPaired() ? AArch64::LDPDi :
AArch64::LDRDui;<br>
- }<br>
+ if (RPI.IsGPR)<br>
+ LdrOpc = RPI.isPaired() ? AArch64::LDPXi :
AArch64::LDRXui;<br>
+ else<br>
+ LdrOpc = RPI.isPaired() ? AArch64::LDPDi :
AArch64::LDRDui;<br>
DEBUG(dbgs() << "CSR restore: (" <<
TRI->getName(Reg1);<br>
if (RPI.isPaired())<br>
dbgs() << ", " <<
TRI->getName(Reg2);<br>
@@ -936,27 +1057,17 @@ bool
AArch64FrameLowering::restoreCallee<br>
dbgs() << ", " << RPI.FrameIdx+1;<br>
dbgs() << ")\n");<br>
<br>
- const int Offset = RPI.Offset;<br>
MachineInstrBuilder MIB = BuildMI(MBB, MI, DL,
TII.get(LdrOpc));<br>
- if (BumpSP)<br>
- MIB.addReg(AArch64::SP, RegState::Define);<br>
-<br>
if (RPI.isPaired()) {<br>
- MIB.addReg(Reg2, getDefRegState(true))<br>
- .addReg(Reg1, getDefRegState(true))<br>
- .addReg(AArch64::SP)<br>
- .addImm(Offset) // [sp], #offset * 8 or [sp,
#offset * 8]<br>
- // where the factor * 8 is implicit<br>
- .setMIFlag(MachineInstr::FrameDestroy);<br>
+ MIB.addReg(Reg2, getDefRegState(true));<br>
MIB.addMemOperand(MF.getMachineMemOperand(<br>
MachinePointerInfo::getFixedStack(MF,
RPI.FrameIdx + 1),<br>
MachineMemOperand::MOLoad, 8, 8));<br>
- } else {<br>
- MIB.addReg(Reg1, getDefRegState(true))<br>
+ }<br>
+ MIB.addReg(Reg1, getDefRegState(true))<br>
.addReg(AArch64::SP)<br>
- .addImm(BumpSP ? Offset * 8 : Offset) // post-dec
version is unscaled<br>
+ .addImm(RPI.Offset) // [sp, #offset*8] where the
factor*8 is implicit<br>
.setMIFlag(MachineInstr::FrameDestroy);<br>
- }<br>
MIB.addMemOperand(MF.getMachineMemOperand(<br>
MachinePointerInfo::getFixedStack(MF,
RPI.FrameIdx),<br>
MachineMemOperand::MOLoad, 8, 8));<br>
<br>
Modified:
llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.h?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.h?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.h
(original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.h Fri
May 6 11:34:59 2016<br>
@@ -66,6 +66,10 @@ public:<br>
bool enableShrinkWrapping(const MachineFunction &MF)
const override {<br>
return true;<br>
}<br>
+<br>
+private:<br>
+ bool shouldCombineCSRLocalStackBump(MachineFunction
&MF,<br>
+ unsigned
StackBumpBytes) const;<br>
};<br>
<br>
} // End llvm namespace<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
(original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Fri
May 6 11:34:59 2016<br>
@@ -2393,6 +2393,9 @@ void
llvm::emitFrameOffset(MachineBasicB<br>
if (DestReg == SrcReg && Offset == 0)<br>
return;<br>
<br>
+ assert((DestReg != AArch64::SP || Offset % 16 == 0)
&&<br>
+ "SP increment/decrement not 16-byte aligned");<br>
+<br>
bool isSub = Offset < 0;<br>
if (isSub)<br>
Offset = -Offset;<br>
<br>
Modified:
llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
---
llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
(original)<br>
+++
llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
Fri May 6 11:34:59 2016<br>
@@ -98,8 +98,8 @@ entry:<br>
; CHECK-LABEL: novla_nodynamicrealign_call<br>
; CHECK: .cfi_startproc<br>
; Check that used callee-saved registers are saved<br>
-; CHECK: stp x19, x30, [sp, #-16]!<br>
-; CHECK: sub sp, sp, #16<br>
+; CHECK: sub sp, sp, #32<br>
+; CHECK: stp x19, x30, [sp, #16]<br>
; Check correctness of cfi pseudo-instructions<br>
; CHECK: .cfi_def_cfa_offset 32<br>
; CHECK: .cfi_offset w30, -8<br>
@@ -110,17 +110,18 @@ entry:<br>
; Check correct access to local variable on the stack,
through stack pointer<br>
; CHECK: ldr w[[ILOC:[0-9]+]], [sp, #12]<br>
; Check epilogue:<br>
-; CHECK: ldp x19, x30, [sp], #16<br>
+; CHECK: ldp x19, x30, [sp, #16]<br>
; CHECK: ret<br>
; CHECK: .cfi_endproc<br>
<br>
; CHECK-MACHO-LABEL: _novla_nodynamicrealign_call:<br>
; CHECK-MACHO: .cfi_startproc<br>
; Check that used callee-saved registers are saved<br>
-; CHECK-MACHO: stp x20, x19, [sp, #-32]!<br>
+; CHECK-MACHO: sub sp, sp, #48<br>
+; CHECK-MACHO: stp x20, x19, [sp, #16]<br>
; Check that the frame pointer is created:<br>
-; CHECK-MACHO: stp x29, x30, [sp, #16]<br>
-; CHECK-MACHO: add x29, sp, #16<br>
+; CHECK-MACHO: stp x29, x30, [sp, #32]<br>
+; CHECK-MACHO: add x29, sp, #32<br>
; Check correctness of cfi pseudo-instructions<br>
; CHECK-MACHO: .cfi_def_cfa w29, 16<br>
; CHECK-MACHO: .cfi_offset w30, -8<br>
@@ -133,8 +134,8 @@ entry:<br>
; Check correct access to local variable on the stack,
through stack pointer<br>
; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [sp, #12]<br>
; Check epilogue:<br>
-; CHECK-MACHO: ldp x29, x30, [sp, #16]<br>
-; CHECK-MACHO: ldp x20, x19, [sp], #32<br>
+; CHECK-MACHO: ldp x29, x30, [sp, #32]<br>
+; CHECK-MACHO: ldp x20, x19, [sp, #16]<br>
; CHECK-MACHO: ret<br>
; CHECK-MACHO: .cfi_endproc<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-aapcs-be.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-aapcs-be.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-aapcs-be.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-aapcs-be.ll
(original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-aapcs-be.ll Fri
May 6 11:34:59 2016<br>
@@ -32,7 +32,8 @@ define float @test_block_addr([8 x float<br>
<br>
define void @test_block_addr_callee() {<br>
; CHECK-LABEL: test_block_addr_callee:<br>
-; CHECK: str {{[a-z0-9]+}}, [sp, #-16]!<br>
+; CHECK: sub sp, sp, #32<br>
+; CHECK: str {{[a-z0-9]+}}, [sp, #16]<br>
; CHECK: bl test_block_addr<br>
%val = insertvalue [1 x float] undef, float 0.0, 0<br>
call float @test_block_addr([8 x float] undef, [1 x
float] %val)<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll Fri May 6
11:34:59 2016<br>
@@ -130,7 +130,7 @@ entry:<br>
; CHECK-LABEL: test3<br>
; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]<br>
; FAST-LABEL: test3<br>
-; FAST: sub sp, sp, #32<br>
+; FAST: sub sp, sp, #48<br>
; FAST: mov x[[ADDR:[0-9]+]], sp<br>
; FAST: str [[REG_1:d[0-9]+]], [x[[ADDR]], #8]<br>
%0 = load <2 x i32>, <2 x i32>* %in, align 8<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll
(original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll Fri
May 6 11:34:59 2016<br>
@@ -291,7 +291,7 @@ entry:<br>
; Space for s2 is allocated at sp<br>
<br>
; FAST-LABEL: caller42<br>
-; FAST: sub sp, sp, #96<br>
+; FAST: sub sp, sp, #112<br>
; Space for s1 is allocated at fp-24 = sp+72<br>
; Space for s2 is allocated at sp+48<br>
; FAST: sub x[[A:[0-9]+]], x29, #24<br>
@@ -317,8 +317,8 @@ declare i32 @f42_stack(i32 %i, i32 %i2,<br>
define i32 @caller42_stack() #3 {<br>
entry:<br>
; CHECK-LABEL: caller42_stack<br>
-; CHECK: mov x29, sp<br>
-; CHECK: sub sp, sp, #96<br>
+; CHECK: sub sp, sp, #112<br>
+; CHECK: add x29, sp, #96<br>
; CHECK: stur {{x[0-9]+}}, [x29, #-16]<br>
; CHECK: stur {{q[0-9]+}}, [x29, #-32]<br>
; CHECK: str {{x[0-9]+}}, [sp, #48]<br>
@@ -399,7 +399,7 @@ entry:<br>
; Space for s2 is allocated at sp<br>
<br>
; FAST-LABEL: caller43<br>
-; FAST: mov x29, sp<br>
+; FAST: add x29, sp, #64<br>
; Space for s1 is allocated at sp+32<br>
; Space for s2 is allocated at sp<br>
; FAST: add x1, sp, #32<br>
@@ -429,8 +429,8 @@ declare i32 @f43_stack(i32 %i, i32 %i2,<br>
define i32 @caller43_stack() #3 {<br>
entry:<br>
; CHECK-LABEL: caller43_stack<br>
-; CHECK: mov x29, sp<br>
-; CHECK: sub sp, sp, #96<br>
+; CHECK: sub sp, sp, #112<br>
+; CHECK: add x29, sp, #96<br>
; CHECK: stur {{q[0-9]+}}, [x29, #-16]<br>
; CHECK: stur {{q[0-9]+}}, [x29, #-32]<br>
; CHECK: str {{q[0-9]+}}, [sp, #48]<br>
@@ -446,7 +446,7 @@ entry:<br>
; CHECK: str w[[C]], [sp]<br>
<br>
; FAST-LABEL: caller43_stack<br>
-; FAST: sub sp, sp, #96<br>
+; FAST: sub sp, sp, #112<br>
; Space for s1 is allocated at fp-32 = sp+64<br>
; Space for s2 is allocated at sp+32<br>
; FAST: sub x[[A:[0-9]+]], x29, #32<br>
@@ -508,7 +508,7 @@ entry:<br>
; "i64 %0" should be in register x7.<br>
; "i32 8" should be on stack at [sp].<br>
; CHECK: ldr x7, [{{x[0-9]+}}]<br>
-; CHECK: str {{w[0-9]+}}, [sp, #-16]!<br>
+; CHECK: str {{w[0-9]+}}, [sp]<br>
; FAST-LABEL: i64_split<br>
; FAST: ldr x7, [{{x[0-9]+}}]<br>
; FAST: mov x[[R0:[0-9]+]], sp<br>
<br>
Modified:
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
---
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll
(original)<br>
+++
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll
Fri May 6 11:34:59 2016<br>
@@ -14,7 +14,7 @@ entry:<br>
define void @main() nounwind {<br>
entry:<br>
; CHECK: main<br>
-; CHECK: mov x29, sp<br>
+; CHECK: add x29, sp, #16<br>
; CHECK: mov [[REG:x[0-9]+]], sp<br>
; CHECK-NEXT: add x0, [[REG]], #8<br>
%E = alloca %struct.S2Ty, align 4<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll
(original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll Fri May
6 11:34:59 2016<br>
@@ -2,26 +2,26 @@<br>
; RUN: llc < %s -mtriple=arm64-linux-gnu
-disable-post-ra | FileCheck %s --check-prefix=CHECK-LINUX<br>
<br>
; CHECK-LABEL: main:<br>
-; CHECK: stp x29, x30, [sp, #-16]!<br>
-; CHECK-NEXT: mov x29, sp<br>
-; CHECK-NEXT: sub sp, sp, #16<br>
+; CHECK: sub sp, sp, #32<br>
+; CHECK-NEXT: stp x29, x30, [sp, #16]<br>
+; CHECK-NEXT: add x29, sp, #16<br>
; CHECK-NEXT: stur wzr, [x29, #-4]<br>
; CHECK: adrp x0, L_.str@PAGE<br>
; CHECK: add x0, x0, L_.str@PAGEOFF<br>
; CHECK-NEXT: bl _puts<br>
-; CHECK-NEXT: add sp, sp, #16<br>
-; CHECK-NEXT: ldp x29, x30, [sp], #16<br>
+; CHECK-NEXT: ldp x29, x30, [sp, #16]<br>
+; CHECK-NEXT: add sp, sp, #32<br>
; CHECK-NEXT: ret<br>
<br>
; CHECK-LINUX-LABEL: main:<br>
-; CHECK-LINUX: str x30, [sp, #-16]!<br>
-; CHECK-LINUX-NEXT: sub sp, sp, #16<br>
+; CHECK-LINUX: sub sp, sp, #32<br>
+; CHECK-LINUX-NEXT: str x30, [sp, #16]<br>
; CHECK-LINUX-NEXT: str wzr, [sp, #12]<br>
; CHECK-LINUX: adrp x0, .L.str<br>
; CHECK-LINUX: add x0, x0, :lo12:.L.str<br>
; CHECK-LINUX-NEXT: bl puts<br>
-; CHECK-LINUX-NEXT: add sp, sp, #16<br>
-; CHECK-LINUX-NEXT: ldr x30, [sp], #16<br>
+; CHECK-LINUX-NEXT: ldr x30, [sp, #16]<br>
+; CHECK-LINUX-NEXT: add sp, sp, #32<br>
; CHECK-LINUX-NEXT: ret<br>
<br>
@.str = private unnamed_addr constant [7 x i8]
c"hello\0A\00"<br>
<br>
Modified:
llvm/trunk/test/CodeGen/AArch64/arm64-join-reserved.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-join-reserved.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-join-reserved.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-join-reserved.ll
(original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-join-reserved.ll
Fri May 6 11:34:59 2016<br>
@@ -5,7 +5,7 @@ target triple = "arm64-apple-macosx10"<br>
; A move isn't necessary.<br>
; <rdar://problem/11492712><br>
; CHECK-LABEL: g:<br>
-; CHECK: str xzr, [sp, #-16]!<br>
+; CHECK: str xzr, [sp]<br>
; CHECK: bl<br>
; CHECK: ret<br>
define void @g() nounwind ssp {<br>
<br>
Modified:
llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
---
llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
(original)<br>
+++
llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
Fri May 6 11:34:59 2016<br>
@@ -7,7 +7,7 @@ define void @jscall_patchpoint_codegen(i<br>
entry:<br>
; CHECK-LABEL: jscall_patchpoint_codegen:<br>
; CHECK: Ltmp<br>
-; CHECK: str x{{.+}}, [sp, #-16]!<br>
+; CHECK: str x{{.+}}, [sp]<br>
; CHECK-NEXT: mov x0, x{{.+}}<br>
; CHECK: Ltmp<br>
; CHECK-NEXT: movz x16, #0xffff, lsl #32<br>
@@ -16,7 +16,7 @@ entry:<br>
; CHECK-NEXT: blr x16<br>
; FAST-LABEL: jscall_patchpoint_codegen:<br>
; FAST: Ltmp<br>
-; FAST: str x{{.+}}, [sp, #-16]!<br>
+; FAST: str x{{.+}}, [sp]<br>
; FAST: Ltmp<br>
; FAST-NEXT: movz x16, #0xffff, lsl #32<br>
; FAST-NEXT: movk x16, #0xdead, lsl #16<br>
@@ -50,7 +50,7 @@ entry:<br>
; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2<br>
; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4<br>
; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6<br>
-; FAST-NEXT: str [[REG1]], [sp, #-32]!<br>
+; FAST-NEXT: str [[REG1]], [sp]<br>
; FAST-NEXT: str [[REG2]], [sp, #16]<br>
; FAST-NEXT: str [[REG3]], [sp, #24]<br>
; FAST: Ltmp<br>
@@ -90,7 +90,7 @@ entry:<br>
; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6<br>
; FAST-NEXT: orr [[REG4:w[0-9]+]], wzr, #0x8<br>
; FAST-NEXT: movz [[REG5:x[0-9]+]], #0xa<br>
-; FAST-NEXT: str [[REG1]], [sp, #-64]!<br>
+; FAST-NEXT: str [[REG1]], [sp]<br>
; FAST-NEXT: str [[REG2]], [sp, #16]<br>
; FAST-NEXT: str [[REG3]], [sp, #24]<br>
; FAST-NEXT: str [[REG4]], [sp, #36]<br>
<br>
Modified:
llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint.ll
(original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint.ll Fri
May 6 11:34:59 2016<br>
@@ -26,10 +26,11 @@ entry:<br>
; as a leaf function.<br>
;<br>
; CHECK-LABEL: caller_meta_leaf<br>
-; CHECK: mov x29, sp<br>
-; CHECK-NEXT: sub sp, sp, #32<br>
+; CHECK: sub sp, sp, #48<br>
+; CHECK-NEXT: stp x29, x30, [sp, #32]<br>
+; CHECK-NEXT: add x29, sp, #32<br>
; CHECK: Ltmp<br>
-; CHECK: add sp, sp, #32<br>
+; CHECK: add sp, sp, #48<br>
; CHECK: ret<br>
<br>
define void @caller_meta_leaf() {<br>
<br>
Modified:
llvm/trunk/test/CodeGen/AArch64/arm64-shrink-wrapping.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-shrink-wrapping.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-shrink-wrapping.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
(original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
Fri May 6 11:34:59 2016<br>
@@ -13,9 +13,9 @@ target triple = "arm64-apple-ios"<br>
; ENABLE-NEXT: <a href="http://b.ge" rel="noreferrer" target="_blank">b.ge</a>
[[EXIT_LABEL:LBB[0-9_]+]]<br>
;<br>
; Prologue code.<br>
-; CHECK: stp [[SAVE_SP:x[0-9]+]], [[CSR:x[0-9]+]], [sp,
#-16]!<br>
-; CHECK-NEXT: mov [[SAVE_SP]], sp<br>
-; CHECK-NEXT: sub sp, sp, #16<br>
+; CHECK: sub sp, sp, #32<br>
+; CHECK-NEXT: stp [[SAVE_SP:x[0-9]+]], [[CSR:x[0-9]+]],
[sp, #16]<br>
+; CHECK-NEXT: add [[SAVE_SP]], sp, #16<br>
;<br>
; Compare the arguments and jump to exit.<br>
; After the prologue is set.<br>
@@ -33,8 +33,8 @@ target triple = "arm64-apple-ios"<br>
; Without shrink-wrapping, epilogue is in the exit block.<br>
; DISABLE: [[EXIT_LABEL]]:<br>
; Epilogue code.<br>
-; CHECK-NEXT: add sp, sp, #16<br>
-; CHECK-NEXT: ldp x{{[0-9]+}}, [[CSR]], [sp], #16<br>
+; CHECK-NEXT: ldp x{{[0-9]+}}, [[CSR]], [sp, #16]<br>
+; CHECK-NEXT: add sp, sp, #32<br>
;<br>
; With shrink-wrapping, exit block is a simple return.<br>
; ENABLE: [[EXIT_LABEL]]:<br>
@@ -454,9 +454,9 @@ if.end:<br>
; ENABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]<br>
;<br>
; Prologue code.<br>
-; CHECK: stp [[CSR1:x[0-9]+]], [[CSR2:x[0-9]+]], [sp,
#-16]!<br>
-; CHECK-NEXT: mov [[NEW_SP:x[0-9]+]], sp<br>
-; CHECK-NEXT: sub sp, sp, #48<br>
+; CHECK: sub sp, sp, #64<br>
+; CHECK-NEXT: stp [[CSR1:x[0-9]+]], [[CSR2:x[0-9]+]], [sp,
#48]<br>
+; CHECK-NEXT: add [[NEW_SP:x[0-9]+]], sp, #48<br>
;<br>
; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]<br>
; Setup of the varags.<br>
@@ -473,8 +473,8 @@ if.end:<br>
; DISABLE: [[IFEND_LABEL]]: ; %if.end<br>
;<br>
; Epilogue code.<br>
-; CHECK: add sp, sp, #48<br>
-; CHECK-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #16<br>
+; CHECK: ldp [[CSR1]], [[CSR2]], [sp, #48]<br>
+; CHECK-NEXT: add sp, sp, #64<br>
; CHECK-NEXT: ret<br>
;<br>
; ENABLE: [[ELSE_LABEL]]: ; %if.else<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/fastcc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fastcc.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fastcc.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/fastcc.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/fastcc.ll Fri May 6
11:34:59 2016<br>
@@ -7,13 +7,15 @@<br>
<br>
define fastcc void @func_stack0() {<br>
; CHECK-LABEL: func_stack0:<br>
-; CHECK: mov x29, sp<br>
-; CHECK: str w{{[0-9]+}}, [sp, #-32]!<br>
+; CHECK: sub sp, sp, #48<br>
+; CHECK: add x29, sp, #32<br>
+; CHECK: str w{{[0-9]+}}, [sp]<br>
<br>
; CHECK-TAIL-LABEL: func_stack0:<br>
-; CHECK-TAIL: stp x29, x30, [sp, #-16]!<br>
-; CHECK-TAIL-NEXT: mov x29, sp<br>
-; CHECK-TAIL: str w{{[0-9]+}}, [sp, #-32]!<br>
+; CHECK-TAIL: sub sp, sp, #48<br>
+; CHECK-TAIL-NEXT: stp x29, x30, [sp, #32]<br>
+; CHECK-TAIL-NEXT: add x29, sp, #32<br>
+; CHECK-TAIL: str w{{[0-9]+}}, [sp]<br>
<br>
<br>
call fastcc void @func_stack8([8 x i32] undef, i32 42)<br>
@@ -42,27 +44,29 @@ define fastcc void @func_stack0() {<br>
; CHECK-TAIL-NOT: sub sp, sp<br>
<br>
ret void<br>
-; CHECK: add sp, sp, #32<br>
-; CHECK-NEXT: ldp x29, x30, [sp], #16<br>
+; CHECK: ldp x29, x30, [sp, #32]<br>
+; CHECK-NEXT: add sp, sp, #48<br>
; CHECK-NEXT: ret<br>
<br>
<br>
-; CHECK-TAIL: add sp, sp, #32<br>
-; CHECK-TAIL-NEXT: ldp x29, x30, [sp], #16<br>
+; CHECK-TAIL: ldp x29, x30, [sp, #32]<br>
+; CHECK-TAIL-NEXT: add sp, sp, #48<br>
; CHECK-TAIL-NEXT: ret<br>
}<br>
<br>
define fastcc void @func_stack8([8 x i32], i32 %stacked) {<br>
; CHECK-LABEL: func_stack8:<br>
-; CHECK: stp x29, x30, [sp, #-16]!<br>
-; CHECK: mov x29, sp<br>
-; CHECK: str w{{[0-9]+}}, [sp, #-32]!<br>
+; CHECK: sub sp, sp, #48<br>
+; CHECK: stp x29, x30, [sp, #32]<br>
+; CHECK: add x29, sp, #32<br>
+; CHECK: str w{{[0-9]+}}, [sp]<br>
<br>
<br>
; CHECK-TAIL-LABEL: func_stack8:<br>
-; CHECK-TAIL: stp x29, x30, [sp, #-16]!<br>
-; CHECK-TAIL: mov x29, sp<br>
-; CHECK-TAIL: str w{{[0-9]+}}, [sp, #-32]!<br>
+; CHECK-TAIL: sub sp, sp, #48<br>
+; CHECK-TAIL: stp x29, x30, [sp, #32]<br>
+; CHECK-TAIL: add x29, sp, #32<br>
+; CHECK-TAIL: str w{{[0-9]+}}, [sp]<br>
<br>
<br>
call fastcc void @func_stack8([8 x i32] undef, i32 42)<br>
@@ -91,23 +95,22 @@ define fastcc void @func_stack8([8 x i32<br>
; CHECK-TAIL-NOT: sub sp, sp<br>
<br>
ret void<br>
-; CHECK: add sp, sp, #32<br>
-; CHECK-NEXT: ldp x29, x30, [sp], #16<br>
+; CHECK-NEXT: ldp x29, x30, [sp, #32]<br>
+; CHECK: add sp, sp, #48<br>
; CHECK-NEXT: ret<br>
<br>
<br>
-; CHECK-TAIL: add sp, sp, #32<br>
-; CHECK-TAIL-NEXT: ldp x29, x30, [sp], #16<br>
-; CHECK-TAIL-NEXT: add sp, sp, #16<br>
+; CHECK-TAIL: ldp x29, x30, [sp, #32]<br>
+; CHECK-TAIL-NEXT: add sp, sp, #64<br>
; CHECK-TAIL-NEXT: ret<br>
}<br>
<br>
define fastcc void @func_stack32([8 x i32], i128 %stacked0,
i128 %stacked1) {<br>
; CHECK-LABEL: func_stack32:<br>
-; CHECK: mov x29, sp<br>
+; CHECK: add x29, sp, #32<br>
<br>
; CHECK-TAIL-LABEL: func_stack32:<br>
-; CHECK-TAIL: mov x29, sp<br>
+; CHECK-TAIL: add x29, sp, #32<br>
<br>
<br>
call fastcc void @func_stack8([8 x i32] undef, i32 42)<br>
@@ -136,13 +139,12 @@ define fastcc void @func_stack32([8 x
i3<br>
; CHECK-TAIL-NOT: sub sp, sp<br>
<br>
ret void<br>
-; CHECK: add sp, sp, #32<br>
-; CHECK-NEXT: ldp x29, x30, [sp], #16<br>
+; CHECK: ldp x29, x30, [sp, #32]<br>
+; CHECK-NEXT: add sp, sp, #48<br>
; CHECK-NEXT: ret<br>
<br>
-; CHECK-TAIL: add sp, sp, #32<br>
-; CHECK-TAIL-NEXT: ldp x29, x30, [sp], #16<br>
-; CHECK-TAIL-NEXT: add sp, sp, #32<br>
+; CHECK-TAIL: ldp x29, x30, [sp, #32]<br>
+; CHECK-TAIL-NEXT: add sp, sp, #80<br>
; CHECK-TAIL-NEXT: ret<br>
}<br>
<br>
@@ -180,22 +182,21 @@ define fastcc void
@func_stack32_leaf([8<br>
; Check that arg stack pop is done after callee-save
restore when no frame pointer is used.<br>
define fastcc void @func_stack32_leaf_local([8 x i32], i128
%stacked0, i128 %stacked1) {<br>
; CHECK-LABEL: func_stack32_leaf_local:<br>
-; CHECK: str x20, [sp, #-16]!<br>
-; CHECK-NEXT: sub sp, sp, #16<br>
+; CHECK: sub sp, sp, #32<br>
+; CHECK-NEXT: str x20, [sp, #16]<br>
; CHECK: nop<br>
; CHECK-NEXT: //NO_APP<br>
-; CHECK-NEXT: add sp, sp, #16<br>
-; CHECK-NEXT: ldr x20, [sp], #16<br>
+; CHECK-NEXT: ldr x20, [sp, #16]<br>
+; CHECK-NEXT: add sp, sp, #32<br>
; CHECK-NEXT: ret<br>
<br>
; CHECK-TAIL-LABEL: func_stack32_leaf_local:<br>
-; CHECK-TAIL: str x20, [sp, #-16]!<br>
-; CHECK-TAIL-NEXT: sub sp, sp, #16<br>
+; CHECK-TAIL: sub sp, sp, #32<br>
+; CHECK-TAIL-NEXT: str x20, [sp, #16]<br>
; CHECK-TAIL: nop<br>
; CHECK-TAIL-NEXT: //NO_APP<br>
-; CHECK-TAIL-NEXT: add sp, sp, #16<br>
-; CHECK-TAIL-NEXT: ldr x20, [sp], #16<br>
-; CHECK-TAIL-NEXT: add sp, sp, #32<br>
+; CHECK-TAIL-NEXT: ldr x20, [sp, #16]<br>
+; CHECK-TAIL-NEXT: add sp, sp, #64<br>
; CHECK-TAIL-NEXT: ret<br>
<br>
; CHECK-TAIL-RZ-LABEL: func_stack32_leaf_local:<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/func-calls.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/func-calls.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/func-calls.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/func-calls.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/func-calls.ll Fri May 6
11:34:59 2016<br>
@@ -89,11 +89,11 @@ define void @check_stack_args() {<br>
; that varstruct is passed on the stack. Rather dependent
on how a<br>
; memcpy gets created, but the following works for now.<br>
<br>
-; CHECK-DAG: str {{q[0-9]+}}, [sp, #-16]<br>
+; CHECK-DAG: str {{q[0-9]+}}, [sp]<br>
; CHECK-DAG: fmov d[[FINAL_DOUBLE:[0-9]+]], #1.0<br>
; CHECK: mov v0.16b, v[[FINAL_DOUBLE]].16b<br>
<br>
-; CHECK-NONEON-DAG: str {{q[0-9]+}}, [sp, #-16]!<br>
+; CHECK-NONEON-DAG: str {{q[0-9]+}}, [sp]<br>
; CHECK-NONEON-DAG: fmov d[[FINAL_DOUBLE:[0-9]+]], #1.0<br>
; CHECK-NONEON: fmov d0, d[[FINAL_DOUBLE]]<br>
<br>
<br>
Modified:
llvm/trunk/test/CodeGen/AArch64/tailcall-implicit-sret.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tailcall-implicit-sret.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tailcall-implicit-sret.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
---
llvm/trunk/test/CodeGen/AArch64/tailcall-implicit-sret.ll
(original)<br>
+++
llvm/trunk/test/CodeGen/AArch64/tailcall-implicit-sret.ll
Fri May 6 11:34:59 2016<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc < %s -mtriple arm64-apple-darwin
-aarch64-load-store-opt=false -asm-verbose=false | FileCheck
%s<br>
+; RUN: llc < %s -mtriple arm64-apple-darwin
-aarch64-load-store-opt=false -disable-post-ra
-asm-verbose=false | FileCheck %s<br>
; Disable the load/store optimizer to avoid having LDP/STPs
and simplify checks.<br>
<br>
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"<br>
<br>
Modified: llvm/trunk/test/DebugInfo/AArch64/prologue_end.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/AArch64/prologue_end.ll?rev=268746&r1=268745&r2=268746&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/AArch64/prologue_end.ll?rev=268746&r1=268745&r2=268746&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/DebugInfo/AArch64/prologue_end.ll
(original)<br>
+++ llvm/trunk/test/DebugInfo/AArch64/prologue_end.ll Fri
May 6 11:34:59 2016<br>
@@ -9,9 +9,9 @@<br>
define void @prologue_end_test() nounwind uwtable !dbg !4 {<br>
; CHECK: prologue_end_test:<br>
; CHECK: .cfi_startproc<br>
- ; CHECK: stp x29, x30<br>
- ; CHECK: mov x29, sp<br>
; CHECK: sub sp, sp<br>
+ ; CHECK: stp x29, x30<br>
+ ; CHECK: add x29, sp<br>
; CHECK: .loc 1 3 3 prologue_end<br>
; CHECK: bl _func<br>
; CHECK: bl _func<br>
<br>
<br>
_______________________________________________<br>
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<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote>
</div>
<br>
</div>
</blockquote>
<br>
</div></div><span class="HOEnZb"><font color="#888888"><pre cols="72">--
Geoff Berry
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
</pre>
</font></span></div>
</blockquote></div><br></div>