<div dir="ltr">I am going to revert this<div><br></div></div><br><div class="gmail_quote"><div dir="ltr">On Wed, May 4, 2016 at 12:31 PM Vitaly Buka <<a href="mailto:vitalybuka@google.com">vitalybuka@google.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">This CL probably is responsible for <a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/11619" target="_blank">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/11619</a></div><br><div class="gmail_quote"><div dir="ltr">On Wed, May 4, 2016 at 11:25 AM Weiming Zhao via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: weimingz<br>
Date: Wed May 4 13:19:33 2016<br>
New Revision: 268529<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=268529&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=268529&view=rev</a><br>
Log:<br>
[ARM] Fix Scavenger assert due to underestimated stack size<br>
<br>
Summary:<br>
Currently, when checking if a stack is "BigStack" or not, it doesn't count into spills and arguments. Therefore, LLVM won't reserve spill slot for this actually "BigStack". This may cause scavenger failure.<br>
<br>
Reviewers: rengolin<br>
<br>
Subscribers: aemerson, rengolin, tberghammer, danalbert, srhines, llvm-commits<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D19896" rel="noreferrer" target="_blank">http://reviews.llvm.org/D19896</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll<br>
Modified:<br>
llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=268529&r1=268528&r2=268529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=268529&r1=268528&r2=268529&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Wed May 4 13:19:33 2016<br>
@@ -1479,6 +1479,7 @@ void ARMFrameLowering::determineCalleeSa<br>
bool CS1Spilled = false;<br>
bool LRSpilled = false;<br>
unsigned NumGPRSpills = 0;<br>
+ unsigned NumFPRSpills = 0;<br>
SmallVector<unsigned, 4> UnspilledCS1GPRs;<br>
SmallVector<unsigned, 4> UnspilledCS2GPRs;<br>
const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(<br>
@@ -1533,8 +1534,17 @@ void ARMFrameLowering::determineCalleeSa<br>
CanEliminateFrame = false;<br>
}<br>
<br>
- if (!ARM::GPRRegClass.contains(Reg))<br>
+ if (!ARM::GPRRegClass.contains(Reg)) {<br>
+ if (Spilled) {<br>
+ if (ARM::SPRRegClass.contains(Reg))<br>
+ NumFPRSpills++;<br>
+ else if (ARM::DPRRegClass.contains(Reg))<br>
+ NumFPRSpills += 2;<br>
+ else if (ARM::QPRRegClass.contains(Reg))<br>
+ NumFPRSpills += 4;<br>
+ }<br>
continue;<br>
+ }<br>
<br>
if (Spilled) {<br>
NumGPRSpills++;<br>
@@ -1607,11 +1617,14 @@ void ARMFrameLowering::determineCalleeSa<br>
// FIXME: We could add logic to be more precise about negative offsets<br>
// and which instructions will need a scratch register for them. Is it<br>
// worth the effort and added fragility?<br>
- bool BigStack = (RS && (MFI->estimateStackSize(MF) +<br>
- ((hasFP(MF) && AFI->hasStackFrame()) ? 4 : 0) >=<br>
- estimateRSStackSizeLimit(MF, this))) ||<br>
- MFI->hasVarSizedObjects() ||<br>
- (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));<br>
+ auto ArgStackSize = MF.getInfo<ARMFunctionInfo>()->getArgumentStackSize();<br>
+ bool BigStack =<br>
+ (RS && (MFI->estimateStackSize(MF) + 4 * (NumGPRSpills + NumFPRSpills) +<br>
+ (!hasFP(MF) ? ArgStackSize : 0) + 16 /* possible paddings */ +<br>
+ ((hasFP(MF) && AFI->hasStackFrame()) ? 4 : 0) >=<br>
+ estimateRSStackSizeLimit(MF, this))) ||<br>
+ MFI->hasVarSizedObjects() ||<br>
+ (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));<br>
<br>
bool ExtraCSSpill = false;<br>
if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {<br>
<br>
Added: llvm/trunk/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll?rev=268529&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll?rev=268529&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll (added)<br>
+++ llvm/trunk/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll Wed May 4 13:19:33 2016<br>
@@ -0,0 +1,192 @@<br>
+; RUN: llc < %s<br>
+; This test has around 4000 bytes of local variables and it also stresses register allocation<br>
+; to force a register scavenging. It tests if the stack is treated as "BigStack" and thus<br>
+; spill slots are reserved. If not, reg scavenger will assert.<br>
+<br>
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n8:16:32-S64"<br>
+target triple = "thumbv7--linux-android"<br>
+<br>
+%struct.r = type { i32 (...)**, [10 x [9 x float]], [10 x [9 x float]], [101 x [9 x float]], [101 x [9 x float]], i32, i32, i32, i32, i32, [8 x [2 x i32]], [432 x float], [432 x i32], [10 x i8*], [10 x i8*], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], i32, i32, i32, i32, float, float, i32, i32, [9 x float], float*, float }<br>
+<br>
+define void @foo(%struct.r* %this, float* %srcR, float* %srcC, float* %tempPntsX, float* %tY, float* %ms, float* %sX, float* %sY, i32* dereferenceable(4) %num, float* %tm, i32 %SR, i32 %lev, i8* %tdata, i32 %siW, i32 %pyw, i32 %pyh, i8* %sdata) #0 align 2 {<br>
+entry:<br>
+ %sFV = alloca [49 x float], align 4<br>
+ %tFV = alloca [49 x float], align 4<br>
+ %TIM = alloca [9 x float], align 4<br>
+ %sort_tmp = alloca [432 x float], align 4<br>
+ %msDiffs = alloca [432 x float], align 4<br>
+ %TM.sroa.0.0.copyload = load float, float* %tm, align 4<br>
+ %TM.sroa.8.0.copyload = load float, float* null, align 4<br>
+ %TM.sroa.9.0..sroa_idx813 = getelementptr inbounds float, float* %tm, i32 6<br>
+ %TM.sroa.9.0.copyload = load float, float* %TM.sroa.9.0..sroa_idx813, align 4<br>
+ %TM.sroa.11.0.copyload = load float, float* undef, align 4<br>
+ br i1 undef, label %<a href="http://for.body.lr.ph" rel="noreferrer" target="_blank">for.body.lr.ph</a>, label %if.then343<br>
+<br>
+<a href="http://for.body.lr.ph" rel="noreferrer" target="_blank">for.body.lr.ph</a>: ; preds = %entry<br>
+ %arrayidx8 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 0<br>
+ %arrayidx12 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 6<br>
+ %arrayidx15 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 4<br>
+ %arrayidx20 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 7<br>
+ %arrayidx24 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 0<br>
+ %arrayidx28 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 6<br>
+ %arrayidx32 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 4<br>
+ %arrayidx36 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 7<br>
+ %arrayidx84 = getelementptr inbounds [9 x float], [9 x float]* %TIM, i32 0, i32 6<br>
+ %arrayidx92 = getelementptr inbounds [9 x float], [9 x float]* %TIM, i32 0, i32 7<br>
+ %add116 = add nsw i32 %pyh, 15<br>
+ br label %for.body<br>
+<br>
+for.body: ; preds = %for.cond.cleanup40, %<a href="http://for.body.lr.ph" rel="noreferrer" target="_blank">for.body.lr.ph</a><br>
+ %arrayidx.phi = phi float* [ %sX, %<a href="http://for.body.lr.ph" rel="noreferrer" target="_blank">for.body.lr.ph</a> ], [ %arrayidx.inc, %for.cond.cleanup40 ]<br>
+ %arrayidx4.phi = phi float* [ %sY, %<a href="http://for.body.lr.ph" rel="noreferrer" target="_blank">for.body.lr.ph</a> ], [ %arrayidx4.inc, %for.cond.cleanup40 ]<br>
+ %0 = load float, float* %arrayidx.phi, align 4<br>
+ %1 = load float, float* %arrayidx4.phi, align 4<br>
+ %2 = load float, float* %arrayidx12, align 4<br>
+ %add = fadd fast float 0.000000e+00, %2<br>
+ %3 = load float, float* %arrayidx20, align 4<br>
+ %add21 = fadd fast float 0.000000e+00, %3<br>
+ %mul3.i = fmul fast float %add21, %TM.sroa.8.0.copyload<br>
+ %add.i = fadd fast float 0.000000e+00, %TM.sroa.11.0.copyload<br>
+ %add5.i = fadd fast float %add.i, %mul3.i<br>
+ %conv6.i = fdiv fast float 1.000000e+00, %add5.i<br>
+ %mul8.i = fmul fast float %add, %TM.sroa.0.0.copyload<br>
+ %add11.i = fadd fast float %mul8.i, %TM.sroa.9.0.copyload<br>
+ %add13.i = fadd fast float %add11.i, 0.000000e+00<br>
+ %4 = load float, float* %arrayidx24, align 4<br>
+ %mul14.i = fmul fast float %add13.i, %4<br>
+ %mul25 = fmul fast float %mul14.i, %conv6.i<br>
+ %add29 = fadd fast float %mul25, 0.000000e+00<br>
+ %arrayidx.inc = getelementptr float, float* %arrayidx.phi, i32 1<br>
+ %arrayidx4.inc = getelementptr float, float* %arrayidx4.phi, i32 1<br>
+ %conv64.1 = sitofp i32 undef to float<br>
+ %conv64.6 = sitofp i32 undef to float<br>
+ br label %for.body41<br>
+<br>
+for.cond.cleanup40: ; preds = %for.body41<br>
+ %call = call fast float undef(%struct.r* nonnull %this, float* undef, i32 49)<br>
+ br label %for.body<br>
+<br>
+for.body41: ; preds = %for.cond.cleanup56.for.body41_crit_edge, %for.body<br>
+ %5 = phi float [ 0.000000e+00, %for.body ], [ %.pre, %for.cond.cleanup56.for.body41_crit_edge ]<br>
+ %sFVData.0840 = phi float* [ undef, %for.body ], [ undef, %for.cond.cleanup56.for.body41_crit_edge ]<br>
+ %dx.0838 = phi i32 [ -3, %for.body ], [ undef, %for.cond.cleanup56.for.body41_crit_edge ]<br>
+ %conv42 = sitofp i32 %dx.0838 to float<br>
+ %add43 = fadd fast float %conv42, %add29<br>
+ %conv44 = fptosi float %add43 to i32<br>
+ %conv48 = sitofp i32 %conv44 to float<br>
+ %mul49 = fmul fast float %5, %conv48<br>
+ %add53 = fadd fast float %mul49, 0.000000e+00<br>
+ %conv111 = fptosi float undef to i32<br>
+ %cond = select i1 undef, i32 %conv111, i32 -16<br>
+ %cond.add116 = select i1 undef, i32 %cond, i32 %add116<br>
+ %cmp132 = icmp sgt i32 undef, -16<br>
+ %cond137 = select i1 %cmp132, i32 undef, i32 -16<br>
+ %cond153 = select i1 undef, i32 %cond137, i32 undef<br>
+ %add.ptr = getelementptr inbounds i8, i8* %sdata, i32 %cond153<br>
+ %mul154 = mul nsw i32 %cond.add116, %siW<br>
+ %add.ptr155 = getelementptr inbounds i8, i8* %add.ptr, i32 %mul154<br>
+ %6 = load i8, i8* %add.ptr155, align 1<br>
+ %conv157 = uitofp i8 %6 to float<br>
+ %incdec.ptr = getelementptr inbounds float, float* %sFVData.0840, i32 1<br>
+ store float %conv157, float* %sFVData.0840, align 4<br>
+ %7 = load float, float* %arrayidx15, align 4<br>
+ %mul65.1 = fmul fast float %7, %conv64.1<br>
+ %8 = load float, float* %arrayidx20, align 4<br>
+ %add69.1 = fadd fast float %mul65.1, %8<br>
+ %conv78.1 = fdiv fast float 1.000000e+00, 0.000000e+00<br>
+ %9 = load float, float* undef, align 4<br>
+ %mul80.1 = fmul fast float %9, %add53<br>
+ %10 = load float, float* undef, align 4<br>
+ %mul82.1 = fmul fast float %10, %add69.1<br>
+ %add83.1 = fadd fast float %mul82.1, %mul80.1<br>
+ %11 = load float, float* %arrayidx84, align 4<br>
+ %add85.1 = fadd fast float %add83.1, %11<br>
+ %mul86.1 = fmul fast float %add85.1, %conv78.1<br>
+ %12 = load float, float* %arrayidx92, align 4<br>
+ %add93.1 = fadd fast float 0.000000e+00, %12<br>
+ %mul94.1 = fmul fast float %add93.1, %conv78.1<br>
+ %13 = load float, float* %arrayidx24, align 4<br>
+ %mul98.1 = fmul fast float %mul86.1, %13<br>
+ %14 = load float, float* %arrayidx28, align 4<br>
+ %add102.1 = fadd fast float %mul98.1, %14<br>
+ %15 = load float, float* %arrayidx32, align 4<br>
+ %mul106.1 = fmul fast float %mul94.1, %15<br>
+ %16 = load float, float* %arrayidx36, align 4<br>
+ %add110.1 = fadd fast float %mul106.1, %16<br>
+ %conv111.1 = fptosi float %add102.1 to i32<br>
+ %conv112.1 = fptosi float %add110.1 to i32<br>
+ %cond.1 = select i1 undef, i32 %conv111.1, i32 -16<br>
+ %cond.add116.1 = select i1 undef, i32 %cond.1, i32 %add116<br>
+ %cond137.1 = select i1 undef, i32 %conv112.1, i32 -16<br>
+ %cond153.1 = select i1 undef, i32 %cond137.1, i32 undef<br>
+ %add.ptr.1 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.1<br>
+ %mul154.1 = mul nsw i32 %cond.add116.1, %siW<br>
+ %add.ptr155.1 = getelementptr inbounds i8, i8* %add.ptr.1, i32 %mul154.1<br>
+ %17 = load i8, i8* %add.ptr155.1, align 1<br>
+ %conv157.1 = uitofp i8 %17 to float<br>
+ %incdec.ptr.1 = getelementptr inbounds float, float* %sFVData.0840, i32 2<br>
+ store float %conv157.1, float* %incdec.ptr, align 4<br>
+ %conv112.2 = fptosi float undef to i32<br>
+ %cond137.2 = select i1 undef, i32 %conv112.2, i32 -16<br>
+ %cond153.2 = select i1 undef, i32 %cond137.2, i32 undef<br>
+ %add.ptr.2 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.2<br>
+ %add.ptr155.2 = getelementptr inbounds i8, i8* %add.ptr.2, i32 0<br>
+ %18 = load i8, i8* %add.ptr155.2, align 1<br>
+ %conv157.2 = uitofp i8 %18 to float<br>
+ %incdec.ptr.2 = getelementptr inbounds float, float* %sFVData.0840, i32 3<br>
+ store float %conv157.2, float* %incdec.ptr.1, align 4<br>
+ %cmp132.3 = icmp sgt i32 undef, -16<br>
+ %cond137.3 = select i1 %cmp132.3, i32 undef, i32 -16<br>
+ %cond153.3 = select i1 undef, i32 %cond137.3, i32 undef<br>
+ %add.ptr.3 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.3<br>
+ %add.ptr155.3 = getelementptr inbounds i8, i8* %add.ptr.3, i32 0<br>
+ %19 = load i8, i8* %add.ptr155.3, align 1<br>
+ %conv157.3 = uitofp i8 %19 to float<br>
+ store float %conv157.3, float* %incdec.ptr.2, align 4<br>
+ %incdec.ptr.5 = getelementptr inbounds float, float* %sFVData.0840, i32 6<br>
+ %20 = load float, float* %arrayidx15, align 4<br>
+ %mul65.6 = fmul fast float %20, %conv64.6<br>
+ %21 = load float, float* %arrayidx20, align 4<br>
+ %add69.6 = fadd fast float %mul65.6, %21<br>
+ %conv78.6 = fdiv fast float 1.000000e+00, 0.000000e+00<br>
+ %22 = load float, float* undef, align 4<br>
+ %mul82.6 = fmul fast float %22, %add69.6<br>
+ %add83.6 = fadd fast float %mul82.6, 0.000000e+00<br>
+ %23 = load float, float* %arrayidx84, align 4<br>
+ %add85.6 = fadd fast float %add83.6, %23<br>
+ %mul86.6 = fmul fast float %add85.6, %conv78.6<br>
+ %24 = load float, float* %arrayidx24, align 4<br>
+ %mul98.6 = fmul fast float %mul86.6, %24<br>
+ %25 = load float, float* %arrayidx28, align 4<br>
+ %add102.6 = fadd fast float %mul98.6, %25<br>
+ %conv111.6 = fptosi float %add102.6 to i32<br>
+ %conv112.6 = fptosi float undef to i32<br>
+ %cond.6 = select i1 undef, i32 %conv111.6, i32 -16<br>
+ %cond.add116.6 = select i1 undef, i32 %cond.6, i32 %add116<br>
+ %cmp132.6 = icmp sgt i32 %conv112.6, -16<br>
+ %cond137.6 = select i1 %cmp132.6, i32 %conv112.6, i32 -16<br>
+ %cond153.6 = select i1 undef, i32 %cond137.6, i32 undef<br>
+ %add.ptr.6 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.6<br>
+ %mul154.6 = mul nsw i32 %cond.add116.6, %siW<br>
+ %add.ptr155.6 = getelementptr inbounds i8, i8* %add.ptr.6, i32 %mul154.6<br>
+ %26 = load i8, i8* %add.ptr155.6, align 1<br>
+ %conv157.6 = uitofp i8 %26 to float<br>
+ store float %conv157.6, float* %incdec.ptr.5, align 4<br>
+ %exitcond874 = icmp eq i32 %dx.0838, 3<br>
+ br i1 %exitcond874, label %for.cond.cleanup40, label %for.cond.cleanup56.for.body41_crit_edge<br>
+<br>
+for.cond.cleanup56.for.body41_crit_edge: ; preds = %for.body41<br>
+ %.pre = load float, float* %arrayidx8, align 4<br>
+ br label %for.body41<br>
+<br>
+if.then343: ; preds = %entry<br>
+ ret void<br>
+}<br>
+<br>
+attributes #0 = { sspstrong uwtable "no-frame-pointer-elim"="false" "target-cpu"="cortex-a7" }<br>
+<br>
+!1 = !{!2, !2, i64 0}<br>
+!2 = !{!"float", !3, i64 0}<br>
+!3 = !{!"omnipotent char", !4, i64 0}<br>
+!4 = !{!"Simple C/C++ TBAA"}<br>
+!5 = !{!3, !3, i64 0}<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote></div></blockquote></div>