<div dir="ltr">This is causing build failures on the bots, please fix or revert. <div><a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/23704/steps/bootstrap%20clang/logs/stdio">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/23704/steps/bootstrap%20clang/logs/stdio</a><br></div><div><br></div><div><pre style="font-family:'courier new',courier,monotype,monospace;color:rgb(0,0,0);font-size:medium"><span class="gmail-stdout">/mnt/b/sanitizer-buildbot1/sanitizer-x86_64-linux/build/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:69:1: error: unused function 'DecodeSGPR_32RegisterClass' [-Werror,-Wunused-function]
DECODE_OPERAND(SGPR_32)
^
/mnt/b/sanitizer-buildbot1/sanitizer-x86_64-linux/build/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:59:34: note: expanded from macro 'DECODE_OPERAND'
#define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass)
^
/mnt/b/sanitizer-buildbot1/sanitizer-x86_64-linux/build/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:51:21: note: expanded from macro 'DECODE_OPERAND2'
static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \
^
<scratch space>:75:1: note: expanded from here
DecodeSGPR_32RegisterClass
^
1 error generated.</span></pre></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Apr 27, 2016 at 9:20 AM, Artem Tamazov via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: artem.tamazov<br>
Date: Wed Apr 27 11:20:23 2016<br>
New Revision: 267733<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=267733&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=267733&view=rev</a><br>
Log:<br>
[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.<br>
<br>
Added support of TTMP quads.<br>
Reworked M0 exclusion machinery for SMRD and similar instructions<br>
to enable usage of TTMP registers in those instructions as destinations.<br>
Tests added.<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D19342" rel="noreferrer" target="_blank">http://reviews.llvm.org/D19342</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp<br>
llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp<br>
llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h<br>
llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td<br>
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td<br>
llvm/trunk/test/MC/AMDGPU/mubuf.s<br>
llvm/trunk/test/MC/AMDGPU/reg-syntax-extra.s<br>
llvm/trunk/test/MC/AMDGPU/smrd.s<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=267733&r1=267732&r2=267733&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=267733&r1=267732&r2=267733&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Wed Apr 27 11:20:23 2016<br>
@@ -611,13 +611,14 @@ static int getRegClass(RegisterKind Is,<br>
default: return -1;<br>
case 1: return AMDGPU::TTMP_32RegClassID;<br>
case 2: return AMDGPU::TTMP_64RegClassID;<br>
+ case 4: return AMDGPU::TTMP_128RegClassID;<br>
}<br>
} else if (Is == IS_SGPR) {<br>
switch (RegWidth) {<br>
default: return -1;<br>
case 1: return AMDGPU::SGPR_32RegClassID;<br>
case 2: return AMDGPU::SGPR_64RegClassID;<br>
- case 4: return AMDGPU::SReg_128RegClassID;<br>
+ case 4: return AMDGPU::SGPR_128RegClassID;<br>
case 8: return AMDGPU::SReg_256RegClassID;<br>
case 16: return AMDGPU::SReg_512RegClassID;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp?rev=267733&r1=267732&r2=267733&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp?rev=267733&r1=267732&r2=267733&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp Wed Apr 27 11:20:23 2016<br>
@@ -68,6 +68,7 @@ DECODE_OPERAND(VReg_128)<br>
<br>
DECODE_OPERAND(SGPR_32)<br>
DECODE_OPERAND(SReg_32)<br>
+DECODE_OPERAND(SReg_32_XM0)<br>
DECODE_OPERAND(SReg_64)<br>
DECODE_OPERAND(SReg_128)<br>
DECODE_OPERAND(SReg_256)<br>
@@ -248,6 +249,11 @@ MCOperand AMDGPUDisassembler::decodeOper<br>
return decodeSrcOp(OP32, Val);<br>
}<br>
<br>
+MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0(unsigned Val) const {<br>
+ // SReg_32_XM0 is SReg_32 without M0<br>
+ return decodeOperand_SReg_32(Val);<br>
+}<br>
+<br>
MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {<br>
// see decodeOperand_SReg_32 comment<br>
return decodeSrcOp(OP64, Val);<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h?rev=267733&r1=267732&r2=267733&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h?rev=267733&r1=267732&r2=267733&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h Wed Apr 27 11:20:23 2016<br>
@@ -64,6 +64,7 @@ namespace llvm {<br>
<br>
MCOperand decodeOperand_SGPR_32(unsigned Val) const;<br>
MCOperand decodeOperand_SReg_32(unsigned Val) const;<br>
+ MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const;<br>
MCOperand decodeOperand_SReg_64(unsigned Val) const;<br>
MCOperand decodeOperand_SReg_128(unsigned Val) const;<br>
MCOperand decodeOperand_SReg_256(unsigned Val) const;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp?rev=267733&r1=267732&r2=267733&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp?rev=267733&r1=267732&r2=267733&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp Wed Apr 27 11:20:23 2016<br>
@@ -240,9 +240,12 @@ void AMDGPUInstPrinter::printRegOperand(<br>
} else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {<br>
Type = "v";<br>
NumRegs = 4;<br>
- } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {<br>
+ } else if (MRI.getRegClass(AMDGPU::SGPR_128RegClassID).contains(reg)) {<br>
Type = "s";<br>
NumRegs = 4;<br>
+ } else if (MRI.getRegClass(AMDGPU::TTMP_128RegClassID).contains(reg)) {<br>
+ Type = "ttmp";<br>
+ NumRegs = 4;<br>
} else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {<br>
Type = "v";<br>
NumRegs = 3;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=267733&r1=267732&r2=267733&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=267733&r1=267732&r2=267733&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Wed Apr 27 11:20:23 2016<br>
@@ -60,17 +60,17 @@ defm EXP : EXP_m;<br>
// SMRD Instructions<br>
//===----------------------------------------------------------------------===//<br>
<br>
-// We are using the SGPR_32 and not the SReg_32 register class for 32-bit<br>
-// SMRD instructions, because the SGPR_32 register class does not include M0<br>
+// We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit<br>
+// SMRD instructions, because the SReg_32_XM0 register class does not include M0<br>
// and writing to M0 from an SMRD instruction will hang the GPU.<br>
-defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SGPR_32>;<br>
+defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SReg_32_XM0>;<br>
defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>;<br>
defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>;<br>
defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>;<br>
defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>;<br>
<br>
defm S_BUFFER_LOAD_DWORD : SMRD_Helper <<br>
- smrd<0x08>, "s_buffer_load_dword", SReg_128, SGPR_32<br>
+ smrd<0x08>, "s_buffer_load_dword", SReg_128, SReg_32_XM0<br>
>;<br>
<br>
defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <<br>
@@ -2087,9 +2087,9 @@ multiclass SI_SPILL_SGPR <RegisterClass<br>
}<br>
<br>
// It's unclear whether you can use M0 as the output of v_readlane_b32<br>
-// instructions, so use SGPR_32 register class for spills to prevent<br>
+// instructions, so use SReg_32_XM0 register class for spills to prevent<br>
// this from happening.<br>
-defm SI_SPILL_S32 : SI_SPILL_SGPR <SGPR_32>;<br>
+defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32_XM0>;<br>
defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;<br>
defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;<br>
defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;<br>
@@ -3431,7 +3431,7 @@ def : ZExt_i64_i1_Pat<anyext>;<br>
def : Pat <<br>
(i64 (sext i32:$src)),<br>
(REG_SEQUENCE SReg_64, $src, sub0,<br>
- (i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SGPR_32)), sub1)<br>
+ (i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SReg_32_XM0)), sub1)<br>
>;<br>
<br>
def : Pat <<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td?rev=267733&r1=267732&r2=267733&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td?rev=267733&r1=267732&r2=267733&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td Wed Apr 27 11:20:23 2016<br>
@@ -132,7 +132,7 @@ def SGPR_64Regs : RegisterTuples<[sub0,<br>
(add (decimate (shl SGPR_32, 1), 2))]>;<br>
<br>
// SGPR 128-bit registers<br>
-def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],<br>
+def SGPR_128Regs : RegisterTuples<[sub0, sub1, sub2, sub3],<br>
[(add (decimate SGPR_32, 4)),<br>
(add (decimate (shl SGPR_32, 1), 4)),<br>
(add (decimate (shl SGPR_32, 2), 4)),<br>
@@ -255,6 +255,13 @@ def SReg_32 : RegisterClass<"AMDGPU", [i<br>
TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)<br>
>;<br>
<br>
+// Subset of SReg_32 without M0 for SMRD instructions and alike.<br>
+// See comments in SIInstructions.td for more info.<br>
+def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32], 32,<br>
+ (add SGPR_32, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI,<br>
+ TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)<br>
+>;<br>
+<br>
def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)>;<br>
<br>
def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add TTMP_64Regs)> {<br>
@@ -265,11 +272,19 @@ def SReg_64 : RegisterClass<"AMDGPU", [v<br>
(add SGPR_64, VCC, EXEC, FLAT_SCR, TTMP_64, TBA, TMA)<br>
>;<br>
<br>
-def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128)> {<br>
- // Requires 2 s_mov_b64 to copy<br>
- let CopyCost = 2;<br>
+// Requires 2 s_mov_b64 to copy<br>
+let CopyCost = 2 in {<br>
+<br>
+def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128Regs)>;<br>
+<br>
+def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add TTMP_128Regs)> {<br>
+ let isAllocatable = 0;<br>
}<br>
<br>
+def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128, TTMP_128)>;<br>
+<br>
+} // End CopyCost = 2<br>
+<br>
def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256)> {<br>
// Requires 4 s_mov_b64 to copy<br>
let CopyCost = 4;<br>
<br>
Modified: llvm/trunk/test/MC/AMDGPU/mubuf.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/mubuf.s?rev=267733&r1=267732&r2=267733&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/mubuf.s?rev=267733&r1=267732&r2=267733&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AMDGPU/mubuf.s (original)<br>
+++ llvm/trunk/test/MC/AMDGPU/mubuf.s Wed Apr 27 11:20:23 2016<br>
@@ -18,6 +18,10 @@ buffer_load_dword v1, s[4:7], s1<br>
// SICI: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]<br>
// VI: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]<br>
<br>
+buffer_load_dword v1, ttmp[4:7], s1<br>
+// SICI: buffer_load_dword v1, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x1d,0x01]<br>
+// VI: buffer_load_dword v1, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x1d,0x01]<br>
+<br>
buffer_load_dword v1, s[4:7], s1 offset:4<br>
// SICI: buffer_load_dword v1, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]<br>
// VI: buffer_load_dword v1, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]<br>
@@ -42,6 +46,9 @@ buffer_load_dword v1, s[4:7], s1 offset:<br>
// SICI: buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01]<br>
// VI: buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0,0x00,0x01,0x81,0x01]<br>
<br>
+buffer_load_dword v1, ttmp[4:7], s1 offset:4 glc slc tfe<br>
+// SICI: buffer_load_dword v1, ttmp[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xdd,0x01]<br>
+// VI: buffer_load_dword v1, ttmp[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0,0x00,0x01,0x9d,0x01]<br>
<br>
//===----------------------------------------------------------------------===//<br>
// load - vgpr offset<br>
@@ -75,6 +82,10 @@ buffer_load_dword v1, v2, s[4:7], s1 off<br>
// SICI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xc1,0x01]<br>
// VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x52,0xe0,0x02,0x01,0x81,0x01]<br>
<br>
+buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe<br>
+// SICI: buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xdd,0x01]<br>
+// VI: buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x52,0xe0,0x02,0x01,0x9d,0x01]<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// load - vgpr index<br>
//===----------------------------------------------------------------------===//<br>
@@ -107,6 +118,10 @@ buffer_load_dword v1, v2, s[4:7], s1 idx<br>
// SICI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xc1,0x01]<br>
// VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52,0xe0,0x02,0x01,0x81,0x01]<br>
<br>
+buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe<br>
+// SICI: buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xdd,0x01]<br>
+// VI: buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52,0xe0,0x02,0x01,0x9d,0x01]<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// load - vgpr index and offset<br>
//===----------------------------------------------------------------------===//<br>
@@ -139,6 +154,10 @@ buffer_load_dword v1, v[2:3], s[4:7], s1<br>
// SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xc1,0x01]<br>
// VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x52,0xe0,0x02,0x01,0x81,0x01]<br>
<br>
+buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe<br>
+// SICI: buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xdd,0x71]<br>
+// VI: buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x52,0xe0,0x02,0x01,0x9d,0x71]<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// load - addr64<br>
//===----------------------------------------------------------------------===//<br>
@@ -171,6 +190,10 @@ buffer_load_dword v1, v[2:3], s[4:7], s1<br>
// SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xc1,0x01]<br>
// NOVI: error: instruction not supported on this GPU<br>
<br>
+buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe<br>
+// SICI: buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xdd,0x71]<br>
+// NOVI: error: instruction not supported on this GPU<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// store - immediate offset only<br>
//===----------------------------------------------------------------------===//<br>
@@ -203,6 +226,10 @@ buffer_store_dword v1, s[4:7], s1 offset<br>
// SICI: buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01]<br>
// VI: buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe0,0x00,0x01,0x81,0x01]<br>
<br>
+buffer_store_dword v1, ttmp[4:7], ttmp1 offset:4 glc slc tfe<br>
+// SICI: buffer_store_dword v1, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xdd,0x71]<br>
+// VI: buffer_store_dword v1, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe0,0x00,0x01,0x9d,0x71]<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// store - vgpr offset<br>
//===----------------------------------------------------------------------===//<br>
@@ -235,6 +262,10 @@ buffer_store_dword v1, v2, s[4:7], s1 of<br>
// SICI: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01]<br>
// VI: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x72,0xe0,0x02,0x01,0x81,0x01]<br>
<br>
+buffer_store_dword v1, v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe<br>
+// SICI: buffer_store_dword v1, v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xdd,0x71]<br>
+// VI: buffer_store_dword v1, v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x72,0xe0,0x02,0x01,0x9d,0x71]<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// store - vgpr index<br>
//===----------------------------------------------------------------------===//<br>
@@ -267,6 +298,10 @@ buffer_store_dword v1, v2, s[4:7], s1 id<br>
// SICI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01]<br>
// VI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x72,0xe0,0x02,0x01,0x81,0x01]<br>
<br>
+buffer_store_dword v1, v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe<br>
+// SICI: buffer_store_dword v1, v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xdd,0x71]<br>
+// VI: buffer_store_dword v1, v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x72,0xe0,0x02,0x01,0x9d,0x71]<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// store - vgpr index and offset<br>
//===----------------------------------------------------------------------===//<br>
@@ -299,6 +334,10 @@ buffer_store_dword v1, v[2:3], s[4:7], s<br>
// SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01]<br>
// VI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x72,0xe0,0x02,0x01,0x81,0x01]<br>
<br>
+buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe<br>
+// SICI: buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xdd,0x71]<br>
+// VI: buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x72,0xe0,0x02,0x01,0x9d,0x71]<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// store - addr64<br>
//===----------------------------------------------------------------------===//<br>
@@ -331,6 +370,10 @@ buffer_store_dword v1, v[2:3], s[4:7], s<br>
// SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01]<br>
// NOVI: error: instruction not supported on this GPU<br>
<br>
+buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe<br>
+// SICI: buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xdd,0x71]<br>
+// NOVI: error: instruction not supported on this GPU<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// Instructions<br>
//===----------------------------------------------------------------------===//<br>
@@ -367,10 +410,18 @@ buffer_store_format_xyzw v[1:4], s[4:7],<br>
// SICI: buffer_store_format_xyzw v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x01,0x01]<br>
// VI: buffer_store_format_xyzw v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x01,0x01]<br>
<br>
+buffer_store_format_xyzw v[1:4], ttmp[4:7], ttmp1<br>
+// SICI: buffer_store_format_xyzw v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x1d,0x71]<br>
+// VI: buffer_store_format_xyzw v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x1d,0x71]<br>
+<br>
buffer_load_ubyte v1, s[4:7], s1<br>
// SICI: buffer_load_ubyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x01,0x01]<br>
// VI: buffer_load_ubyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x40,0xe0,0x00,0x01,0x01,0x01]<br>
<br>
+buffer_load_ubyte v1, ttmp[4:7], ttmp1<br>
+// SICI: buffer_load_ubyte v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x1d,0x71]<br>
+// VI: buffer_load_ubyte v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x40,0xe0,0x00,0x01,0x1d,0x71]<br>
+<br>
buffer_load_sbyte v1, s[4:7], s1<br>
// SICI: buffer_load_sbyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x24,0xe0,0x00,0x01,0x01,0x01]<br>
// VI: buffer_load_sbyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x44,0xe0,0x00,0x01,0x01,0x01]<br>
@@ -387,6 +438,10 @@ buffer_load_dword v1, s[4:7], s1<br>
// SICI: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]<br>
// VI: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]<br>
<br>
+buffer_load_dword v1, ttmp[4:7], ttmp1<br>
+// SICI: buffer_load_dword v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x1d,0x71]<br>
+// VI: buffer_load_dword v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x1d,0x71]<br>
+<br>
buffer_load_dwordx2 v[1:2], s[4:7], s1<br>
// SICI: buffer_load_dwordx2 v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x34,0xe0,0x00,0x01,0x01,0x01]<br>
// VI: buffer_load_dwordx2 v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x54,0xe0,0x00,0x01,0x01,0x01]<br>
@@ -395,10 +450,18 @@ buffer_load_dwordx4 v[1:4], s[4:7], s1<br>
// SICI: buffer_load_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x01,0x01,0x01]<br>
// VI: buffer_load_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x5c,0xe0,0x00,0x01,0x01,0x01]<br>
<br>
+buffer_load_dwordx4 v[1:4], ttmp[4:7], ttmp1<br>
+// SICI: buffer_load_dwordx4 v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x01,0x1d,0x71]<br>
+// VI: buffer_load_dwordx4 v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x5c,0xe0,0x00,0x01,0x1d,0x71]<br>
+<br>
buffer_store_byte v1, s[4:7], s1<br>
// SICI: buffer_store_byte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x01,0x01]<br>
// VI: buffer_store_byte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x01,0x01]<br>
<br>
+buffer_store_byte v1, ttmp[4:7], ttmp1<br>
+// SICI: buffer_store_byte v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x1d,0x71]<br>
+// VI: buffer_store_byte v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x1d,0x71]<br>
+<br>
buffer_store_short v1, s[4:7], s1<br>
// SICI: buffer_store_short v1, s[4:7], s1 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x01,0x01]<br>
// VI: buffer_store_short v1, s[4:7], s1 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x01,0x01]<br>
@@ -415,6 +478,10 @@ buffer_store_dwordx4 v[1:4], s[4:7], s1<br>
// SICI: buffer_store_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x01,0x01]<br>
// VI: buffer_store_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x01,0x01]<br>
<br>
+buffer_store_dwordx4 v[1:4], ttmp[4:7], ttmp1<br>
+// SICI: buffer_store_dwordx4 v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x1d,0x71]<br>
+// VI: buffer_store_dwordx4 v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x1d,0x71]<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// Cache invalidation<br>
//===----------------------------------------------------------------------===//<br>
<br>
Modified: llvm/trunk/test/MC/AMDGPU/reg-syntax-extra.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/reg-syntax-extra.s?rev=267733&r1=267732&r2=267733&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/reg-syntax-extra.s?rev=267733&r1=267732&r2=267733&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AMDGPU/reg-syntax-extra.s (original)<br>
+++ llvm/trunk/test/MC/AMDGPU/reg-syntax-extra.s Wed Apr 27 11:20:23 2016<br>
@@ -53,3 +53,31 @@ v_rcp_f64 [v1,v2], [v2,v3]<br>
buffer_load_dwordx4 [v1,v2,v3,v4], [s4,s5,s6,s7], s1<br>
// SICI: buffer_load_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x01,0x01,0x01]<br>
// VI: buffer_load_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x5c,0xe0,0x00,0x01,0x01,0x01]<br>
+<br>
+buffer_load_dword v1, [ttmp4,ttmp5,ttmp6,ttmp7], s1<br>
+// SICI: buffer_load_dword v1, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x1d,0x01]<br>
+// VI: buffer_load_dword v1, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x1d,0x01]<br>
+<br>
+buffer_store_format_xyzw v[1:4], [ttmp4,ttmp5,ttmp6,ttmp7], ttmp1<br>
+// SICI: buffer_store_format_xyzw v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x1d,0x71]<br>
+// VI: buffer_store_format_xyzw v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x1d,0x71]<br>
+<br>
+buffer_load_ubyte v1, [ttmp4,ttmp5,ttmp6,ttmp7], ttmp1<br>
+// SICI: buffer_load_ubyte v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x1d,0x71]<br>
+// VI: buffer_load_ubyte v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x40,0xe0,0x00,0x01,0x1d,0x71]<br>
+<br>
+buffer_store_dwordx4 v[1:4], [ttmp4,ttmp5,ttmp6,ttmp7], ttmp1<br>
+// SICI: buffer_store_dwordx4 v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x1d,0x71]<br>
+// VI: buffer_store_dwordx4 v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x1d,0x71]<br>
+<br>
+s_load_dwordx4 [ttmp4,ttmp5,ttmp6,ttmp7], [ttmp2,ttmp3], ttmp4<br>
+// SICI: s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 ; encoding: [0x74,0x72,0xba,0xc0]<br>
+// VI: s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 ; encoding: [0x39,0x1d,0x08,0xc0,0x74,0x00,0x00,0x00]<br>
+<br>
+s_buffer_load_dword ttmp1, [ttmp4,ttmp5,ttmp6,ttmp7], ttmp4<br>
+// SICI: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x74,0xf4,0x38,0xc2]<br>
+// VI: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x7a,0x1c,0x20,0xc0,0x74,0x00,0x00,0x00]<br>
+<br>
+s_buffer_load_dwordx4 [ttmp8,ttmp9,ttmp10,ttmp11], [ttmp4,ttmp5,ttmp6,ttmp7], ttmp4<br>
+// SICI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x74,0x74,0xbc,0xc2]<br>
+// VI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x3a,0x1e,0x28,0xc0,0x74,0x00,0x00,0x00]<br>
<br>
Modified: llvm/trunk/test/MC/AMDGPU/smrd.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/smrd.s?rev=267733&r1=267732&r2=267733&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/smrd.s?rev=267733&r1=267732&r2=267733&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AMDGPU/smrd.s (original)<br>
+++ llvm/trunk/test/MC/AMDGPU/smrd.s Wed Apr 27 11:20:23 2016<br>
@@ -52,6 +52,10 @@ s_load_dwordx4 s[4:7], s[2:3], s4<br>
// GCN: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x04,0x02,0x82,0xc0]<br>
// VI: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x01,0x01,0x08,0xc0,0x04,0x00,0x00,0x00]<br>
<br>
+s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4<br>
+// GCN: s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 ; encoding: [0x74,0x72,0xba,0xc0]<br>
+// VI: s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 ; encoding: [0x39,0x1d,0x08,0xc0,0x74,0x00,0x00,0x00]<br>
+<br>
s_load_dwordx4 s[100:103], s[2:3], s4<br>
// GCN: s_load_dwordx4 s[100:103], s[2:3], s4 ; encoding: [0x04,0x02,0xb2,0xc0]<br>
// NOVI: error: invalid operand for instruction<br>
@@ -88,6 +92,10 @@ s_buffer_load_dword s1, s[4:7], s4<br>
// GCN: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x04,0x84,0x00,0xc2]<br>
// VI: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x42,0x00,0x20,0xc0,0x04,0x00,0x00,0x00]<br>
<br>
+s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4<br>
+// GCN: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x74,0xf4,0x38,0xc2]<br>
+// VI: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x7a,0x1c,0x20,0xc0,0x74,0x00,0x00,0x00]<br>
+<br>
s_buffer_load_dwordx2 s[8:9], s[4:7], 1<br>
// GCN: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x01,0x05,0x44,0xc2]<br>
// VI: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x02,0x02,0x26,0xc0,0x01,0x00,0x00,0x00]<br>
@@ -104,6 +112,10 @@ s_buffer_load_dwordx4 s[8:11], s[4:7], s<br>
// GCN: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x04,0x04,0x84,0xc2]<br>
// VI: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x02,0x02,0x28,0xc0,0x04,0x00,0x00,0x00]<br>
<br>
+s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4<br>
+// GCN: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x74,0x74,0xbc,0xc2]<br>
+// VI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x3a,0x1e,0x28,0xc0,0x74,0x00,0x00,0x00]<br>
+<br>
s_buffer_load_dwordx4 s[100:103], s[4:7], s4<br>
// GCN: s_buffer_load_dwordx4 s[100:103], s[4:7], s4 ; encoding: [0x04,0x04,0xb2,0xc2]<br>
// NOVI: error: invalid operand for instruction<br>
<br>
<br>
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</blockquote></div><br></div>