<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Apr 22, 2016 at 2:01 PM, Matt Arsenault via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: arsenm<br>
Date: Fri Apr 22 16:01:41 2016<br>
New Revision: 267217<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=267217&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=267217&view=rev</a><br>
Log:<br>
DAGCombiner: Relax alignment restriction when changing store type<br>
<br>
If the target allows the alignment, this should be OK.<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll<br>
Modified:<br>
llvm/trunk/include/llvm/Target/TargetLowering.h<br>
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll<br>
<br>
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=267217&r1=267216&r2=267217&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=267217&r1=267216&r2=267217&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)<br>
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Fri Apr 22 16:01:41 2016<br>
@@ -286,6 +286,15 @@ public:<br>
return true;<br>
}<br>
<br>
+ /// isStoreBitCastBeneficial() - Mirror of isLoadBitCastBeneficial(). Return<br>
+ /// true if the following transform is beneficial.<br>
+ ///<br>
+ /// (store (y (conv x)), y*)) -> (store x, (x*))<br>
+ virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {<br>
+ // Default to the same logic as stores.<br></blockquote><div><br></div><div>Should this comment say "loads" instead of "stores"?</div><div><br></div><div>-- Sean Silva</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+ return isLoadBitCastBeneficial(StoreVT, BitcastVT);<br>
+ }<br>
+<br>
/// Return true if it is expected to be cheaper to do a store of a non-zero<br>
/// vector constant with the given size and type for the address space than to<br>
/// store the individual scalar element constants.<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=267217&r1=267216&r2=267217&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=267217&r1=267216&r2=267217&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Apr 22 16:01:41 2016<br>
@@ -11970,17 +11970,21 @@ SDValue DAGCombiner::visitSTORE(SDNode *<br>
// resultant store does not need a higher alignment than the original.<br>
if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&<br>
ST->isUnindexed()) {<br>
- unsigned OrigAlign = ST->getAlignment();<br>
EVT SVT = Value.getOperand(0).getValueType();<br>
- unsigned Align = DAG.getDataLayout().getABITypeAlignment(<br>
- SVT.getTypeForEVT(*DAG.getContext()));<br>
- if (Align <= OrigAlign &&<br>
- ((!LegalOperations && !ST->isVolatile()) ||<br>
- TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))<br>
- return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0),<br>
- Ptr, ST->getPointerInfo(), ST->isVolatile(),<br>
- ST->isNonTemporal(), OrigAlign,<br>
- ST->getAAInfo());<br>
+ if (((!LegalOperations && !ST->isVolatile()) ||<br>
+ TLI.isOperationLegalOrCustom(ISD::STORE, SVT)) &&<br>
+ TLI.isStoreBitCastBeneficial(Value.getValueType(), SVT)) {<br>
+ unsigned OrigAlign = ST->getAlignment();<br>
+ bool Fast = false;<br>
+ if (TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), SVT,<br>
+ ST->getAddressSpace(), OrigAlign, &Fast) &&<br>
+ Fast) {<br>
+ return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0),<br>
+ Ptr, ST->getPointerInfo(), ST->isVolatile(),<br>
+ ST->isNonTemporal(), OrigAlign,<br>
+ ST->getAAInfo());<br>
+ }<br>
+ }<br>
}<br>
<br>
// Turn 'store undef, Ptr' -> nothing.<br>
<br>
Added: llvm/trunk/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll?rev=267217&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll?rev=267217&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll (added)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll Fri Apr 22 16:01:41 2016<br>
@@ -0,0 +1,53 @@<br>
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s<br>
+<br>
+; GCN-LABEL: {{^}}store_v2i32_as_v4i16_align_4:<br>
+; GCN: s_load_dwordx2<br>
+; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}<br>
+define void @store_v2i32_as_v4i16_align_4(<4 x i16> addrspace(3)* align 4 %out, <2 x i32> %x) #0 {<br>
+ %x.bc = bitcast <2 x i32> %x to <4 x i16><br>
+ store <4 x i16> %x.bc, <4 x i16> addrspace(3)* %out, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; GCN-LABEL: {{^}}store_v4i32_as_v8i16_align_4:<br>
+; GCN: s_load_dwordx4<br>
+; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3<br>
+; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}<br>
+define void @store_v4i32_as_v8i16_align_4(<8 x i16> addrspace(3)* align 4 %out, <4 x i32> %x) #0 {<br>
+ %x.bc = bitcast <4 x i32> %x to <8 x i16><br>
+ store <8 x i16> %x.bc, <8 x i16> addrspace(3)* %out, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; GCN-LABEL: {{^}}store_v2i32_as_i64_align_4:<br>
+; GCN: s_load_dwordx2<br>
+; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}<br>
+define void @store_v2i32_as_i64_align_4(<4 x i16> addrspace(3)* align 4 %out, <2 x i32> %x) #0 {<br>
+ %x.bc = bitcast <2 x i32> %x to <4 x i16><br>
+ store <4 x i16> %x.bc, <4 x i16> addrspace(3)* %out, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; GCN-LABEL: {{^}}store_v4i32_as_v2i64_align_4:<br>
+; GCN: s_load_dwordx4<br>
+; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3<br>
+; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}<br>
+define void @store_v4i32_as_v2i64_align_4(<2 x i64> addrspace(3)* align 4 %out, <4 x i32> %x) #0 {<br>
+ %x.bc = bitcast <4 x i32> %x to <2 x i64><br>
+ store <2 x i64> %x.bc, <2 x i64> addrspace(3)* %out, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; GCN-LABEL: {{^}}store_v4i16_as_v2i32_align_4:<br>
+; GCN: buffer_load_ushort<br>
+; GCN: buffer_load_ushort<br>
+; GCN: buffer_load_ushort<br>
+; GCN: buffer_load_ushort<br>
+; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}<br>
+define void @store_v4i16_as_v2i32_align_4(<2 x i32> addrspace(3)* align 4 %out, <4 x i16> %x) #0 {<br>
+ %x.bc = bitcast <4 x i16> %x to <2 x i32><br>
+ store <2 x i32> %x.bc, <2 x i32> addrspace(3)* %out, align 4<br>
+ ret void<br>
+}<br>
+<br>
+attributes #0 = { nounwind }<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll?rev=267217&r1=267216&r2=267217&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll?rev=267217&r1=267216&r2=267217&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll Fri Apr 22 16:01:41 2016<br>
@@ -119,7 +119,7 @@ entry:<br>
define void @t9(i64* %p) {<br>
; CHECK-LABEL: t9:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0<br>
+; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0<br>
; CHECK-NEXT: vmovups %ymm0, (%rdi)<br>
; CHECK-NEXT: vzeroupper<br>
; CHECK-NEXT: retq<br>
<br>
<br>
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</blockquote></div><br></div></div>