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FYI, I’ve resubmitted the change (rL266086). Let me know if you see any problem.
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<div class="">Artur</div>
<div class=""><br class="">
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<blockquote type="cite" class="">
<div class="">On 08 Apr 2016, at 14:01, Artur Pilipenko via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div>
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<blockquote type="cite" class="">
<div class=""><br class="Apple-interchange-newline">
On 07 Apr 2016, at 23:11, Matthias Braun <<a href="mailto:mbraun@apple.com" class="">mbraun@apple.com</a>> wrote:</div>
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On Apr 1, 2016, at 6:25 AM, Artur Pilipenko <<a href="mailto:apilipenko@azulsystems.com" class="">apilipenko@azulsystems.com</a>> wrote:<br class="">
<br class="">
Are you sure that you are using the updated version of libLTO? It took me a while to set the LTO up (including some confusion with libLTO) but eventually it worked fine. On OS X I used DYLD_LIBRARY_PATH=<build_output>/lib to make it use the right lib.<br class="">
<br class="">
Another evidence that it’s lib versioning issue is that it expects (according to your log) the old mangling llvm.masked.load.v4p0struct.foobar but gets the new one.<br class="">
<br class="">
Artur<br class="">
<br class="">
<blockquote type="cite" class="">On 22 Mar 2016, at 07:42, Matthias Braun <<a href="mailto:mbraun@apple.com" class="">mbraun@apple.com</a>> wrote:<br class="">
<br class="">
Sorry for reporting this with a long delay after the commit (the problem was hidden by an unrelated failure).<br class="">
<br class="">
Could you look into the problem with the reduced testcase below? Would you have a problem with us reverting the patch for the time being? I fear that we may hide other errors if we keep our bots in a broken state much longer...<br class="">
</blockquote>
</blockquote>
<span class="" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; float: none; display: inline !important;">I
just looked at -emit-llvm -S output with latest clang and r263158 re-applied and I see:</span><br class="" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px;">
<span class="" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; float: none; display: inline !important;">...</span><br class="" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px;">
<span class="" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; float: none; display: inline !important;">%wide.masked.load
= call <4 x %struct.foobar*> @llvm.masked.load.v4p0struct.foobar(<4 x %struct.foobar*>* %13, i32 8, <4 x i1> %9, <4 x %struct.foobar*> undef), !tbaa !2, !alias.scope !9</span><br class="" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px;">
<span class="" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; float: none; display: inline !important;">...</span><br class="" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px;">
<span class="" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; float: none; display: inline !important;">is
this the old mangling and should look differently?</span><br class="" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px;">
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</blockquote>
That’s weird, yes it’s the old mangling. But when I do the same I don’t get it:</div>
<div class="">clang -O3 -march=core-avx2 -emit-llvm -S t.c</div>
<div class="">
<div class="">cat t.ll | grep @llvm.masked.load</div>
<div class=""> %wide.masked.load = call <4 x %struct.foobar*> @llvm.masked.load.v4p0struct.foobar.p0v4p0struct.foobar(<4 x %struct.foobar*>* %13, i32 8, <4 x i1> %9, <4 x %struct.foobar*> undef), !tbaa !2, !alias.scope !9</div>
<div class=""> %wide.masked.load34 = call <4 x %struct.foobar*> @llvm.masked.load.v4p0struct.foobar.p0v4p0struct.foobar(<4 x %struct.foobar*>* %15, i32 8, <4 x i1> %10, <4 x %struct.foobar*> undef), !tbaa !2, !alias.scope !9</div>
<div class=""> … cut similar lines …</div>
<div class="">Both .c and .ll files are attached.</div>
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<div class="">Artur</div>
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<blockquote type="cite" class=""><br class="">
It looks like serializing+deserializing the masked loads to bitcode is broken in the LTO setting now:<br class="">
<br class="">
[mbraun@mbraun-imac] ~ > cat t.c<br class="">
typedef struct { int x; } foobar;<br class="">
<br class="">
void foo1(foobar **A, foobar **B, foobar **trigger) {<br class="">
<span class="x_Apple-tab-span" style="white-space: pre;"></span>for (int i=0; i<10000; i++) {<br class="">
<span class="x_Apple-tab-span" style="white-space: pre;"></span><span class="x_Apple-tab-span" style="white-space: pre;"></span>//if (trigger[i] < 100) {<br class="">
<span class="x_Apple-tab-span" style="white-space: pre;"></span><span class="x_Apple-tab-span" style="white-space: pre;"></span>if (trigger[i] != 0) {<br class="">
<span class="x_Apple-tab-span" style="white-space: pre;"></span><span class="x_Apple-tab-span" style="white-space: pre;"></span><span class="x_Apple-tab-span" style="white-space: pre;"></span>A[i] = B[i] + (trigger[i] != 0);<br class="">
<span class="x_Apple-tab-span" style="white-space: pre;"></span><span class="x_Apple-tab-span" style="white-space: pre;"></span>}<br class="">
<span class="x_Apple-tab-span" style="white-space: pre;"></span>}<br class="">
}<br class="">
[mbraun@mbraun-imac] ~ > cat t2.c<br class="">
int main(void) {<br class="">
}<br class="">
[mbraun@mbraun-imac] ~ > clang -O3 -march=core-avx2 -flto -c t.c<br class="">
[mbraun@mbraun-imac] ~ > clang -O3 -march=core-avx2 -flto -c t2.c<br class="">
[mbraun@mbraun-imac] ~ > clang t.o t2.o<br class="">
Intrinsic name not mangled correctly for type arguments! Should be: llvm.masked.load.v4p0struct.foobar<br class="">
<4 x %struct.foobar*> (<4 x %struct.foobar*>*, i32, <4 x i1>, <4 x %struct.foobar*>)* @llvm.masked.load.v4p0struct.foobar.p0v4p0struct.foobar<br class="">
... error repeating a few times...<br class="">
<br class="">
- Matthias<br class="">
<br class="">
<blockquote type="cite" class="">On Mar 16, 2016, at 1:40 PM, Chris Bieneman via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class="">
<br class="">
We have an internal bot failing building SPEC with LTO as a result of this change. It looks like the problem is an assert being hit in the autoupgrader, and I think it is the result of a masked load or store with TBAA.<br class="">
<br class="">
I believe the fix for this is to upgrade TBAA *before* updating intrinsic calls.<br class="">
<br class="">
I’m trying to get a reduced test case and patch prepared.<br class="">
<br class="">
-Chris<br class="">
<br class="">
<blockquote type="cite" class="">On Mar 10, 2016, at 12:39 PM, Artur Pilipenko via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class="">
<br class="">
Author: apilipenko<br class="">
Date: Thu Mar 10 14:39:22 2016<br class="">
New Revision: 263158<br class="">
<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project?rev=263158&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=263158&view=rev</a><br class="">
Log:<br class="">
Support arbitrary addrspace pointers in masked load/store intrinsics<br class="">
<br class="">
This patch fixes the problem which occurs when loop-vectorize tries to use @llvm.masked.load/store intrinsic for a non-default addrspace pointer. It fails with "Calling a function with a bad signature!" assertion in CallInst constructor because it tries to
pass a non-default addrspace pointer to the pointer argument which has default addrspace.<br class="">
<br class="">
The fix is to add pointer type as another overloaded type to @llvm.masked.load/store intrinsics.<br class="">
<br class="">
Reviewed By: reames<br class="">
<br class="">
Differential Revision:<span class="Apple-converted-space"> </span><a href="http://reviews.llvm.org/D17270" class="">http://reviews.llvm.org/D17270</a><br class="">
<br class="">
Modified:<br class="">
llvm/trunk/docs/LangRef.rst<br class="">
llvm/trunk/include/llvm/IR/IRBuilder.h<br class="">
llvm/trunk/include/llvm/IR/Intrinsics.td<br class="">
llvm/trunk/lib/IR/AutoUpgrade.cpp<br class="">
llvm/trunk/lib/IR/IRBuilder.cpp<br class="">
llvm/trunk/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll<br class="">
llvm/trunk/test/Assembler/auto_upgrade_intrinsics.ll<br class="">
llvm/trunk/test/CodeGen/X86/avx512-bugfix-26264.ll<br class="">
llvm/trunk/test/CodeGen/X86/masked_memop.ll<br class="">
llvm/trunk/test/Transforms/InstCombine/masked_intrinsics.ll<br class="">
llvm/trunk/test/Transforms/InstCombine/x86-masked-memops.ll<br class="">
llvm/trunk/test/Transforms/LoopVectorize/X86/masked_load_store.ll<br class="">
<br class="">
Modified: llvm/trunk/docs/LangRef.rst<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.rst?rev=263158&r1=263157&r2=263158&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.rst?rev=263158&r1=263157&r2=263158&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/docs/LangRef.rst (original)<br class="">
+++ llvm/trunk/docs/LangRef.rst Thu Mar 10 14:39:22 2016<br class="">
@@ -11342,12 +11342,12 @@ This is an overloaded intrinsic. The loa<br class="">
<br class="">
::<br class="">
<br class="">
- declare <16 x float> @llvm.masked.load.v16f32 (<16 x float>* <ptr>, i32 <alignment>, <16 x i1> <mask>, <16 x float> <passthru>)<br class="">
- declare <2 x double> @llvm.masked.load.v2f64 (<2 x double>* <ptr>, i32 <alignment>, <2 x i1> <mask>, <2 x double> <passthru>)<br class="">
+ declare <16 x float> @llvm.masked.load.v16f32.p0v16f32 (<16 x float>* <ptr>, i32 <alignment>, <16 x i1> <mask>, <16 x float> <passthru>)<br class="">
+ declare <2 x double> @llvm.masked.load.v2f64.p0v2f64 (<2 x double>* <ptr>, i32 <alignment>, <2 x i1> <mask>, <2 x double> <passthru>)<br class="">
;; The data is a vector of pointers to double<br class="">
- declare <8 x double*> @llvm.masked.load.v8p0f64 (<8 x double*>* <ptr>, i32 <alignment>, <8 x i1> <mask>, <8 x double*> <passthru>)<br class="">
+ declare <8 x double*> @llvm.masked.load.v8p0f64.p0v8p0f64 (<8 x double*>* <ptr>, i32 <alignment>, <8 x i1> <mask>, <8 x double*> <passthru>)<br class="">
;; The data is a vector of function pointers<br class="">
- declare <8 x i32 ()*> @llvm.masked.load.v8p0f_i32f (<8 x i32 ()*>* <ptr>, i32 <alignment>, <8 x i1> <mask>, <8 x i32 ()*> <passthru>)<br class="">
+ declare <8 x i32 ()*> @llvm.masked.load.v8p0f_i32f.p0v8p0f_i32f (<8 x i32 ()*>* <ptr>, i32 <alignment>, <8 x i1> <mask>, <8 x i32 ()*> <passthru>)<br class="">
<br class="">
Overview:<br class="">
"""""""""<br class="">
@@ -11370,7 +11370,7 @@ The result of this operation is equivale<br class="">
<br class="">
::<br class="">
<br class="">
- %res = call <16 x float> @llvm.masked.load.v16f32 (<16 x float>* %ptr, i32 4, <16 x i1>%mask, <16 x float> %passthru)<br class="">
+ %res = call <16 x float> @llvm.masked.load.v16f32.p0v16f32 (<16 x float>* %ptr, i32 4, <16 x i1>%mask, <16 x float> %passthru)<br class="">
<br class="">
;; The result of the two following instructions is identical aside from potential memory access exception<br class="">
%loadlal = load <16 x float>, <16 x float>* %ptr, align 4<br class="">
@@ -11387,12 +11387,12 @@ This is an overloaded intrinsic. The dat<br class="">
<br class="">
::<br class="">
<br class="">
- declare void @llvm.masked.store.v8i32 (<8 x i32> <value>, <8 x i32>* <ptr>, i32 <alignment>, <8 x i1> <mask>)<br class="">
- declare void @llvm.masked.store.v16f32 (<16 x float> <value>, <16 x float>* <ptr>, i32 <alignment>, <16 x i1> <mask>)<br class="">
+ declare void @llvm.masked.store.v8i32.p0v8i32 (<8 x i32> <value>, <8 x i32>* <ptr>, i32 <alignment>, <8 x i1> <mask>)<br class="">
+ declare void @llvm.masked.store.v16f32.p0v16f32 (<16 x float> <value>, <16 x float>* <ptr>, i32 <alignment>, <16 x i1> <mask>)<br class="">
;; The data is a vector of pointers to double<br class="">
- declare void @llvm.masked.store.v8p0f64 (<8 x double*> <value>, <8 x double*>* <ptr>, i32 <alignment>, <8 x i1> <mask>)<br class="">
+ declare void @llvm.masked.store.v8p0f64.p0v8p0f64 (<8 x double*> <value>, <8 x double*>* <ptr>, i32 <alignment>, <8 x i1> <mask>)<br class="">
;; The data is a vector of function pointers<br class="">
- declare void @llvm.masked.store.v4p0f_i32f (<4 x i32 ()*> <value>, <4 x i32 ()*>* <ptr>, i32 <alignment>, <4 x i1> <mask>)<br class="">
+ declare void @llvm.masked.store.v4p0f_i32f.p0v4p0f_i32f (<4 x i32 ()*> <value>, <4 x i32 ()*>* <ptr>, i32 <alignment>, <4 x i1> <mask>)<br class="">
<br class="">
Overview:<br class="">
"""""""""<br class="">
@@ -11413,7 +11413,7 @@ The result of this operation is equivale<br class="">
<br class="">
::<br class="">
<br class="">
- call void @llvm.masked.store.v16f32(<16 x float> %value, <16 x float>* %ptr, i32 4, <16 x i1> %mask)<br class="">
+ call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> %value, <16 x float>* %ptr, i32 4, <16 x i1> %mask)<br class="">
<br class="">
;; The result of the following instructions is identical aside from potential data races and memory access exceptions<br class="">
%oldval = load <16 x float>, <16 x float>* %ptr, align 4<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/IR/IRBuilder.h<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IRBuilder.h?rev=263158&r1=263157&r2=263158&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IRBuilder.h?rev=263158&r1=263157&r2=263158&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/IR/IRBuilder.h (original)<br class="">
+++ llvm/trunk/include/llvm/IR/IRBuilder.h Thu Mar 10 14:39:22 2016<br class="">
@@ -520,9 +520,9 @@ public:<br class="">
<br class="">
private:<br class="">
/// \brief Create a call to a masked intrinsic with given Id.<br class="">
- /// Masked intrinsic has only one overloaded type - data type.<br class="">
CallInst *CreateMaskedIntrinsic(Intrinsic::ID Id, ArrayRef<Value *> Ops,<br class="">
- Type *DataTy, const Twine &Name = "");<br class="">
+ ArrayRef<Type *> OverloadedTypes,<br class="">
+ const Twine &Name = "");<br class="">
<br class="">
Value *getCastedInt8PtrValue(Value *Ptr);<br class="">
};<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/IR/Intrinsics.td<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/Intrinsics.td?rev=263158&r1=263157&r2=263158&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/Intrinsics.td?rev=263158&r1=263157&r2=263158&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/IR/Intrinsics.td (original)<br class="">
+++ llvm/trunk/include/llvm/IR/Intrinsics.td Thu Mar 10 14:39:22 2016<br class="">
@@ -632,13 +632,14 @@ def int_clear_cache : Intrinsic<[], [llv<br class="">
<br class="">
//===-------------------------- Masked Intrinsics -------------------------===//<br class="">
//<br class="">
-def int_masked_store : Intrinsic<[], [llvm_anyvector_ty, LLVMPointerTo<0>,<br class="">
+def int_masked_store : Intrinsic<[], [llvm_anyvector_ty,<br class="">
+ LLVMAnyPointerType<LLVMMatchType<0>>,<br class="">
llvm_i32_ty,<br class="">
LLVMVectorSameWidth<0, llvm_i1_ty>],<br class="">
[IntrReadWriteArgMem]>;<br class="">
<br class="">
def int_masked_load : Intrinsic<[llvm_anyvector_ty],<br class="">
- [LLVMPointerTo<0>, llvm_i32_ty,<br class="">
+ [LLVMAnyPointerType<LLVMMatchType<0>>, llvm_i32_ty,<br class="">
LLVMVectorSameWidth<0, llvm_i1_ty>, LLVMMatchType<0>],<br class="">
[IntrReadArgMem]>;<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/lib/IR/AutoUpgrade.cpp<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=263158&r1=263157&r2=263158&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=263158&r1=263157&r2=263158&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/IR/AutoUpgrade.cpp (original)<br class="">
+++ llvm/trunk/lib/IR/AutoUpgrade.cpp Thu Mar 10 14:39:22 2016<br class="">
@@ -145,6 +145,31 @@ static bool UpgradeIntrinsicFunction1(Fu<br class="">
break;<br class="">
}<br class="">
<br class="">
+ case 'm': {<br class="">
+ if (Name.startswith("masked.load.")) {<br class="">
+ Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() };<br class="">
+ if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) {<br class="">
+ F->setName(Name + ".old");<br class="">
+ NewFn = Intrinsic::getDeclaration(F->getParent(),<br class="">
+ Intrinsic::masked_load,<br class="">
+ Tys);<br class="">
+ return true;<br class="">
+ }<br class="">
+ }<br class="">
+ if (Name.startswith("masked.store.")) {<br class="">
+ auto Args = F->getFunctionType()->params();<br class="">
+ Type *Tys[] = { Args[0], Args[1] };<br class="">
+ if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) {<br class="">
+ F->setName(Name + ".old");<br class="">
+ NewFn = Intrinsic::getDeclaration(F->getParent(),<br class="">
+ Intrinsic::masked_store,<br class="">
+ Tys);<br class="">
+ return true;<br class="">
+ }<br class="">
+ }<br class="">
+ break;<br class="">
+ }<br class="">
+<br class="">
case 'o':<br class="">
// We only need to change the name to match the mangling including the<br class="">
// address space.<br class="">
@@ -790,6 +815,15 @@ void llvm::UpgradeIntrinsicCall(CallInst<br class="">
CI->eraseFromParent();<br class="">
return;<br class="">
}<br class="">
+<br class="">
+ case Intrinsic::masked_load:<br class="">
+ case Intrinsic::masked_store: {<br class="">
+ SmallVector<Value *, 4> Args(CI->arg_operands().begin(),<br class="">
+ CI->arg_operands().end());<br class="">
+ CI->replaceAllUsesWith(Builder.CreateCall(NewFn, Args));<br class="">
+ CI->eraseFromParent();<br class="">
+ return;<br class="">
+ }<br class="">
}<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/lib/IR/IRBuilder.cpp<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/IRBuilder.cpp?rev=263158&r1=263157&r2=263158&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/IRBuilder.cpp?rev=263158&r1=263157&r2=263158&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/IR/IRBuilder.cpp (original)<br class="">
+++ llvm/trunk/lib/IR/IRBuilder.cpp Thu Mar 10 14:39:22 2016<br class="">
@@ -212,13 +212,15 @@ CallInst *IRBuilderBase::CreateAssumptio<br class="">
CallInst *IRBuilderBase::CreateMaskedLoad(Value *Ptr, unsigned Align,<br class="">
Value *Mask, Value *PassThru,<br class="">
const Twine &Name) {<br class="">
- // DataTy is the overloaded type<br class="">
- Type *DataTy = cast<PointerType>(Ptr->getType())->getElementType();<br class="">
+ PointerType *PtrTy = cast<PointerType>(Ptr->getType());<br class="">
+ Type *DataTy = PtrTy->getElementType();<br class="">
assert(DataTy->isVectorTy() && "Ptr should point to a vector");<br class="">
if (!PassThru)<br class="">
PassThru = UndefValue::get(DataTy);<br class="">
+ Type *OverloadedTypes[] = { DataTy, PtrTy };<br class="">
Value *Ops[] = { Ptr, getInt32(Align), Mask, PassThru};<br class="">
- return CreateMaskedIntrinsic(Intrinsic::masked_load, Ops, DataTy, Name);<br class="">
+ return CreateMaskedIntrinsic(Intrinsic::masked_load, Ops,<br class="">
+ OverloadedTypes, Name);<br class="">
}<br class="">
<br class="">
/// \brief Create a call to a Masked Store intrinsic.<br class="">
@@ -229,19 +231,22 @@ CallInst *IRBuilderBase::CreateMaskedLoa<br class="">
/// be accessed in memory<br class="">
CallInst *IRBuilderBase::CreateMaskedStore(Value *Val, Value *Ptr,<br class="">
unsigned Align, Value *Mask) {<br class="">
+ PointerType *PtrTy = cast<PointerType>(Ptr->getType());<br class="">
+ Type *DataTy = PtrTy->getElementType();<br class="">
+ assert(DataTy->isVectorTy() && "Ptr should point to a vector");<br class="">
+ Type *OverloadedTypes[] = { DataTy, PtrTy };<br class="">
Value *Ops[] = { Val, Ptr, getInt32(Align), Mask };<br class="">
- // Type of the data to be stored - the only one overloaded type<br class="">
- return CreateMaskedIntrinsic(Intrinsic::masked_store, Ops, Val->getType());<br class="">
+ return CreateMaskedIntrinsic(Intrinsic::masked_store, Ops, OverloadedTypes);<br class="">
}<br class="">
<br class="">
/// Create a call to a Masked intrinsic, with given intrinsic Id,<br class="">
-/// an array of operands - Ops, and one overloaded type - DataTy<br class="">
+/// an array of operands - Ops, and an array of overloaded types -<br class="">
+/// OverloadedTypes.<br class="">
CallInst *IRBuilderBase::CreateMaskedIntrinsic(Intrinsic::ID Id,<br class="">
ArrayRef<Value *> Ops,<br class="">
- Type *DataTy,<br class="">
+ ArrayRef<Type *> OverloadedTypes,<br class="">
const Twine &Name) {<br class="">
Module *M = BB->getParent()->getParent();<br class="">
- Type *OverloadedTypes[] = { DataTy };<br class="">
Value *TheFn = Intrinsic::getDeclaration(M, Id, OverloadedTypes);<br class="">
return createCallHelper(TheFn, Ops, this, Name);<br class="">
}<br class="">
@@ -270,7 +275,7 @@ CallInst *IRBuilderBase::CreateMaskedGat<br class="">
<br class="">
// We specify only one type when we create this intrinsic. Types of other<br class="">
// arguments are derived from this type.<br class="">
- return CreateMaskedIntrinsic(Intrinsic::masked_gather, Ops, DataTy, Name);<br class="">
+ return CreateMaskedIntrinsic(Intrinsic::masked_gather, Ops, { DataTy }, Name);<br class="">
}<br class="">
<br class="">
/// \brief Create a call to a Masked Scatter intrinsic.<br class="">
@@ -300,7 +305,7 @@ CallInst *IRBuilderBase::CreateMaskedSca<br class="">
<br class="">
// We specify only one type when we create this intrinsic. Types of other<br class="">
// arguments are derived from this type.<br class="">
- return CreateMaskedIntrinsic(Intrinsic::masked_scatter, Ops, DataTy);<br class="">
+ return CreateMaskedIntrinsic(Intrinsic::masked_scatter, Ops, { DataTy });<br class="">
}<br class="">
<br class="">
template <typename T0, typename T1, typename T2, typename T3><br class="">
<br class="">
Modified: llvm/trunk/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll?rev=263158&r1=263157&r2=263158&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll?rev=263158&r1=263157&r2=263158&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll (original)<br class="">
+++ llvm/trunk/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll Thu Mar 10 14:39:22 2016<br class="">
@@ -7,7 +7,7 @@<br class="">
; AVX2: Found an estimated cost of 4 {{.*}}.masked<br class="">
define <2 x double> @test1(<2 x i64> %trigger, <2 x double>* %addr, <2 x double> %dst) {<br class="">
%mask = icmp eq <2 x i64> %trigger, zeroinitializer<br class="">
- %res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst)<br class="">
+ %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst)<br class="">
ret <2 x double> %res<br class="">
}<br class="">
<br class="">
@@ -15,7 +15,7 @@ define <2 x double> @test1(<2 x i64> %tr<br class="">
; AVX2: Found an estimated cost of 4 {{.*}}.masked<br class="">
define <4 x i32> @test2(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %dst) {<br class="">
%mask = icmp eq <4 x i32> %trigger, zeroinitializer<br class="">
- %res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst)<br class="">
+ %res = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst)<br class="">
ret <4 x i32> %res<br class="">
}<br class="">
<br class="">
@@ -23,7 +23,7 @@ define <4 x i32> @test2(<4 x i32> %trigg<br class="">
; AVX2: Found an estimated cost of 4 {{.*}}.masked<br class="">
define void @test3(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) {<br class="">
%mask = icmp eq <4 x i32> %trigger, zeroinitializer<br class="">
- call void @llvm.masked.store.v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -31,7 +31,7 @@ define void @test3(<4 x i32> %trigger, <<br class="">
; AVX2: Found an estimated cost of 4 {{.*}}.masked<br class="">
define <8 x float> @test4(<8 x i32> %trigger, <8 x float>* %addr, <8 x float> %dst) {<br class="">
%mask = icmp eq <8 x i32> %trigger, zeroinitializer<br class="">
- %res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 4, <8 x i1>%mask, <8 x float>%dst)<br class="">
+ %res = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %addr, i32 4, <8 x i1>%mask, <8 x float>%dst)<br class="">
ret <8 x float> %res<br class="">
}<br class="">
<br class="">
@@ -39,7 +39,7 @@ define <8 x float> @test4(<8 x i32> %tri<br class="">
; AVX2: Found an estimated cost of 5 {{.*}}.masked<br class="">
define void @test5(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %val) {<br class="">
%mask = icmp eq <2 x i32> %trigger, zeroinitializer<br class="">
- call void @llvm.masked.store.v2f32(<2 x float>%val, <2 x float>* %addr, i32 4, <2 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v2f32.p0v2f32(<2 x float>%val, <2 x float>* %addr, i32 4, <2 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -47,7 +47,7 @@ define void @test5(<2 x i32> %trigger, <<br class="">
; AVX2: Found an estimated cost of 6 {{.*}}.masked<br class="">
define void @test6(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %val) {<br class="">
%mask = icmp eq <2 x i32> %trigger, zeroinitializer<br class="">
- call void @llvm.masked.store.v2i32(<2 x i32>%val, <2 x i32>* %addr, i32 4, <2 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32>%val, <2 x i32>* %addr, i32 4, <2 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -55,7 +55,7 @@ define void @test6(<2 x i32> %trigger, <<br class="">
; AVX2: Found an estimated cost of 5 {{.*}}.masked<br class="">
define <2 x float> @test7(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %dst) {<br class="">
%mask = icmp eq <2 x i32> %trigger, zeroinitializer<br class="">
- %res = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>%dst)<br class="">
+ %res = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>%dst)<br class="">
ret <2 x float> %res<br class="">
}<br class="">
<br class="">
@@ -63,7 +63,7 @@ define <2 x float> @test7(<2 x i32> %tri<br class="">
; AVX2: Found an estimated cost of 6 {{.*}}.masked<br class="">
define <2 x i32> @test8(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %dst) {<br class="">
%mask = icmp eq <2 x i32> %trigger, zeroinitializer<br class="">
- %res = call <2 x i32> @llvm.masked.load.v2i32(<2 x i32>* %addr, i32 4, <2 x i1>%mask, <2 x i32>%dst)<br class="">
+ %res = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %addr, i32 4, <2 x i1>%mask, <2 x i32>%dst)<br class="">
ret <2 x i32> %res<br class="">
}<br class="">
<br class="">
@@ -279,24 +279,22 @@ declare void @llvm.masked.scatter.v4i32(<br class="">
declare void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32, <16 x i1> %imask)<br class="">
declare <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.v, i32, <16 x i1> %mask, <16 x float>)<br class="">
<br class="">
-declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)<br class="">
-declare <4 x i32> @llvm.masked.load.v4i32(<4 x i32>*, i32, <4 x i1>, <4 x i32>)<br class="">
-declare <2 x i32> @llvm.masked.load.v2i32(<2 x i32>*, i32, <2 x i1>, <2 x i32>)<br class="">
-declare void @llvm.masked.store.v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)<br class="">
-declare void @llvm.masked.store.v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)<br class="">
-declare void @llvm.masked.store.v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)<br class="">
-declare void @llvm.masked.store.v2f32(<2 x float>, <2 x float>*, i32, <2 x i1>)<br class="">
-declare void @llvm.masked.store.v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>)<br class="">
-declare void @llvm.masked.store.v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)<br class="">
-declare void @llvm.masked.store.v16f32p(<16 x float>*, <16 x float>**, i32, <16 x i1>)<br class="">
-declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)<br class="">
-declare <8 x float> @llvm.masked.load.v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>)<br class="">
-declare <4 x float> @llvm.masked.load.v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>)<br class="">
-declare <2 x float> @llvm.masked.load.v2f32(<2 x float>*, i32, <2 x i1>, <2 x float>)<br class="">
-declare <8 x double> @llvm.masked.load.v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>)<br class="">
-declare <4 x double> @llvm.masked.load.v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>)<br class="">
-declare <2 x double> @llvm.masked.load.v2f64(<2 x double>*, i32, <2 x i1>, <2 x double>)<br class="">
-declare void @llvm.masked.store.v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>)<br class="">
-declare void @llvm.masked.store.v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>)<br class="">
-declare void @llvm.masked.store.v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)<br class="">
-<br class="">
+declare <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)<br class="">
+declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32, <4 x i1>, <4 x i32>)<br class="">
+declare <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>*, i32, <2 x i1>, <2 x i32>)<br class="">
+declare void @llvm.masked.store.v16i32.p0v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)<br class="">
+declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)<br class="">
+declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)<br class="">
+declare void @llvm.masked.store.v2f32.p0v2f32(<2 x float>, <2 x float>*, i32, <2 x i1>)<br class="">
+declare void @llvm.masked.store.v2i32.p0v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>)<br class="">
+declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)<br class="">
+declare <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)<br class="">
+declare <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>)<br class="">
+declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>)<br class="">
+declare <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>*, i32, <2 x i1>, <2 x float>)<br class="">
+declare <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>)<br class="">
+declare <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>)<br class="">
+declare <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>*, i32, <2 x i1>, <2 x double>)<br class="">
+declare void @llvm.masked.store.v8f64.p0v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>)<br class="">
+declare void @llvm.masked.store.v2f64.p0v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>)<br class="">
+declare void @llvm.masked.store.v2i64.p0v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)<br class="">
<br class="">
Modified: llvm/trunk/test/Assembler/auto_upgrade_intrinsics.ll<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/auto_upgrade_intrinsics.ll?rev=263158&r1=263157&r2=263158&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/auto_upgrade_intrinsics.ll?rev=263158&r1=263157&r2=263158&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/Assembler/auto_upgrade_intrinsics.ll (original)<br class="">
+++ llvm/trunk/test/Assembler/auto_upgrade_intrinsics.ll Thu Mar 10 14:39:22 2016<br class="">
@@ -54,7 +54,24 @@ entry:<br class="">
define i32 @test.objectsize() {<br class="">
; CHECK-LABEL: @test.objectsize(<br class="">
; CHECK: @llvm.objectsize.i32.p0i8<br class="">
-; CHECK-DAG: declare i32 @llvm.objectsize.i32.p0i8<br class="">
%s = call i32 @llvm.objectsize.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i1 false)<br class="">
ret i32 %s<br class="">
}<br class="">
+<br class="">
+declare <2 x double> @llvm.masked.load.v2f64(<2 x double>* %ptrs, i32, <2 x i1> %mask, <2 x double> %src0)<br class="">
+<br class="">
+define <2 x double> @tests.masked.load(<2 x double>* %ptr, <2 x i1> %mask, <2 x double> %passthru) {<br class="">
+; CHECK-LABEL: @tests.masked.load(<br class="">
+; CHECK: @llvm.masked.load.v2f64.p0v2f64<br class="">
+ %res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %ptr, i32 1, <2 x i1> %mask, <2 x double> %passthru)<br class="">
+ ret <2 x double> %res<br class="">
+}<br class="">
+<br class="">
+declare void @llvm.masked.store.v2f64(<2 x double> %val, <2 x double>* %ptrs, i32, <2 x i1> %mask)<br class="">
+<br class="">
+define void @tests.masked.store(<2 x double>* %ptr, <2 x i1> %mask, <2 x double> %val) {<br class="">
+; CHECK-LABEL: @tests.masked.store(<br class="">
+; CHECK: @llvm.masked.store.v2f64.p0v2f64<br class="">
+ call void @llvm.masked.store.v2f64(<2 x double> %val, <2 x double>* %ptr, i32 3, <2 x i1> %mask)<br class="">
+ ret void<br class="">
+}<br class="">
\ No newline at end of file<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/avx512-bugfix-26264.ll<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-bugfix-26264.ll?rev=263158&r1=263157&r2=263158&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-bugfix-26264.ll?rev=263158&r1=263157&r2=263158&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/avx512-bugfix-26264.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/avx512-bugfix-26264.ll Thu Mar 10 14:39:22 2016<br class="">
@@ -18,7 +18,7 @@ define <32 x double> @test_load_32f64(<3<br class="">
; AVX512BW-NEXT: vmovaps %zmm3, %zmm2<br class="">
; AVX512BW-NEXT: vmovaps %zmm4, %zmm3<br class="">
; AVX512BW-NEXT: retq<br class="">
- %res = call <32 x double> @llvm.masked.load.v32f64(<32 x double>* %ptrs, i32 4, <32 x i1> %mask, <32 x double> %src0)<br class="">
+ %res = call <32 x double> @llvm.masked.load.v32f64.p0v32f64(<32 x double>* %ptrs, i32 4, <32 x i1> %mask, <32 x double> %src0)<br class="">
ret <32 x double> %res<br class="">
}<br class="">
<br class="">
@@ -39,9 +39,9 @@ define <32 x i64> @test_load_32i64(<32 x<br class="">
; AVX512BW-NEXT: vmovaps %zmm3, %zmm2<br class="">
; AVX512BW-NEXT: vmovaps %zmm4, %zmm3<br class="">
; AVX512BW-NEXT: retq<br class="">
- %res = call <32 x i64> @llvm.masked.load.v32i64(<32 x i64>* %ptrs, i32 4, <32 x i1> %mask, <32 x i64> %src0)<br class="">
+ %res = call <32 x i64> @llvm.masked.load.v32i64.p0v32i64(<32 x i64>* %ptrs, i32 4, <32 x i1> %mask, <32 x i64> %src0)<br class="">
ret <32 x i64> %res<br class="">
}<br class="">
<br class="">
-declare <32 x i64> @llvm.masked.load.v32i64(<32 x i64>* %ptrs, i32, <32 x i1> %mask, <32 x i64> %src0)<br class="">
-declare <32 x double> @llvm.masked.load.v32f64(<32 x double>* %ptrs, i32, <32 x i1> %mask, <32 x double> %src0)<br class="">
+declare <32 x i64> @llvm.masked.load.v32i64.p0v32i64(<32 x i64>* %ptrs, i32, <32 x i1> %mask, <32 x i64> %src0)<br class="">
+declare <32 x double> @llvm.masked.load.v32f64.p0v32f64(<32 x double>* %ptrs, i32, <32 x i1> %mask, <32 x double> %src0)<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/masked_memop.ll<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/masked_memop.ll?rev=263158&r1=263157&r2=263158&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/masked_memop.ll?rev=263158&r1=263157&r2=263158&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/masked_memop.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/masked_memop.ll Thu Mar 10 14:39:22 2016<br class="">
@@ -40,7 +40,7 @@ define <16 x i32> @test1(<16 x i32> %tri<br class="">
; AVX512-NEXT: vmovdqu32 (%rdi), %zmm0 {%k1} {z}<br class="">
; AVX512-NEXT: retq<br class="">
%mask = icmp eq <16 x i32> %trigger, zeroinitializer<br class="">
- %res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>undef)<br class="">
+ %res = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>undef)<br class="">
ret <16 x i32> %res<br class="">
}<br class="">
<br class="">
@@ -76,7 +76,7 @@ define <16 x i32> @test2(<16 x i32> %tri<br class="">
; AVX512-NEXT: vmovdqu32 (%rdi), %zmm0 {%k1} {z}<br class="">
; AVX512-NEXT: retq<br class="">
%mask = icmp eq <16 x i32> %trigger, zeroinitializer<br class="">
- %res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>zeroinitializer)<br class="">
+ %res = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>zeroinitializer)<br class="">
ret <16 x i32> %res<br class="">
}<br class="">
<br class="">
@@ -114,7 +114,7 @@ define void @test3(<16 x i32> %trigger,<br class="">
; AVX512-NEXT: vmovdqu32 %zmm1, (%rdi) {%k1}<br class="">
; AVX512-NEXT: retq<br class="">
%mask = icmp eq <16 x i32> %trigger, zeroinitializer<br class="">
- call void @llvm.masked.store.v16i32(<16 x i32>%val, <16 x i32>* %addr, i32 4, <16 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v16i32.p0v16i32(<16 x i32>%val, <16 x i32>* %addr, i32 4, <16 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -155,7 +155,7 @@ define <16 x float> @test4(<16 x i32> %t<br class="">
; AVX512-NEXT: vmovaps %zmm1, %zmm0<br class="">
; AVX512-NEXT: retq<br class="">
%mask = icmp eq <16 x i32> %trigger, zeroinitializer<br class="">
- %res = call <16 x float> @llvm.masked.load.v16f32(<16 x float>* %addr, i32 4, <16 x i1>%mask, <16 x float> %dst)<br class="">
+ %res = call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* %addr, i32 4, <16 x i1>%mask, <16 x float> %dst)<br class="">
ret <16 x float> %res<br class="">
}<br class="">
<br class="">
@@ -210,7 +210,7 @@ define <8 x double> @test5(<8 x i32> %tr<br class="">
; SKX-NEXT: vmovaps %zmm1, %zmm0<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <8 x i32> %trigger, zeroinitializer<br class="">
- %res = call <8 x double> @llvm.masked.load.v8f64(<8 x double>* %addr, i32 4, <8 x i1>%mask, <8 x double>%dst)<br class="">
+ %res = call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* %addr, i32 4, <8 x i1>%mask, <8 x double>%dst)<br class="">
ret <8 x double> %res<br class="">
}<br class="">
<br class="">
@@ -239,7 +239,7 @@ define <2 x double> @test6(<2 x i64> %tr<br class="">
; SKX-NEXT: vmovaps %zmm1, %zmm0<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <2 x i64> %trigger, zeroinitializer<br class="">
- %res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst)<br class="">
+ %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst)<br class="">
ret <2 x double> %res<br class="">
}<br class="">
<br class="">
@@ -268,7 +268,7 @@ define <4 x float> @test7(<4 x i32> %tri<br class="">
; SKX-NEXT: vmovaps %zmm1, %zmm0<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <4 x i32> %trigger, zeroinitializer<br class="">
- %res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 4, <4 x i1>%mask, <4 x float>%dst)<br class="">
+ %res = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %addr, i32 4, <4 x i1>%mask, <4 x float>%dst)<br class="">
ret <4 x float> %res<br class="">
}<br class="">
<br class="">
@@ -305,7 +305,7 @@ define <4 x i32> @test8(<4 x i32> %trigg<br class="">
; SKX-NEXT: vmovaps %zmm1, %zmm0<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <4 x i32> %trigger, zeroinitializer<br class="">
- %res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst)<br class="">
+ %res = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst)<br class="">
ret <4 x i32> %res<br class="">
}<br class="">
<br class="">
@@ -338,7 +338,7 @@ define void @test9(<4 x i32> %trigger, <<br class="">
; SKX-NEXT: vmovdqu32 %xmm1, (%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <4 x i32> %trigger, zeroinitializer<br class="">
- call void @llvm.masked.store.v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -381,7 +381,7 @@ define <4 x double> @test10(<4 x i32> %t<br class="">
; SKX-NEXT: vmovaps %zmm1, %zmm0<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <4 x i32> %trigger, zeroinitializer<br class="">
- %res = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %addr, i32 32, <4 x i1>%mask, <4 x double>%dst)<br class="">
+ %res = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %addr, i32 32, <4 x i1>%mask, <4 x double>%dst)<br class="">
ret <4 x double> %res<br class="">
}<br class="">
<br class="">
@@ -420,7 +420,7 @@ define <4 x double> @test10b(<4 x i32> %<br class="">
; SKX-NEXT: vmovapd (%rdi), %ymm0 {%k1} {z}<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <4 x i32> %trigger, zeroinitializer<br class="">
- %res = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %addr, i32 32, <4 x i1>%mask, <4 x double>zeroinitializer)<br class="">
+ %res = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %addr, i32 32, <4 x i1>%mask, <4 x double>zeroinitializer)<br class="">
ret <4 x double> %res<br class="">
}<br class="">
<br class="">
@@ -462,7 +462,7 @@ define <8 x float> @test11a(<8 x i32> %t<br class="">
; SKX-NEXT: vmovaps %zmm1, %zmm0<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <8 x i32> %trigger, zeroinitializer<br class="">
- %res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 32, <8 x i1>%mask, <8 x float>%dst)<br class="">
+ %res = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %addr, i32 32, <8 x i1>%mask, <8 x float>%dst)<br class="">
ret <8 x float> %res<br class="">
}<br class="">
<br class="">
@@ -507,7 +507,7 @@ define <8 x i32> @test11b(<8 x i1> %mask<br class="">
; SKX-NEXT: vmovdqu32 (%rdi), %ymm1 {%k1}<br class="">
; SKX-NEXT: vmovaps %zmm1, %zmm0<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %addr, i32 4, <8 x i1>%mask, <8 x i32>%dst)<br class="">
+ %res = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %addr, i32 4, <8 x i1>%mask, <8 x i32>%dst)<br class="">
ret <8 x i32> %res<br class="">
}<br class="">
<br class="">
@@ -548,7 +548,7 @@ define <8 x float> @test11c(<8 x i1> %ma<br class="">
; SKX-NEXT: vpmovw2m %xmm0, %k1<br class="">
; SKX-NEXT: vmovaps (%rdi), %ymm0 {%k1} {z}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 32, <8 x i1> %mask, <8 x float> zeroinitializer)<br class="">
+ %res = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %addr, i32 32, <8 x i1> %mask, <8 x float> zeroinitializer)<br class="">
ret <8 x float> %res<br class="">
}<br class="">
<br class="">
@@ -589,7 +589,7 @@ define <8 x i32> @test11d(<8 x i1> %mask<br class="">
; SKX-NEXT: vpmovw2m %xmm0, %k1<br class="">
; SKX-NEXT: vmovdqu32 (%rdi), %ymm0 {%k1} {z}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %addr, i32 4, <8 x i1> %mask, <8 x i32> zeroinitializer)<br class="">
+ %res = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %addr, i32 4, <8 x i1> %mask, <8 x i32> zeroinitializer)<br class="">
ret <8 x i32> %res<br class="">
}<br class="">
<br class="">
@@ -629,7 +629,7 @@ define void @test12(<8 x i32> %trigger,<br class="">
; SKX-NEXT: vmovdqu32 %ymm1, (%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <8 x i32> %trigger, zeroinitializer<br class="">
- call void @llvm.masked.store.v8i32(<8 x i32>%val, <8 x i32>* %addr, i32 4, <8 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>%val, <8 x i32>* %addr, i32 4, <8 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -667,7 +667,7 @@ define void @test13(<16 x i32> %trigger,<br class="">
; AVX512-NEXT: vmovups %zmm1, (%rdi) {%k1}<br class="">
; AVX512-NEXT: retq<br class="">
%mask = icmp eq <16 x i32> %trigger, zeroinitializer<br class="">
- call void @llvm.masked.store.v16f32(<16 x float>%val, <16 x float>* %addr, i32 4, <16 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v16f32.p0v16f32(<16 x float>%val, <16 x float>* %addr, i32 4, <16 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -712,7 +712,7 @@ define void @test14(<2 x i32> %trigger,<br class="">
; SKX-NEXT: vmovups %xmm1, (%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <2 x i32> %trigger, zeroinitializer<br class="">
- call void @llvm.masked.store.v2f32(<2 x float>%val, <2 x float>* %addr, i32 4, <2 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v2f32.p0v2f32(<2 x float>%val, <2 x float>* %addr, i32 4, <2 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -758,7 +758,7 @@ define void @test15(<2 x i32> %trigger,<br class="">
; SKX-NEXT: vpmovqd %xmm1, (%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <2 x i32> %trigger, zeroinitializer<br class="">
- call void @llvm.masked.store.v2i32(<2 x i32>%val, <2 x i32>* %addr, i32 4, <2 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32>%val, <2 x i32>* %addr, i32 4, <2 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -807,7 +807,7 @@ define <2 x float> @test16(<2 x i32> %tr<br class="">
; SKX-NEXT: vmovaps %zmm1, %zmm0<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <2 x i32> %trigger, zeroinitializer<br class="">
- %res = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>%dst)<br class="">
+ %res = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>%dst)<br class="">
ret <2 x float> %res<br class="">
}<br class="">
<br class="">
@@ -863,7 +863,7 @@ define <2 x i32> @test17(<2 x i32> %trig<br class="">
; SKX-NEXT: vpmovsxdq %xmm0, %xmm0<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <2 x i32> %trigger, zeroinitializer<br class="">
- %res = call <2 x i32> @llvm.masked.load.v2i32(<2 x i32>* %addr, i32 4, <2 x i1>%mask, <2 x i32>%dst)<br class="">
+ %res = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %addr, i32 4, <2 x i1>%mask, <2 x i32>%dst)<br class="">
ret <2 x i32> %res<br class="">
}<br class="">
<br class="">
@@ -908,7 +908,7 @@ define <2 x float> @test18(<2 x i32> %tr<br class="">
; SKX-NEXT: vmovups (%rdi), %xmm0 {%k1} {z}<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <2 x i32> %trigger, zeroinitializer<br class="">
- %res = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>undef)<br class="">
+ %res = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>undef)<br class="">
ret <2 x float> %res<br class="">
}<br class="">
<br class="">
@@ -931,7 +931,7 @@ define <4 x float> @load_all(<4 x i32> %<br class="">
; SKX-NEXT: vmovups (%rdi), %xmm0 {%k1} {z}<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <4 x i32> %trigger, zeroinitializer<br class="">
- %res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 4, <4 x i1><i1 true, i1 true, i1 true, i1 true>, <4 x float>undef)<br class="">
+ %res = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %addr, i32 4, <4 x i1><i1 true, i1 true, i1 true, i1 true>, <4 x float>undef)<br class="">
ret <4 x float> %res<br class="">
}<br class="">
<br class="">
@@ -960,7 +960,7 @@ define <4 x float> @mload_constmask_v4f3<br class="">
; SKX-NEXT: kmovw %eax, %k1<br class="">
; SKX-NEXT: vmovups (%rdi), %xmm0 {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 4, <4 x i1> <i1 1, i1 0, i1 1, i1 1>, <4 x float> %dst)<br class="">
+ %res = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %addr, i32 4, <4 x i1> <i1 1, i1 0, i1 1, i1 1>, <4 x float> %dst)<br class="">
ret <4 x float> %res<br class="">
}<br class="">
<br class="">
@@ -994,7 +994,7 @@ define <4 x i32> @mload_constmask_v4i32(<br class="">
; SKX-NEXT: kmovw %eax, %k1<br class="">
; SKX-NEXT: vmovdqu32 (%rdi), %xmm0 {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1> <i1 0, i1 1, i1 1, i1 1>, <4 x i32> %dst)<br class="">
+ %res = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr, i32 4, <4 x i1> <i1 0, i1 1, i1 1, i1 1>, <4 x i32> %dst)<br class="">
ret <4 x i32> %res<br class="">
}<br class="">
<br class="">
@@ -1021,7 +1021,7 @@ define <8 x float> @mload_constmask_v8f3<br class="">
; SKX-NEXT: kmovw %eax, %k1<br class="">
; SKX-NEXT: vmovups (%rdi), %ymm0 {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 4, <8 x i1> <i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0>, <8 x float> %dst)<br class="">
+ %res = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %addr, i32 4, <8 x i1> <i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0>, <8 x float> %dst)<br class="">
ret <8 x float> %res<br class="">
}<br class="">
<br class="">
@@ -1046,7 +1046,7 @@ define <4 x double> @mload_constmask_v4f<br class="">
; SKX-NEXT: kmovw %eax, %k1<br class="">
; SKX-NEXT: vmovupd (%rdi), %ymm0 {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %addr, i32 4, <4 x i1> <i1 1, i1 1, i1 1, i1 0>, <4 x double> %dst)<br class="">
+ %res = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %addr, i32 4, <4 x i1> <i1 1, i1 1, i1 1, i1 0>, <4 x double> %dst)<br class="">
ret <4 x double> %res<br class="">
}<br class="">
<br class="">
@@ -1080,7 +1080,7 @@ define <8 x i32> @mload_constmask_v8i32(<br class="">
; SKX-NEXT: kmovw %eax, %k1<br class="">
; SKX-NEXT: vmovdqu32 (%rdi), %ymm0 {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %addr, i32 4, <8 x i1> <i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1>, <8 x i32> %dst)<br class="">
+ %res = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %addr, i32 4, <8 x i1> <i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1>, <8 x i32> %dst)<br class="">
ret <8 x i32> %res<br class="">
}<br class="">
<br class="">
@@ -1112,7 +1112,7 @@ define <4 x i64> @mload_constmask_v4i64(<br class="">
; SKX-NEXT: kmovw %eax, %k1<br class="">
; SKX-NEXT: vmovdqu64 (%rdi), %ymm0 {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <4 x i64> @llvm.masked.load.v4i64(<4 x i64>* %addr, i32 4, <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i64> %dst)<br class="">
+ %res = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* %addr, i32 4, <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i64> %dst)<br class="">
ret <4 x i64> %res<br class="">
}<br class="">
<br class="">
@@ -1135,7 +1135,7 @@ define <8 x double> @mload_constmask_v8f<br class="">
; AVX512-NEXT: kmovw %eax, %k1<br class="">
; AVX512-NEXT: vmovupd (%rdi), %zmm0 {%k1}<br class="">
; AVX512-NEXT: retq<br class="">
- %res = call <8 x double> @llvm.masked.load.v8f64(<8 x double>* %addr, i32 4, <8 x i1> <i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1>, <8 x double> %dst)<br class="">
+ %res = call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* %addr, i32 4, <8 x i1> <i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1>, <8 x double> %dst)<br class="">
ret <8 x double> %res<br class="">
}<br class="">
<br class="">
@@ -1160,7 +1160,7 @@ define <4 x double> @mload_constmask_v4f<br class="">
; SKX-NEXT: kmovw %eax, %k1<br class="">
; SKX-NEXT: vmovupd (%rdi), %ymm0 {%k1} {z}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %addr, i32 4, <4 x i1> <i1 1, i1 1, i1 1, i1 0>, <4 x double> undef)<br class="">
+ %res = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %addr, i32 4, <4 x i1> <i1 1, i1 1, i1 1, i1 0>, <4 x double> undef)<br class="">
ret <4 x double> %res<br class="">
}<br class="">
<br class="">
@@ -1189,7 +1189,7 @@ define <4 x i64> @mload_constmask_v4i64_<br class="">
; SKX-NEXT: kmovw %eax, %k1<br class="">
; SKX-NEXT: vmovdqu64 (%rdi), %ymm0 {%k1} {z}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <4 x i64> @llvm.masked.load.v4i64(<4 x i64>* %addr, i32 4, <4 x i1> <i1 0, i1 1, i1 1, i1 0>, <4 x i64> undef)<br class="">
+ %res = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* %addr, i32 4, <4 x i1> <i1 0, i1 1, i1 1, i1 0>, <4 x i64> undef)<br class="">
ret <4 x i64> %res<br class="">
}<br class="">
<br class="">
@@ -1218,7 +1218,7 @@ define void @test21(<4 x i32> %trigger,<br class="">
; SKX-NEXT: vmovdqu32 %xmm1, (%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
%mask = icmp eq <4 x i32> %trigger, zeroinitializer<br class="">
- call void @llvm.masked.store.v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1><i1 true, i1 true, i1 true, i1 true>)<br class="">
+ call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1><i1 true, i1 true, i1 true, i1 true>)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -1234,7 +1234,7 @@ define void @one_mask_bit_set1(<4 x i32><br class="">
; AVX512: ## BB#0:<br class="">
; AVX512-NEXT: vmovd %xmm0, (%rdi)<br class="">
; AVX512-NEXT: retq<br class="">
- call void @llvm.masked.store.v4i32(<4 x i32> %val, <4 x i32>* %addr, i32 4, <4 x i1><i1 true, i1 false, i1 false, i1 false>)<br class="">
+ call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %val, <4 x i32>* %addr, i32 4, <4 x i1><i1 true, i1 false, i1 false, i1 false>)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -1250,7 +1250,7 @@ define void @one_mask_bit_set2(<4 x floa<br class="">
; AVX512: ## BB#0:<br class="">
; AVX512-NEXT: vextractps $2, %xmm0, 8(%rdi)<br class="">
; AVX512-NEXT: retq<br class="">
- call void @llvm.masked.store.v4f32(<4 x float> %val, <4 x float>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>)<br class="">
+ call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %val, <4 x float>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -1269,7 +1269,7 @@ define void @one_mask_bit_set3(<4 x i64><br class="">
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0<br class="">
; AVX512-NEXT: vmovq %xmm0, 16(%rdi)<br class="">
; AVX512-NEXT: retq<br class="">
- call void @llvm.masked.store.v4i64(<4 x i64> %val, <4 x i64>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>)<br class="">
+ call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %val, <4 x i64>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -1288,7 +1288,7 @@ define void @one_mask_bit_set4(<4 x doub<br class="">
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0<br class="">
; AVX512-NEXT: vmovhpd %xmm0, 24(%rdi)<br class="">
; AVX512-NEXT: retq<br class="">
- call void @llvm.masked.store.v4f64(<4 x double> %val, <4 x double>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 false, i1 true>)<br class="">
+ call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> %val, <4 x double>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 false, i1 true>)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -1307,7 +1307,7 @@ define void @one_mask_bit_set5(<8 x doub<br class="">
; AVX512-NEXT: vextractf32x4 $3, %zmm0, %xmm0<br class="">
; AVX512-NEXT: vmovlpd %xmm0, 48(%rdi)<br class="">
; AVX512-NEXT: retq<br class="">
- call void @llvm.masked.store.v8f64(<8 x double> %val, <8 x double>* %addr, i32 4, <8 x i1><i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 false>)<br class="">
+ call void @llvm.masked.store.v8f64.p0v8f64(<8 x double> %val, <8 x double>* %addr, i32 4, <8 x i1><i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 false>)<br class="">
ret void<br class="">
}<br class="">
<br class="">
@@ -1323,7 +1323,7 @@ define <4 x i32> @load_one_mask_bit_set1<br class="">
; AVX512: ## BB#0:<br class="">
; AVX512-NEXT: vpinsrd $0, (%rdi), %xmm0, %xmm0<br class="">
; AVX512-NEXT: retq<br class="">
- %res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1><i1 true, i1 false, i1 false, i1 false>, <4 x i32> %val)<br class="">
+ %res = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr, i32 4, <4 x i1><i1 true, i1 false, i1 false, i1 false>, <4 x i32> %val)<br class="">
ret <4 x i32> %res<br class="">
}<br class="">
<br class="">
@@ -1339,7 +1339,7 @@ define <4 x float> @load_one_mask_bit_se<br class="">
; AVX512: ## BB#0:<br class="">
; AVX512-NEXT: vinsertps $32, 8(%rdi), %xmm0, %xmm0 ## xmm0 = xmm0[0,1],mem[0],xmm0[3]<br class="">
; AVX512-NEXT: retq<br class="">
- %res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>, <4 x float> %val)<br class="">
+ %res = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>, <4 x float> %val)<br class="">
ret <4 x float> %res<br class="">
}<br class="">
<br class="">
@@ -1373,7 +1373,7 @@ define <4 x i64> @load_one_mask_bit_set3<br class="">
; SKX-NEXT: vpinsrq $0, 16(%rdi), %xmm1, %xmm1<br class="">
; SKX-NEXT: vinserti32x4 $1, %xmm1, %ymm0, %ymm0<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <4 x i64> @llvm.masked.load.v4i64(<4 x i64>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>, <4 x i64> %val)<br class="">
+ %res = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>, <4 x i64> %val)<br class="">
ret <4 x i64> %res<br class="">
}<br class="">
<br class="">
@@ -1400,7 +1400,7 @@ define <4 x double> @load_one_mask_bit_s<br class="">
; SKX-NEXT: vmovhpd 24(%rdi), %xmm1, %xmm1 ## xmm1 = xmm1[0],mem[0]<br class="">
; SKX-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 false, i1 true>, <4 x double> %val)<br class="">
+ %res = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 false, i1 true>, <4 x double> %val)<br class="">
ret <4 x double> %res<br class="">
}<br class="">
<br class="">
@@ -1421,37 +1421,36 @@ define <8 x double> @load_one_mask_bit_s<br class="">
; AVX512-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0]<br class="">
; AVX512-NEXT: vinsertf32x4 $3, %xmm1, %zmm0, %zmm0<br class="">
; AVX512-NEXT: retq<br class="">
- %res = call <8 x double> @llvm.masked.load.v8f64(<8 x double>* %addr, i32 4, <8 x i1><i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x double> %val)<br class="">
+ %res = call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* %addr, i32 4, <8 x i1><i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x double> %val)<br class="">
ret <8 x double> %res<br class="">
}<br class="">
<br class="">
-declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)<br class="">
-declare <4 x i32> @llvm.masked.load.v4i32(<4 x i32>*, i32, <4 x i1>, <4 x i32>)<br class="">
-declare <2 x i32> @llvm.masked.load.v2i32(<2 x i32>*, i32, <2 x i1>, <2 x i32>)<br class="">
-declare <4 x i64> @llvm.masked.load.v4i64(<4 x i64>*, i32, <4 x i1>, <4 x i64>)<br class="">
-declare void @llvm.masked.store.v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)<br class="">
-declare void @llvm.masked.store.v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)<br class="">
-declare void @llvm.masked.store.v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)<br class="">
-declare void @llvm.masked.store.v4i64(<4 x i64>, <4 x i64>*, i32, <4 x i1>)<br class="">
-declare void @llvm.masked.store.v2f32(<2 x float>, <2 x float>*, i32, <2 x i1>)<br class="">
-declare void @llvm.masked.store.v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>)<br class="">
-declare void @llvm.masked.store.v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>)<br class="">
-declare void @llvm.masked.store.v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)<br class="">
-declare void @llvm.masked.store.v16f32p(<16 x float>*, <16 x float>**, i32, <16 x i1>)<br class="">
-declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)<br class="">
-declare <8 x float> @llvm.masked.load.v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>)<br class="">
-declare <8 x i32> @llvm.masked.load.v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>)<br class="">
-declare <4 x float> @llvm.masked.load.v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>)<br class="">
-declare <2 x float> @llvm.masked.load.v2f32(<2 x float>*, i32, <2 x i1>, <2 x float>)<br class="">
-declare <8 x double> @llvm.masked.load.v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>)<br class="">
-declare <4 x double> @llvm.masked.load.v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>)<br class="">
-declare <2 x double> @llvm.masked.load.v2f64(<2 x double>*, i32, <2 x i1>, <2 x double>)<br class="">
-declare void @llvm.masked.store.v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>)<br class="">
-declare void @llvm.masked.store.v4f64(<4 x double>, <4 x double>*, i32, <4 x i1>)<br class="">
-declare void @llvm.masked.store.v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>)<br class="">
-declare void @llvm.masked.store.v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)<br class="">
+declare <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)<br class="">
+declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32, <4 x i1>, <4 x i32>)<br class="">
+declare <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>*, i32, <2 x i1>, <2 x i32>)<br class="">
+declare <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>*, i32, <4 x i1>, <4 x i64>)<br class="">
+declare void @llvm.masked.store.v16i32.p0v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)<br class="">
+declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)<br class="">
+declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)<br class="">
+declare void @llvm.masked.store.v4i64.p0v4i64(<4 x i64>, <4 x i64>*, i32, <4 x i1>)<br class="">
+declare void @llvm.masked.store.v2f32.p0v2f32(<2 x float>, <2 x float>*, i32, <2 x i1>)<br class="">
+declare void @llvm.masked.store.v2i32.p0v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>)<br class="">
+declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>)<br class="">
+declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)<br class="">
+declare <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)<br class="">
+declare <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>)<br class="">
+declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>)<br class="">
+declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>)<br class="">
+declare <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>*, i32, <2 x i1>, <2 x float>)<br class="">
+declare <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>)<br class="">
+declare <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>)<br class="">
+declare <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>*, i32, <2 x i1>, <2 x double>)<br class="">
+declare void @llvm.masked.store.v8f64.p0v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>)<br class="">
+declare void @llvm.masked.store.v4f64.p0v4f64(<4 x double>, <4 x double>*, i32, <4 x i1>)<br class="">
+declare void @llvm.masked.store.v2f64.p0v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>)<br class="">
+declare void @llvm.masked.store.v2i64.p0v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)<br class="">
<br class="">
-declare <16 x i32*> @llvm.masked.load.v16p0i32(<16 x i32*>*, i32, <16 x i1>, <16 x i32*>)<br class="">
+declare <16 x i32*> @llvm.masked.load.v16p0i32.p0v16p0i32(<16 x i32*>*, i32, <16 x i1>, <16 x i32*>)<br class="">
<br class="">
define <16 x i32*> @test23(<16 x i32*> %trigger, <16 x i32*>* %addr) {<br class="">
; AVX1-LABEL: test23:<br class="">
@@ -1501,13 +1500,13 @@ define <16 x i32*> @test23(<16 x i32*> %<br class="">
; AVX512-NEXT: vmovdqu64 (%rdi), %zmm0 {%k1} {z}<br class="">
; AVX512-NEXT: retq<br class="">
%mask = icmp eq <16 x i32*> %trigger, zeroinitializer<br class="">
- %res = call <16 x i32*> @llvm.masked.load.v16p0i32(<16 x i32*>* %addr, i32 4, <16 x i1>%mask, <16 x i32*>zeroinitializer)<br class="">
+ %res = call <16 x i32*> @llvm.masked.load.v16p0i32.p0v16p0i32(<16 x i32*>* %addr, i32 4, <16 x i1>%mask, <16 x i32*>zeroinitializer)<br class="">
ret <16 x i32*> %res<br class="">
}<br class="">
<br class="">
%mystruct = type { i16, i16, [1 x i8*] }<br class="">
<br class="">
-declare <16 x %mystruct*> @llvm.masked.load.v16p0mystruct(<16 x %mystruct*>*, i32, <16 x i1>, <16 x %mystruct*>)<br class="">
+declare <16 x %mystruct*> @llvm.masked.load.v16p0mystruct.p0v16p0mystruct(<16 x %mystruct*>*, i32, <16 x i1>, <16 x %mystruct*>)<br class="">
<br class="">
define <16 x %mystruct*> @test24(<16 x i1> %mask, <16 x %mystruct*>* %addr) {<br class="">
; AVX1-LABEL: test24:<br class="">
@@ -1596,7 +1595,7 @@ define <16 x %mystruct*> @test24(<16 x i<br class="">
; SKX-NEXT: kshiftrw $8, %k1, %k1<br class="">
; SKX-NEXT: vmovdqu64 64(%rdi), %zmm1 {%k1} {z}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <16 x %mystruct*> @llvm.masked.load.v16p0mystruct(<16 x %mystruct*>* %addr, i32 4, <16 x i1>%mask, <16 x %mystruct*>zeroinitializer)<br class="">
+ %res = call <16 x %mystruct*> @llvm.masked.load.v16p0mystruct.p0v16p0mystruct(<16 x %mystruct*>* %addr, i32 4, <16 x i1>%mask, <16 x %mystruct*>zeroinitializer)<br class="">
ret <16 x %mystruct*> %res<br class="">
}<br class="">
<br class="">
@@ -1687,10 +1686,10 @@ define void @test_store_16i64(<16 x i64><br class="">
; SKX-NEXT: kshiftrw $8, %k1, %k1<br class="">
; SKX-NEXT: vmovdqu64 %zmm2, 64(%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- call void @llvm.masked.store.v16i64(<16 x i64> %src0, <16 x i64>* %ptrs, i32 4, <16 x i1> %mask)<br class="">
+ call void @llvm.masked.store.v16i64.p0v16i64(<16 x i64> %src0, <16 x i64>* %ptrs, i32 4, <16 x i1> %mask)<br class="">
ret void<br class="">
}<br class="">
-declare void @llvm.masked.store.v16i64(<16 x i64> %src0, <16 x i64>* %ptrs, i32, <16 x i1> %mask)<br class="">
+declare void @llvm.masked.store.v16i64.p0v16i64(<16 x i64> %src0, <16 x i64>* %ptrs, i32, <16 x i1> %mask)<br class="">
<br class="">
define void @test_store_16f64(<16 x double>* %ptrs, <16 x i1> %mask, <16 x double> %src0) {<br class="">
; AVX1-LABEL: test_store_16f64:<br class="">
@@ -1779,10 +1778,10 @@ define void @test_store_16f64(<16 x doub<br class="">
; SKX-NEXT: kshiftrw $8, %k1, %k1<br class="">
; SKX-NEXT: vmovupd %zmm2, 64(%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- call void @llvm.masked.store.v16f64(<16 x double> %src0, <16 x double>* %ptrs, i32 4, <16 x i1> %mask)<br class="">
+ call void @llvm.masked.store.v16f64.p0v16f64(<16 x double> %src0, <16 x double>* %ptrs, i32 4, <16 x i1> %mask)<br class="">
ret void<br class="">
}<br class="">
-declare void @llvm.masked.store.v16f64(<16 x double> %src0, <16 x double>* %ptrs, i32, <16 x i1> %mask)<br class="">
+declare void @llvm.masked.store.v16f64.p0v16f64(<16 x double> %src0, <16 x double>* %ptrs, i32, <16 x i1> %mask)<br class="">
<br class="">
define <16 x i64> @test_load_16i64(<16 x i64>* %ptrs, <16 x i1> %mask, <16 x i64> %src0) {<br class="">
; AVX1-LABEL: test_load_16i64:<br class="">
@@ -1883,10 +1882,10 @@ define <16 x i64> @test_load_16i64(<16 x<br class="">
; SKX-NEXT: vmovaps %zmm1, %zmm0<br class="">
; SKX-NEXT: vmovaps %zmm2, %zmm1<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <16 x i64> @llvm.masked.load.v16i64(<16 x i64>* %ptrs, i32 4, <16 x i1> %mask, <16 x i64> %src0)<br class="">
+ %res = call <16 x i64> @llvm.masked.load.v16i64.p0v16i64(<16 x i64>* %ptrs, i32 4, <16 x i1> %mask, <16 x i64> %src0)<br class="">
ret <16 x i64> %res<br class="">
}<br class="">
-declare <16 x i64> @llvm.masked.load.v16i64(<16 x i64>* %ptrs, i32, <16 x i1> %mask, <16 x i64> %src0)<br class="">
+declare <16 x i64> @llvm.masked.load.v16i64.p0v16i64(<16 x i64>* %ptrs, i32, <16 x i1> %mask, <16 x i64> %src0)<br class="">
<br class="">
define <16 x double> @test_load_16f64(<16 x double>* %ptrs, <16 x i1> %mask, <16 x double> %src0) {<br class="">
; AVX1-LABEL: test_load_16f64:<br class="">
@@ -1987,10 +1986,10 @@ define <16 x double> @test_load_16f64(<1<br class="">
; SKX-NEXT: vmovaps %zmm1, %zmm0<br class="">
; SKX-NEXT: vmovaps %zmm2, %zmm1<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <16 x double> @llvm.masked.load.v16f64(<16 x double>* %ptrs, i32 4, <16 x i1> %mask, <16 x double> %src0)<br class="">
+ %res = call <16 x double> @llvm.masked.load.v16f64.p0v16f64(<16 x double>* %ptrs, i32 4, <16 x i1> %mask, <16 x double> %src0)<br class="">
ret <16 x double> %res<br class="">
}<br class="">
-declare <16 x double> @llvm.masked.load.v16f64(<16 x double>* %ptrs, i32, <16 x i1> %mask, <16 x double> %src0)<br class="">
+declare <16 x double> @llvm.masked.load.v16f64.p0v16f64(<16 x double>* %ptrs, i32, <16 x i1> %mask, <16 x double> %src0)<br class="">
<br class="">
define <32 x double> @test_load_32f64(<32 x double>* %ptrs, <32 x i1> %mask, <32 x double> %src0) {<br class="">
; AVX1-LABEL: test_load_32f64:<br class="">
@@ -2218,10 +2217,11 @@ define <32 x double> @test_load_32f64(<3<br class="">
; SKX-NEXT: vmovaps %zmm3, %zmm2<br class="">
; SKX-NEXT: vmovaps %zmm4, %zmm3<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <32 x double> @llvm.masked.load.v32f64(<32 x double>* %ptrs, i32 4, <32 x i1> %mask, <32 x double> %src0)<br class="">
+ %res = call <32 x double> @llvm.masked.load.v32f64.p0v32f64(<32 x double>* %ptrs, i32 4, <32 x i1> %mask, <32 x double> %src0)<br class="">
ret <32 x double> %res<br class="">
}<br class="">
-declare <32 x double> @llvm.masked.load.v32f64(<32 x double>* %ptrs, i32, <32 x i1> %mask, <32 x double> %src0)<br class="">
+<br class="">
+declare <32 x double> @llvm.masked.load.v32f64.p0v32f64(<32 x double>* %ptrs, i32, <32 x i1> %mask, <32 x double> %src0)<br class="">
<br class="">
define <16 x i8> @test_mask_load_16xi8(<16 x i1> %mask, <16 x i8>* %addr, <16 x i8> %val) {<br class="">
; SKX-LABEL: test_mask_load_16xi8:<br class="">
@@ -2230,10 +2230,10 @@ define <16 x i8> @test_mask_load_16xi8(<<br class="">
; SKX-NEXT: vpmovb2m %xmm0, %k1<br class="">
; SKX-NEXT: vmovdqu8 (%rdi), %xmm0 {%k1} {z}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <16 x i8> @llvm.masked.load.v16i8(<16 x i8>* %addr, i32 4, <16 x i1>%mask, <16 x i8> undef)<br class="">
+ %res = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %addr, i32 4, <16 x i1>%mask, <16 x i8> undef)<br class="">
ret <16 x i8> %res<br class="">
}<br class="">
-declare <16 x i8> @llvm.masked.load.v16i8(<16 x i8>*, i32, <16 x i1>, <16 x i8>)<br class="">
+declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32, <16 x i1>, <16 x i8>)<br class="">
<br class="">
define <32 x i8> @test_mask_load_32xi8(<32 x i1> %mask, <32 x i8>* %addr, <32 x i8> %val) {<br class="">
; SKX-LABEL: test_mask_load_32xi8:<br class="">
@@ -2242,10 +2242,10 @@ define <32 x i8> @test_mask_load_32xi8(<<br class="">
; SKX-NEXT: vpmovb2m %ymm0, %k1<br class="">
; SKX-NEXT: vmovdqu8 (%rdi), %ymm0 {%k1} {z}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <32 x i8> @llvm.masked.load.v32i8(<32 x i8>* %addr, i32 4, <32 x i1>%mask, <32 x i8> zeroinitializer)<br class="">
+ %res = call <32 x i8> @llvm.masked.load.v32i8.p0v32i8(<32 x i8>* %addr, i32 4, <32 x i1>%mask, <32 x i8> zeroinitializer)<br class="">
ret <32 x i8> %res<br class="">
}<br class="">
-declare <32 x i8> @llvm.masked.load.v32i8(<32 x i8>*, i32, <32 x i1>, <32 x i8>)<br class="">
+declare <32 x i8> @llvm.masked.load.v32i8.p0v32i8(<32 x i8>*, i32, <32 x i1>, <32 x i8>)<br class="">
<br class="">
define <64 x i8> @test_mask_load_64xi8(<64 x i1> %mask, <64 x i8>* %addr, <64 x i8> %val) {<br class="">
; SKX-LABEL: test_mask_load_64xi8:<br class="">
@@ -2255,10 +2255,10 @@ define <64 x i8> @test_mask_load_64xi8(<<br class="">
; SKX-NEXT: vmovdqu8 (%rdi), %zmm1 {%k1}<br class="">
; SKX-NEXT: vmovaps %zmm1, %zmm0<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <64 x i8> @llvm.masked.load.v64i8(<64 x i8>* %addr, i32 4, <64 x i1>%mask, <64 x i8> %val)<br class="">
+ %res = call <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>* %addr, i32 4, <64 x i1>%mask, <64 x i8> %val)<br class="">
ret <64 x i8> %res<br class="">
}<br class="">
-declare <64 x i8> @llvm.masked.load.v64i8(<64 x i8>*, i32, <64 x i1>, <64 x i8>)<br class="">
+declare <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>*, i32, <64 x i1>, <64 x i8>)<br class="">
<br class="">
define <8 x i16> @test_mask_load_8xi16(<8 x i1> %mask, <8 x i16>* %addr, <8 x i16> %val) {<br class="">
; SKX-LABEL: test_mask_load_8xi16:<br class="">
@@ -2267,10 +2267,10 @@ define <8 x i16> @test_mask_load_8xi16(<<br class="">
; SKX-NEXT: vpmovw2m %xmm0, %k1<br class="">
; SKX-NEXT: vmovdqu16 (%rdi), %xmm0 {%k1} {z}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <8 x i16> @llvm.masked.load.v8i16(<8 x i16>* %addr, i32 4, <8 x i1>%mask, <8 x i16> undef)<br class="">
+ %res = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %addr, i32 4, <8 x i1>%mask, <8 x i16> undef)<br class="">
ret <8 x i16> %res<br class="">
}<br class="">
-declare <8 x i16> @llvm.masked.load.v8i16(<8 x i16>*, i32, <8 x i1>, <8 x i16>)<br class="">
+declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32, <8 x i1>, <8 x i16>)<br class="">
<br class="">
define <16 x i16> @test_mask_load_16xi16(<16 x i1> %mask, <16 x i16>* %addr, <16 x i16> %val) {<br class="">
; SKX-LABEL: test_mask_load_16xi16:<br class="">
@@ -2279,10 +2279,10 @@ define <16 x i16> @test_mask_load_16xi16<br class="">
; SKX-NEXT: vpmovb2m %xmm0, %k1<br class="">
; SKX-NEXT: vmovdqu16 (%rdi), %ymm0 {%k1} {z}<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <16 x i16> @llvm.masked.load.v16i16(<16 x i16>* %addr, i32 4, <16 x i1>%mask, <16 x i16> zeroinitializer)<br class="">
+ %res = call <16 x i16> @llvm.masked.load.v16i16.p0v16i16(<16 x i16>* %addr, i32 4, <16 x i1>%mask, <16 x i16> zeroinitializer)<br class="">
ret <16 x i16> %res<br class="">
}<br class="">
-declare <16 x i16> @llvm.masked.load.v16i16(<16 x i16>*, i32, <16 x i1>, <16 x i16>)<br class="">
+declare <16 x i16> @llvm.masked.load.v16i16.p0v16i16(<16 x i16>*, i32, <16 x i1>, <16 x i16>)<br class="">
<br class="">
define <32 x i16> @test_mask_load_32xi16(<32 x i1> %mask, <32 x i16>* %addr, <32 x i16> %val) {<br class="">
; SKX-LABEL: test_mask_load_32xi16:<br class="">
@@ -2292,10 +2292,10 @@ define <32 x i16> @test_mask_load_32xi16<br class="">
; SKX-NEXT: vmovdqu16 (%rdi), %zmm1 {%k1}<br class="">
; SKX-NEXT: vmovaps %zmm1, %zmm0<br class="">
; SKX-NEXT: retq<br class="">
- %res = call <32 x i16> @llvm.masked.load.v32i16(<32 x i16>* %addr, i32 4, <32 x i1>%mask, <32 x i16> %val)<br class="">
+ %res = call <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>* %addr, i32 4, <32 x i1>%mask, <32 x i16> %val)<br class="">
ret <32 x i16> %res<br class="">
}<br class="">
-declare <32 x i16> @llvm.masked.load.v32i16(<32 x i16>*, i32, <32 x i1>, <32 x i16>)<br class="">
+declare <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>*, i32, <32 x i1>, <32 x i16>)<br class="">
<br class="">
define void @test_mask_store_16xi8(<16 x i1> %mask, <16 x i8>* %addr, <16 x i8> %val) {<br class="">
; SKX-LABEL: test_mask_store_16xi8:<br class="">
@@ -2304,10 +2304,10 @@ define void @test_mask_store_16xi8(<16 x<br class="">
; SKX-NEXT: vpmovb2m %xmm0, %k1<br class="">
; SKX-NEXT: vmovdqu8 %xmm1, (%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- call void @llvm.masked.store.v16i8(<16 x i8> %val, <16 x i8>* %addr, i32 4, <16 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %val, <16 x i8>* %addr, i32 4, <16 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
-declare void @llvm.masked.store.v16i8(<16 x i8>, <16 x i8>*, i32, <16 x i1>)<br class="">
+declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32, <16 x i1>)<br class="">
<br class="">
define void @test_mask_store_32xi8(<32 x i1> %mask, <32 x i8>* %addr, <32 x i8> %val) {<br class="">
; SKX-LABEL: test_mask_store_32xi8:<br class="">
@@ -2316,10 +2316,10 @@ define void @test_mask_store_32xi8(<32 x<br class="">
; SKX-NEXT: vpmovb2m %ymm0, %k1<br class="">
; SKX-NEXT: vmovdqu8 %ymm1, (%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- call void @llvm.masked.store.v32i8(<32 x i8> %val, <32 x i8>* %addr, i32 4, <32 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v32i8.p0v32i8(<32 x i8> %val, <32 x i8>* %addr, i32 4, <32 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
-declare void @llvm.masked.store.v32i8(<32 x i8>, <32 x i8>*, i32, <32 x i1>)<br class="">
+declare void @llvm.masked.store.v32i8.p0v32i8(<32 x i8>, <32 x i8>*, i32, <32 x i1>)<br class="">
<br class="">
define void @test_mask_store_64xi8(<64 x i1> %mask, <64 x i8>* %addr, <64 x i8> %val) {<br class="">
; SKX-LABEL: test_mask_store_64xi8:<br class="">
@@ -2328,10 +2328,10 @@ define void @test_mask_store_64xi8(<64 x<br class="">
; SKX-NEXT: vpmovb2m %zmm0, %k1<br class="">
; SKX-NEXT: vmovdqu8 %zmm1, (%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- call void @llvm.masked.store.v64i8(<64 x i8> %val, <64 x i8>* %addr, i32 4, <64 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v64i8.p0v64i8(<64 x i8> %val, <64 x i8>* %addr, i32 4, <64 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
-declare void @llvm.masked.store.v64i8(<64 x i8>, <64 x i8>*, i32, <64 x i1>)<br class="">
+declare void @llvm.masked.store.v64i8.p0v64i8(<64 x i8>, <64 x i8>*, i32, <64 x i1>)<br class="">
<br class="">
define void @test_mask_store_8xi16(<8 x i1> %mask, <8 x i16>* %addr, <8 x i16> %val) {<br class="">
; SKX-LABEL: test_mask_store_8xi16:<br class="">
@@ -2340,10 +2340,10 @@ define void @test_mask_store_8xi16(<8 x<br class="">
; SKX-NEXT: vpmovw2m %xmm0, %k1<br class="">
; SKX-NEXT: vmovdqu16 %xmm1, (%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- call void @llvm.masked.store.v8i16(<8 x i16> %val, <8 x i16>* %addr, i32 4, <8 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %val, <8 x i16>* %addr, i32 4, <8 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
-declare void @llvm.masked.store.v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>)<br class="">
+declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>)<br class="">
<br class="">
define void @test_mask_store_16xi16(<16 x i1> %mask, <16 x i16>* %addr, <16 x i16> %val) {<br class="">
; SKX-LABEL: test_mask_store_16xi16:<br class="">
@@ -2352,10 +2352,10 @@ define void @test_mask_store_16xi16(<16<br class="">
; SKX-NEXT: vpmovb2m %xmm0, %k1<br class="">
; SKX-NEXT: vmovdqu16 %ymm1, (%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- call void @llvm.masked.store.v16i16(<16 x i16> %val, <16 x i16>* %addr, i32 4, <16 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v16i16.p0v16i16(<16 x i16> %val, <16 x i16>* %addr, i32 4, <16 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
-declare void @llvm.masked.store.v16i16(<16 x i16>, <16 x i16>*, i32, <16 x i1>)<br class="">
+declare void @llvm.masked.store.v16i16.p0v16i16(<16 x i16>, <16 x i16>*, i32, <16 x i1>)<br class="">
<br class="">
define void @test_mask_store_32xi16(<32 x i1> %mask, <32 x i16>* %addr, <32 x i16> %val) {<br class="">
; SKX-LABEL: test_mask_store_32xi16:<br class="">
@@ -2364,7 +2364,8 @@ define void @test_mask_store_32xi16(<32<br class="">
; SKX-NEXT: vpmovb2m %ymm0, %k1<br class="">
; SKX-NEXT: vmovdqu16 %zmm1, (%rdi) {%k1}<br class="">
; SKX-NEXT: retq<br class="">
- call void @llvm.masked.store.v32i16(<32 x i16> %val, <32 x i16>* %addr, i32 4, <32 x i1>%mask)<br class="">
+ call void @llvm.masked.store.v32i16.p0v32i16(<32 x i16> %val, <32 x i16>* %addr, i32 4, <32 x i1>%mask)<br class="">
ret void<br class="">
}<br class="">
-declare void @llvm.masked.store.v32i16(<32 x i16>, <32 x i16>*, i32, <32 x i1>)<br class="">
+<br class="">
+declare void @llvm.masked.store.v32i16.p0v32i16(<32 x i16>, <32 x i16>*, i32, <32 x i1>)<br class="">
<br class="">
Modified: llvm/trunk/test/Transforms/InstCombine/masked_intrinsics.ll<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/masked_intrinsics.ll?rev=263158&r1=263157&r2=263158&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/masked_intrinsics.ll?rev=263158&r1=263157&r2=263158&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/Transforms/InstCombine/masked_intrinsics.ll (original)<br class="">
+++ llvm/trunk/test/Transforms/InstCombine/masked_intrinsics.ll Thu Mar 10 14:39:22 2016<br class="">
@@ -1,12 +1,12 @@<br class="">
; RUN: opt -instcombine -S < %s | FileCheck %s<br class="">
<br class="">
-declare <2 x double> @llvm.masked.load.v2f64(<2 x double>* %ptrs, i32, <2 x i1> %mask, <2 x double> %src0)<br class="">
-declare void @llvm.masked.store.v2f64(<2 x double> %val, <2 x double>* %ptrs, i32, <2 x i1> %mask)<br class="">
+declare <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptrs, i32, <2 x i1> %mask, <2 x double> %src0)<br class="">
+declare void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %val, <2 x double>* %ptrs, i32, <2 x i1> %mask)<br class="">
declare <2 x double> @llvm.masked.gather.v2f64(<2 x double*> %ptrs, i32, <2 x i1> %mask, <2 x double> %passthru)<br class="">
declare void @llvm.masked.scatter.v2f64(<2 x double> %val, <2 x double*> %ptrs, i32, <2 x i1> %mask)<br class="">
<br class="">
define <2 x double> @load_zeromask(<2 x double>* %ptr, <2 x double> %passthru) {<br class="">
- %res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %ptr, i32 1, <2 x i1> zeroinitializer, <2 x double> %passthru)<br class="">
+ %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptr, i32 1, <2 x i1> zeroinitializer, <2 x double> %passthru)<br class="">
ret <2 x double> %res<br class="">
<br class="">
; CHECK-LABEL: @load_zeromask(<br class="">
@@ -14,7 +14,7 @@ define <2 x double> @load_zeromask(<2 x<br class="">
}<br class="">
<br class="">
define <2 x double> @load_onemask(<2 x double>* %ptr, <2 x double> %passthru) {<br class="">
- %res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %ptr, i32 2, <2 x i1> <i1 1, i1 1>, <2 x double> %passthru)<br class="">
+ %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptr, i32 2, <2 x i1> <i1 1, i1 1>, <2 x double> %passthru)<br class="">
ret <2 x double> %res<br class="">
<br class="">
; CHECK-LABEL: @load_onemask(<br class="">
@@ -23,7 +23,7 @@ define <2 x double> @load_onemask(<2 x d<br class="">
}<br class="">
<br class="">
define void @store_zeromask(<2 x double>* %ptr, <2 x double> %val) {<br class="">
- call void @llvm.masked.store.v2f64(<2 x double> %val, <2 x double>* %ptr, i32 3, <2 x i1> zeroinitializer)<br class="">
+ call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %val, <2 x double>* %ptr, i32 3, <2 x i1> zeroinitializer)<br class="">
ret void<br class="">
<br class="">
; CHECK-LABEL: @store_zeromask(<br class="">
@@ -31,7 +31,7 @@ define void @store_zeromask(<2 x double><br class="">
}<br class="">
<br class="">
define void @store_onemask(<2 x double>* %ptr, <2 x double> %val) {<br class="">
- call void @llvm.masked.store.v2f64(<2 x double> %val, <2 x double>* %ptr, i32 4, <2 x i1> <i1 1, i1 1>)<br class="">
+ call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %val, <2 x double>* %ptr, i32 4, <2 x i1> <i1 1, i1 1>)<br class="">
ret void<br class="">
<br class="">
; CHECK-LABEL: @store_onemask(<br class="">
<br class="">
Modified: llvm/trunk/test/Transforms/InstCombine/x86-masked-memops.ll<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/x86-masked-memops.ll?rev=263158&r1=263157&r2=263158&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/x86-masked-memops.ll?rev=263158&r1=263157&r2=263158&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/Transforms/InstCombine/x86-masked-memops.ll (original)<br class="">
+++ llvm/trunk/test/Transforms/InstCombine/x86-masked-memops.ll Thu Mar 10 14:39:22 2016<br class="">
@@ -53,7 +53,7 @@ define <4 x float> @mload_one_one(i8* %f<br class="">
<br class="">
; CHECK-LABEL: @mload_one_one(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x float>*<br class="">
-; CHECK-NEXT: %1 = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> undef)<br class="">
+; CHECK-NEXT: %1 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> undef)<br class="">
; CHECK-NEXT: ret <4 x float> %1<br class="">
}<br class="">
<br class="">
@@ -65,7 +65,7 @@ define <2 x double> @mload_one_one_doubl<br class="">
<br class="">
; CHECK-LABEL: @mload_one_one_double(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <2 x double>*<br class="">
-; CHECK-NEXT: %1 = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>, <2 x double> undef)<br class="">
+; CHECK-NEXT: %1 = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>, <2 x double> undef)<br class="">
; CHECK-NEXT: ret <2 x double> %1<br class="">
}<br class="">
<br class="">
@@ -77,7 +77,7 @@ define <8 x float> @mload_v8f32(i8* %f)<br class="">
<br class="">
; CHECK-LABEL: @mload_v8f32(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <8 x float>*<br class="">
-; CHECK-NEXT: %1 = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x float> undef)<br class="">
+; CHECK-NEXT: %1 = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x float> undef)<br class="">
; CHECK-NEXT: ret <8 x float> %1<br class="">
}<br class="">
<br class="">
@@ -87,7 +87,7 @@ define <4 x double> @mload_v4f64(i8* %f)<br class="">
<br class="">
; CHECK-LABEL: @mload_v4f64(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x double>*<br class="">
-; CHECK-NEXT: %1 = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> undef)<br class="">
+; CHECK-NEXT: %1 = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> undef)<br class="">
; CHECK-NEXT: ret <4 x double> %1<br class="">
}<br class="">
<br class="">
@@ -99,7 +99,7 @@ define <4 x i32> @mload_v4i32(i8* %f) {<br class="">
<br class="">
; CHECK-LABEL: @mload_v4i32(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x i32>*<br class="">
-; CHECK-NEXT: %1 = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32> undef)<br class="">
+; CHECK-NEXT: %1 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32> undef)<br class="">
; CHECK-NEXT: ret <4 x i32> %1<br class="">
}<br class="">
<br class="">
@@ -109,7 +109,7 @@ define <2 x i64> @mload_v2i64(i8* %f) {<br class="">
<br class="">
; CHECK-LABEL: @mload_v2i64(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <2 x i64>*<br class="">
-; CHECK-NEXT: %1 = call <2 x i64> @llvm.masked.load.v2i64(<2 x i64>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>, <2 x i64> undef)<br class="">
+; CHECK-NEXT: %1 = call <2 x i64> @llvm.masked.load.v2i64.p0v2i64(<2 x i64>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>, <2 x i64> undef)<br class="">
; CHECK-NEXT: ret <2 x i64> %1<br class="">
}<br class="">
<br class="">
@@ -119,7 +119,7 @@ define <8 x i32> @mload_v8i32(i8* %f) {<br class="">
<br class="">
; CHECK-LABEL: @mload_v8i32(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <8 x i32>*<br class="">
-; CHECK-NEXT: %1 = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i32> undef)<br class="">
+; CHECK-NEXT: %1 = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i32> undef)<br class="">
; CHECK-NEXT: ret <8 x i32> %1<br class="">
}<br class="">
<br class="">
@@ -129,7 +129,7 @@ define <4 x i64> @mload_v4i64(i8* %f) {<br class="">
<br class="">
; CHECK-LABEL: @mload_v4i64(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x i64>*<br class="">
-; CHECK-NEXT: %1 = call <4 x i64> @llvm.masked.load.v4i64(<4 x i64>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> undef)<br class="">
+; CHECK-NEXT: %1 = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> undef)<br class="">
; CHECK-NEXT: ret <4 x i64> %1<br class="">
}<br class="">
<br class="">
@@ -187,7 +187,7 @@ define void @mstore_one_one(i8* %f, <4 x<br class="">
<br class="">
; CHECK-LABEL: @mstore_one_one(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x float>*<br class="">
-; CHECK-NEXT: call void @llvm.masked.store.v4f32(<4 x float> %v, <4 x float>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>)<br class="">
+; CHECK-NEXT: call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %v, <4 x float>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>)<br class="">
; CHECK-NEXT: ret void<br class="">
}<br class="">
<br class="">
@@ -199,7 +199,7 @@ define void @mstore_one_one_double(i8* %<br class="">
<br class="">
; CHECK-LABEL: @mstore_one_one_double(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <2 x double>*<br class="">
-; CHECK-NEXT: call void @llvm.masked.store.v2f64(<2 x double> %v, <2 x double>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>)<br class="">
+; CHECK-NEXT: call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %v, <2 x double>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>)<br class="">
; CHECK-NEXT: ret void<br class="">
}<br class="">
<br class="">
@@ -211,7 +211,7 @@ define void @mstore_v8f32(i8* %f, <8 x f<br class="">
<br class="">
; CHECK-LABEL: @mstore_v8f32(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <8 x float>*<br class="">
-; CHECK-NEXT: call void @llvm.masked.store.v8f32(<8 x float> %v, <8 x float>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>)<br class="">
+; CHECK-NEXT: call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> %v, <8 x float>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>)<br class="">
; CHECK-NEXT: ret void<br class="">
}<br class="">
<br class="">
@@ -221,7 +221,7 @@ define void @mstore_v4f64(i8* %f, <4 x d<br class="">
<br class="">
; CHECK-LABEL: @mstore_v4f64(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x double>*<br class="">
-; CHECK-NEXT: call void @llvm.masked.store.v4f64(<4 x double> %v, <4 x double>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>)<br class="">
+; CHECK-NEXT: call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> %v, <4 x double>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>)<br class="">
; CHECK-NEXT: ret void<br class="">
}<br class="">
<br class="">
@@ -233,7 +233,7 @@ define void @mstore_v4i32(i8* %f, <4 x i<br class="">
<br class="">
; CHECK-LABEL: @mstore_v4i32(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x i32>*<br class="">
-; CHECK-NEXT: call void @llvm.masked.store.v4i32(<4 x i32> %v, <4 x i32>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 true, i1 true>)<br class="">
+; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %v, <4 x i32>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 true, i1 true>)<br class="">
; CHECK-NEXT: ret void<br class="">
}<br class="">
<br class="">
@@ -243,7 +243,7 @@ define void @mstore_v2i64(i8* %f, <2 x i<br class="">
<br class="">
; CHECK-LABEL: @mstore_v2i64(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <2 x i64>*<br class="">
-; CHECK-NEXT: call void @llvm.masked.store.v2i64(<2 x i64> %v, <2 x i64>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>)<br class="">
+; CHECK-NEXT: call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %v, <2 x i64>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>)<br class="">
; CHECK-NEXT: ret void<br class="">
}<br class="">
<br class="">
@@ -253,7 +253,7 @@ define void @mstore_v8i32(i8* %f, <8 x i<br class="">
<br class="">
; CHECK-LABEL: @mstore_v8i32(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <8 x i32>*<br class="">
-; CHECK-NEXT: call void @llvm.masked.store.v8i32(<8 x i32> %v, <8 x i32>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>)<br class="">
+; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %v, <8 x i32>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>)<br class="">
; CHECK-NEXT: ret void<br class="">
}<br class="">
<br class="">
@@ -263,7 +263,7 @@ define void @mstore_v4i64(i8* %f, <4 x i<br class="">
<br class="">
; CHECK-LABEL: @mstore_v4i64(<br class="">
; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x i64>*<br class="">
-; CHECK-NEXT: call void @llvm.masked.store.v4i64(<4 x i64> %v, <4 x i64>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>)<br class="">
+; CHECK-NEXT: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>)<br class="">
; CHECK-NEXT: ret void<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/test/Transforms/LoopVectorize/X86/masked_load_store.ll<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/masked_load_store.ll?rev=263158&r1=263157&r2=263158&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/masked_load_store.ll?rev=263158&r1=263157&r2=263158&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/Transforms/LoopVectorize/X86/masked_load_store.ll (original)<br class="">
+++ llvm/trunk/test/Transforms/LoopVectorize/X86/masked_load_store.ll Thu Mar 10 14:39:22 2016<br class="">
@@ -18,16 +18,16 @@ target triple = "x86_64-pc_linux"<br class="">
<br class="">
;AVX-LABEL: @foo1<br class="">
;AVX: icmp slt <8 x i32> %wide.load, <i32 100, i32 100, i32 100<br class="">
-;AVX: call <8 x i32> @llvm.masked.load.v8i32<br class="">
+;AVX: call <8 x i32> @llvm.masked.load.v8i32.p0v8i32<br class="">
;AVX: add nsw <8 x i32><br class="">
-;AVX: call void @llvm.masked.store.v8i32<br class="">
+;AVX: call void @llvm.masked.store.v8i32.p0v8i32<br class="">
;AVX: ret void<br class="">
<br class="">
;AVX512-LABEL: @foo1<br class="">
;AVX512: icmp slt <16 x i32> %wide.load, <i32 100, i32 100, i32 100<br class="">
-;AVX512: call <16 x i32> @llvm.masked.load.v16i32<br class="">
+;AVX512: call <16 x i32> @llvm.masked.load.v16i32.p0v16i32<br class="">
;AVX512: add nsw <16 x i32><br class="">
-;AVX512: call void @llvm.masked.store.v16i32<br class="">
+;AVX512: call void @llvm.masked.store.v16i32.p0v16i32<br class="">
;AVX512: ret void<br class="">
<br class="">
; Function Attrs: nounwind uwtable<br class="">
@@ -89,6 +89,81 @@ for.end:<br class="">
ret void<br class="">
}<br class="">
<br class="">
+; The same as @foo1 but all the pointers are address space 1 pointers.<br class="">
+<br class="">
+;AVX-LABEL: @foo1_addrspace1<br class="">
+;AVX: icmp slt <8 x i32> %wide.load, <i32 100, i32 100, i32 100<br class="">
+;AVX: call <8 x i32> @llvm.masked.load.v8i32.p1v8i32<br class="">
+;AVX: add nsw <8 x i32><br class="">
+;AVX: call void @llvm.masked.store.v8i32.p1v8i32<br class="">
+;AVX: ret void<br class="">
+<br class="">
+;AVX512-LABEL: @foo1_addrspace1<br class="">
+;AVX512: icmp slt <16 x i32> %wide.load, <i32 100, i32 100, i32 100<br class="">
+;AVX512: call <16 x i32> @llvm.masked.load.v16i32.p1v16i32<br class="">
+;AVX512: add nsw <16 x i32><br class="">
+;AVX512: call void @llvm.masked.store.v16i32.p1v16i32<br class="">
+;AVX512: ret void<br class="">
+<br class="">
+; Function Attrs: nounwind uwtable<br class="">
+define void @foo1_addrspace1(i32 addrspace(1)* %A, i32 addrspace(1)* %B, i32 addrspace(1)* %trigger) {<br class="">
+entry:<br class="">
+ %A.addr = alloca i32 addrspace(1)*, align 8<br class="">
+ %B.addr = alloca i32 addrspace(1)*, align 8<br class="">
+ %trigger.addr = alloca i32 addrspace(1)*, align 8<br class="">
+ %i = alloca i32, align 4<br class="">
+ store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 8<br class="">
+ store i32 addrspace(1)* %B, i32 addrspace(1)** %B.addr, align 8<br class="">
+ store i32 addrspace(1)* %trigger, i32 addrspace(1)** %trigger.addr, align 8<br class="">
+ store i32 0, i32* %i, align 4<br class="">
+ br label %for.cond<br class="">
+<br class="">
+for.cond: ; preds = %for.inc, %entry<br class="">
+ %0 = load i32, i32* %i, align 4<br class="">
+ %cmp = icmp slt i32 %0, 10000<br class="">
+ br i1 %cmp, label %for.body, label %for.end<br class="">
+<br class="">
+for.body: ; preds = %for.cond<br class="">
+ %1 = load i32, i32* %i, align 4<br class="">
+ %idxprom = sext i32 %1 to i64<br class="">
+ %2 = load i32 addrspace(1)*, i32 addrspace(1)** %trigger.addr, align 8<br class="">
+ %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %2, i64 %idxprom<br class="">
+ %3 = load i32, i32 addrspace(1)* %arrayidx, align 4<br class="">
+ %cmp1 = icmp slt i32 %3, 100<br class="">
+ br i1 %cmp1, label %if.then, label %if.end<br class="">
+<br class="">
+if.then: ; preds = %for.body<br class="">
+ %4 = load i32, i32* %i, align 4<br class="">
+ %idxprom2 = sext i32 %4 to i64<br class="">
+ %5 = load i32 addrspace(1)*, i32 addrspace(1)** %B.addr, align 8<br class="">
+ %arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %5, i64 %idxprom2<br class="">
+ %6 = load i32, i32 addrspace(1)* %arrayidx3, align 4<br class="">
+ %7 = load i32, i32* %i, align 4<br class="">
+ %idxprom4 = sext i32 %7 to i64<br class="">
+ %8 = load i32 addrspace(1)*, i32 addrspace(1)** %trigger.addr, align 8<br class="">
+ %arrayidx5 = getelementptr inbounds i32, i32 addrspace(1)* %8, i64 %idxprom4<br class="">
+ %9 = load i32, i32 addrspace(1)* %arrayidx5, align 4<br class="">
+ %add = add nsw i32 %6, %9<br class="">
+ %10 = load i32, i32* %i, align 4<br class="">
+ %idxprom6 = sext i32 %10 to i64<br class="">
+ %11 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 8<br class="">
+ %arrayidx7 = getelementptr inbounds i32, i32 addrspace(1)* %11, i64 %idxprom6<br class="">
+ store i32 %add, i32 addrspace(1)* %arrayidx7, align 4<br class="">
+ br label %if.end<br class="">
+<br class="">
+if.end: ; preds = %if.then, %for.body<br class="">
+ br label %for.inc<br class="">
+<br class="">
+for.inc: ; preds = %if.end<br class="">
+ %12 = load i32, i32* %i, align 4<br class="">
+ %inc = add nsw i32 %12, 1<br class="">
+ store i32 %inc, i32* %i, align 4<br class="">
+ br label %for.cond<br class="">
+<br class="">
+for.end: ; preds = %for.cond<br class="">
+ ret void<br class="">
+}<br class="">
+<br class="">
; The source code:<br class="">
;<br class="">
;void foo2(float *A, float *B, int *trigger) {<br class="">
@@ -102,16 +177,16 @@ for.end:<br class="">
<br class="">
;AVX-LABEL: @foo2<br class="">
;AVX: icmp slt <8 x i32> %wide.load, <i32 100, i32 100, i32 100<br class="">
-;AVX: call <8 x float> @llvm.masked.load.v8f32<br class="">
+;AVX: call <8 x float> @llvm.masked.load.v8f32.p0v8f32<br class="">
;AVX: fadd <8 x float><br class="">
-;AVX: call void @llvm.masked.store.v8f32<br class="">
+;AVX: call void @llvm.masked.store.v8f32.p0v8f32<br class="">
;AVX: ret void<br class="">
<br class="">
;AVX512-LABEL: @foo2<br class="">
;AVX512: icmp slt <16 x i32> %wide.load, <i32 100, i32 100, i32 100<br class="">
-;AVX512: call <16 x float> @llvm.masked.load.v16f32<br class="">
+;AVX512: call <16 x float> @llvm.masked.load.v16f32.p0v16f32<br class="">
;AVX512: fadd <16 x float><br class="">
-;AVX512: call void @llvm.masked.store.v16f32<br class="">
+;AVX512: call void @llvm.masked.store.v16f32.p0v16f32<br class="">
;AVX512: ret void<br class="">
<br class="">
; Function Attrs: nounwind uwtable<br class="">
@@ -187,18 +262,18 @@ for.end:<br class="">
<br class="">
;AVX-LABEL: @foo3<br class="">
;AVX: icmp slt <4 x i32> %wide.load, <i32 100, i32 100,<br class="">
-;AVX: call <4 x double> @llvm.masked.load.v4f64<br class="">
+;AVX: call <4 x double> @llvm.masked.load.v4f64.p0v4f64<br class="">
;AVX: sitofp <4 x i32> %wide.load to <4 x double><br class="">
;AVX: fadd <4 x double><br class="">
-;AVX: call void @llvm.masked.store.v4f64<br class="">
+;AVX: call void @llvm.masked.store.v4f64.p0v4f64<br class="">
;AVX: ret void<br class="">
<br class="">
;AVX512-LABEL: @foo3<br class="">
;AVX512: icmp slt <8 x i32> %wide.load, <i32 100, i32 100,<br class="">
-;AVX512: call <8 x double> @llvm.masked.load.v8f64<br class="">
+;AVX512: call <8 x double> @llvm.masked.load.v8f64.p0v8f64<br class="">
;AVX512: sitofp <8 x i32> %wide.load to <8 x double><br class="">
;AVX512: fadd <8 x double><br class="">
-;AVX512: call void @llvm.masked.store.v8f64<br class="">
+;AVX512: call void @llvm.masked.store.v8f64.p0v8f64<br class="">
;AVX512: ret void<br class="">
<br class="">
<br class="">
@@ -429,17 +504,17 @@ for.end:<br class="">
;AVX2-LABEL: @foo6<br class="">
;AVX2: icmp sgt <4 x i32> %reverse, zeroinitializer<br class="">
;AVX2: shufflevector <4 x i1>{{.*}}<4 x i32> <i32 3, i32 2, i32 1, i32 0><br class="">
-;AVX2: call <4 x double> @llvm.masked.load.v4f64<br class="">
+;AVX2: call <4 x double> @llvm.masked.load.v4f64.p0v4f64<br class="">
;AVX2: fadd <4 x double><br class="">
-;AVX2: call void @llvm.masked.store.v4f64<br class="">
+;AVX2: call void @llvm.masked.store.v4f64.p0v4f64<br class="">
;AVX2: ret void<br class="">
<br class="">
;AVX512-LABEL: @foo6<br class="">
;AVX512: icmp sgt <8 x i32> %reverse, zeroinitializer<br class="">
;AVX512: shufflevector <8 x i1>{{.*}}<8 x i32> <i32 7, i32 6, i32 5, i32 4<br class="">
-;AVX512: call <8 x double> @llvm.masked.load.v8f64<br class="">
+;AVX512: call <8 x double> @llvm.masked.load.v8f64.p0v8f64<br class="">
;AVX512: fadd <8 x double><br class="">
-;AVX512: call void @llvm.masked.store.v8f64<br class="">
+;AVX512: call void @llvm.masked.store.v8f64.p0v8f64<br class="">
;AVX512: ret void<br class="">
<br class="">
<br class="">
@@ -507,8 +582,8 @@ for.end:<br class="">
; }<br class="">
<br class="">
;AVX512-LABEL: @foo7<br class="">
-;AVX512: call <8 x double*> @llvm.masked.load.v8p0f64(<8 x double*>*<br class="">
-;AVX512: call void @llvm.masked.store.v8f64<br class="">
+;AVX512: call <8 x double*> @llvm.masked.load.v8p0f64.p0v8p0f64(<8 x double*>*<br class="">
+;AVX512: call void @llvm.masked.store.v8f64.p0v8f64<br class="">
;AVX512: ret void<br class="">
<br class="">
define void @foo7(double* noalias %out, double** noalias %in, i8* noalias %trigger, i32 %size) #0 {<br class="">
@@ -579,8 +654,8 @@ for.end:<br class="">
;}<br class="">
<br class="">
;AVX512-LABEL: @foo8<br class="">
-;AVX512: call <8 x i32 ()*> @llvm.masked.load.v8p0f_i32f(<8 x i32 ()*>* %<br class="">
-;AVX512: call void @llvm.masked.store.v8f64<br class="">
+;AVX512: call <8 x i32 ()*> @llvm.masked.load.v8p0f_i32f.p0v8p0f_i32f(<8 x i32 ()*>* %<br class="">
+;AVX512: call void @llvm.masked.store.v8f64.p0v8f64<br class="">
;AVX512: ret void<br class="">
<br class="">
define void @foo8(double* noalias %out, i32 ()** noalias %in, i8* noalias %trigger, i32 %size) #0 {<br class="">
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