<div dir="ltr">That's correct. Just reverted the other one now. Builds seem to be passing now.<div><br></div><div>Nikolay</div></div><div class="gmail_extra"><br><div class="gmail_quote">2016-03-02 14:20 GMT+03:00 Renato Golin via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Nikolay,<br>
<br>
Have you reverted the wrong patch?<br>
<br>
I'm still seeing build errors with AMDKernelCodeTUtils.cpp, and this<br>
patch seems to be the one after that one. Maybe both need to be<br>
reverted?<br>
<br>
cheers,<br>
--renato<br>
<br>
On 2 March 2016 at 10:54, Nikolay Haustov via llvm-commits<br>
<div class="HOEnZb"><div class="h5"><<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br>
> Author: nhaustov<br>
> Date: Wed Mar 2 04:54:21 2016<br>
> New Revision: 262475<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=262475&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=262475&view=rev</a><br>
> Log:<br>
> Revert "[AMDGPU] Using table-driven amd_kernel_code_t field parser in assembler."<br>
><br>
> Build failure with clang.<br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp<br>
> llvm/trunk/lib/Target/AMDGPU/AsmParser/CMakeLists.txt<br>
><br>
> Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=262475&r1=262474&r2=262475&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=262475&r1=262474&r2=262475&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)<br>
> +++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Wed Mar 2 04:54:21 2016<br>
> @@ -12,7 +12,6 @@<br>
> #include "MCTargetDesc/AMDGPUTargetStreamer.h"<br>
> #include "SIDefines.h"<br>
> #include "Utils/AMDGPUBaseInfo.h"<br>
> -#include "Utils/AMDKernelCodeTUtils.h"<br>
> #include "llvm/ADT/APFloat.h"<br>
> #include "llvm/ADT/STLExtras.h"<br>
> #include "llvm/ADT/SmallString.h"<br>
> @@ -812,12 +811,164 @@ bool AMDGPUAsmParser::ParseDirectiveHSAC<br>
><br>
> bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,<br>
> amd_kernel_code_t &Header) {<br>
> - SmallString<40> ErrStr;<br>
> - raw_svector_ostream Err(ErrStr);<br>
> - if (!parseAmdKernelCodeField(ID, getLexer(), Header, Err)) {<br>
> - return TokError(Err.str());<br>
> - }<br>
> +<br>
> + if (getLexer().isNot(AsmToken::Equal))<br>
> + return TokError("expected '='");<br>
> + Lex();<br>
> +<br>
> + if (getLexer().isNot(AsmToken::Integer))<br>
> + return TokError("amd_kernel_code_t values must be integers");<br>
> +<br>
> + uint64_t Value = getLexer().getTok().getIntVal();<br>
> Lex();<br>
> +<br>
> + if (ID == "kernel_code_version_major")<br>
> + Header.amd_kernel_code_version_major = Value;<br>
> + else if (ID == "kernel_code_version_minor")<br>
> + Header.amd_kernel_code_version_minor = Value;<br>
> + else if (ID == "machine_kind")<br>
> + Header.amd_machine_kind = Value;<br>
> + else if (ID == "machine_version_major")<br>
> + Header.amd_machine_version_major = Value;<br>
> + else if (ID == "machine_version_minor")<br>
> + Header.amd_machine_version_minor = Value;<br>
> + else if (ID == "machine_version_stepping")<br>
> + Header.amd_machine_version_stepping = Value;<br>
> + else if (ID == "kernel_code_entry_byte_offset")<br>
> + Header.kernel_code_entry_byte_offset = Value;<br>
> + else if (ID == "kernel_code_prefetch_byte_size")<br>
> + Header.kernel_code_prefetch_byte_size = Value;<br>
> + else if (ID == "max_scratch_backing_memory_byte_size")<br>
> + Header.max_scratch_backing_memory_byte_size = Value;<br>
> + else if (ID == "compute_pgm_rsrc1_vgprs")<br>
> + Header.compute_pgm_resource_registers |= S_00B848_VGPRS(Value);<br>
> + else if (ID == "compute_pgm_rsrc1_sgprs")<br>
> + Header.compute_pgm_resource_registers |= S_00B848_SGPRS(Value);<br>
> + else if (ID == "compute_pgm_rsrc1_priority")<br>
> + Header.compute_pgm_resource_registers |= S_00B848_PRIORITY(Value);<br>
> + else if (ID == "compute_pgm_rsrc1_float_mode")<br>
> + Header.compute_pgm_resource_registers |= S_00B848_FLOAT_MODE(Value);<br>
> + else if (ID == "compute_pgm_rsrc1_priv")<br>
> + Header.compute_pgm_resource_registers |= S_00B848_PRIV(Value);<br>
> + else if (ID == "compute_pgm_rsrc1_dx10_clamp")<br>
> + Header.compute_pgm_resource_registers |= S_00B848_DX10_CLAMP(Value);<br>
> + else if (ID == "compute_pgm_rsrc1_debug_mode")<br>
> + Header.compute_pgm_resource_registers |= S_00B848_DEBUG_MODE(Value);<br>
> + else if (ID == "compute_pgm_rsrc1_ieee_mode")<br>
> + Header.compute_pgm_resource_registers |= S_00B848_IEEE_MODE(Value);<br>
> + else if (ID == "compute_pgm_rsrc2_scratch_en")<br>
> + Header.compute_pgm_resource_registers |= (S_00B84C_SCRATCH_EN(Value) << 32);<br>
> + else if (ID == "compute_pgm_rsrc2_user_sgpr")<br>
> + Header.compute_pgm_resource_registers |= (S_00B84C_USER_SGPR(Value) << 32);<br>
> + else if (ID == "compute_pgm_rsrc2_tgid_x_en")<br>
> + Header.compute_pgm_resource_registers |= (S_00B84C_TGID_X_EN(Value) << 32);<br>
> + else if (ID == "compute_pgm_rsrc2_tgid_y_en")<br>
> + Header.compute_pgm_resource_registers |= (S_00B84C_TGID_Y_EN(Value) << 32);<br>
> + else if (ID == "compute_pgm_rsrc2_tgid_z_en")<br>
> + Header.compute_pgm_resource_registers |= (S_00B84C_TGID_Z_EN(Value) << 32);<br>
> + else if (ID == "compute_pgm_rsrc2_tg_size_en")<br>
> + Header.compute_pgm_resource_registers |= (S_00B84C_TG_SIZE_EN(Value) << 32);<br>
> + else if (ID == "compute_pgm_rsrc2_tidig_comp_cnt")<br>
> + Header.compute_pgm_resource_registers |=<br>
> + (S_00B84C_TIDIG_COMP_CNT(Value) << 32);<br>
> + else if (ID == "compute_pgm_rsrc2_excp_en_msb")<br>
> + Header.compute_pgm_resource_registers |=<br>
> + (S_00B84C_EXCP_EN_MSB(Value) << 32);<br>
> + else if (ID == "compute_pgm_rsrc2_lds_size")<br>
> + Header.compute_pgm_resource_registers |= (S_00B84C_LDS_SIZE(Value) << 32);<br>
> + else if (ID == "compute_pgm_rsrc2_excp_en")<br>
> + Header.compute_pgm_resource_registers |= (S_00B84C_EXCP_EN(Value) << 32);<br>
> + else if (ID == "compute_pgm_resource_registers")<br>
> + Header.compute_pgm_resource_registers = Value;<br>
> + else if (ID == "enable_sgpr_private_segment_buffer")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT);<br>
> + else if (ID == "enable_sgpr_dispatch_ptr")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_SHIFT);<br>
> + else if (ID == "enable_sgpr_queue_ptr")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_SHIFT);<br>
> + else if (ID == "enable_sgpr_kernarg_segment_ptr")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT);<br>
> + else if (ID == "enable_sgpr_dispatch_id")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_SHIFT);<br>
> + else if (ID == "enable_sgpr_flat_scratch_init")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT);<br>
> + else if (ID == "enable_sgpr_private_segment_size")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT);<br>
> + else if (ID == "enable_sgpr_grid_workgroup_count_x")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_SHIFT);<br>
> + else if (ID == "enable_sgpr_grid_workgroup_count_y")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_SHIFT);<br>
> + else if (ID == "enable_sgpr_grid_workgroup_count_z")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_SHIFT);<br>
> + else if (ID == "enable_ordered_append_gds")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_ENABLE_ORDERED_APPEND_GDS_SHIFT);<br>
> + else if (ID == "private_element_size")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE_SHIFT);<br>
> + else if (ID == "is_ptr64")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_IS_PTR64_SHIFT);<br>
> + else if (ID == "is_dynamic_callstack")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK_SHIFT);<br>
> + else if (ID == "is_debug_enabled")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED_SHIFT);<br>
> + else if (ID == "is_xnack_enabled")<br>
> + Header.code_properties |=<br>
> + (Value << AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED_SHIFT);<br>
> + else if (ID == "workitem_private_segment_byte_size")<br>
> + Header.workitem_private_segment_byte_size = Value;<br>
> + else if (ID == "workgroup_group_segment_byte_size")<br>
> + Header.workgroup_group_segment_byte_size = Value;<br>
> + else if (ID == "gds_segment_byte_size")<br>
> + Header.gds_segment_byte_size = Value;<br>
> + else if (ID == "kernarg_segment_byte_size")<br>
> + Header.kernarg_segment_byte_size = Value;<br>
> + else if (ID == "workgroup_fbarrier_count")<br>
> + Header.workgroup_fbarrier_count = Value;<br>
> + else if (ID == "wavefront_sgpr_count")<br>
> + Header.wavefront_sgpr_count = Value;<br>
> + else if (ID == "workitem_vgpr_count")<br>
> + Header.workitem_vgpr_count = Value;<br>
> + else if (ID == "reserved_vgpr_first")<br>
> + Header.reserved_vgpr_first = Value;<br>
> + else if (ID == "reserved_vgpr_count")<br>
> + Header.reserved_vgpr_count = Value;<br>
> + else if (ID == "reserved_sgpr_first")<br>
> + Header.reserved_sgpr_first = Value;<br>
> + else if (ID == "reserved_sgpr_count")<br>
> + Header.reserved_sgpr_count = Value;<br>
> + else if (ID == "debug_wavefront_private_segment_offset_sgpr")<br>
> + Header.debug_wavefront_private_segment_offset_sgpr = Value;<br>
> + else if (ID == "debug_private_segment_buffer_sgpr")<br>
> + Header.debug_private_segment_buffer_sgpr = Value;<br>
> + else if (ID == "kernarg_segment_alignment")<br>
> + Header.kernarg_segment_alignment = Value;<br>
> + else if (ID == "group_segment_alignment")<br>
> + Header.group_segment_alignment = Value;<br>
> + else if (ID == "private_segment_alignment")<br>
> + Header.private_segment_alignment = Value;<br>
> + else if (ID == "wavefront_size")<br>
> + Header.wavefront_size = Value;<br>
> + else if (ID == "call_convention")<br>
> + Header.call_convention = Value;<br>
> + else if (ID == "runtime_loader_kernel_symbol")<br>
> + Header.runtime_loader_kernel_symbol = Value;<br>
> + else<br>
> + return TokError("amd_kernel_code_t value not recognized.");<br>
> +<br>
> return false;<br>
> }<br>
><br>
><br>
> Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/CMakeLists.txt<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/CMakeLists.txt?rev=262475&r1=262474&r2=262475&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/CMakeLists.txt?rev=262475&r1=262474&r2=262475&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AMDGPU/AsmParser/CMakeLists.txt (original)<br>
> +++ llvm/trunk/lib/Target/AMDGPU/AsmParser/CMakeLists.txt Wed Mar 2 04:54:21 2016<br>
> @@ -1,5 +1,3 @@<br>
> add_llvm_library(LLVMAMDGPUAsmParser<br>
> AMDGPUAsmParser.cpp<br>
> )<br>
> -<br>
> -add_dependencies(LLVMAMDGPUAsmParser AMDGPUUtils)<br>
><br>
><br>
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</div></div></blockquote></div><br></div>