<div dir="ltr"><div>$ cat out.ll</div><div><div>target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"</div><div>target triple = "i686-pc-windows-msvc18.0.0"</div><div><br></div><div>@winMutex_lock = external global i32, align 4</div><div><br></div><div>; Function Attrs: nounwind</div><div>define i1 @winMutexEnd(i1 %B) #0 {</div><div>entry:</div><div> %0 = cmpxchg volatile i32* @winMutex_lock, i32 1, i32 0 seq_cst seq_cst</div><div> %cmp = extractvalue { i32, i1 } %0, 1</div><div> %or.cond = and i1 %cmp, %B</div><div> ret i1 %or.cond</div><div>}</div></div><div>$ ~/llvm/Release+Asserts/bin/llc out.ll<br></div><div><div>llc: ~/llvm/src/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:3495: llvm::SDValue llvm::SelectionDAG::getNode(unsigned int, llvm::SDLoc, llvm::EVT, llvm::SDValue, llvm::SDValue, const llvm::SDNodeFlags *): Assertion `N1.getValueType() == N2.getValueType() && N1.getValueType() == VT && "Binary operator types must match!"' failed.</div></div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Mar 1, 2016 at 12:33 PM, Vasileios Kalintiris via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Evgenii,<br>
<br>
I reverted this in r262387. If you could provide me with a test-case it would be quite useful.<br>
<br>
Thanks,<br>
Vasileios<br>
________________________________________<br>
From: Evgenii Stepanov [<a href="mailto:eugeni.stepanov@gmail.com">eugeni.stepanov@gmail.com</a>]<br>
Sent: 01 March 2016 20:02<br>
To: Vasileios Kalintiris; Nico Weber<br>
Cc: LLVM Commits<br>
Subject: Re: [llvm] r262316 - [mips] Promote the result of SETCC nodes to GPR width.<br>
<br>
Hi,<br>
<br>
you broke x86_64 with this commit. I'm reducing the testcase now.<br>
<br>
See:<br>
<a href="https://build.chromium.org/p/chromium.fyi/builders/ClangToTLinux/builds/4488/steps/compile/logs/stdio" rel="noreferrer" target="_blank">https://build.chromium.org/p/chromium.fyi/builders/ClangToTLinux/builds/4488/steps/compile/logs/stdio</a><br>
<br>
On Tue, Mar 1, 2016 at 2:08 AM, Vasileios Kalintiris via llvm-commits<br>
<<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br>
> Author: vkalintiris<br>
> Date: Tue Mar 1 04:08:01 2016<br>
> New Revision: 262316<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=262316&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=262316&view=rev</a><br>
> Log:<br>
> [mips] Promote the result of SETCC nodes to GPR width.<br>
><br>
> Summary:<br>
> This patch modifies the existing comparison, branch, conditional-move<br>
> and select patterns, and adds new ones where needed. Also, the updated<br>
> SLT{u,i,iu} set of instructions generate a GPR width result.<br>
><br>
> The majority of the code changes in the Mips back-end fix the wrong<br>
> assumption that the result of SETCC nodes always produce an i32 value.<br>
> The changes in the common code path account for the fact that in 64-bit<br>
> MIPS targets, i1 is promoted to i32 instead of i64.<br>
><br>
> Reviewers: dsanders<br>
><br>
> Subscribers: dsanders, llvm-commits<br>
><br>
> Differential Revision: <a href="http://reviews.llvm.org/D10970" rel="noreferrer" target="_blank">http://reviews.llvm.org/D10970</a><br>
><br>
> Modified:<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
> llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp<br>
> llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td<br>
> llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td<br>
> llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td<br>
> llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td<br>
> llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td<br>
> llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td<br>
> llvm/trunk/lib/Target/Mips/MipsCondMov.td<br>
> llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
> llvm/trunk/lib/Target/Mips/MipsISelLowering.h<br>
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.td<br>
> llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td<br>
> llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp<br>
> llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp<br>
> llvm/trunk/test/CodeGen/Mips/atomic.ll<br>
> llvm/trunk/test/CodeGen/Mips/blez_bgez.ll<br>
> llvm/trunk/test/CodeGen/Mips/cmov.ll<br>
> llvm/trunk/test/CodeGen/Mips/countleading.ll<br>
> llvm/trunk/test/CodeGen/Mips/fcmp.ll<br>
> llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll<br>
> llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll<br>
> llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll<br>
> llvm/trunk/test/CodeGen/Mips/octeon.ll<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Mar 1 04:08:01 2016<br>
> @@ -14151,8 +14151,7 @@ SDValue DAGCombiner::SimplifySelectCC(SD<br>
> Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),<br>
> N2.getValueType());<br>
> else<br>
> - Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),<br>
> - N2.getValueType(), SCC);<br>
> + Temp = DAG.getZExtOrTrunc(SCC, SDLoc(N2), N2.getValueType());<br>
> } else {<br>
> SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);<br>
> Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Mar 1 04:08:01 2016<br>
> @@ -520,7 +520,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_<br>
> /// Promote the overflow flag of an overflowing arithmetic node.<br>
> SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {<br>
> // Simply change the return type of the boolean result.<br>
> - EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));<br>
> + EVT NVT = getSetCCResultType(N->getValueType(1));<br>
> EVT ValueVTs[] = { N->getValueType(0), NVT };<br>
> SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };<br>
> SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Tue Mar 1 04:08:01 2016<br>
> @@ -750,8 +750,9 @@ void DAGTypeLegalizer::ReplaceValueWith(<br>
> }<br>
><br>
> void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {<br>
> - assert(Result.getValueType() ==<br>
> - TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&<br>
> + assert(((Result.getValueType() ==<br>
> + TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType())) ||<br>
> + (Result.getValueType() == getSetCCResultType(Op.getValueType()))) &&<br>
> "Invalid type for promoted integer");<br>
> AnalyzeNewValue(Result);<br>
><br>
><br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Mar 1 04:08:01 2016<br>
> @@ -3656,6 +3656,9 @@ void SelectionDAGBuilder::visitMaskedGat<br>
> }<br>
><br>
> void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {<br>
> + const TargetLowering &TLI = DAG.getTargetLoweringInfo();<br>
> + LLVMContext &Ctx = *DAG.getContext();<br>
> +<br>
> SDLoc dl = getCurSDLoc();<br>
> AtomicOrdering SuccessOrder = I.getSuccessOrdering();<br>
> AtomicOrdering FailureOrder = I.getFailureOrdering();<br>
> @@ -3664,7 +3667,14 @@ void SelectionDAGBuilder::visitAtomicCmp<br>
> SDValue InChain = getRoot();<br>
><br>
> MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();<br>
> - SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);<br>
> + EVT CCVT = TLI.getSetCCResultType(DAG.getDataLayout(), Ctx, MVT::i1);<br>
> +<br>
> + // Only use the result of getSetCCResultType if it is legal,<br>
> + // otherwise just use the promoted result type (NVT).<br>
> + if (!TLI.isTypeLegal(CCVT))<br>
> + CCVT = TLI.getTypeToTransformTo(Ctx, MVT::i1);<br>
> +<br>
> + SDVTList VTs = DAG.getVTList(MemVT, CCVT, MVT::Other);<br>
> SDValue L = DAG.getAtomicCmpSwap(<br>
> ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,<br>
> getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)<br>
> +++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Tue Mar 1 04:08:01 2016<br>
> @@ -124,9 +124,13 @@ static DecodeStatus DecodeFCCRegisterCla<br>
> uint64_t Address,<br>
> const void *Decoder);<br>
><br>
> -static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,<br>
> - uint64_t Address,<br>
> - const void *Decoder);<br>
> +static DecodeStatus DecodeFGRCC32RegisterClass(MCInst &Inst, unsigned RegNo,<br>
> + uint64_t Address,<br>
> + const void *Decoder);<br>
> +<br>
> +static DecodeStatus DecodeFGRCC64RegisterClass(MCInst &Inst, unsigned RegNo,<br>
> + uint64_t Address,<br>
> + const void *Decoder);<br>
><br>
> static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,<br>
> unsigned Insn,<br>
> @@ -898,6 +902,17 @@ DecodeStatus MipsDisassembler::getInstru<br>
> if (Result == MCDisassembler::Fail)<br>
> return MCDisassembler::Fail;<br>
><br>
> + if (hasMips32r6() && isGP64()) {<br>
> + DEBUG(dbgs() << "Trying MicroMipsR6_GP64 table (32-bit instructions):\n");<br>
> + // Calling the auto-generated decoder function.<br>
> + Result = decodeInstruction(DecoderTableMicroMipsR6_GP6432, Instr, Insn,<br>
> + Address, this, STI);<br>
> + if (Result != MCDisassembler::Fail) {<br>
> + Size = 4;<br>
> + return Result;<br>
> + }<br>
> + }<br>
> +<br>
> if (hasMips32r6()) {<br>
> DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");<br>
> // Calling the auto-generated decoder function.<br>
> @@ -940,9 +955,9 @@ DecodeStatus MipsDisassembler::getInstru<br>
> }<br>
><br>
> if (hasMips32r6() && isGP64()) {<br>
> - DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");<br>
> - Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,<br>
> - Address, this, STI);<br>
> + DEBUG(dbgs() << "Trying Mips64r6 (GPR64) table (32-bit opcodes):\n");<br>
> + Result = decodeInstruction(DecoderTableMips64r632, Instr, Insn, Address,<br>
> + this, STI);<br>
> if (Result != MCDisassembler::Fail) {<br>
> Size = 4;<br>
> return Result;<br>
> @@ -1121,13 +1136,24 @@ static DecodeStatus DecodeFCCRegisterCla<br>
> return MCDisassembler::Success;<br>
> }<br>
><br>
> -static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,<br>
> - uint64_t Address,<br>
> - const void *Decoder) {<br>
> +static DecodeStatus DecodeFGRCC32RegisterClass(MCInst &Inst, unsigned RegNo,<br>
> + uint64_t Address,<br>
> + const void *Decoder) {<br>
> + if (RegNo > 31)<br>
> + return MCDisassembler::Fail;<br>
> +<br>
> + unsigned Reg = getReg(Decoder, Mips::FGRCC32RegClassID, RegNo);<br>
> + Inst.addOperand(MCOperand::createReg(Reg));<br>
> + return MCDisassembler::Success;<br>
> +}<br>
> +<br>
> +static DecodeStatus DecodeFGRCC64RegisterClass(MCInst &Inst, unsigned RegNo,<br>
> + uint64_t Address,<br>
> + const void *Decoder) {<br>
> if (RegNo > 31)<br>
> return MCDisassembler::Fail;<br>
><br>
> - unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);<br>
> + unsigned Reg = getReg(Decoder, Mips::FGRCC64RegClassID, RegNo);<br>
> Inst.addOperand(MCOperand::createReg(Reg));<br>
> return MCDisassembler::Success;<br>
> }<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Tue Mar 1 04:08:01 2016<br>
> @@ -634,71 +634,71 @@ class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_<br>
> II_CVT>, FGR_64;<br>
><br>
> multiclass CMP_CC_MMR6<bits<6> format, string Typestr,<br>
> - RegisterOperand FGROpnd> {<br>
> + RegisterOperand FGRCCOpnd, RegisterOperand FGROpnd> {<br>
> def CMP_AF_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("<a href="http://cmp.af" rel="noreferrer" target="_blank">cmp.af</a>.", Typestr), format, FIELD_CMP_COND_AF>,<br>
> - CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"af", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_UN_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,<br>
> - CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"un", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_EQ_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,<br>
> - CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"eq", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_UEQ_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,<br>
> - CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"ueq", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_LT_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("<a href="http://cmp.lt" rel="noreferrer" target="_blank">cmp.lt</a>.", Typestr), format, FIELD_CMP_COND_LT>,<br>
> - CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"lt", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_ULT_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,<br>
> - CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"ult", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_LE_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,<br>
> - CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"le", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_ULE_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,<br>
> - CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"ule", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_SAF_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,<br>
> - CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"saf", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_SUN_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,<br>
> - CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"sun", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_SEQ_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,<br>
> - CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"seq", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_SUEQ_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,<br>
> - CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"sueq", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_SLT_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,<br>
> - CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"slt", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_SULT_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,<br>
> - CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"sult", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_SLE_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,<br>
> - CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"sle", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> def CMP_SULE_#NAME : POOL32F_CMP_FM<<br>
> !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,<br>
> - CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,<br>
> - ISA_MICROMIPS32R6;<br>
> + CMP_CONDN_DESC_BASE<"sule", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;<br>
> }<br>
><br>
> class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,<br>
> @@ -763,8 +763,8 @@ class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6<br>
> class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,<br>
> FGR64Opnd, II_ROUND>;<br>
><br>
> -class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;<br>
> -class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {<br>
> +class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGRCC32Opnd, FGR32Opnd>;<br>
> +class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGRCC32Opnd, FGR64Opnd> {<br>
> // We must insert a SUBREG_TO_REG around $fd_in<br>
> bit usesCustomInserter = 1;<br>
> }<br>
> @@ -1115,8 +1115,8 @@ def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_M<br>
> ISA_MICROMIPS32R6;<br>
> def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,<br>
> ISA_MICROMIPS32R6;<br>
> -defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;<br>
> -defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;<br>
> +defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGRCC32Opnd, FGR32Opnd>;<br>
> +defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGRCC32Opnd, FGR64Opnd>;<br>
> def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;<br>
> def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;<br>
> def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,<br>
> @@ -1200,8 +1200,10 @@ def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W<br>
> ISA_MICROMIPS32R6;<br>
> def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,<br>
> ISA_MICROMIPS32R6;<br>
> -def SEL_S_MMR6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;<br>
> -def SEL_D_MMR6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;<br>
> +def SEL_S_MMR6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6,<br>
> + HARDFLOAT;<br>
> +def SEL_D_MMR6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6,<br>
> + HARDFLOAT;<br>
> def SELEQZ_S_MMR6 : StdMMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,<br>
> ISA_MICROMIPS32R6;<br>
> def SELEQZ_D_MMR6 : StdMMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td Tue Mar 1 04:08:01 2016<br>
> @@ -99,6 +99,12 @@ class DINSM_MM64R6_DESC : InsBase<"dinsm<br>
> class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,<br>
> MipsIns>;<br>
><br>
> +class SEL_S_MM64R6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGRCC64Opnd, FGR32Opnd> {<br>
> + // We must copy FGRCC64Opnd's subreg into FGR32.<br>
> + bit usesCustomInserter = 1;<br>
> +}<br>
> +class SEL_D_MM64R6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGRCC64Opnd, FGR64Opnd>;<br>
> +<br>
> //===----------------------------------------------------------------------===//<br>
> //<br>
> // Instruction Definitions<br>
> @@ -132,3 +138,10 @@ let DecoderNamespace = "MicroMipsR6" in<br>
> def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC,<br>
> ISA_MICROMIPS64R6;<br>
> }<br>
> +<br>
> +let DecoderNamespace = "MicroMipsR6_GP64" in {<br>
> +def SEL_S_MM64R6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MM64R6_DESC,<br>
> + ISA_MICROMIPS64R6, HARDFLOAT;<br>
> +def SEL_D_MM64R6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MM64R6_DESC,<br>
> + ISA_MICROMIPS64R6, HARDFLOAT;<br>
> +}<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Tue Mar 1 04:08:01 2016<br>
> @@ -671,10 +671,10 @@ let DecoderNamespace = "MicroMips", Pred<br>
> ADDI_FM_MM<0xc>;<br>
> def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,<br>
> ADDI_FM_MM<0x4>;<br>
> - def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,<br>
> - SLTI_FM_MM<0x24>;<br>
> - def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,<br>
> - SLTI_FM_MM<0x2c>;<br>
> + def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd,<br>
> + GPR32Opnd>, SLTI_FM_MM<0x24>;<br>
> + def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd,<br>
> + GPR32Opnd>, SLTI_FM_MM<0x2c>;<br>
> def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,<br>
> ADDI_FM_MM<0x34>;<br>
> def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,<br>
> @@ -694,8 +694,9 @@ let DecoderNamespace = "MicroMips", Pred<br>
> def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;<br>
> def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;<br>
> def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;<br>
> - def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;<br>
> - def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,<br>
> + def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd, GPR32Opnd>,<br>
> + ADD_FM_MM<0, 0x350>;<br>
> + def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd, GPR32Opnd>,<br>
> ADD_FM_MM<0, 0x390>;<br>
> def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,<br>
> ADD_FM_MM<0, 0x250>;<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Tue Mar 1 04:08:01 2016<br>
> @@ -176,7 +176,7 @@ class SDBBP_R6_ENC : SPECIAL_SDBBP_FM;<br>
> //===----------------------------------------------------------------------===//<br>
><br>
> class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,<br>
> - RegisterOperand FGROpnd,<br>
> + RegisterOperand FGRCCOpnd, RegisterOperand FGROpnd,<br>
> SDPatternOperator Op = null_frag> {<br>
> dag OutOperandList = (outs FGRCCOpnd:$fd);<br>
> dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);<br>
> @@ -184,58 +184,58 @@ class CMP_CONDN_DESC_BASE<string CondStr<br>
> list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];<br>
> }<br>
><br>
> -multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,<br>
> - RegisterOperand FGROpnd>{<br>
> - let AdditionalPredicates = [NotInMicroMips] in {<br>
> - def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,<br>
> - CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,<br>
> - CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,<br>
> - CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,<br>
> - CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,<br>
> - CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,<br>
> - CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,<br>
> - CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,<br>
> - CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_SAF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SAF>,<br>
> - CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_SUN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUN>,<br>
> - CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,<br>
> - CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_SUEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUEQ>,<br>
> - CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_SLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLT>,<br>
> - CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_SULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULT>,<br>
> - CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_SLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLE>,<br>
> - CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - def CMP_SULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULE>,<br>
> - CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>,<br>
> - ISA_MIPS32R6, HARDFLOAT;<br>
> - }<br>
> +multiclass CMP_CC_M<FIELD_CMP_FORMAT Format, string Typestr,<br>
> + RegisterOperand FGRCCOpnd, RegisterOperand FGROpnd>{<br>
> +let AdditionalPredicates = [NotInMicroMips] in {<br>
> +def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,<br>
> + CMP_CONDN_DESC_BASE<"af", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,<br>
> + CMP_CONDN_DESC_BASE<"un", Typestr, FGRCCOpnd, FGROpnd,<br>
> + setuo>, ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,<br>
> + CMP_CONDN_DESC_BASE<"eq", Typestr, FGRCCOpnd, FGROpnd,<br>
> + setoeq>, ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,<br>
> + CMP_CONDN_DESC_BASE<"ueq", Typestr, FGRCCOpnd, FGROpnd,<br>
> + setueq>, ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,<br>
> + CMP_CONDN_DESC_BASE<"lt", Typestr, FGRCCOpnd, FGROpnd,<br>
> + setolt>, ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,<br>
> + CMP_CONDN_DESC_BASE<"ult", Typestr, FGRCCOpnd, FGROpnd,<br>
> + setult>, ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,<br>
> + CMP_CONDN_DESC_BASE<"le", Typestr, FGRCCOpnd, FGROpnd,<br>
> + setole>, ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,<br>
> + CMP_CONDN_DESC_BASE<"ule", Typestr, FGRCCOpnd, FGROpnd,<br>
> + setule>, ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_SAF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SAF>,<br>
> + CMP_CONDN_DESC_BASE<"saf", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_SUN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUN>,<br>
> + CMP_CONDN_DESC_BASE<"sun", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,<br>
> + CMP_CONDN_DESC_BASE<"seq", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_SUEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUEQ>,<br>
> + CMP_CONDN_DESC_BASE<"sueq", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_SLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLT>,<br>
> + CMP_CONDN_DESC_BASE<"slt", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_SULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULT>,<br>
> + CMP_CONDN_DESC_BASE<"sult", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_SLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLE>,<br>
> + CMP_CONDN_DESC_BASE<"sle", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + ISA_MIPS32R6, HARDFLOAT;<br>
> +def CMP_SULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULE>,<br>
> + CMP_CONDN_DESC_BASE<"sule", Typestr, FGRCCOpnd, FGROpnd>,<br>
> + ISA_MIPS32R6, HARDFLOAT;<br>
> +}<br>
> }<br>
><br>
> //===----------------------------------------------------------------------===//<br>
> @@ -472,7 +472,8 @@ class MUHU_DESC : MUL_R6_DESC_BASE<"mu<br>
> class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;<br>
> class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;<br>
><br>
> -class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {<br>
> +class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGRCCOpnd,<br>
> + RegisterOperand FGROpnd> {<br>
> dag OutOperandList = (outs FGROpnd:$fd);<br>
> dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);<br>
> string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");<br>
> @@ -482,11 +483,12 @@ class COP1_SEL_DESC_BASE<string instr_as<br>
> string Constraints = "$fd_in = $fd";<br>
> }<br>
><br>
> -class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {<br>
> +class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGRCC32Opnd, FGR64Opnd> {<br>
> // We must insert a SUBREG_TO_REG around $fd_in<br>
> bit usesCustomInserter = 1;<br>
> }<br>
> -class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;<br>
> +<br>
> +class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGRCC32Opnd, FGR32Opnd>;<br>
><br>
> class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd><br>
> : MipsR6Arch<instr_asm> {<br>
> @@ -693,8 +695,8 @@ let AdditionalPredicates = [NotInMicroMi<br>
> }<br>
> def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;<br>
> def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;<br>
> -defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;<br>
> -defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;<br>
> +defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGRCC32Opnd, FGR32Opnd>;<br>
> +defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGRCC32Opnd, FGR64Opnd>;<br>
> def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;<br>
> def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;<br>
> def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Mar 1 04:08:01 2016<br>
> @@ -98,10 +98,14 @@ def DADDiu : ArithLogicI<"daddiu", simm<br>
> ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;<br>
><br>
> let isCodeGenOnly = 1 in {<br>
> -def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,<br>
> - SLTI_FM<0xa>;<br>
> -def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,<br>
> - SLTI_FM<0xb>;<br>
> +def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd,<br>
> + GPR64Opnd>, SLTI_FM<0xa>;<br>
> +def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd,<br>
> + GPR64Opnd>, SLTI_FM<0xb>;<br>
> +def SLTi64_32 : SetCC_I<"slti", setlt, simm16, immSExt16, GPR64Opnd,<br>
> + GPR32Opnd>, SLTI_FM<0xa>;<br>
> +def SLTiu64_32 : SetCC_I<"sltiu", setult, simm16, immSExt16, GPR64Opnd,<br>
> + GPR32Opnd>, SLTI_FM<0xb>;<br>
> def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,<br>
> ADDI_FM<0xc>;<br>
> def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,<br>
> @@ -122,8 +126,10 @@ def DSUB : ArithLogicR<"dsub", GPR64Op<br>
> ISA_MIPS3;<br>
><br>
> let isCodeGenOnly = 1 in {<br>
> -def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;<br>
> -def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;<br>
> +def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd, GPR64Opnd>, ADD_FM<0, 0x2a>;<br>
> +def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd, GPR64Opnd>, ADD_FM<0, 0x2b>;<br>
> +def SLT64_32 : SetCC_R<"slt", setlt, GPR64Opnd, GPR32Opnd>, ADD_FM<0, 0x2a>;<br>
> +def SLTu64_32 : SetCC_R<"sltu", setult, GPR64Opnd, GPR32Opnd>, ADD_FM<0, 0x2b>;<br>
> def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;<br>
> def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;<br>
> def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;<br>
> @@ -325,8 +331,7 @@ class ExtsCins<string opstr, SDPatternOp<br>
> class SetCC64_R<string opstr, PatFrag cond_op> :<br>
> InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),<br>
> !strconcat(opstr, "\t$rd, $rs, $rt"),<br>
> - [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,<br>
> - GPR64Opnd:$rt)))],<br>
> + [(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],<br>
> II_SEQ_SNE, FrmR, opstr> {<br>
> let TwoOperandAliasConstraint = "$rd = $rs";<br>
> }<br>
> @@ -334,8 +339,7 @@ class SetCC64_R<string opstr, PatFrag co<br>
> class SetCC64_I<string opstr, PatFrag cond_op>:<br>
> InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),<br>
> !strconcat(opstr, "\t$rt, $rs, $imm10"),<br>
> - [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,<br>
> - immSExt10_64:$imm10)))],<br>
> + [(set GPR64Opnd:$rt, (cond_op GPR64Opnd:$rs, immSExt10_64:$imm10))],<br>
> II_SEQI_SNEI, FrmI, opstr> {<br>
> let TwoOperandAliasConstraint = "$rt = $rs";<br>
> }<br>
> @@ -344,7 +348,7 @@ class CBranchBitNum<string opstr, DAGOpe<br>
> RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> :<br>
> InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),<br>
> !strconcat(opstr, "\t$rs, $p, $offset"),<br>
> - [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),<br>
> + [(brcond (i64 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),<br>
> bb:$offset)], II_BBIT, FrmI, opstr> {<br>
> let isBranch = 1;<br>
> let isTerminator = 1;<br>
> @@ -480,20 +484,30 @@ def : WrapperPat<tblockaddress, DADDiu,<br>
> def : WrapperPat<tjumptable, DADDiu, GPR64>;<br>
> def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;<br>
><br>
> -defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,<br>
> - ZERO_64>;<br>
> +defm : BrcondPats1<GPR64, BEQ64, BNE64, ZERO_64, i64>;<br>
> +defm : BrcondPats1<GPR32, BEQ, BNE, ZERO, i64>;<br>
><br>
> -def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),<br>
> +def : MipsPat<(brcond (i64 (setlt i64:$lhs, 1)), bb:$dst),<br>
> (BLEZ64 i64:$lhs, bb:$dst)>;<br>
> -def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),<br>
> +def : MipsPat<(brcond (i64 (setgt i64:$lhs, -1)), bb:$dst),<br>
> (BGEZ64 i64:$lhs, bb:$dst)>;<br>
> +def : MipsPat<(brcond (i64 (setlt i32:$lhs, 1)), bb:$dst),<br>
> + (BLEZ64 (SUBREG_TO_REG (i32 0), i32:$lhs, sub_32), bb:$dst)>;<br>
> +def : MipsPat<(brcond (i64 (setgt i32:$lhs, -1)), bb:$dst),<br>
> + (BGEZ64 (SUBREG_TO_REG (i32 0), i32:$lhs, sub_32), bb:$dst)>;<br>
><br>
> // setcc patterns<br>
> defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;<br>
> -defm : SetlePats<GPR64, SLT64, SLTu64>;<br>
> +defm : SetlePats<GPR64, SLT64, SLTu64, XORi64>;<br>
> defm : SetgtPats<GPR64, SLT64, SLTu64>;<br>
> -defm : SetgePats<GPR64, SLT64, SLTu64>;<br>
> -defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;<br>
> +defm : SetgePats<GPR64, SLT64, SLTu64, XORi64>;<br>
> +defm : SetgeImmPats<GPR64, SLTi64, SLTiu64, XORi64>;<br>
> +<br>
> +defm : SeteqPats<GPR32, SLTiu64_32, XOR, SLTu64_32, ZERO>;<br>
> +defm : SetlePats<GPR32, SLT64_32, SLTu64_32, XORi64>;<br>
> +defm : SetgtPats<GPR32, SLT64_32, SLTu64_32>;<br>
> +defm : SetgePats<GPR32, SLT64_32, SLTu64_32, XORi64>;<br>
> +defm : SetgeImmPats<GPR32, SLTi64_32, SLTiu64_32, XORi64>;<br>
><br>
> // truncate<br>
> def : MipsPat<(trunc (assertsext GPR64:$src)),<br>
> @@ -538,13 +552,13 @@ let AdditionalPredicates = [NotDSP] in {<br>
><br>
> // Octeon bbit0/bbit1 MipsPattern<br>
> let Predicates = [HasMips64, HasCnMips] in {<br>
> -def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),<br>
> +def : MipsPat<(brcond (i64 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),<br>
> (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;<br>
> -def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),<br>
> +def : MipsPat<(brcond (i64 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),<br>
> (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;<br>
> -def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),<br>
> +def : MipsPat<(brcond (i64 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),<br>
> (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;<br>
> -def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),<br>
> +def : MipsPat<(brcond (i64 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),<br>
> (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;<br>
> }<br>
><br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td Tue Mar 1 04:08:01 2016<br>
> @@ -74,6 +74,11 @@ class LLD_R6_DESC : LL_R6_DESC_BASE<"l<br>
> class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd>;<br>
> class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;<br>
> class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;<br>
> +class SEL64_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGRCC64Opnd, FGR32Opnd> {<br>
> + // We must copy FGRCC64Opnd's subreg into FGR32.<br>
> + bit usesCustomInserter = 1;<br>
> +}<br>
> +class SEL64_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGRCC64Opnd, FGR64Opnd>;<br>
><br>
> //===----------------------------------------------------------------------===//<br>
> //<br>
> @@ -100,11 +105,18 @@ def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MI<br>
> def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;<br>
> def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;<br>
> def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;<br>
> -def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;<br>
> -def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;<br>
> -let DecoderNamespace = "Mips32r6_64r6_GP64" in {<br>
> - def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;<br>
> - def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;<br>
> +def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;<br>
> +def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS64R6;<br>
> +let AdditionalPredicates = [NotInMicroMips],<br>
> + DecoderNamespace = "Mips64r6" in {<br>
> + def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS64R6;<br>
> + def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS64R6;<br>
> + def SEL64_S : SEL_S_ENC, SEL64_S_DESC, ISA_MIPS64R6, HARDFLOAT;<br>
> + def SEL64_D : SEL_D_ENC, SEL64_D_DESC, ISA_MIPS64R6, HARDFLOAT;<br>
> + defm S64: CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGRCC64Opnd, FGR32Opnd>,<br>
> + ISA_MIPS64R6;<br>
> + defm D64: CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGRCC64Opnd, FGR64Opnd>,<br>
> + ISA_MIPS64R6;<br>
> }<br>
><br>
> //===----------------------------------------------------------------------===//<br>
> @@ -121,99 +133,71 @@ def : MipsInstAlias<"jr $rs", (JALR64 ZE<br>
> //<br>
> //===----------------------------------------------------------------------===//<br>
><br>
> +// comparisons supported via another comparison<br>
> +defm S64: Cmp_Pats<f32, NOR64, ZERO_64>, ISA_MIPS64R6;<br>
> +defm D64: Cmp_Pats<f64, NOR64, ZERO_64>, ISA_MIPS64R6;<br>
> +<br>
> +// i32 selects<br>
> +defm : SelectInt_Pats<i32, OR, XORi, SLTi, SLTiu, SELEQZ, SELNEZ,<br>
> + immZExt16, i64>, ISA_MIPS64R6;<br>
> +<br>
> +def : MipsPat<(select i64:$cond, i32:$t, i32:$f),<br>
> + (OR (SELNEZ i32:$t, (EXTRACT_SUBREG i64:$cond, sub_32)),<br>
> + (SELEQZ i32:$f, (EXTRACT_SUBREG i64:$cond, sub_32)))>,<br>
> + ISA_MIPS64R6;<br>
> +def : MipsPat<(select i64:$cond, i32:$t, immz),<br>
> + (SELNEZ i32:$t, (EXTRACT_SUBREG i64:$cond, sub_32))>,<br>
> + ISA_MIPS64R6;<br>
> +def : MipsPat<(select i64:$cond, immz, i32:$f),<br>
> + (SELEQZ i32:$f, (EXTRACT_SUBREG i64:$cond, sub_32))>,<br>
> + ISA_MIPS64R6;<br>
> +<br>
> // i64 selects<br>
> +defm : SelectInt_Pats<i64, OR64, XORi64, SLTi64, SLTiu64, SELEQZ64, SELNEZ64,<br>
> + immZExt16_64, i64>, ISA_MIPS64R6;<br>
> +<br>
> def : MipsPat<(select i64:$cond, i64:$t, i64:$f),<br>
> (OR64 (SELNEZ64 i64:$t, i64:$cond),<br>
> (SELEQZ64 i64:$f, i64:$cond))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),<br>
> - (OR64 (SELEQZ64 i64:$t, i64:$cond),<br>
> - (SELNEZ64 i64:$f, i64:$cond))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),<br>
> - (OR64 (SELNEZ64 i64:$t, i64:$cond),<br>
> - (SELEQZ64 i64:$f, i64:$cond))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),<br>
> - (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),<br>
> - (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),<br>
> - (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),<br>
> - (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<<br>
> - (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),<br>
> - (OR64 (SELEQZ64 i64:$t,<br>
> - (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),<br>
> - sub_32)),<br>
> - (SELNEZ64 i64:$f,<br>
> - (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),<br>
> - sub_32)))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<<br>
> - (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),<br>
> - (OR64 (SELEQZ64 i64:$t,<br>
> - (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),<br>
> - sub_32)),<br>
> - (SELNEZ64 i64:$f,<br>
> - (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),<br>
> - sub_32)))>,<br>
> - ISA_MIPS64R6;<br>
> -<br>
> -def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),<br>
> - (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),<br>
> - (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),<br>
> - (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),<br>
> - (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;<br>
> + ISA_MIPS64R6;<br>
><br>
> // i64 selects from an i32 comparison<br>
> -// One complicating factor here is that bits 32-63 of an i32 are undefined.<br>
> -// FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.<br>
> -// This would allow us to remove the sign-extensions here.<br>
> def : MipsPat<(select i32:$cond, i64:$t, i64:$f),<br>
> - (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),<br>
> - (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),<br>
> - (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),<br>
> - (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),<br>
> - (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),<br>
> - (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),<br>
> - (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,<br>
> - immZExt16:$imm))),<br>
> - (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,<br>
> - immZExt16:$imm))))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),<br>
> - (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,<br>
> - immZExt16:$imm))),<br>
> - (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,<br>
> - immZExt16:$imm))))>,<br>
> - ISA_MIPS64R6;<br>
> + (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),<br>
> + (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,<br>
> + ISA_MIPS64R6;<br>
> +def : MipsPat<(select (i64 (seteq i32:$cond, immz)), i64:$t, i64:$f),<br>
> + (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),<br>
> + (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,<br>
> + ISA_MIPS64R6;<br>
> +def : MipsPat<(select (i64 (setne i32:$cond, immz)), i64:$t, i64:$f),<br>
> + (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),<br>
> + (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,<br>
> + ISA_MIPS64R6;<br>
> +def : MipsPat<(select (i64 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),<br>
> + (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond, immZExt16:$imm))),<br>
> + (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond, immZExt16:$imm))))>,<br>
> + ISA_MIPS64R6;<br>
> +def : MipsPat<(select (i64 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),<br>
> + (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond, immZExt16:$imm))),<br>
> + (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond, immZExt16:$imm))))>,<br>
> + ISA_MIPS64R6;<br>
><br>
> def : MipsPat<(select i32:$cond, i64:$t, immz),<br>
> (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),<br>
> + ISA_MIPS64R6;<br>
> +def : MipsPat<(select (i64 (setne i32:$cond, immz)), i64:$t, immz),<br>
> (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),<br>
> + ISA_MIPS64R6;<br>
> +def : MipsPat<(select (i64 (seteq i32:$cond, immz)), i64:$t, immz),<br>
> (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,<br>
> - ISA_MIPS64R6;<br>
> + ISA_MIPS64R6;<br>
> def : MipsPat<(select i32:$cond, immz, i64:$f),<br>
> (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),<br>
> + ISA_MIPS64R6;<br>
> +def : MipsPat<(select (i64 (setne i32:$cond, immz)), immz, i64:$f),<br>
> (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,<br>
> - ISA_MIPS64R6;<br>
> -def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),<br>
> + ISA_MIPS64R6;<br>
> +def : MipsPat<(select (i64 (seteq i32:$cond, immz)), immz, i64:$f),<br>
> (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,<br>
> - ISA_MIPS64R6;<br>
> + ISA_MIPS64R6;<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MipsCondMov.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCondMov.td?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCondMov.td?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MipsCondMov.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MipsCondMov.td Tue Mar 1 04:08:01 2016<br>
> @@ -52,57 +52,6 @@ class CMov_F_F_FT<string opstr, Register<br>
> let Constraints = "$F = $fd";<br>
> }<br>
><br>
> -// select patterns<br>
> -multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,<br>
> - Instruction MOVZInst, Instruction SLTOp,<br>
> - Instruction SLTuOp, Instruction SLTiOp,<br>
> - Instruction SLTiuOp> {<br>
> - def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),<br>
> - (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;<br>
> - def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),<br>
> - (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;<br>
> - def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),<br>
> - (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;<br>
> - def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),<br>
> - (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;<br>
> - def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),<br>
> - (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;<br>
> - def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),<br>
> - (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;<br>
> - def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),<br>
> - DRC:$T, DRC:$F),<br>
> - (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;<br>
> - def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)),<br>
> - DRC:$T, DRC:$F),<br>
> - (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)),<br>
> - DRC:$F)>;<br>
> -}<br>
> -<br>
> -multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,<br>
> - Instruction MOVZInst, Instruction XOROp> {<br>
> - def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),<br>
> - (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;<br>
> - def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),<br>
> - (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;<br>
> -}<br>
> -<br>
> -multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,<br>
> - Instruction MOVZInst, Instruction XORiOp> {<br>
> - def : MipsPat<<br>
> - (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),<br>
> - (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;<br>
> -}<br>
> -<br>
> -multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,<br>
> - Instruction XOROp> {<br>
> - def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),<br>
> - (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;<br>
> - def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),<br>
> - (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;<br>
> - def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),<br>
> - (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;<br>
> -}<br>
> -<br>
> // Instantiation of instructions.<br>
> def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>,<br>
> ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;<br>
> @@ -199,96 +148,189 @@ let DecoderNamespace = "Mips64" in {<br>
> CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;<br>
> }<br>
><br>
> -// Instantiation of conditional move patterns.<br>
> -defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,<br>
> +// select patterns<br>
> +multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,<br>
> + Instruction MOVZInst, Instruction SLTOp,<br>
> + Instruction SLTuOp, Instruction SLTiOp,<br>
> + Instruction SLTiuOp, ValueType VT> {<br>
> +// reg, reg<br>
> +def : MipsPat<(select (VT (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),<br>
> + (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;<br>
> +def : MipsPat<(select (VT (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),<br>
> + (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;<br>
> +def : MipsPat<(select (VT (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),<br>
> + (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;<br>
> +def : MipsPat<(select (VT (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),<br>
> + (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;<br>
> +<br>
> +// reg, imm<br>
> +def : MipsPat<(select (VT (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),<br>
> + (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;<br>
> +def : MipsPat<(select (VT (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),<br>
> + (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;<br>
> +def : MipsPat<<br>
> + (select (VT (setgt CRC:$lhs, immSExt16Plus1:$rhs)), DRC:$T, DRC:$F),<br>
> + (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;<br>
> +def : MipsPat<<br>
> + (select (VT (setugt CRC:$lhs, immSExt16Plus1:$rhs)), DRC:$T, DRC:$F),<br>
> + (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;<br>
> +}<br>
> +<br>
> +// We have to wrap the instantiation of the MovzPats0 patterns in another<br>
> +// multiclass that specifies the result type of the SETCC nodes. The patterns<br>
> +// with VT=i64 (or i32) will be ignored when GPR-width=i32 (or i64).<br>
> +multiclass MovzPats0_SuperClass<ValueType VT> {<br>
> +defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu, VT>,<br>
> INSN_MIPS4_32_NOT_32R6_64R6;<br>
> -defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;<br>
> -defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6;<br>
> +defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu, VT>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> +defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu, VT>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6;<br>
> +defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu, VT>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;<br>
> +defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu, VT>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;<br>
> +<br>
> +defm : MovzPats0<GPR32, GPR32, MOVZ_I64_I, SLT64_32, SLTu64_32, SLTi64_32,<br>
> + SLTiu64_32, VT>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> +defm : MovzPats0<GPR32, GPR64, MOVZ_I64_I64, SLT64_32, SLTu64_32, SLTi64_32,<br>
> + SLTiu64_32, VT>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> +defm : MovzPats0<GPR32, FGR32, MOVZ_I64_S, SLT64_32, SLTu64_32, SLTi64_32,<br>
> + SLTiu64_32, VT>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> +defm : MovzPats0<GPR32, FGR64, MOVZ_I64_D64, SLT64_32, SLTu64_32, SLTi64_32,<br>
> + SLTiu64_32, VT>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;<br>
><br>
> -defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,<br>
> +defm : MovzPats0<GPR64, GPR32, MOVZ_I64_I, SLT64, SLTu64, SLTi64, SLTiu64, VT>,<br>
> INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> -defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,<br>
> +defm : MovzPats0<GPR64, GPR64, MOVZ_I64_I64, SLT64, SLTu64, SLTi64, SLTiu64, VT>,<br>
> INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> -defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,<br>
> +defm : MovzPats0<GPR64, FGR32, MOVZ_I64_S, SLT64, SLTu64, SLTi64, SLTiu64, VT>,<br>
> INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> -defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,<br>
> +defm : MovzPats0<GPR64, FGR64, MOVZ_I64_D64, SLT64, SLTu64, SLTi64, SLTiu64, VT>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;<br>
> +}<br>
> +<br>
> +defm : MovzPats0_SuperClass<i32>;<br>
> +defm : MovzPats0_SuperClass<i64>;<br>
> +<br>
> +multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,<br>
> + Instruction MOVZInst, Instruction XOROp, ValueType VT> {<br>
> +def : MipsPat<(select (VT (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),<br>
> + (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;<br>
> +def : MipsPat<(select (VT (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),<br>
> + (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;<br>
> +}<br>
> +<br>
> +multiclass MovzPats1_SuperClass<ValueType VT> {<br>
> +defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR, VT>, INSN_MIPS4_32_NOT_32R6_64R6;<br>
> +defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR, VT>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> +defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR, VT>, INSN_MIPS4_32_NOT_32R6_64R6;<br>
> +defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR, VT>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;<br>
> +defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR, VT>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;<br>
> +<br>
> +defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64, VT>,<br>
> INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> -defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,<br>
> +defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64, VT>,<br>
> INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> -defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,<br>
> +defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64, VT>,<br>
> INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> -defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,<br>
> +defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64, VT>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;<br>
> +}<br>
> +<br>
> +defm : MovzPats1_SuperClass<i32>;<br>
> +defm : MovzPats1_SuperClass<i64>;<br>
> +<br>
> +multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,<br>
> + Instruction MOVZInst, Instruction XORiOp, ValueType VT> {<br>
> +def : MipsPat<<br>
> + (select (VT (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),<br>
> + (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;<br>
> +}<br>
> +<br>
> +multiclass MovzPats2_SuperClass<ValueType VT> {<br>
> +defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi, VT>, INSN_MIPS4_32_NOT_32R6_64R6;<br>
> +defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi, VT>,<br>
> INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> -defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,<br>
> +defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64, VT>,<br>
> INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> -defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,<br>
> +defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64, VT>,<br>
> INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> +}<br>
><br>
> -defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;<br>
> +defm : MovzPats2_SuperClass<i32>;<br>
> +defm : MovzPats2_SuperClass<i64>;<br>
><br>
> -defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> - GPR_64;<br>
> -defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> - GPR_64;<br>
> -defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> - GPR_64;<br>
> +multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,<br>
> + Instruction XOROp, ValueType VT = i32> {<br>
> + def : MipsPat<(select (VT (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),<br>
> + (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;<br>
> + def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),<br>
> + (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;<br>
> + def : MipsPat<(select (VT (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),<br>
> + (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;<br>
> +}<br>
><br>
> -defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,<br>
> - INSN_MIPS4_32_NOT_32R6_64R6;<br>
> -defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;<br>
> +defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;<br>
> defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;<br>
> +defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> + FGR_32;<br>
> +defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> + FGR_64;<br>
><br>
> -defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>,<br>
> - INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> -defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> +defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR, i64>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> GPR_64;<br>
> -defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> +defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR, i64>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> +defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR, i64>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> GPR_64;<br>
> -<br>
> -defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,<br>
> +defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR, i64>,<br>
> INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;<br>
> -defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> - FGR_32;<br>
> -defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> - FGR_32;<br>
> +defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR, i64>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;<br>
><br>
> -defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,<br>
> - INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;<br>
> -defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, SLTiu64>,<br>
> - INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;<br>
> -defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> - FGR_64;<br>
> -defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>,<br>
> - INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;<br>
> -defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> - FGR_64;<br>
> -defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,<br>
> - FGR_64;<br>
> +defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64, i64>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> +defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64, i64>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> +defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64, i64>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;<br>
> +defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64, i64>,<br>
> + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;<br>
><br>
> // For targets that don't have conditional-move instructions<br>
> // we have to match SELECT nodes with pseudo instructions.<br>
> let usesCustomInserter = 1 in {<br>
> - class Select_Pseudo<RegisterOperand RC> :<br>
> - PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),<br>
> - [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,<br>
> + class Select_Pseudo<RegisterOperand RC, RegisterOperand RO> :<br>
> + PseudoSE<(outs RO:$dst), (ins RC:$cond, RO:$T, RO:$F),<br>
> + [(set RO:$dst, (select RC:$cond, RO:$T, RO:$F))]>,<br>
> ISA_MIPS1_NOT_4_32;<br>
><br>
> - class SelectFP_Pseudo_T<RegisterOperand RC> :<br>
> - PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),<br>
> - [(set RC:$dst, (MipsCMovFP_T RC:$T, GPR32Opnd:$cond, RC:$F))]>,<br>
> + class SelectFP_Pseudo_T<RegisterOperand RO> :<br>
> + PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$cond, RO:$T, RO:$F),<br>
> + [(set RO:$dst, (MipsCMovFP_T RO:$T, GPR32Opnd:$cond, RO:$F))]>,<br>
> ISA_MIPS1_NOT_4_32;<br>
><br>
> - class SelectFP_Pseudo_F<RegisterOperand RC> :<br>
> - PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),<br>
> - [(set RC:$dst, (MipsCMovFP_F RC:$T, GPR32Opnd:$cond, RC:$F))]>,<br>
> + class SelectFP_Pseudo_F<RegisterOperand RO> :<br>
> + PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$cond, RO:$T, RO:$F),<br>
> + [(set RO:$dst, (MipsCMovFP_F RO:$T, GPR32Opnd:$cond, RO:$F))]>,<br>
> ISA_MIPS1_NOT_4_32;<br>
> }<br>
><br>
> -def PseudoSELECT_I : Select_Pseudo<GPR32Opnd>;<br>
> -def PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd>;<br>
> -def PseudoSELECT_S : Select_Pseudo<FGR32Opnd>;<br>
> -def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>, FGR_32;<br>
> -def PseudoSELECT_D64 : Select_Pseudo<FGR64Opnd>, FGR_64;<br>
> +def PseudoSELECT_I : Select_Pseudo<GPR32Opnd, GPR32Opnd>;<br>
> +def PseudoSELECT_I64 : Select_Pseudo<GPR32Opnd, GPR64Opnd>;<br>
> +def PseudoSELECT_S : Select_Pseudo<GPR32Opnd, FGR32Opnd>;<br>
> +def PseudoSELECT_D32 : Select_Pseudo<GPR32Opnd, AFGR64Opnd>, FGR_32;<br>
> +def PseudoSELECT_D64 : Select_Pseudo<GPR32Opnd, FGR64Opnd>, FGR_64;<br>
> +<br>
> +def PseudoSELECT64_I : Select_Pseudo<GPR64Opnd, GPR32Opnd>, GPR_64;<br>
> +def PseudoSELECT64_I64 : Select_Pseudo<GPR64Opnd, GPR64Opnd>, GPR_64;<br>
> +def PseudoSELECT64_S : Select_Pseudo<GPR64Opnd, FGR32Opnd>, GPR_64;<br>
> +def PseudoSELECT64_D32 : Select_Pseudo<GPR64Opnd, AFGR64Opnd>, GPR_64, FGR_32;<br>
> +def PseudoSELECT64_D64 : Select_Pseudo<GPR64Opnd, FGR64Opnd>, GPR_64, FGR_64;<br>
><br>
> def PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>;<br>
> def PseudoSELECTFP_T_I64 : SelectFP_Pseudo_T<GPR64Opnd>;<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Mar 1 04:08:01 2016<br>
> @@ -265,7 +265,8 @@ MipsTargetLowering::MipsTargetLowering(c<br>
> // Without this, every float setcc comes with a AND/OR with the result,<br>
> // we don't want this, since the fpcmp result goes to a flag register,<br>
> // which is used implicitly by brcond and select operations.<br>
> - AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);<br>
> + AddPromotedToType(ISD::SETCC, MVT::i1,<br>
> + ABI.AreGprs64bit() ? MVT::i64 : MVT::i32);<br>
><br>
> // Mips Custom Operations<br>
> setOperationAction(ISD::BR_JT, MVT::Other, Custom);<br>
> @@ -462,9 +463,10 @@ MipsTargetLowering::createFastISel(Funct<br>
><br>
> EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,<br>
> EVT VT) const {<br>
> - if (!VT.isVector())<br>
> - return MVT::i32;<br>
> - return VT.changeVectorElementTypeToInteger();<br>
> + if (VT.isVector())<br>
> + return VT.changeVectorElementTypeToInteger();<br>
> +<br>
> + return ABI.AreGprs64bit() ? MVT::i64 : MVT::i32;<br>
> }<br>
><br>
> static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,<br>
> @@ -627,19 +629,19 @@ static SDValue performSELECTCombine(SDNo<br>
> if (!TrueC || !True.getValueType().isInteger())<br>
> return SDValue();<br>
><br>
> - // We'll also ignore MVT::i64 operands as this optimizations proves<br>
> - // to be ineffective because of the required sign extensions as the result<br>
> - // of a SETCC operator is always MVT::i32 for non-vector types.<br>
> - if (True.getValueType() == MVT::i64)<br>
> - return SDValue();<br>
> -<br>
> int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();<br>
><br>
> // 1) (a < x) ? y : y-1<br>
> // slti $reg1, a, x<br>
> // addiu $reg2, $reg1, y-1<br>
> - if (Diff == 1)<br>
> - return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);<br>
> + if (Diff == 1) {<br>
> + if (SetCC.getValueType().getSizeInBits() ><br>
> + False.getValueType().getSizeInBits())<br>
> + SetCC = DAG.getNode(ISD::TRUNCATE, DL, False.getValueType(), SetCC);<br>
> +<br>
> + SDValue Ret = DAG.getNode(ISD::ADD, DL, False.getValueType(), SetCC, False);<br>
> + return Ret;<br>
> + }<br>
><br>
> // 2) (a < x) ? y-1 : y<br>
> // slti $reg1, a, x<br>
> @@ -649,6 +651,11 @@ static SDValue performSELECTCombine(SDNo<br>
> ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();<br>
> SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),<br>
> SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));<br>
> +<br>
> + if (SetCC.getValueType().getSizeInBits() ><br>
> + True.getValueType().getSizeInBits())<br>
> + SetCC = DAG.getNode(ISD::TRUNCATE, DL, True.getValueType(), SetCC);<br>
> +<br>
> return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);<br>
> }<br>
><br>
> @@ -1027,19 +1034,30 @@ MipsTargetLowering::EmitInstrWithCustomI<br>
> return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true);<br>
> case Mips::SEL_D:<br>
> return emitSEL_D(MI, BB);<br>
> + case Mips::SEL64_S:<br>
> + return emitSEL64_S(MI, BB);<br>
><br>
> case Mips::PseudoSELECT_I:<br>
> case Mips::PseudoSELECT_I64:<br>
> case Mips::PseudoSELECT_S:<br>
> case Mips::PseudoSELECT_D32:<br>
> case Mips::PseudoSELECT_D64:<br>
> - return emitPseudoSELECT(MI, BB, false, Mips::BNE);<br>
> + // 64-bit version<br>
> + case Mips::PseudoSELECT64_I:<br>
> + case Mips::PseudoSELECT64_I64:<br>
> + case Mips::PseudoSELECT64_S:<br>
> + case Mips::PseudoSELECT64_D32:<br>
> + case Mips::PseudoSELECT64_D64:<br>
> + return emitPseudoSELECT(MI, BB, false,<br>
> + Subtarget.isGP32bit() ? Mips::BNE : Mips::BNE64);<br>
> +<br>
> case Mips::PseudoSELECTFP_F_I:<br>
> case Mips::PseudoSELECTFP_F_I64:<br>
> case Mips::PseudoSELECTFP_F_S:<br>
> case Mips::PseudoSELECTFP_F_D32:<br>
> case Mips::PseudoSELECTFP_F_D64:<br>
> return emitPseudoSELECT(MI, BB, true, Mips::BC1F);<br>
> +<br>
> case Mips::PseudoSELECTFP_T_I:<br>
> case Mips::PseudoSELECTFP_T_I64:<br>
> case Mips::PseudoSELECTFP_T_S:<br>
> @@ -1574,6 +1592,30 @@ MachineBasicBlock *MipsTargetLowering::e<br>
> return BB;<br>
> }<br>
><br>
> +MachineBasicBlock *<br>
> +MipsTargetLowering::emitSEL64_S(MachineInstr *MI, MachineBasicBlock *BB) const {<br>
> + MachineFunction *MF = BB->getParent();<br>
> + const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();<br>
> + const TargetInstrInfo *TII = Subtarget.getInstrInfo();<br>
> + MachineRegisterInfo &RegInfo = MF->getRegInfo();<br>
> + DebugLoc DL = MI->getDebugLoc();<br>
> + MachineBasicBlock::iterator II(MI);<br>
> +<br>
> + unsigned Fc64 = MI->getOperand(1).getReg();<br>
> +<br>
> + const auto &FGR32RegClass = TRI->getRegClass(Mips::FGR32RegClassID);<br>
> + unsigned Fc32 = RegInfo.createVirtualRegister(FGR32RegClass);<br>
> +<br>
> + BuildMI(*BB, II, DL, TII->get(Mips::COPY), Fc32)<br>
> + .addReg(Fc64, 0, Mips::sub_lo);<br>
> +<br>
> + // We don't erase the original instruction, we just replace the condition<br>
> + // register with the 32-bit sub-register.<br>
> + MI->getOperand(1).setReg(Fc32);<br>
> +<br>
> + return BB;<br>
> +}<br>
> +<br>
> //===----------------------------------------------------------------------===//<br>
> // Misc Lower Operation implementation<br>
> //===----------------------------------------------------------------------===//<br>
> @@ -1655,8 +1697,10 @@ SDValue MipsTargetLowering::lowerSETCC(S<br>
> "Floating point operand expected.");<br>
><br>
> SDLoc DL(Op);<br>
> - SDValue True = DAG.getConstant(1, DL, MVT::i32);<br>
> - SDValue False = DAG.getConstant(0, DL, MVT::i32);<br>
> + EVT VT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),<br>
> + Op.getValueType());<br>
> + SDValue True = DAG.getConstant(1, DL, VT);<br>
> + SDValue False = DAG.getConstant(0, DL, VT);<br>
><br>
> return createCMovFP(DAG, Cond, True, False, DL);<br>
> }<br>
> @@ -3910,9 +3954,9 @@ MipsTargetLowering::emitPseudoSELECT(Mac<br>
> } else {<br>
> // bne rs, $0, sinkMBB<br>
> BuildMI(BB, DL, TII->get(Opc))<br>
> - .addReg(MI->getOperand(1).getReg())<br>
> - .addReg(Mips::ZERO)<br>
> - .addMBB(sinkMBB);<br>
> + .addReg(MI->getOperand(1).getReg())<br>
> + .addReg(ABI.GetZeroReg())<br>
> + .addMBB(sinkMBB);<br>
> }<br>
><br>
> // copy0MBB:<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Tue Mar 1 04:08:01 2016<br>
> @@ -444,6 +444,8 @@ namespace llvm {<br>
> bool IsSRA) const;<br>
> SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;<br>
> SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;<br>
> + SDValue lowerATOMIC_CMP_SWAP_WITH_SUCCESS(SDValue Op,<br>
> + SelectionDAG &DAG) const;<br>
><br>
> /// isEligibleForTailCallOptimization - Check whether the call is eligible<br>
> /// for tail call optimization.<br>
> @@ -577,6 +579,10 @@ namespace llvm {<br>
> MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,<br>
> MachineBasicBlock *BB, unsigned Size) const;<br>
> MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;<br>
> +<br>
> + MachineBasicBlock *emitSEL64_S(MachineInstr *MI,<br>
> + MachineBasicBlock *BB) const;<br>
> +<br>
> MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,<br>
> MachineBasicBlock *BB, bool isFPCmp,<br>
> unsigned Opc) const;<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Mar 1 04:08:01 2016<br>
> @@ -1035,17 +1035,18 @@ class CBranchZero<string opstr, DAGOpera<br>
> }<br>
><br>
> // SetCC<br>
> -class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :<br>
> - InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),<br>
> +class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RD,<br>
> + RegisterOperand RO> :<br>
> + InstSE<(outs RD:$rd), (ins RO:$rs, RO:$rt),<br>
> !strconcat(opstr, "\t$rd, $rs, $rt"),<br>
> - [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],<br>
> + [(set RD:$rd, (cond_op RO:$rs, RO:$rt))],<br>
> II_SLT_SLTU, FrmR, opstr>;<br>
><br>
> class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,<br>
> - RegisterOperand RO>:<br>
> - InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),<br>
> + RegisterOperand RD, RegisterOperand RO>:<br>
> + InstSE<(outs RD:$rt), (ins RO:$rs, Od:$imm16),<br>
> !strconcat(opstr, "\t$rt, $rs, $imm16"),<br>
> - [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],<br>
> + [(set RD:$rt, (cond_op RO:$rs, imm_type:$imm16))],<br>
> II_SLTI_SLTIU, FrmI, opstr>;<br>
><br>
> // Jump<br>
> @@ -1426,10 +1427,10 @@ def ADDiu : MMRel, StdMMR6Rel, ArithLogi<br>
> }<br>
> def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,<br>
> ISA_MIPS1_NOT_32R6_64R6;<br>
> -def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,<br>
> - SLTI_FM<0xa>;<br>
> -def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,<br>
> - SLTI_FM<0xb>;<br>
> +def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd,<br>
> + GPR32Opnd>, SLTI_FM<0xa>;<br>
> +def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd,<br>
> + GPR32Opnd>, SLTI_FM<0xb>;<br>
> let AdditionalPredicates = [NotInMicroMips] in {<br>
> def ANDi : MMRel, StdMMR6Rel,<br>
> ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,<br>
> @@ -1454,8 +1455,8 @@ def MUL : MMRel, ArithLogicR<"mul", GP<br>
> ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;<br>
> def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;<br>
> def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;<br>
> -def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;<br>
> -def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;<br>
> +def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd, GPR32Opnd>, ADD_FM<0, 0x2a>;<br>
> +def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd, GPR32Opnd>, ADD_FM<0, 0x2b>;<br>
> let AdditionalPredicates = [NotInMicroMips] in {<br>
> def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,<br>
> ADD_FM<0, 0x24>;<br>
> @@ -2241,37 +2242,40 @@ def : MipsPat<(i32 (extloadi16 addr:$src<br>
> def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;<br>
><br>
> // brcond patterns<br>
> -multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,<br>
> - Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,<br>
> - Instruction SLTiuOp, Register ZEROReg> {<br>
> -def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),<br>
> +multiclass BrcondPats1<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,<br>
> + Register ZEROReg, ValueType VT> {<br>
> +def : MipsPat<(brcond (VT (setne RC:$lhs, 0)), bb:$dst),<br>
> (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;<br>
> -def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),<br>
> +def : MipsPat<(brcond (VT (seteq RC:$lhs, 0)), bb:$dst),<br>
> (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;<br>
> -<br>
> -def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),<br>
> - (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;<br>
> -def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),<br>
> - (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;<br>
> -def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),<br>
> - (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;<br>
> -def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),<br>
> - (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;<br>
> -def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),<br>
> - (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;<br>
> -def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),<br>
> - (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;<br>
> -<br>
> -def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),<br>
> - (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;<br>
> -def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),<br>
> - (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;<br>
> -<br>
> def : MipsPat<(brcond RC:$cond, bb:$dst),<br>
> (BNEOp RC:$cond, ZEROReg, bb:$dst)>;<br>
> }<br>
><br>
> -defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;<br>
> +multiclass BrcondPats2<RegisterClass RC, Instruction BEQOp, Register ZEROReg,<br>
> + Instruction SLTOp, Instruction SLTuOp,<br>
> + Instruction SLTiOp, Instruction SLTiuOp,<br>
> + ValueType VT> {<br>
> +def : MipsPat<(brcond (VT (setge RC:$lhs, RC:$rhs)), bb:$dst),<br>
> + (BEQOp (SLTOp RC:$lhs, RC:$rhs), ZEROReg, bb:$dst)>;<br>
> +def : MipsPat<(brcond (VT (setuge RC:$lhs, RC:$rhs)), bb:$dst),<br>
> + (BEQOp (SLTuOp RC:$lhs, RC:$rhs), ZEROReg, bb:$dst)>;<br>
> +def : MipsPat<(brcond (VT (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),<br>
> + (BEQOp (SLTiOp RC:$lhs, immSExt16:$rhs), ZEROReg, bb:$dst)>;<br>
> +def : MipsPat<(brcond (VT (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),<br>
> + (BEQOp (SLTiuOp RC:$lhs, immSExt16:$rhs), ZEROReg, bb:$dst)>;<br>
> +def : MipsPat<(brcond (VT (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),<br>
> + (BEQOp (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZEROReg, bb:$dst)>;<br>
> +def : MipsPat<(brcond (VT (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),<br>
> + (BEQOp (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZEROReg, bb:$dst)>;<br>
> +def : MipsPat<(brcond (VT (setle RC:$lhs, RC:$rhs)), bb:$dst),<br>
> + (BEQOp (SLTOp RC:$rhs, RC:$lhs), ZEROReg, bb:$dst)>;<br>
> +def : MipsPat<(brcond (VT (setule RC:$lhs, RC:$rhs)), bb:$dst),<br>
> + (BEQOp (SLTuOp RC:$rhs, RC:$lhs), ZEROReg, bb:$dst)>;<br>
> +}<br>
> +<br>
> +defm : BrcondPats1<GPR32, BEQ, BNE, ZERO, i32>;<br>
> +defm : BrcondPats2<GPR32, BEQ, ZERO, SLT, SLTu, SLTi, SLTiu, i32>;<br>
><br>
> def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),<br>
> (BLEZ i32:$lhs, bb:$dst)>;<br>
> @@ -2291,11 +2295,12 @@ multiclass SeteqPats<RegisterClass RC, I<br>
> (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;<br>
> }<br>
><br>
> -multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {<br>
> +multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp,<br>
> + Instruction XORiOp> {<br>
> def : MipsPat<(setle RC:$lhs, RC:$rhs),<br>
> - (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;<br>
> + (XORiOp (SLTOp RC:$rhs, RC:$lhs), 1)>;<br>
> def : MipsPat<(setule RC:$lhs, RC:$rhs),<br>
> - (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;<br>
> + (XORiOp (SLTuOp RC:$rhs, RC:$lhs), 1)>;<br>
> }<br>
><br>
> multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {<br>
> @@ -2305,26 +2310,27 @@ multiclass SetgtPats<RegisterClass RC, I<br>
> (SLTuOp RC:$rhs, RC:$lhs)>;<br>
> }<br>
><br>
> -multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {<br>
> +multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp,<br>
> + Instruction XORiOp> {<br>
> def : MipsPat<(setge RC:$lhs, RC:$rhs),<br>
> - (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;<br>
> + (XORiOp (SLTOp RC:$lhs, RC:$rhs), 1)>;<br>
> def : MipsPat<(setuge RC:$lhs, RC:$rhs),<br>
> - (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;<br>
> + (XORiOp (SLTuOp RC:$lhs, RC:$rhs), 1)>;<br>
> }<br>
><br>
> multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,<br>
> - Instruction SLTiuOp> {<br>
> + Instruction SLTiuOp, Instruction XORiOp> {<br>
> def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),<br>
> - (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;<br>
> + (XORiOp (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;<br>
> def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),<br>
> - (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;<br>
> + (XORiOp (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;<br>
> }<br>
><br>
> defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;<br>
> -defm : SetlePats<GPR32, SLT, SLTu>;<br>
> +defm : SetlePats<GPR32, SLT, SLTu, XORi>;<br>
> defm : SetgtPats<GPR32, SLT, SLTu>;<br>
> -defm : SetgePats<GPR32, SLT, SLTu>;<br>
> -defm : SetgeImmPats<GPR32, SLTi, SLTiu>;<br>
> +defm : SetgePats<GPR32, SLT, SLTu, XORi>;<br>
> +defm : SetgeImmPats<GPR32, SLTi, SLTiu, XORi>;<br>
><br>
> // bswap pattern<br>
> def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Tue Mar 1 04:08:01 2016<br>
> @@ -391,8 +391,9 @@ def FCC : RegisterClass<"Mips", [i32], 3<br>
> Unallocatable;<br>
><br>
> // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.<br>
> -// This class allows us to represent this in codegen patterns.<br>
> -def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;<br>
> +// These classes allow us to represent this in codegen patterns.<br>
> +def FGRCC32 : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;<br>
> +def FGRCC64 : RegisterClass<"Mips", [i64], 64, (sequence "D%u_64", 0, 31)>;<br>
><br>
> def MSA128B: RegisterClass<"Mips", [v16i8], 128,<br>
> (sequence "W%u", 0, 31)>;<br>
> @@ -595,7 +596,13 @@ def FGR32Opnd : RegisterOperand<FGR32> {<br>
> let ParserMatchClass = FGR32AsmOperand;<br>
> }<br>
><br>
> -def FGRCCOpnd : RegisterOperand<FGRCC> {<br>
> +def FGRCC32Opnd : RegisterOperand<FGRCC32> {<br>
> + // The assembler doesn't use register classes so we can re-use<br>
> + // FGR32AsmOperand.<br>
> + let ParserMatchClass = FGR32AsmOperand;<br>
> +}<br>
> +<br>
> +def FGRCC64Opnd : RegisterOperand<FGRCC64> {<br>
> // The assembler doesn't use register classes so we can re-use<br>
> // FGR32AsmOperand.<br>
> let ParserMatchClass = FGR32AsmOperand;<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Tue Mar 1 04:08:01 2016<br>
> @@ -251,28 +251,14 @@ SDNode *MipsSEDAGToDAGISel::selectAddESu<br>
> SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);<br>
> EVT VT = LHS.getValueType();<br>
><br>
> - SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);<br>
> -<br>
> - if (Subtarget->isGP64bit()) {<br>
> - // On 64-bit targets, sltu produces an i64 but our backend currently says<br>
> - // that SLTu64 produces an i32. We need to fix this in the long run but for<br>
> - // now, just make the DAG type-correct by asserting the upper bits are zero.<br>
> - Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,<br>
> - CurDAG->getTargetConstant(0, DL, VT),<br>
> - SDValue(Carry, 0),<br>
> - CurDAG->getTargetConstant(Mips::sub_32, DL,<br>
> - VT));<br>
> - }<br>
> -<br>
> // Generate a second addition only if we know that RHS is not a<br>
> // constant-zero node.<br>
> - SDNode *AddCarry = Carry;<br>
> + SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);<br>
> ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);<br>
> if (!C || C->getZExtValue())<br>
> - AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS);<br>
> + Carry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS);<br>
><br>
> - return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,<br>
> - SDValue(AddCarry, 0));<br>
> + return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, SDValue(Carry, 0));<br>
> }<br>
><br>
> /// Match frameindex<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Tue Mar 1 04:08:01 2016<br>
> @@ -1292,7 +1292,6 @@ SDValue MipsSETargetLowering::lowerMulDi<br>
> return DAG.getMergeValues(Vals, DL);<br>
> }<br>
><br>
> -<br>
> static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {<br>
> SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,<br>
> DAG.getConstant(0, DL, MVT::i32));<br>
><br>
> Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/Mips/atomic.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/Mips/atomic.ll Tue Mar 1 04:08:01 2016<br>
> @@ -344,7 +344,11 @@ entry:<br>
> ; HAS-SEB-SEH: seb $[[R19:[0-9]+]], $[[R17]]<br>
><br>
> ; ALL: xor $[[R20:[0-9]+]], $[[R19]], $5<br>
> -; ALL: sltiu $2, $[[R20]], 1<br>
> +<br>
> +; MIPS32-ANY: sltiu $2, $[[R20]], 1<br>
> +<br>
> +; MIPS64-ANY: sltiu $[[R21:[0-9]+]], $[[R20]], 1<br>
> +; MIPS64-ANY: sll $2, $[[R21]], 0<br>
> }<br>
><br>
> ; Check one i16 so that we cover the seh sign extend<br>
><br>
> Modified: llvm/trunk/test/CodeGen/Mips/blez_bgez.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/blez_bgez.ll?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/blez_bgez.ll?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/Mips/blez_bgez.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/Mips/blez_bgez.ll Tue Mar 1 04:08:01 2016<br>
> @@ -1,10 +1,13 @@<br>
> -; RUN: llc -march=mipsel < %s | FileCheck %s<br>
> -; RUN: llc -march=mips64el < %s | FileCheck %s<br>
> +; RUN: llc -march=mipsel < %s | \<br>
> +; RUN: FileCheck %s -check-prefix=ALL<br>
> +; RUN: llc -march=mips64el < %s | \<br>
> +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=GP64<br>
><br>
> -; CHECK-LABEL: test_blez:<br>
> -; CHECK: blez ${{[0-9]+}}, $BB<br>
> +declare void @foo1()<br>
><br>
> define void @test_blez(i32 %a) {<br>
> +; ALL-LABEL: test_blez:<br>
> +; ALL: blez ${{[0-9]+}}, $BB<br>
> entry:<br>
> %cmp = icmp sgt i32 %a, 0<br>
> br i1 %cmp, label %if.then, label %if.end<br>
> @@ -17,17 +20,44 @@ if.end:<br>
> ret void<br>
> }<br>
><br>
> -declare void @foo1()<br>
> -<br>
> -; CHECK-LABEL: test_bgez:<br>
> -; CHECK: bgez ${{[0-9]+}}, $BB<br>
> -<br>
> define void @test_bgez(i32 %a) {<br>
> entry:<br>
> +; ALL-LABEL: test_bgez:<br>
> +; ALL: bgez ${{[0-9]+}}, $BB<br>
> %cmp = icmp slt i32 %a, 0<br>
> br i1 %cmp, label %if.then, label %if.end<br>
><br>
> if.then:<br>
> + tail call void @foo1()<br>
> + br label %if.end<br>
> +<br>
> +if.end:<br>
> + ret void<br>
> +}<br>
> +<br>
> +define void @test_blez_64(i64 %a) {<br>
> +; GP64-LABEL: test_blez_64:<br>
> +; GP64: blez ${{[0-9]+}}, $BB<br>
> +entry:<br>
> + %cmp = icmp sgt i64 %a, 0<br>
> + br i1 %cmp, label %if.then, label %if.end<br>
> +<br>
> +if.then:<br>
> + tail call void @foo1()<br>
> + br label %if.end<br>
> +<br>
> +if.end:<br>
> + ret void<br>
> +}<br>
> +<br>
> +define void @test_bgez_64(i64 %a) {<br>
> +entry:<br>
> +; ALL-LABEL: test_bgez_64:<br>
> +; ALL: bgez ${{[0-9]+}}, $BB<br>
> + %cmp = icmp slt i64 %a, 0<br>
> + br i1 %cmp, label %if.then, label %if.end<br>
> +<br>
> +if.then:<br>
> tail call void @foo1()<br>
> br label %if.end<br>
><br>
><br>
> Modified: llvm/trunk/test/CodeGen/Mips/cmov.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cmov.ll?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cmov.ll?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/Mips/cmov.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/Mips/cmov.ll Tue Mar 1 04:08:01 2016<br>
> @@ -1,10 +1,17 @@<br>
> -; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV<br>
> -; RUN: llc -march=mips -mcpu=mips32 -regalloc=basic < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV<br>
> -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV<br>
> -; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMP<br>
> -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV<br>
> -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV<br>
> -; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMP<br>
> +; RUN: llc -march=mips -mcpu=mips32 < %s | \<br>
> +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV<br>
> +; RUN: llc -march=mips -mcpu=mips32 -regalloc=basic < %s | \<br>
> +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV<br>
> +; RUN: llc -march=mips -mcpu=mips32r2 < %s | \<br>
> +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV<br>
> +; RUN: llc -march=mips -mcpu=mips32r6 < %s | \<br>
> +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-CMP<br>
> +; RUN: llc -march=mips64el -mcpu=mips4 < %s | \<br>
> +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -check-prefix=64<br>
> +; RUN: llc -march=mips64el -mcpu=mips64 < %s | \<br>
> +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -check-prefix=64<br>
> +; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | \<br>
> +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-CMP -check-prefix=64<br>
><br>
> @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4<br>
> @i3 = common global i32* null, align 4<br>
> @@ -413,20 +420,9 @@ entry:<br>
> ; 32-CMP-DAG: or $3, $[[T1]], $[[T0]]<br>
> ; 32-CMP-DAG: addiu $2, $zero, 0<br>
><br>
> -; 64-CMOV-DAG: addiu $[[I5:[0-9]+]], $zero, 5<br>
> -; 64-CMOV-DAG: addiu $[[I4:2]], $zero, 4<br>
> -; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767<br>
> -; 64-CMOV-DAG: movz $[[I4]], $[[I5]], $[[R0]]<br>
> -<br>
> -; 64-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5<br>
> -; 64-CMP-DAG: addiu $[[I4:[0-9]+]], $zero, 4<br>
> -; 64-CMP-DAG: slti $[[R0:[0-9]+]], $4, 32767<br>
> -; FIXME: We can do better than this by adding/subtracting the result of slti<br>
> -; to/from one of the constants.<br>
> -; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I5]], $[[R0]]<br>
> -; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I4]], $[[R0]]<br>
> -; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]<br>
> -<br>
> +; 64-DAG: daddiu $[[T0:[0-9]+]], $zero, 32766<br>
> +; 64-DAG: slt $[[T1:[0-9]+]], $[[T0]], $4<br>
> +; 64-DAG: ori $2, $[[T1]], 4<br>
> define i64 @slti64_0(i64 %a) {<br>
> entry:<br>
> %cmp = icmp sgt i64 %a, 32766<br>
> @@ -458,21 +454,9 @@ entry:<br>
> ; 32-CMP-DAG: or $3, $[[T1]], $[[T0]]<br>
> ; 32-CMP-DAG: addiu $2, $zero, 0<br>
><br>
> -; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5<br>
> -; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4<br>
> -; 64-CMOV-DAG: daddiu $[[R1:[0-9]+]], $zero, 32767<br>
> -; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4<br>
> -; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]]<br>
> -<br>
> -; 64-CMP-DAG: daddiu $[[I5:[0-9]+]], $zero, 5<br>
> -; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4<br>
> -; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], $zero, 32767<br>
> -; 64-CMP-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4<br>
> -; FIXME: We can do better than this by using selccz to choose between -0 and -2<br>
> -; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I5]], $[[R0]]<br>
> -; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]]<br>
> -; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]<br>
> -<br>
> +; 64-DAG: daddiu $[[T0:[0-9]+]], $zero, 32767<br>
> +; 64-DAG: slt $[[T1:[0-9]+]], $[[T0]], $4<br>
> +; 64-DAG: ori $2, $[[T1]], 4<br>
> define i64 @slti64_1(i64 %a) {<br>
> entry:<br>
> %cmp = icmp sgt i64 %a, 32767<br>
> @@ -480,27 +464,23 @@ entry:<br>
> ret i64 %conv<br>
> }<br>
><br>
> -; ALL-LABEL: slti64_2:<br>
> +; ALL-LABEL: slti32_2:<br>
><br>
> -; FIXME: The 32-bit versions of this test are too complicated to reasonably<br>
> -; match at the moment. They do show some missing optimizations though<br>
> -; such as:<br>
> -; (movz $a, $b, (neg $c)) -> (movn $a, $b, $c)<br>
> -<br>
> -; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3<br>
> -; 64-CMOV-DAG: addiu $[[I4:2]], $zero, 4<br>
> -; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768<br>
> -; 64-CMOV-DAG: movz $[[I4]], $[[I3]], $[[R0]]<br>
> +; FIXME: Remove unecessary sign-extension.<br>
> +; 64-DAG: slti $[[T0:[0-9]+]], $4, -32768<br>
> +; 64-DAG: sll $[[T1:[0-9]+]], $[[T0]], 0<br>
> +; 64-DAG: addiu $2, $[[T1]], 3<br>
> +define i32 @slti32_2(i32 signext %a) {<br>
> +entry:<br>
> + %cmp = icmp sgt i32 %a, -32769<br>
> + %conv = select i1 %cmp, i32 3, i32 4<br>
> + ret i32 %conv<br>
> +}<br>
><br>
> -; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3<br>
> -; 64-CMP-DAG: addiu $[[I4:[0-9]+]], $zero, 4<br>
> -; 64-CMP-DAG: slti $[[R0:[0-9]+]], $4, -32768<br>
> -; FIXME: We can do better than this by adding/subtracting the result of slti<br>
> -; to/from one of the constants.<br>
> -; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]<br>
> -; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I4]], $[[R0]]<br>
> -; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]<br>
> +; ALL-LABEL: slti64_2:<br>
><br>
> +; 64-DAG: slti $[[T0:[0-9]+]], $4, -32768<br>
> +; 64-DAG: daddiu $2, $[[T0]], 3<br>
> define i64 @slti64_2(i64 %a) {<br>
> entry:<br>
> %cmp = icmp sgt i64 %a, -32769<br>
> @@ -508,28 +488,24 @@ entry:<br>
> ret i64 %conv<br>
> }<br>
><br>
> -; ALL-LABEL: slti64_3:<br>
> +; ALL-LABEL: slti32_3:<br>
><br>
> -; FIXME: The 32-bit versions of this test are too complicated to reasonably<br>
> -; match at the moment. They do show some missing optimizations though<br>
> -; such as:<br>
> -; (movz $a, $b, (neg $c)) -> (movn $a, $b, $c)<br>
> -<br>
> -; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5<br>
> -; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4<br>
> -; 64-CMOV-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766<br>
> -; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4<br>
> -; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]]<br>
> +; FIXME: Remove unecessary sign-extension.<br>
> +; 64-DAG: slt $[[R0:[0-9]+]], ${{[0-9]+}}, $4<br>
> +; 64-DAG: sll $[[R1:[0-9]+]], $[[R0]], 0<br>
> +; 64-DAG: ori $2, $[[R1]], 4<br>
> +define i32 @slti32_3(i32 signext %a) {<br>
> +entry:<br>
> + %cmp = icmp sgt i32 %a, -32770<br>
> + %conv = select i1 %cmp, i32 5, i32 4<br>
> + ret i32 %conv<br>
> +}<br>
><br>
> -; 64-CMP-DAG: daddiu $[[I5:[0-9]+]], $zero, 5<br>
> -; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4<br>
> -; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766<br>
> -; 64-CMP-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4<br>
> -; FIXME: We can do better than this by using selccz to choose between -0 and -2<br>
> -; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I5]], $[[R0]]<br>
> -; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]]<br>
> -; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]<br>
> +; ALL-LABEL: slti64_3:<br>
><br>
> +; 64-DAG: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32766<br>
> +; 64-DAG: slt $[[R1:[0-9]+]], $[[R0]], $4<br>
> +; 64-DAG: ori $2, $[[R1]], 4<br>
> define i64 @slti64_3(i64 %a) {<br>
> entry:<br>
> %cmp = icmp sgt i64 %a, -32770<br>
><br>
> Modified: llvm/trunk/test/CodeGen/Mips/countleading.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/countleading.ll?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/countleading.ll?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/Mips/countleading.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/Mips/countleading.ll Tue Mar 1 04:08:01 2016<br>
> @@ -4,7 +4,7 @@<br>
> ; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s<br>
> ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s<br>
> ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s<br>
> -; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s<br>
> +; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s<br>
><br>
> ; Prefixes:<br>
> ; ALL - All<br>
><br>
> Modified: llvm/trunk/test/CodeGen/Mips/fcmp.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fcmp.ll?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fcmp.ll?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/Mips/fcmp.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/Mips/fcmp.ll Tue Mar 1 04:08:01 2016<br>
> @@ -29,17 +29,21 @@ define i32 @oeq_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.eq.s $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.eq.s $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> ; 32-CMP-DAG: andi $2, $[[T1]], 1<br>
><br>
> +; FIXME: The sign extension below is redundant.<br>
> ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13<br>
> -; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> -; 64-CMP-DAG: andi $2, $[[T1]], 1<br>
> +; 64-CMP-DAG: dmfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> +; 64-CMP-DAG: sll $[[T2:[0-9]+]], $[[T1]], 0<br>
> +; 64-CMP-DAG: andi $2, $[[T2]], 1<br>
><br>
> %1 = fcmp oeq float %a, %b<br>
> %2 = zext i1 %1 to i32<br>
> @@ -53,9 +57,11 @@ define i32 @ogt_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.ule.s $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ule.s $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -77,9 +83,11 @@ define i32 @oge_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.ult.s $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ult.s $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -101,9 +109,11 @@ define i32 @olt_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.olt.s $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.olt.s $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -125,9 +135,11 @@ define i32 @ole_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.ole.s $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ole.s $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -149,9 +161,11 @@ define i32 @one_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.ueq.s $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ueq.s $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -175,9 +189,11 @@ define i32 @ord_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.un.s $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.un.s $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -201,9 +217,11 @@ define i32 @ueq_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.ueq.s $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ueq.s $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -225,9 +243,11 @@ define i32 @ugt_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.ole.s $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ole.s $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -249,9 +269,11 @@ define i32 @uge_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.olt.s $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.olt.s $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -273,9 +295,11 @@ define i32 @ult_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.ult.s $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ult.s $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -298,9 +322,11 @@ define i32 @ule_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.ule.s $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ule.s $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -322,9 +348,11 @@ define i32 @une_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.eq.s $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.eq.s $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -348,9 +376,11 @@ define i32 @uno_f32(float %a, float %b)<br>
> ; 32-C-DAG: c.un.s $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.un.s $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -390,9 +420,11 @@ define i32 @oeq_f64(double %a, double %b<br>
> ; 32-C-DAG: c.eq.d $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.eq.d $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -414,9 +446,11 @@ define i32 @ogt_f64(double %a, double %b<br>
> ; 32-C-DAG: c.ule.d $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ule.d $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -438,9 +472,11 @@ define i32 @oge_f64(double %a, double %b<br>
> ; 32-C-DAG: c.ult.d $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ult.d $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -462,9 +498,11 @@ define i32 @olt_f64(double %a, double %b<br>
> ; 32-C-DAG: c.olt.d $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.olt.d $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -486,9 +524,11 @@ define i32 @ole_f64(double %a, double %b<br>
> ; 32-C-DAG: c.ole.d $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ole.d $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -510,9 +550,11 @@ define i32 @one_f64(double %a, double %b<br>
> ; 32-C-DAG: c.ueq.d $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ueq.d $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -536,9 +578,11 @@ define i32 @ord_f64(double %a, double %b<br>
> ; 32-C-DAG: c.un.d $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.un.d $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -562,9 +606,11 @@ define i32 @ueq_f64(double %a, double %b<br>
> ; 32-C-DAG: c.ueq.d $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ueq.d $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -586,9 +632,11 @@ define i32 @ugt_f64(double %a, double %b<br>
> ; 32-C-DAG: c.ole.d $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ole.d $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -610,9 +658,11 @@ define i32 @uge_f64(double %a, double %b<br>
> ; 32-C-DAG: c.olt.d $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.olt.d $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -634,9 +684,11 @@ define i32 @ult_f64(double %a, double %b<br>
> ; 32-C-DAG: c.ult.d $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ult.d $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -658,9 +710,11 @@ define i32 @ule_f64(double %a, double %b<br>
> ; 32-C-DAG: c.ule.d $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.ule.d $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -682,9 +736,11 @@ define i32 @une_f64(double %a, double %b<br>
> ; 32-C-DAG: c.eq.d $f12, $f14<br>
> ; 32-C: movt $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.eq.d $f12, $f13<br>
> -; 64-C: movt $2, $zero, $fcc0<br>
> +; 64-C-DAG: movt $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
> @@ -708,9 +764,11 @@ define i32 @uno_f64(double %a, double %b<br>
> ; 32-C-DAG: c.un.d $f12, $f14<br>
> ; 32-C: movf $2, $zero, $fcc0<br>
><br>
> -; 64-C-DAG: addiu $2, $zero, 1<br>
> +; FIXME: Remove redundant sign extension.<br>
> +; 64-C-DAG: daddiu $[[T0:[0-9]+]], $zero, 1<br>
> ; 64-C-DAG: c.un.d $f12, $f13<br>
> -; 64-C: movf $2, $zero, $fcc0<br>
> +; 64-C-DAG: movf $[[T0]], $zero, $fcc0<br>
> +; 64-C: sll $2, $[[T0]], 0<br>
><br>
> ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14<br>
> ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]<br>
><br>
> Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll Tue Mar 1 04:08:01 2016<br>
> @@ -29,7 +29,7 @@<br>
> ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \<br>
> ; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64<br>
><br>
> -define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {<br>
> +define double @tst_select_i1_double(i1 %s, double %x, double %y) {<br>
> entry:<br>
> ; ALL-LABEL: tst_select_i1_double:<br>
><br>
> @@ -53,8 +53,10 @@ entry:<br>
><br>
> ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]<br>
> ; SEL-32: mthc1 $6, $[[F0]]<br>
> + ; SEL-32: sll $[[T0:[0-9]+]], $4, 31<br>
> + ; SEL-32: sra $[[T1:[0-9]+]], $[[T0]], 31<br>
> ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp)<br>
> - ; SEL-32: mtc1 $4, $f0<br>
> + ; SEL-32: mtc1 $[[T1]], $f0<br>
> ; SEL-32: sel.d $f0, $[[F1]], $[[F0]]<br>
><br>
> ; M3: andi $[[T0:[0-9]+]], $4, 1<br>
> @@ -69,14 +71,15 @@ entry:<br>
> ; CMOV-64: movn.d $f14, $f13, $[[T0]]<br>
> ; CMOV-64: mov.d $f0, $f14<br>
><br>
> - ; SEL-64: mtc1 $4, $f0<br>
> + ; SEL-64: dsll $[[T0:[0-9]+]], $4, 63<br>
> + ; SEL-64: dsra $[[T1:[0-9]+]], $[[T0]], 63<br>
> + ; SEL-64: dmtc1 $[[T1]], $f0<br>
> ; SEL-64: sel.d $f0, $f14, $f13<br>
> %r = select i1 %s, double %x, double %y<br>
> ret double %r<br>
> }<br>
><br>
> -define double @tst_select_i1_double_reordered(double %x, double %y,<br>
> - i1 signext %s) {<br>
> +define double @tst_select_i1_double_reordered(double %x, double %y, i1 %s) {<br>
> entry:<br>
> ; ALL-LABEL: tst_select_i1_double_reordered:<br>
><br>
> @@ -110,7 +113,9 @@ entry:<br>
> ; CMOV-64: movn.d $f13, $f12, $[[T0]]<br>
> ; CMOV-64: mov.d $f0, $f13<br>
><br>
> - ; SEL-64: mtc1 $6, $f0<br>
> + ; SEL-64: dsll $[[T0:[0-9]+]], $6, 63<br>
> + ; SEL-64: dsra $[[T1:[0-9]+]], $[[T0]], 63<br>
> + ; SEL-64: dmtc1 $[[T1]], $f0<br>
> ; SEL-64: sel.d $f0, $f13, $f12<br>
> %r = select i1 %s, double %x, double %y<br>
> ret double %r<br>
><br>
> Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll Tue Mar 1 04:08:01 2016<br>
> @@ -29,7 +29,7 @@<br>
> ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \<br>
> ; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64<br>
><br>
> -define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {<br>
> +define float @tst_select_i1_float(i1 %s, float %x, float %y) {<br>
> entry:<br>
> ; ALL-LABEL: tst_select_i1_float:<br>
><br>
> @@ -51,21 +51,24 @@ entry:<br>
><br>
> ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]<br>
> ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]]<br>
> - ; SEL-32: mtc1 $4, $f0<br>
> + ; SEL-32: sll $[[T0:[0-9]+]], $4, 31<br>
> + ; SEL-32: sra $[[T1:[0-9]+]], $[[T0]], 31<br>
> + ; SEL-32: mtc1 $[[T1]], $f0<br>
> ; SEL-32: sel.s $f0, $[[F1]], $[[F0]]<br>
><br>
> ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1<br>
> ; CMOV-64: movn.s $f14, $f13, $[[T0]]<br>
> ; CMOV-64: mov.s $f0, $f14<br>
><br>
> - ; SEL-64: mtc1 $4, $f0<br>
> + ; SEL-64: dsll $[[T0:[0-9]+]], $4, 63<br>
> + ; SEL-64: dsra $[[T1:[0-9]+]], $[[T0]], 63<br>
> + ; SEL-64: dmtc1 $[[T1]], $f0<br>
> ; SEL-64: sel.s $f0, $f14, $f13<br>
> %r = select i1 %s, float %x, float %y<br>
> ret float %r<br>
> }<br>
><br>
> -define float @tst_select_i1_float_reordered(float %x, float %y,<br>
> - i1 signext %s) {<br>
> +define float @tst_select_i1_float_reordered(float %x, float %y, i1 %s) {<br>
> entry:<br>
> ; ALL-LABEL: tst_select_i1_float_reordered:<br>
><br>
> @@ -82,14 +85,18 @@ entry:<br>
> ; CMOV-32: movn.s $f14, $f12, $[[T0]]<br>
> ; CMOV-32: mov.s $f0, $f14<br>
><br>
> - ; SEL-32: mtc1 $6, $f0<br>
> + ; SEL-32: sll $[[T0:[0-9]+]], $6, 31<br>
> + ; SEL-32: sra $[[T1:[0-9]+]], $[[T0]], 31<br>
> + ; SEL-32: mtc1 $[[T1]], $f0<br>
> ; SEL-32: sel.s $f0, $f14, $f12<br>
><br>
> ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1<br>
> ; CMOV-64: movn.s $f13, $f12, $[[T0]]<br>
> ; CMOV-64: mov.s $f0, $f13<br>
><br>
> - ; SEL-64: mtc1 $6, $f0<br>
> + ; SEL-64: dsll $[[T0:[0-9]+]], $6, 63<br>
> + ; SEL-64: dsra $[[T1:[0-9]+]], $[[T0]], 63<br>
> + ; SEL-64: dmtc1 $[[T1]], $f0<br>
> ; SEL-64: sel.s $f0, $f13, $f12<br>
> %r = select i1 %s, float %x, float %y<br>
> ret float %r<br>
><br>
> Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll Tue Mar 1 04:08:01 2016<br>
> @@ -29,8 +29,7 @@<br>
> ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \<br>
> ; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64<br>
><br>
> -define signext i1 @tst_select_i1_i1(i1 signext %s,<br>
> - i1 signext %x, i1 signext %y) {<br>
> +define signext i1 @tst_select_i1_i1(i1 %s, i1 signext %x, i1 signext %y) {<br>
> entry:<br>
> ; ALL-LABEL: tst_select_i1_i1:<br>
><br>
> @@ -54,8 +53,7 @@ entry:<br>
> ret i1 %r<br>
> }<br>
><br>
> -define signext i8 @tst_select_i1_i8(i1 signext %s,<br>
> - i8 signext %x, i8 signext %y) {<br>
> +define signext i8 @tst_select_i1_i8(i1 %s, i8 signext %x, i8 signext %y) {<br>
> entry:<br>
> ; ALL-LABEL: tst_select_i1_i8:<br>
><br>
> @@ -79,8 +77,7 @@ entry:<br>
> ret i8 %r<br>
> }<br>
><br>
> -define signext i32 @tst_select_i1_i32(i1 signext %s,<br>
> - i32 signext %x, i32 signext %y) {<br>
> +define signext i32 @tst_select_i1_i32(i1 %s, i32 signext %x, i32 signext %y) {<br>
> entry:<br>
> ; ALL-LABEL: tst_select_i1_i32:<br>
><br>
> @@ -104,8 +101,7 @@ entry:<br>
> ret i32 %r<br>
> }<br>
><br>
> -define signext i64 @tst_select_i1_i64(i1 signext %s,<br>
> - i64 signext %x, i64 signext %y) {<br>
> +define signext i64 @tst_select_i1_i64(i1 %s, i64 signext %x, i64 signext %y) {<br>
> entry:<br>
> ; ALL-LABEL: tst_select_i1_i64:<br>
><br>
> @@ -152,8 +148,6 @@ entry:<br>
> ; CMOV-64: move $2, $6<br>
><br>
> ; SEL-64: andi $[[T0:[0-9]+]], $4, 1<br>
> - ; FIXME: This shift is redundant<br>
> - ; SEL-64: sll $[[T0]], $[[T0]], 0<br>
> ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]]<br>
> ; SEL-64: selnez $[[T0]], $5, $[[T0]]<br>
> ; SEL-64: or $2, $[[T0]], $[[T1]]<br>
><br>
> Modified: llvm/trunk/test/CodeGen/Mips/octeon.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/octeon.ll?rev=262316&r1=262315&r2=262316&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/octeon.ll?rev=262316&r1=262315&r2=262316&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/Mips/octeon.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/Mips/octeon.ll Tue Mar 1 04:08:01 2016<br>
> @@ -32,10 +32,8 @@ entry:<br>
> ; OCTEON: jr $ra<br>
> ; OCTEON: seq $2, $4, $5<br>
> ; MIPS64: xor $[[T0:[0-9]+]], $4, $5<br>
> -; MIPS64: sltiu $[[T1:[0-9]+]], $[[T0]], 1<br>
> -; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32<br>
> ; MIPS64: jr $ra<br>
> -; MIPS64: dsrl $2, $[[T2]], 32<br>
> +; MIPS64: sltiu $2, $[[T0]], 1<br>
> %res = icmp eq i64 %a, %b<br>
> %res2 = zext i1 %res to i64<br>
> ret i64 %res2<br>
> @@ -48,10 +46,8 @@ entry:<br>
> ; OCTEON: seqi $2, $4, 42<br>
> ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42<br>
> ; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]]<br>
> -; MIPS64: sltiu $[[T2:[0-9]+]], $[[T1]], 1<br>
> -; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32<br>
> ; MIPS64: jr $ra<br>
> -; MIPS64: dsrl $2, $[[T3]], 32<br>
> +; MIPS64: sltiu $2, $[[T1]], 1<br>
> %res = icmp eq i64 %a, 42<br>
> %res2 = zext i1 %res to i64<br>
> ret i64 %res2<br>
> @@ -63,10 +59,8 @@ entry:<br>
> ; OCTEON: jr $ra<br>
> ; OCTEON: sne $2, $4, $5<br>
> ; MIPS64: xor $[[T0:[0-9]+]], $4, $5<br>
> -; MIPS64: sltu $[[T1:[0-9]+]], $zero, $[[T0]]<br>
> -; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32<br>
> ; MIPS64: jr $ra<br>
> -; MIPS64: dsrl $2, $[[T2]], 32<br>
> +; MIPS64: sltu $2, $zero, $[[T0]]<br>
> %res = icmp ne i64 %a, %b<br>
> %res2 = zext i1 %res to i64<br>
> ret i64 %res2<br>
> @@ -79,10 +73,8 @@ entry:<br>
> ; OCTEON: snei $2, $4, 42<br>
> ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42<br>
> ; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]]<br>
> -; MIPS64: sltu $[[T2:[0-9]+]], $zero, $[[T1]]<br>
> -; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32<br>
> ; MIPS64: jr $ra<br>
> -; MIPS64: dsrl $2, $[[T3]], 32<br>
> +; MIPS64: sltu $2, $zero, $[[T1]]<br>
> %res = icmp ne i64 %a, 42<br>
> %res2 = zext i1 %res to i64<br>
> ret i64 %res2<br>
><br>
><br>
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</blockquote></div><br></div>