<div dir="ltr">Please include the revision number of the patch being reverted, and the reason for the revert (what kind of breakage? Link to a buildbot failure?)</div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Feb 26, 2016 at 4:20 AM, Chris Dewhurst via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: lerochris<br>
Date: Fri Feb 26 06:20:10 2016<br>
New Revision: 262007<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=262007&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=262007&view=rev</a><br>
Log:<br>
Reverting breaking change. Sorry.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp<br>
llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp<br>
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td<br>
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td<br>
llvm/trunk/test/MC/Disassembler/Sparc/sparc-special-registers.txt<br>
llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp?rev=262007&r1=262006&r2=262007&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp?rev=262007&r1=262006&r2=262007&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Fri Feb 26 06:20:10 2016<br>
@@ -150,22 +150,6 @@ public:<br>
Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,<br>
Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};<br>
<br>
- static const MCPhysReg CoprocRegs[32] = {<br>
- Sparc::C0, Sparc::C1, Sparc::C2, Sparc::C3,<br>
- Sparc::C4, Sparc::C5, Sparc::C6, Sparc::C7,<br>
- Sparc::C8, Sparc::C9, Sparc::C10, Sparc::C11,<br>
- Sparc::C12, Sparc::C13, Sparc::C14, Sparc::C15,<br>
- Sparc::C16, Sparc::C17, Sparc::C18, Sparc::C19,<br>
- Sparc::C20, Sparc::C21, Sparc::C22, Sparc::C23,<br>
- Sparc::C24, Sparc::C25, Sparc::C26, Sparc::C27,<br>
- Sparc::C28, Sparc::C29, Sparc::C30, Sparc::C31 };<br>
-<br>
- static const MCPhysReg CoprocPairRegs[] = {<br>
- Sparc::C0_C1, Sparc::C2_C3, Sparc::C4_C5, Sparc::C6_C7,<br>
- Sparc::C8_C9, Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15,<br>
- Sparc::C16_C17, Sparc::C18_C19, Sparc::C20_C21, Sparc::C22_C23,<br>
- Sparc::C24_C25, Sparc::C26_C27, Sparc::C28_C29, Sparc::C30_C31};<br>
-<br>
/// SparcOperand - Instances of this class represent a parsed Sparc machine<br>
/// instruction.<br>
class SparcOperand : public MCParsedAsmOperand {<br>
@@ -177,8 +161,6 @@ public:<br>
rk_FloatReg,<br>
rk_DoubleReg,<br>
rk_QuadReg,<br>
- rk_CoprocReg,<br>
- rk_CoprocPairReg,<br>
rk_Special,<br>
};<br>
<br>
@@ -242,9 +224,6 @@ public:<br>
|| Reg.Kind == rk_DoubleReg));<br>
}<br>
<br>
- bool isCoprocReg() const {<br>
- return (Kind == k_Register && Reg.Kind == rk_CoprocReg);<br>
- }<br>
<br>
StringRef getToken() const {<br>
assert(Kind == k_Token && "Invalid access!");<br>
@@ -419,19 +398,6 @@ public:<br>
return true;<br>
}<br>
<br>
- static bool MorphToCoprocPairReg(SparcOperand &Op) {<br>
- unsigned Reg = Op.getReg();<br>
- assert(Op.Reg.Kind == rk_CoprocReg);<br>
- unsigned regIdx = 32;<br>
- if (Reg >= Sparc::C0 && Reg <= Sparc::C31)<br>
- regIdx = Reg - Sparc::C0;<br>
- if (regIdx % 2 || regIdx > 31)<br>
- return false;<br>
- Op.Reg.RegNum = CoprocPairRegs[regIdx / 2];<br>
- Op.Reg.Kind = rk_CoprocPairReg;<br>
- return true;<br>
- }<br>
-<br>
static std::unique_ptr<SparcOperand><br>
MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {<br>
unsigned offsetReg = Op->getReg();<br>
@@ -843,15 +809,6 @@ SparcAsmParser::parseSparcAsmOperand(std<br>
case Sparc::FSR:<br>
Op = SparcOperand::CreateToken("%fsr", S);<br>
break;<br>
- case Sparc::FQ:<br>
- Op = SparcOperand::CreateToken("%fq", S);<br>
- break;<br>
- case Sparc::CPSR:<br>
- Op = SparcOperand::CreateToken("%csr", S);<br>
- break;<br>
- case Sparc::CPQ:<br>
- Op = SparcOperand::CreateToken("%cq", S);<br>
- break;<br>
case Sparc::WIM:<br>
Op = SparcOperand::CreateToken("%wim", S);<br>
break;<br>
@@ -984,24 +941,6 @@ bool SparcAsmParser::matchRegisterName(c<br>
return true;<br>
}<br>
<br>
- if (name.equals("fq")) {<br>
- RegNo = Sparc::FQ;<br>
- RegKind = SparcOperand::rk_Special;<br>
- return true;<br>
- }<br>
-<br>
- if (name.equals("csr")) {<br>
- RegNo = Sparc::CPSR;<br>
- RegKind = SparcOperand::rk_Special;<br>
- return true;<br>
- }<br>
-<br>
- if (name.equals("cq")) {<br>
- RegNo = Sparc::CPQ;<br>
- RegKind = SparcOperand::rk_Special;<br>
- return true;<br>
- }<br>
-<br>
if (name.equals("wim")) {<br>
RegNo = Sparc::WIM;<br>
RegKind = SparcOperand::rk_Special;<br>
@@ -1086,15 +1025,6 @@ bool SparcAsmParser::matchRegisterName(c<br>
return true;<br>
}<br>
<br>
- // %c0 - %c31<br>
- if (name.substr(0, 1).equals_lower("c")<br>
- && !name.substr(1).getAsInteger(10, intVal)<br>
- && intVal < 32) {<br>
- RegNo = CoprocRegs[intVal];<br>
- RegKind = SparcOperand::rk_CoprocReg;<br>
- return true;<br>
- }<br>
-<br>
if (name.equals("tpc")) {<br>
RegNo = Sparc::TPC;<br>
RegKind = SparcOperand::rk_Special;<br>
@@ -1285,9 +1215,5 @@ unsigned SparcAsmParser::validateTargetO<br>
if (SparcOperand::MorphToIntPairReg(Op))<br>
return MCTargetAsmParser::Match_Success;<br>
}<br>
- if (Op.isCoprocReg() && Kind == MCK_CoprocPair) {<br>
- if (SparcOperand::MorphToCoprocPairReg(Op))<br>
- return MCTargetAsmParser::Match_Success;<br>
- }<br>
return Match_InvalidOperand;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp?rev=262007&r1=262006&r2=262007&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp?rev=262007&r1=262006&r2=262007&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp (original)<br>
+++ llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp Fri Feb 26 06:20:10 2016<br>
@@ -130,25 +130,6 @@ static const uint16_t IntPairDecoderTabl<br>
SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,<br>
};<br>
<br>
-static const unsigned CPRegDecoderTable[] = {<br>
- SP::C0, SP::C1, SP::C2, SP::C3,<br>
- SP::C4, SP::C5, SP::C6, SP::C7,<br>
- SP::C8, SP::C9, SP::C10, SP::C11,<br>
- SP::C12, SP::C13, SP::C14, SP::C15,<br>
- SP::C16, SP::C17, SP::C18, SP::C19,<br>
- SP::C20, SP::C21, SP::C22, SP::C23,<br>
- SP::C24, SP::C25, SP::C26, SP::C27,<br>
- SP::C28, SP::C29, SP::C30, SP::C31<br>
-};<br>
-<br>
-<br>
-static const uint16_t CPPairDecoderTable[] = {<br>
- SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,<br>
- SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,<br>
- SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,<br>
- SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31<br>
-};<br>
-<br>
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,<br>
unsigned RegNo,<br>
uint64_t Address,<br>
@@ -210,17 +191,6 @@ static DecodeStatus DecodeQFPRegsRegiste<br>
return MCDisassembler::Success;<br>
}<br>
<br>
-static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst,<br>
- unsigned RegNo,<br>
- uint64_t Address,<br>
- const void *Decoder) {<br>
- if (RegNo > 31)<br>
- return MCDisassembler::Fail;<br>
- unsigned Reg = CPRegDecoderTable[RegNo];<br>
- Inst.addOperand(MCOperand::createReg(Reg));<br>
- return MCDisassembler::Success;<br>
-}<br>
-<br>
static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>
uint64_t Address,<br>
const void *Decoder) {<br>
@@ -263,16 +233,6 @@ static DecodeStatus DecodeIntPairRegiste<br>
return S;<br>
}<br>
<br>
-static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo,<br>
- uint64_t Address, const void *Decoder) {<br>
- if (RegNo > 31)<br>
- return MCDisassembler::Fail;<br>
-<br>
- unsigned RegisterPair = CPPairDecoderTable[RegNo/2];<br>
- Inst.addOperand(MCOperand::createReg(RegisterPair));<br>
- return MCDisassembler::Success;<br>
-}<br>
-<br>
static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,<br>
const void *Decoder);<br>
static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,<br>
@@ -283,10 +243,6 @@ static DecodeStatus DecodeLoadDFP(MCInst<br>
const void *Decoder);<br>
static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,<br>
const void *Decoder);<br>
-static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,<br>
- const void *Decoder);<br>
-static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,<br>
- const void *Decoder);<br>
static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,<br>
uint64_t Address, const void *Decoder);<br>
static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,<br>
@@ -297,10 +253,6 @@ static DecodeStatus DecodeStoreDFP(MCIns<br>
uint64_t Address, const void *Decoder);<br>
static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,<br>
uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,<br>
- uint64_t Address, const void *Decoder);<br>
-static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,<br>
- uint64_t Address, const void *Decoder);<br>
static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,<br>
uint64_t Address, const void *Decoder);<br>
static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,<br>
@@ -438,18 +390,6 @@ static DecodeStatus DecodeLoadQFP(MCInst<br>
DecodeQFPRegsRegisterClass);<br>
}<br>
<br>
-static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,<br>
- const void *Decoder) {<br>
- return DecodeMem(Inst, insn, Address, Decoder, true,<br>
- DecodeCPRegsRegisterClass);<br>
-}<br>
-<br>
-static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,<br>
- const void *Decoder) {<br>
- return DecodeMem(Inst, insn, Address, Decoder, true,<br>
- DecodeCPPairRegisterClass);<br>
-}<br>
-<br>
static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,<br>
uint64_t Address, const void *Decoder) {<br>
return DecodeMem(Inst, insn, Address, Decoder, false,<br>
@@ -480,18 +420,6 @@ static DecodeStatus DecodeStoreQFP(MCIns<br>
DecodeQFPRegsRegisterClass);<br>
}<br>
<br>
-static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,<br>
- uint64_t Address, const void *Decoder) {<br>
- return DecodeMem(Inst, insn, Address, Decoder, false,<br>
- DecodeCPRegsRegisterClass);<br>
-}<br>
-<br>
-static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,<br>
- uint64_t Address, const void *Decoder) {<br>
- return DecodeMem(Inst, insn, Address, Decoder, false,<br>
- DecodeCPPairRegisterClass);<br>
-}<br>
-<br>
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,<br>
uint64_t Address, uint64_t Offset,<br>
uint64_t Width, MCInst &MI,<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=262007&r1=262006&r2=262007&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=262007&r1=262006&r2=262007&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Fri Feb 26 06:20:10 2016<br>
@@ -235,28 +235,12 @@ def FCC_UL : FCC_VAL<19>; // Unordered<br>
def FCC_LG : FCC_VAL<18>; // Less or Greater<br>
def FCC_NE : FCC_VAL<17>; // Not Equal<br>
def FCC_E : FCC_VAL<25>; // Equal<br>
-def FCC_UE : FCC_VAL<26>; // Unordered or Equal<br>
-def FCC_GE : FCC_VAL<27>; // Greater or Equal<br>
-def FCC_UGE : FCC_VAL<28>; // Unordered or Greater or Equal<br>
-def FCC_LE : FCC_VAL<29>; // Less or Equal<br>
-def FCC_ULE : FCC_VAL<30>; // Unordered or Less or Equal<br>
-def FCC_O : FCC_VAL<31>; // Ordered<br>
-<br>
-class CPCC_VAL<int N> : PatLeaf<(i32 N)>;<br>
-def CPCC_3 : CPCC_VAL<39>; // 3<br>
-def CPCC_2 : CPCC_VAL<38>; // 2<br>
-def CPCC_23 : CPCC_VAL<37>; // 2 or 3<br>
-def CPCC_1 : CPCC_VAL<36>; // 1<br>
-def CPCC_13 : CPCC_VAL<35>; // 1 or 3<br>
-def CPCC_12 : CPCC_VAL<34>; // 1 or 2<br>
-def CPCC_123 : CPCC_VAL<33>; // 1 or 2 or 3<br>
-def CPCC_0 : CPCC_VAL<41>; // 0<br>
-def CPCC_03 : CPCC_VAL<42>; // 0 or 3<br>
-def CPCC_02 : CPCC_VAL<43>; // 0 or 2<br>
-def CPCC_023 : CPCC_VAL<44>; // 0 or 2 or 3<br>
-def CPCC_01 : CPCC_VAL<45>; // 0 or 1<br>
-def CPCC_013 : CPCC_VAL<46>; // 0 or 1 or 3<br>
-def CPCC_012 : CPCC_VAL<47>; // 0 or 1 or 2<br>
+def FCC_UE : FCC_VAL<24>; // Unordered or Equal<br>
+def FCC_GE : FCC_VAL<25>; // Greater or Equal<br>
+def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal<br>
+def FCC_LE : FCC_VAL<27>; // Less or Equal<br>
+def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal<br>
+def FCC_O : FCC_VAL<29>; // Ordered<br>
<br>
//===----------------------------------------------------------------------===//<br>
// Instruction Class Templates<br>
@@ -461,20 +445,6 @@ let DecoderMethod = "DecodeLoadQFP" in<br>
defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,<br>
Requires<[HasV9, HasHardQuad]>;<br>
<br>
-let DecoderMethod = "DecodeLoadCP" in<br>
- defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>;<br>
-let DecoderMethod = "DecodeLoadCPPair" in<br>
- defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32>;<br>
-<br>
-let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in {<br>
- let rd = 0 in {<br>
- def LDCSRrr : F3_1<3, 0b110001, (outs), (ins MEMrr:$addr),<br>
- "ld [$addr], %csr", []>;<br>
- def LDCSRri : F3_2<3, 0b110001, (outs), (ins MEMri:$addr),<br>
- "ld [$addr], %csr", []>;<br>
- }<br>
-}<br>
-<br>
let DecoderMethod = "DecodeLoadFP" in<br>
let Defs = [FSR] in {<br>
let rd = 0 in {<br>
@@ -516,27 +486,6 @@ let DecoderMethod = "DecodeStoreQFP" in<br>
defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,<br>
Requires<[HasV9, HasHardQuad]>;<br>
<br>
-let DecoderMethod = "DecodeStoreCP" in<br>
- defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>;<br>
-<br>
-let DecoderMethod = "DecodeStoreCPPair" in<br>
- defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32>;<br>
-<br>
-let DecoderMethod = "DecodeStoreCP", rd = 0 in {<br>
- let Defs = [CPSR] in {<br>
- def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins),<br>
- "st %csr, [$addr]", []>;<br>
- def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins),<br>
- "st %csr, [$addr]", []>;<br>
- }<br>
- let Defs = [CPQ] in {<br>
- def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins),<br>
- "std %cq, [$addr]", []>;<br>
- def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins),<br>
- "std %cq, [$addr]", []>;<br>
- }<br>
-}<br>
-<br>
let DecoderMethod = "DecodeStoreFP" in<br>
let Defs = [FSR] in {<br>
let rd = 0 in {<br>
@@ -552,14 +501,6 @@ let DecoderMethod = "DecodeStoreFP" in<br>
"stx %fsr, [$addr]", []>, Requires<[HasV9]>;<br>
}<br>
}<br>
- let Defs = [FQ] in {<br>
- let rd = 0 in {<br>
- def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins),<br>
- "std %fq, [$addr]", []>;<br>
- def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins),<br>
- "std %fq, [$addr]", []>;<br>
- }<br>
- }<br>
<br>
// Section B.8 - SWAP Register with Memory Instruction<br>
// (Atomic swap)<br>
@@ -814,25 +755,7 @@ let Uses = [FCC0] in {<br>
let Predicates = [HasV9] in<br>
defm BPF : FPredBranch;<br>
<br>
-// Section B.22 - Branch on Co-processor Condition Codes Instructions, p. 123<br>
-let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {<br>
-<br>
-// co-processor conditional branch class:<br>
-class CPBranchSP<dag ins, string asmstr, list<dag> pattern><br>
- : F2_2<0b111, 0, (outs), ins, asmstr, pattern>;<br>
-<br>
-// co-processor conditional branch with annul class:<br>
-class CPBranchSPA<dag ins, string asmstr, list<dag> pattern><br>
- : F2_2<0b111, 1, (outs), ins, asmstr, pattern>;<br>
-<br>
-} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1<br>
<br>
-def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),<br>
- "cb$cond $imm22",<br>
- [(SPbrfcc bb:$imm22, imm:$cond)]>;<br>
-def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),<br>
- "cb$cond,a $imm22", []>;<br>
-<br>
// Section B.24 - Call and Link Instruction, p. 125<br>
// This is the only Format 1 instruction<br>
let Uses = [O6],<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td?rev=262007&r1=262006&r2=262007&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td?rev=262007&r1=262006&r2=262007&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td (original)<br>
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td Fri Feb 26 06:20:10 2016<br>
@@ -62,12 +62,6 @@ foreach I = 0-3 in<br>
<br>
def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.<br>
<br>
-def FQ : SparcCtrlReg<0, "FQ">; // Floating-point deferred-trap queue.<br>
-<br>
-def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.<br>
-<br>
-def CPQ : SparcCtrlReg<0, "CPQ">; // Co-processor queue.<br>
-<br>
// Y register<br>
def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;<br>
// Ancillary state registers (implementation defined)<br>
@@ -210,40 +204,6 @@ def D13 : Rd<26, "F26", [F26, F27]>, Dwa<br>
def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>;<br>
def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>;<br>
<br>
-// Co-processor registers<br>
-def C0 : Ri< 0, "C0">;<br>
-def C1 : Ri< 1, "C1">;<br>
-def C2 : Ri< 2, "C2">;<br>
-def C3 : Ri< 3, "C3">;<br>
-def C4 : Ri< 4, "C4">;<br>
-def C5 : Ri< 5, "C5">;<br>
-def C6 : Ri< 6, "C6">;<br>
-def C7 : Ri< 7, "C7">;<br>
-def C8 : Ri< 8, "C8">;<br>
-def C9 : Ri< 9, "C9">;<br>
-def C10 : Ri< 10, "C10">;<br>
-def C11 : Ri< 11, "C11">;<br>
-def C12 : Ri< 12, "C12">;<br>
-def C13 : Ri< 13, "C13">;<br>
-def C14 : Ri< 14, "C14">;<br>
-def C15 : Ri< 15, "C15">;<br>
-def C16 : Ri< 16, "C16">;<br>
-def C17 : Ri< 17, "C17">;<br>
-def C18 : Ri< 18, "C18">;<br>
-def C19 : Ri< 19, "C19">;<br>
-def C20 : Ri< 20, "C20">;<br>
-def C21 : Ri< 21, "C21">;<br>
-def C22 : Ri< 22, "C22">;<br>
-def C23 : Ri< 23, "C23">;<br>
-def C24 : Ri< 24, "C24">;<br>
-def C25 : Ri< 25, "C25">;<br>
-def C26 : Ri< 26, "C26">;<br>
-def C27 : Ri< 27, "C27">;<br>
-def C28 : Ri< 28, "C28">;<br>
-def C29 : Ri< 29, "C29">;<br>
-def C30 : Ri< 30, "C30">;<br>
-def C31 : Ri< 31, "C31">;<br>
-<br>
// Unaliased double precision floating point registers.<br>
// FIXME: Define DwarfRegNum for these registers.<br>
def D16 : SparcReg< 1, "F32">;<br>
@@ -299,24 +259,6 @@ def I2_I3 : Rdi<26, "I2", [I2, I3]>;<br>
def I4_I5 : Rdi<28, "I4", [I4, I5]>;<br>
def I6_I7 : Rdi<30, "I6", [I6, I7]>;<br>
<br>
-// Aliases of the co-processor registers used for LDD/STD double-word operations<br>
-def C0_C1 : Rdi<0, "C0", [C0, C1]>;<br>
-def C2_C3 : Rdi<2, "C2", [C2, C3]>;<br>
-def C4_C5 : Rdi<4, "C4", [C4, C5]>;<br>
-def C6_C7 : Rdi<6, "C6", [C6, C7]>;<br>
-def C8_C9 : Rdi<8, "C8", [C8, C9]>;<br>
-def C10_C11 : Rdi<10, "C10", [C10, C11]>;<br>
-def C12_C13 : Rdi<12, "C12", [C12, C13]>;<br>
-def C14_C15 : Rdi<14, "C14", [C14, C15]>;<br>
-def C16_C17 : Rdi<16, "C16", [C16, C17]>;<br>
-def C18_C19 : Rdi<18, "C18", [C18, C19]>;<br>
-def C20_C21 : Rdi<20, "C20", [C20, C21]>;<br>
-def C22_C23 : Rdi<22, "C22", [C22, C23]>;<br>
-def C24_C25 : Rdi<24, "C24", [C24, C25]>;<br>
-def C26_C27 : Rdi<26, "C26", [C26, C27]>;<br>
-def C28_C29 : Rdi<28, "C28", [C28, C29]>;<br>
-def C30_C31 : Rdi<30, "C30", [C30, C31]>;<br>
-<br>
// Register classes.<br>
//<br>
// FIXME: the register order should be defined in terms of the preferred<br>
@@ -331,7 +273,6 @@ def IntRegs : RegisterClass<"SP", [i32,<br>
(sequence "L%u", 0, 7),<br>
(sequence "O%u", 0, 7))>;<br>
<br>
-<br>
// Should be in the same order as IntRegs.<br>
def IntPair : RegisterClass<"SP", [v2i32], 64,<br>
(add I0_I1, I2_I3, I4_I5, I6_I7,<br>
@@ -355,21 +296,10 @@ def QFPRegs : RegisterClass<"SP", [f128]<br>
// Floating point control register classes.<br>
def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;<br>
<br>
-let isAllocatable = 0 in {<br>
- // Ancillary state registers<br>
- def ASRRegs : RegisterClass<"SP", [i32], 32,<br>
- (add Y, (sequence "ASR%u", 1, 31))>;<br>
-<br>
- // This register class should not be used to hold i64 values.<br>
- def CoprocRegs : RegisterClass<"SP", [i32], 32,<br>
- (add (sequence "C%u", 0, 31))>;<br>
-<br>
- // Should be in the same order as CoprocRegs.<br>
- def CoprocPair : RegisterClass<"SP", [v2i32], 64,<br>
- (add C0_C1, C2_C3, C4_C5, C6_C7,<br>
- C8_C9, C10_C11, C12_C13, C14_C15,<br>
- C16_C17, C18_C19, C20_C21, C22_C23,<br>
- C24_C25, C26_C27, C28_C29, C30_C31)>;<br>
+// Ancillary state registers<br>
+def ASRRegs : RegisterClass<"SP", [i32], 32,<br>
+ (add Y, (sequence "ASR%u", 1, 31))> {<br>
+ let isAllocatable = 0;<br>
}<br>
<br>
// Privileged Registers<br>
<br>
Modified: llvm/trunk/test/MC/Disassembler/Sparc/sparc-special-registers.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Sparc/sparc-special-registers.txt?rev=262007&r1=262006&r2=262007&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Sparc/sparc-special-registers.txt?rev=262007&r1=262006&r2=262007&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/Sparc/sparc-special-registers.txt (original)<br>
+++ llvm/trunk/test/MC/Disassembler/Sparc/sparc-special-registers.txt Fri Feb 26 06:20:10 2016<br>
@@ -32,15 +32,3 @@<br>
<br>
# CHECK: wr %i0, 5, %tbr<br>
0x81 0x9e 0x20 0x05<br>
-<br>
-# CHECK: st %fsr, [%i5]<br>
-0xc1 0x2f 0x40 0x00<br>
-<br>
-# CHECK: st %csr, [%i5]<br>
-0xc1 0xaf 0x40 0x00<br>
-<br>
-# CHECK: std %cq, [%o3+-93]<br>
-0xc1 0xb2 0xff 0xa3<br>
-<br>
-# CHECK: std %fq, [%i5+%l1]<br>
-0xc1 0x37 0x40 0x11<br>
\ No newline at end of file<br>
<br>
Modified: llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s?rev=262007&r1=262006&r2=262007&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s?rev=262007&r1=262006&r2=262007&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s (original)<br>
+++ llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s Fri Feb 26 06:20:10 2016<br>
@@ -65,8 +65,8 @@<br>
faddq %f0, %f4, %f8<br>
<br>
! make sure we can handle V9 double registers and their aliased quad registers.<br>
- ! CHECK: faddd %f32, %f34, %f62 ! encoding: [0xbf,0xa0,0x48,0x43]<br>
- ! CHECK: faddq %f32, %f36, %f60 ! encoding: [0xbb,0xa0,0x48,0x65]<br>
+ ! CHECK: faddd %f32, %f34, %f62 ! encoding: [0xbf,0xa0,0x48,0x43]<br>
+ ! CHECK: faddq %f32, %f36, %f60 ! encoding: [0xbb,0xa0,0x48,0x65]<br>
faddd %f32, %f34, %f62<br>
faddq %f32, %f36, %f60<br>
<br>
@@ -103,23 +103,23 @@<br>
fcmpd %f0, %f4<br>
fcmpq %f0, %f4<br>
<br>
- ! CHECK: fcmpes %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xa4]<br>
- ! CHECK: fcmped %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xc4]<br>
- ! CHECK: fcmpeq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xe4]<br>
+ ! CHECK: fcmpes %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xa4]<br>
+ ! CHECK: fcmped %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xc4]<br>
+ ! CHECK: fcmpeq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xe4]<br>
fcmpes %f0, %f4<br>
fcmped %f0, %f4<br>
fcmpeq %f0, %f4<br>
<br>
- ! CHECK: fcmps %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x24]<br>
- ! CHECK: fcmpd %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x44]<br>
- ! CHECK: fcmpq %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x64]<br>
+ ! CHECK: fcmps %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x24]<br>
+ ! CHECK: fcmpd %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x44]<br>
+ ! CHECK: fcmpq %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x64]<br>
fcmps %fcc2, %f0, %f4<br>
fcmpd %fcc2, %f0, %f4<br>
fcmpq %fcc2, %f0, %f4<br>
<br>
- ! CHECK: fcmpes %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xa4]<br>
- ! CHECK: fcmped %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xc4]<br>
- ! CHECK: fcmpeq %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xe4]<br>
+ ! CHECK: fcmpes %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xa4]<br>
+ ! CHECK: fcmped %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xc4]<br>
+ ! CHECK: fcmpeq %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xe4]<br>
fcmpes %fcc2, %f0, %f4<br>
fcmped %fcc2, %f0, %f4<br>
fcmpeq %fcc2, %f0, %f4<br>
@@ -147,11 +147,3 @@<br>
! CHECK: std %f48, [%l0] ! encoding: [0xe3,0x3c,0x00,0x00]<br>
st %f29, [%l0]<br>
std %f48, [%l0]<br>
-<br>
- ! CHECK: std %fq, [%o4] ! encoding: [0xc1,0x33,0x00,0x00]<br>
- ! CHECK: std %fq, [%l1+62] ! encoding: [0xc1,0x34,0x60,0x3e]<br>
- ! CHECK: std %fq, [%i3+%l7] ! encoding: [0xc1,0x36,0xc0,0x17]<br>
- std %fq, [%o4]<br>
- std %fq, [%l1+62]<br>
- std %fq, [%i3+%l7]<br>
-<br>
\ No newline at end of file<br>
<br>
<br>
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</blockquote></div><br></div>