<div dir="ltr">Could we get this merged into 3.8?<br><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Feb 8, 2016 at 2:52 PM, Andrew Kaylor via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: akaylor<br>
Date: Mon Feb 8 16:52:51 2016<br>
New Revision: 260164<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=260164&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=260164&view=rev</a><br>
Log:<br>
[regalloc][WinEH] Do not mark intervals as not spillable if they contain a regmask<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D16831" rel="noreferrer" target="_blank">http://reviews.llvm.org/D16831</a><br>
<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/regalloc-spill-at-ehpad.ll<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/LiveInterval.h<br>
llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp<br>
llvm/trunk/lib/CodeGen/LiveInterval.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=260164&r1=260163&r2=260164&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=260164&r1=260163&r2=260164&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Mon Feb 8 16:52:51 2016<br>
@@ -544,6 +544,11 @@ namespace llvm {<br>
return true;<br>
}<br>
<br>
+ // Returns true if any segment in the live range contains any of the<br>
+ // provided slot indexes. Slots which occur in holes between<br>
+ // segments will not cause the function to return true.<br>
+ bool isLiveAtIndexes(ArrayRef<SlotIndex> Slots) const;<br>
+<br>
bool operator<(const LiveRange& other) const {<br>
const SlotIndex &thisIndex = beginIndex();<br>
const SlotIndex &otherIndex = other.beginIndex();<br>
<br>
Modified: llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp?rev=260164&r1=260163&r2=260164&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp?rev=260164&r1=260163&r2=260164&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp Mon Feb 8 16:52:51 2016<br>
@@ -213,8 +213,11 @@ VirtRegAuxInfo::calculateSpillWeightAndH<br>
if (!Spillable)<br>
return;<br>
<br>
- // Mark li as unspillable if all live ranges are tiny.<br>
- if (li.isZeroLength(LIS.getSlotIndexes())) {<br>
+ // Mark li as unspillable if all live ranges are tiny and the interval<br>
+ // is not live at any reg mask. If the interval is live at a reg mask<br>
+ // spilling may be required.<br>
+ if (li.isZeroLength(LIS.getSlotIndexes()) &&<br>
+ !li.isLiveAtIndexes(LIS.getRegMaskSlots())) {<br>
li.markNotSpillable();<br>
return;<br>
}<br>
<br>
Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=260164&r1=260163&r2=260164&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=260164&r1=260163&r2=260164&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Mon Feb 8 16:52:51 2016<br>
@@ -748,6 +748,40 @@ void LiveRange::flushSegmentSet() {<br>
verify();<br>
}<br>
<br>
+bool LiveRange::isLiveAtIndexes(ArrayRef<SlotIndex> Slots) const {<br>
+ ArrayRef<SlotIndex>::iterator SlotI = Slots.begin();<br>
+ ArrayRef<SlotIndex>::iterator SlotE = Slots.end();<br>
+<br>
+ // If there are no regmask slots, we have nothing to search.<br>
+ if (SlotI == SlotE)<br>
+ return false;<br>
+<br>
+ // Start our search at the first segment that ends after the first slot.<br>
+ const_iterator SegmentI = find(*SlotI);<br>
+ const_iterator SegmentE = end();<br>
+<br>
+ // If there are no segments that end after the first slot, we're done.<br>
+ if (SegmentI == SegmentE)<br>
+ return false;<br>
+<br>
+ // Look for each slot in the live range.<br>
+ for ( ; SlotI != SlotE; ++SlotI) {<br>
+ // Go to the next segment that ends after the current slot.<br>
+ // The slot may be within a hole in the range.<br>
+ SegmentI = advanceTo(SegmentI, *SlotI);<br>
+ if (SegmentI == SegmentE)<br>
+ return false;<br>
+<br>
+ // If this segment contains the slot, we're done.<br>
+ if (SegmentI->contains(*SlotI))<br>
+ return true;<br>
+ // Otherwise, look for the next slot.<br>
+ }<br>
+<br>
+ // We didn't find a segment containing any of the slots.<br>
+ return false;<br>
+}<br>
+<br>
void LiveInterval::freeSubRange(SubRange *S) {<br>
S->~SubRange();<br>
// Memory was allocated with BumpPtr allocator and is not freed here.<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/regalloc-spill-at-ehpad.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/regalloc-spill-at-ehpad.ll?rev=260164&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/regalloc-spill-at-ehpad.ll?rev=260164&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/regalloc-spill-at-ehpad.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/regalloc-spill-at-ehpad.ll Mon Feb 8 16:52:51 2016<br>
@@ -0,0 +1,75 @@<br>
+; RUN: llc -regalloc=greedy -mtriple=x86_64-pc-windows-msvc < %s -o - | FileCheck %s<br>
+<br>
+; This test checks for proper handling of a condition where the greedy register<br>
+; allocator encounters a very short interval that contains no uses but does<br>
+; contain an EH pad unwind edge, which requires spilling. Previously the<br>
+; register allocator marked a interval like this as unspillable, resulting in<br>
+; a compilation failure.<br>
+<br>
+<br>
+; The following checks that the value %p is reloaded within the catch handler.<br>
+; CHECK-LABEL: "?catch$8@?0?test@4HA":<br>
+; CHECK: .seh_endprologue<br>
+; CHECK: movq -16(%rbp), %rax<br>
+; CHECK: movb $0, (%rax)<br>
+<br>
+define i32* @test(i32* %a) personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {<br>
+entry:<br>
+ %call = call i32 @f()<br>
+ %p = bitcast i32* %a to i8*<br>
+ br i1 undef, label %if.end, label %if.else<br>
+<br>
+if.else: ; preds = %entry<br>
+ br i1 undef, label %cond.false.i, label %if.else.else<br>
+<br>
+if.else.else: ; preds = %if.else<br>
+ br i1 undef, label %cond.true.i, label %cond.false.i<br>
+<br>
+cond.true.i: ; preds = %if.else.else<br>
+ br label %invoke.cont<br>
+<br>
+cond.false.i: ; preds = %if.else.else, %if.else<br>
+ %call.i = invoke i32 @f()<br>
+ to label %invoke.cont unwind label %catch.dispatch<br>
+<br>
+catch.dispatch: ; preds = %cond.false.i<br>
+ %tmp0 = catchswitch within none [label %catch] unwind label %ehcleanup<br>
+<br>
+catch: ; preds = %catch.dispatch<br>
+ %tmp1 = catchpad within %tmp0 [i8* null, i32 64, i8* null]<br>
+ %p.0 = getelementptr inbounds i8, i8* %p, i64 0<br>
+ store i8 0, i8* %p.0, align 8<br>
+ invoke void @_CxxThrowException(i8* null, %eh.ThrowInfo* null) [ "funclet"(token %tmp1) ]<br>
+ to label %noexc unwind label %ehcleanup<br>
+<br>
+noexc: ; preds = %catch<br>
+ unreachable<br>
+<br>
+invoke.cont: ; preds = %cond.false.i, %cond.true.i<br>
+ %cond.i = phi i32 [ %call, %cond.true.i ], [ %call.i, %cond.false.i ]<br>
+ %cmp = icmp eq i32 %cond.i, -1<br>
+ %tmp3 = select i1 %cmp, i32 4, i32 0<br>
+ br label %if.end<br>
+<br>
+if.end: ; preds = %invoke.cont, %entry<br>
+ %state.0 = phi i32 [ %tmp3, %invoke.cont ], [ 4, %entry ]<br>
+ %p.1 = getelementptr inbounds i8, i8* %p, i64 0<br>
+ invoke void @g(i8* %p.1, i32 %state.0)<br>
+ to label %invoke.cont.1 unwind label %ehcleanup<br>
+<br>
+invoke.cont.1: ; preds = %if.end<br>
+ ret i32* %a<br>
+<br>
+ehcleanup: ; preds = %if.end, %catch, %catch.dispatch<br>
+ %tmp4 = cleanuppad within none []<br>
+ cleanupret from %tmp4 unwind to caller<br>
+}<br>
+<br>
+%eh.ThrowInfo = type { i32, i32, i32, i32 }<br>
+<br>
+declare i32 @__CxxFrameHandler3(...)<br>
+<br>
+declare void @_CxxThrowException(i8*, %eh.ThrowInfo*)<br>
+<br>
+declare i32 @f()<br>
+declare void @g(i8*, i32)<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote></div><br></div></div>