<div dir="ltr">Sorry I'm a bit late to this. Is there a way we can inherit features from one project to the next without creating wrapper SubtargetFeatures? Can we just pass like an inherited list and new feature list and !listconcat them when creating each processor? I don't like the idea of these wrapper processor feature sets. I don't like the SLM and Atom ones we already had. It always felt like the checks that were based on Atom/SLM should be based on -mcpu or -march and not a "feature". I don't think its a good idea to encourage more of this.<div><br></div><div>PowerPC does something like this</div><div><br></div><div><div>def ProcessorFeatures {</div><div>Â list<SubtargetFeature> Power7FeatureList =</div><div>Â Â Â [DirectivePwr7, FeatureAltivec, FeatureVSX,</div><div>Â Â Â Â FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,</div><div>Â Â Â Â FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,</div><div>Â Â Â Â FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,</div><div>Â Â Â Â FeatureFPRND, FeatureFPCVT, FeatureISEL,</div><div>Â Â Â Â FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,</div><div>Â Â Â Â Feature64Bit /*, Feature64BitRegs */,</div><div>Â Â Â Â FeatureBPERMD, FeatureExtDiv,</div><div>Â Â Â Â FeatureMFTB, DeprecatedDST];</div><div>Â list<SubtargetFeature> Power8SpecificFeatures =</div><div>Â Â Â [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,</div><div>Â Â Â Â FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic,</div><div>Â Â Â Â FeatureFusion];</div><div>Â list<SubtargetFeature> Power8FeatureList =</div><div>Â Â Â !listconcat(Power7FeatureList, Power8SpecificFeatures);</div><div>}</div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Jan 24, 2016 at 2:41 AM, Elena Demikhovsky via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: delena<br>
Date: Sun Jan 24 04:41:28 2016<br>
New Revision: 258659<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=258659&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=258659&view=rev</a><br>
Log:<br>
Added Skylake client to X86 targets and features<br>
<br>
Changes in X86.td:<br>
<br>
I set features of Intel processors in incremental form: IVB = SNB + X HSW = IVB + X ..<br>
I added Skylake client processor and defined it's features<br>
FeatureADX was missing on KNL<br>
Added some new features to appropriate processors SMAP, IFMA, PREFETCHWT1, VMFUNC and others<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D16357" rel="noreferrer" target="_blank">http://reviews.llvm.org/D16357</a><br>
<br>
<br>
Modified:<br>
  llvm/trunk/lib/Support/Host.cpp<br>
  llvm/trunk/lib/Target/X86/X86.td<br>
  llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
  llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>
  llvm/trunk/lib/Target/X86/X86Subtarget.h<br>
  llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll<br>
<br>
Modified: llvm/trunk/lib/Support/Host.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=258659&r1=258658&r2=258659&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=258659&r1=258658&r2=258659&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Support/Host.cpp (original)<br>
+++ llvm/trunk/lib/Support/Host.cpp Sun Jan 24 04:41:28 2016<br>
@@ -805,25 +805,34 @@ bool sys::getHostCPUFeatures(StringMap<b<br>
  Features["avx2"]   = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);<br>
<br>
  Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);<br>
+Â Features["sgx"]Â Â Â = HasLeaf7 && ((EBX >>Â 2) & 1);<br>
  Features["bmi"]   = HasLeaf7 && ((EBX >> 3) & 1);<br>
  Features["hle"]   = HasLeaf7 && ((EBX >> 4) & 1);<br>
  Features["bmi2"]   = HasLeaf7 && ((EBX >> 8) & 1);<br>
+Â Features["invpcid"]Â = HasLeaf7 && ((EBX >> 10) & 1);<br>
  Features["rtm"]   = HasLeaf7 && ((EBX >> 11) & 1);<br>
  Features["rdseed"]  = HasLeaf7 && ((EBX >> 18) & 1);<br>
  Features["adx"]   = HasLeaf7 && ((EBX >> 19) & 1);<br>
+Â Features["smap"]Â Â Â = HasLeaf7 && ((EBX >> 20) & 1);<br>
+Â Features["pcommit"]Â = HasLeaf7 && ((EBX >> 22) & 1);<br>
+Â Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);<br>
+Â Features["clwb"]Â Â Â = HasLeaf7 && ((EBX >> 24) & 1);<br>
  Features["sha"]   = HasLeaf7 && ((EBX >> 29) & 1);<br>
-Â // Enable protection keys<br>
-Â Features["pku"]Â Â = HasLeaf7 && ((ECX >> 4) & 1);<br>
<br>
  // AVX512 is only supported if the OS supports the context save for it.<br>
  Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;<br>
  Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;<br>
+Â Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;<br>
  Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;<br>
  Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;<br>
  Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;<br>
  Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;<br>
  Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;<br>
-Â Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;<br>
+<br>
+Â Features["prefetchwt1"] = HasLeaf7 && (ECX & 1);<br>
+Â Features["avx512vbmi"]Â = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;<br>
+Â // Enable protection keys<br>
+Â Features["pku"]Â Â Â Â Â = HasLeaf7 && ((ECX >> 4) & 1);<br>
<br>
  bool HasLeafD = MaxLevel >= 0xd &&<br>
   !GetX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=258659&r1=258658&r2=258659&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=258659&r1=258658&r2=258659&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86.td Sun Jan 24 04:41:28 2016<br>
@@ -125,6 +125,9 @@ def FeatureCDIÂ Â Â : SubtargetFeature<"<br>
 def FeaturePFI   : SubtargetFeature<"avx512pf", "HasPFI", "true",<br>
            "Enable AVX-512 PreFetch Instructions",<br>
                    [FeatureAVX512]>;<br>
+def FeaturePREFETCHWT1Â : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "true",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "Prefetch with Intent to Write and T1 Hint">;<br>
 def FeatureDQI   : SubtargetFeature<"avx512dq", "HasDQI", "true",<br>
            "Enable AVX-512 Doubleword and Quadword Instructions",<br>
                    [FeatureAVX512]>;<br>
@@ -137,6 +140,9 @@ def FeatureVLXÂ Â Â : SubtargetFeature<"a<br>
 def FeatureVBMI   : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",<br>
            "Enable AVX-512 Vector Bit Manipulation Instructions",<br>
                    [FeatureAVX512]>;<br>
+def FeatureIFMAÂ Â Â : SubtargetFeature<"ifma", "HasIFMA", "true",<br>
+Â Â Â Â Â Â Â Â Â Â Â "Enable AVX-512 Integer Fused Multiple-Add",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â [FeatureAVX512]>;<br>
 def FeaturePKU  : SubtargetFeature<"pku", "HasPKU", "true",<br>
            "Enable protection keys">;<br>
 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",<br>
@@ -202,6 +208,20 @@ def FeatureSlowDivide64 : SubtargetFeatu<br>
 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",<br>
                   "PadShortFunctions", "true",<br>
                   "Pad short functions">;<br>
+def FeatureINVPCID : SubtargetFeature<"invpcid", "HasInvPCId", "true",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "Invalidate Process-Context Identifier">;<br>
+def FeatureVMFUNCÂ : SubtargetFeature<"vmfunc", "HasVMFUNC", "true",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "VM Functions">;<br>
+def FeatureSMAPÂ Â : SubtargetFeature<"smap", "HasSMAP", "true",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "Supervisor Mode Access Protection">;<br>
+def FeatureSGXÂ Â Â : SubtargetFeature<"sgx", "HasSGX", "true",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "Enable Software Guard Extensions">;<br>
+def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "Flush A Cache Line Optimized">;<br>
+def FeaturePCOMMIT : SubtargetFeature<"pcommit", "HasPCOMMIT", "true",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "Enable Persistent Commit">;<br>
+def FeatureCLWBÂ Â : SubtargetFeature<"clwb", "HasCLWB", "true",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "Cache Line Write Back">;<br>
 // TODO: This feature ought to be renamed.<br>
 // What it really refers to are CPUs for which certain instructions<br>
 // (which ones besides the example below?) are microcoded.<br>
@@ -365,13 +385,12 @@ def : WestmereProc<"westmere">;<br>
<br>
 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,<br>
 // rather than a superset.<br>
-class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [<br>
+def ProcIntelSNB : SubtargetFeature<"snb", "X86ProcFamily", "IntelSNB",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â " Intel SandyBridge Processor", [<br>
  FeatureMMX,<br>
  FeatureAVX,<br>
  FeatureFXSR,<br>
  FeatureCMPXCHG16B,<br>
-Â FeatureSlowBTMem,<br>
-Â FeatureSlowUAMem32,<br>
  FeaturePOPCNT,<br>
  FeatureAES,<br>
  FeaturePCLMUL,<br>
@@ -379,187 +398,125 @@ class SandyBridgeProc<string Name> : Pro<br>
  FeatureXSAVEOPT,<br>
  FeatureLAHFSAHF<br>
 ]>;<br>
+<br>
+class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [<br>
+Â ProcIntelSNB,<br>
+Â FeatureSlowBTMem,<br>
+Â FeatureSlowUAMem32<br>
+]>;<br>
 def : SandyBridgeProc<"sandybridge">;<br>
 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.<br>
<br>
-class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [<br>
-Â FeatureMMX,<br>
-Â FeatureAVX,<br>
-Â FeatureFXSR,<br>
-Â FeatureCMPXCHG16B,<br>
-Â FeatureSlowBTMem,<br>
-Â FeatureSlowUAMem32,<br>
-Â FeaturePOPCNT,<br>
-Â FeatureAES,<br>
-Â FeaturePCLMUL,<br>
-Â FeatureXSAVE,<br>
-Â FeatureXSAVEOPT,<br>
+def ProcIntelIVB : SubtargetFeature<"ivb", "X86ProcFamily", "IntelIVB",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â " Intel IvyBridge Processor", [<br>
+Â ProcIntelSNB,<br>
  FeatureRDRAND,<br>
  FeatureF16C,<br>
-Â FeatureFSGSBase,<br>
-Â FeatureLAHFSAHF<br>
+Â FeatureFSGSBase<br>
+]>;<br>
+<br>
+class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [<br>
+Â ProcIntelIVB,<br>
+Â FeatureSlowBTMem,<br>
+Â FeatureSlowUAMem32<br>
 ]>;<br>
 def : IvyBridgeProc<"ivybridge">;<br>
 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.<br>
<br>
-class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [<br>
-Â FeatureMMX,<br>
+def ProcIntelHSW : SubtargetFeature<"hsw", "X86ProcFamily", "IntelHSW",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â " Intel Haswell Processor", [<br>
+Â ProcIntelIVB,<br>
  FeatureAVX2,<br>
-Â FeatureFXSR,<br>
-Â FeatureCMPXCHG16B,<br>
-Â FeatureSlowBTMem,<br>
-Â FeaturePOPCNT,<br>
-Â FeatureAES,<br>
-Â FeaturePCLMUL,<br>
-Â FeatureRDRAND,<br>
-Â FeatureXSAVE,<br>
-Â FeatureXSAVEOPT,<br>
-Â FeatureF16C,<br>
-Â FeatureFSGSBase,<br>
-Â FeatureMOVBE,<br>
-Â FeatureLZCNT,<br>
  FeatureBMI,<br>
  FeatureBMI2,<br>
  FeatureFMA,<br>
+Â FeatureLZCNT,<br>
+Â FeatureMOVBE,<br>
+Â FeatureINVPCID,<br>
+Â FeatureVMFUNC,<br>
  FeatureRTM,<br>
  FeatureHLE,<br>
-Â FeatureSlowIncDec,<br>
-Â FeatureLAHFSAHF<br>
+Â FeatureSlowIncDec<br>
 ]>;<br>
+<br>
+class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel,<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â [ProcIntelHSW]>;<br>
 def : HaswellProc<"haswell">;<br>
 def : HaswellProc<"core-avx2">; // Legacy alias.<br>
<br>
-class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [<br>
-Â FeatureMMX,<br>
-Â FeatureAVX2,<br>
-Â FeatureFXSR,<br>
-Â FeatureCMPXCHG16B,<br>
-Â FeatureSlowBTMem,<br>
-Â FeaturePOPCNT,<br>
-Â FeatureAES,<br>
-Â FeaturePCLMUL,<br>
-Â FeatureXSAVE,<br>
-Â FeatureXSAVEOPT,<br>
-Â FeatureRDRAND,<br>
-Â FeatureF16C,<br>
-Â FeatureFSGSBase,<br>
-Â FeatureMOVBE,<br>
-Â FeatureLZCNT,<br>
-Â FeatureBMI,<br>
-Â FeatureBMI2,<br>
-Â FeatureFMA,<br>
-Â FeatureRTM,<br>
-Â FeatureHLE,<br>
+def ProcIntelBDW : SubtargetFeature<"bdw", "X86ProcFamily", "IntelBDW",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â " Intel Broadwell Processor", [<br>
+Â ProcIntelHSW,<br>
  FeatureADX,<br>
  FeatureRDSEED,<br>
-Â FeatureSlowIncDec,<br>
-Â FeatureLAHFSAHF<br>
+Â FeatureSMAP<br>
 ]>;<br>
+class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel,<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â [ProcIntelBDW]>;<br>
 def : BroadwellProc<"broadwell">;<br>
<br>
+def ProcIntelSKL : SubtargetFeature<"skl", "X86ProcFamily", "IntelSKL",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â " Intel Skylake Client Processor", [<br>
+Â ProcIntelBDW,<br>
+Â FeatureMPX,<br>
+Â FeatureXSAVEC,<br>
+Â FeatureXSAVES,<br>
+Â FeatureSGX,<br>
+Â FeatureCLFLUSHOPT<br>
+]>;<br>
+<br>
+// FIXME: define SKL model<br>
+class SkylakeClientProc<string Name> : ProcessorModel<Name, HaswellModel,<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â [ProcIntelSKL]>;<br>
+def : SkylakeClientProc<"skl">;<br>
+<br>
 // FIXME: define KNL model<br>
-class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [<br>
-Â FeatureMMX,<br>
+class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,[<br>
+Â ProcIntelIVB,<br>
  FeatureAVX512,<br>
-Â FeatureFXSR,<br>
  FeatureERI,<br>
  FeatureCDI,<br>
  FeaturePFI,<br>
-Â FeatureCMPXCHG16B,<br>
-Â FeaturePOPCNT,<br>
-Â FeatureAES,<br>
-Â FeaturePCLMUL,<br>
-Â FeatureXSAVE,<br>
-Â FeatureXSAVEOPT,<br>
-Â FeatureRDRAND,<br>
-Â FeatureF16C,<br>
-Â FeatureFSGSBase,<br>
+Â FeaturePREFETCHWT1,<br>
+Â FeatureADX,<br>
+Â FeatureRDSEED,<br>
  FeatureMOVBE,<br>
  FeatureLZCNT,<br>
  FeatureBMI,<br>
  FeatureBMI2,<br>
-Â FeatureFMA,<br>
-Â FeatureRTM,<br>
-Â FeatureHLE,<br>
-Â FeatureSlowIncDec,<br>
-Â FeatureMPX,<br>
-Â FeatureLAHFSAHF<br>
+Â FeatureFMA<br>
 ]>;<br>
 def : KnightsLandingProc<"knl">;<br>
<br>
-// FIXME: define SKX model<br>
-class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [<br>
-Â FeatureMMX,<br>
+def ProcIntelSKX : SubtargetFeature<"skx", "X86ProcFamily", "IntelSKX",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â " Intel Skylake Server Processor", [<br>
+Â ProcIntelSKL,<br>
  FeatureAVX512,<br>
-Â FeatureFXSR,<br>
  FeatureCDI,<br>
  FeatureDQI,<br>
  FeatureBWI,<br>
  FeatureVLX,<br>
  FeaturePKU,<br>
-Â FeatureCMPXCHG16B,<br>
-Â FeatureSlowBTMem,<br>
-Â FeaturePOPCNT,<br>
-Â FeatureAES,<br>
-Â FeaturePCLMUL,<br>
-Â FeatureXSAVE,<br>
-Â FeatureXSAVEOPT,<br>
-Â FeatureRDRAND,<br>
-Â FeatureF16C,<br>
-Â FeatureFSGSBase,<br>
-Â FeatureMOVBE,<br>
-Â FeatureLZCNT,<br>
-Â FeatureBMI,<br>
-Â FeatureBMI2,<br>
-Â FeatureFMA,<br>
-Â FeatureRTM,<br>
-Â FeatureHLE,<br>
-Â FeatureADX,<br>
-Â FeatureRDSEED,<br>
-Â FeatureSlowIncDec,<br>
-Â FeatureMPX,<br>
-Â FeatureXSAVEC,<br>
-Â FeatureXSAVES,<br>
-Â FeatureLAHFSAHF<br>
+Â FeaturePCOMMIT,<br>
+Â FeatureCLWB<br>
 ]>;<br>
-def : SkylakeProc<"skylake">;<br>
-def : SkylakeProc<"skx">; // Legacy alias.<br>
<br>
-class CannonlakeProc<string Name> : ProcessorModel<Name, HaswellModel, [<br>
-Â FeatureMMX,<br>
-Â FeatureAVX512,<br>
-Â FeatureFXSR,<br>
-Â FeatureCDI,<br>
-Â FeatureDQI,<br>
-Â FeatureBWI,<br>
-Â FeatureVLX,<br>
-Â FeaturePKU,<br>
-Â FeatureCMPXCHG16B,<br>
-Â FeatureSlowBTMem,<br>
-Â FeaturePOPCNT,<br>
-Â FeatureAES,<br>
-Â FeaturePCLMUL,<br>
-Â FeatureXSAVE,<br>
-Â FeatureXSAVEOPT,<br>
-Â FeatureRDRAND,<br>
-Â FeatureF16C,<br>
-Â FeatureFSGSBase,<br>
-Â FeatureMOVBE,<br>
-Â FeatureLZCNT,<br>
-Â FeatureBMI,<br>
-Â FeatureBMI2,<br>
+// FIXME: define SKX model<br>
+class SkylakeServerProc<string Name> : ProcessorModel<Name, HaswellModel,<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â [ ProcIntelSKX]>;<br>
+def : SkylakeServerProc<"skylake">;<br>
+def : SkylakeServerProc<"skx">; // Legacy alias.<br>
+<br>
+def ProcIntelCNL : SubtargetFeature<"cnl", "X86ProcFamily", "IntelCNL",<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â " Intel Cannonlake Processor", [<br>
+Â ProcIntelSKX,<br>
  FeatureVBMI,<br>
-Â FeatureFMA,<br>
-Â FeatureRTM,<br>
-Â FeatureHLE,<br>
-Â FeatureADX,<br>
-Â FeatureRDSEED,<br>
-Â FeatureSlowIncDec,<br>
-Â FeatureMPX,<br>
-Â FeatureXSAVEC,<br>
-Â FeatureXSAVES,<br>
-Â FeatureLAHFSAHF<br>
+Â FeatureIFMA,<br>
+Â FeatureSHA<br>
 ]>;<br>
+<br>
+class CannonlakeProc<string Name> : ProcessorModel<Name, HaswellModel,<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â [ ProcIntelCNL ]>;<br>
 def : CannonlakeProc<"cannonlake">;<br>
 def : CannonlakeProc<"cnl">;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=258659&r1=258658&r2=258659&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=258659&r1=258658&r2=258659&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun Jan 24 04:41:28 2016<br>
@@ -797,6 +797,8 @@ def HasBMIÂ Â Â Â : Predicate<"Subtarget-<br>
 def HasBMI2   : Predicate<"Subtarget->hasBMI2()">;<br>
 def HasVBMI   : Predicate<"Subtarget->hasVBMI()">,<br>
           AssemblerPredicate<"FeatureVBMI", "AVX-512 VBMI ISA">;<br>
+def HasIFMAÂ Â Â : Predicate<"Subtarget->hasIFMA()">,<br>
+Â Â Â Â Â Â Â Â Â Â Â AssemblerPredicate<"FeatureIFMA", "AVX-512 IFMA ISA">;<br>
 def HasRTM    : Predicate<"Subtarget->hasRTM()">;<br>
 def HasHLE    : Predicate<"Subtarget->hasHLE()">;<br>
 def HasTSX    : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=258659&r1=258658&r2=258659&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=258659&r1=258658&r2=258659&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Sun Jan 24 04:41:28 2016<br>
@@ -262,6 +262,7 @@ void X86Subtarget::initializeEnvironment<br>
  HasBMI = false;<br>
  HasBMI2 = false;<br>
  HasVBMI = false;<br>
+Â HasIFMA = false;<br>
  HasRTM = false;<br>
  HasHLE = false;<br>
  HasERI = false;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=258659&r1=258658&r2=258659&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=258659&r1=258658&r2=258659&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Sun Jan 24 04:41:28 2016<br>
@@ -55,7 +55,8 @@ protected:<br>
  };<br>
<br>
  enum X86ProcFamilyEnum {<br>
-Â Â Others, IntelAtom, IntelSLM<br>
+Â Â Others, IntelAtom, IntelSLM, IntelSNB, IntelIVB, IntelHSW, IntelBDW,<br>
+Â Â IntelKNL, IntelSKL, IntelSKX, IntelCNL<br>
  };<br>
<br>
  /// X86 processor family: Intel Atom, and others<br>
@@ -137,6 +138,9 @@ protected:<br>
  /// Processor has VBMI instructions.<br>
  bool HasVBMI;<br>
<br>
+Â /// Processor has Integer Fused Multiply Add<br>
+Â bool HasIFMA;<br>
+<br>
  /// Processor has RTM instructions.<br>
  bool HasRTM;<br>
<br>
@@ -158,6 +162,9 @@ protected:<br>
  /// Processor has LAHF/SAHF instructions.<br>
  bool HasLAHFSAHF;<br>
<br>
+Â /// Processor has Prefetch with intent to Write instruction<br>
+Â bool HasPFPREFETCHWT1;<br>
+<br>
  /// True if BT (bit test) of memory instructions are slow.<br>
  bool IsBTMemSlow;<br>
<br>
@@ -229,9 +236,30 @@ protected:<br>
  /// Processor has PKU extenstions<br>
  bool HasPKU;<br>
<br>
-Â /// Processot supports MPX - Memory Protection Extensions<br>
+Â /// Processor supports MPX - Memory Protection Extensions<br>
  bool HasMPX;<br>
<br>
+Â /// Processor supports Invalidate Process-Context Identifier<br>
+Â bool HasInvPCId;<br>
+<br>
+Â /// Processor has VM Functions<br>
+Â bool HasVMFUNC;<br>
+<br>
+Â /// Processor has Supervisor Mode Access Protection<br>
+Â bool HasSMAP;<br>
+<br>
+Â /// Processor has Software Guard Extensions<br>
+Â bool HasSGX;<br>
+<br>
+Â /// Processor supports Flush Cache Line instruction<br>
+Â bool HasCLFLUSHOPT;<br>
+<br>
+Â /// Processor has Persistent Commit feature<br>
+Â bool HasPCOMMIT;<br>
+<br>
+Â /// Processor supports Cache Line Write Back instruction<br>
+Â bool HasCLWB;<br>
+<br>
  /// Use software floating point for code generation.<br>
  bool UseSoftFloat;<br>
<br>
@@ -378,6 +406,7 @@ public:<br>
  bool hasBMI() const { return HasBMI; }<br>
  bool hasBMI2() const { return HasBMI2; }<br>
  bool hasVBMI() const { return HasVBMI; }<br>
+Â bool hasIFMA() const { return HasIFMA; }<br>
  bool hasRTM() const { return HasRTM; }<br>
  bool hasHLE() const { return HasHLE; }<br>
  bool hasADX() const { return HasADX; }<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll?rev=258659&r1=258658&r2=258659&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll?rev=258659&r1=258658&r2=258659&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll Sun Jan 24 04:41:28 2016<br>
@@ -214,31 +214,31 @@ define i64 @test_cmp_b_512(<64 x i8> %a0<br>
 ; AVX512F-32-NEXT:  vpcmpltb %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpleb %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpunordb %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpneqb %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpnltb %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpnleb %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpordb %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, (%esp)<br>
 ; AVX512F-32-NEXT:  addl (%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  addl $68, %esp<br>
 ; AVX512F-32-NEXT:  retl<br>
  %res0 = call i64 @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 0, i64 -1)<br>
@@ -303,31 +303,31 @@ define i64 @test_mask_cmp_b_512(<64 x i8<br>
 ; AVX512F-32-NEXT:  vpcmpltb %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpleb %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpunordb %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpneqb %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpnltb %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpnleb %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpordb %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  addl $68, %esp<br>
 ; AVX512F-32-NEXT:  retl<br>
  %res0 = call i64 @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 0, i64 %mask)<br>
@@ -390,31 +390,31 @@ define i64 @test_ucmp_b_512(<64 x i8> %a<br>
 ; AVX512F-32-NEXT:  vpcmpltub %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpleub %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpunordub %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpnequb %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpnltub %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpnleub %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpordub %zmm1, %zmm0, %k0<br>
 ; AVX512F-32-NEXT:  kmovq %k0, (%esp)<br>
 ; AVX512F-32-NEXT:  addl (%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  addl $68, %esp<br>
 ; AVX512F-32-NEXT:  retl<br>
  %res0 = call i64 @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 0, i64 -1)<br>
@@ -479,31 +479,31 @@ define i64 @test_mask_x86_avx512_ucmp_b_<br>
 ; AVX512F-32-NEXT:  vpcmpltub %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpleub %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpunordub %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpnequb %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpnltub %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpnleub %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  vpcmpordub %zmm1, %zmm0, %k0 {%k1}<br>
 ; AVX512F-32-NEXT:  kmovq %k0, {{[0-9]+}}(%esp)<br>
 ; AVX512F-32-NEXT:  addl {{[0-9]+}}(%esp), %eax<br>
-; AVX512F-32-NEXT:Â Â adcl {{[0-9]+}}(%esp), %edx<br>
+; AVX512F-32-NEXT:Â Â adcxl {{[0-9]+}}(%esp), %edx<br>
 ; AVX512F-32-NEXT:  addl $68, %esp<br>
 ; AVX512F-32-NEXT:  retl<br>
  %res0 = call i64 @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 0, i64 %mask)<br>
@@ -2879,6 +2879,16 @@ define <32 x i16>@test_int_x86_avx512_ma<br>
 ; AVX512BW-NEXT:  vpaddw %zmm0, %zmm2, %zmm0<br>
 ; AVX512BW-NEXT:  vpaddw %zmm3, %zmm0, %zmm0<br>
 ; AVX512BW-NEXT:  retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_psrl_w_512:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpsrlw %xmm1, %zmm0, %zmm2 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpsrlw %xmm1, %zmm0, %zmm3 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpsrlw %xmm1, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm2, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm3, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.psrl.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.psrl.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> %x2, i32 -1)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.psrl.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)<br>
@@ -2899,6 +2909,16 @@ define <32 x i16>@test_int_x86_avx512_ma<br>
 ; AVX512BW-NEXT:  vpaddw %zmm0, %zmm1, %zmm0<br>
 ; AVX512BW-NEXT:  vpaddw %zmm2, %zmm0, %zmm0<br>
 ; AVX512BW-NEXT:  retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_psrl_wi_512:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpsrlw $3, %zmm0, %zmm1 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpsrlw $3, %zmm0, %zmm2 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpsrlw $3, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm2, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.psrl.wi.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 %x3)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.psrl.wi.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 -1)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.psrl.wi.512(<32 x i16> %x0, i8 3, <32 x i16> zeroinitializer, i32 %x3)<br>
@@ -2919,6 +2939,16 @@ define <32 x i16>@test_int_x86_avx512_ma<br>
 ; AVX512BW-NEXT:  vpaddw %zmm3, %zmm2, %zmm1<br>
 ; AVX512BW-NEXT:  vpaddw %zmm0, %zmm1, %zmm0<br>
 ; AVX512BW-NEXT:  retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_psrlv32hi:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpsrlvw %zmm1, %zmm0, %zmm2 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpsrlvw %zmm1, %zmm0, %zmm3 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpsrlvw %zmm1, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm3, %zmm2, %zmm1<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.psrlv32hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.psrlv32hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.psrlv32hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br>
@@ -2939,6 +2969,16 @@ define <32 x i16>@test_int_x86_avx512_ma<br>
 ; AVX512BW-NEXT:  vpaddw %zmm3, %zmm2, %zmm1<br>
 ; AVX512BW-NEXT:  vpaddw %zmm0, %zmm1, %zmm0<br>
 ; AVX512BW-NEXT:  retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_psra_w_512:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpsraw %xmm1, %zmm0, %zmm2 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpsraw %xmm1, %zmm0, %zmm3 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpsraw %xmm1, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm3, %zmm2, %zmm1<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.psra.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.psra.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.psra.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> %x2, i32 -1)<br>
@@ -2959,6 +2999,16 @@ define <32 x i16>@test_int_x86_avx512_ma<br>
 ; AVX512BW-NEXT:  vpaddw %zmm2, %zmm1, %zmm1<br>
 ; AVX512BW-NEXT:  vpaddw %zmm0, %zmm1, %zmm0<br>
 ; AVX512BW-NEXT:  retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_psra_wi_512:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpsraw $3, %zmm0, %zmm1 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpsraw $3, %zmm0, %zmm2 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpsraw $3, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm2, %zmm1, %zmm1<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.psra.wi.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 %x3)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.psra.wi.512(<32 x i16> %x0, i8 3, <32 x i16> zeroinitializer, i32 %x3)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.psra.wi.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 -1)<br>
@@ -2979,6 +3029,16 @@ define <32 x i16>@test_int_x86_avx512_ma<br>
 ; AVX512BW-NEXT:  vpaddw %zmm2, %zmm1, %zmm1<br>
 ; AVX512BW-NEXT:  vpaddw %zmm0, %zmm1, %zmm0<br>
 ; AVX512BW-NEXT:  retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_pshufh_w_512:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpshufhw $3, %zmm0, %zmm1 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpshufhw $3, %zmm0, %zmm2 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpshufhw $3, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm2, %zmm1, %zmm1<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.pshufh.w.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 %x3)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.pshufh.w.512(<32 x i16> %x0, i8 3, <32 x i16> zeroinitializer, i32 %x3)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.pshufh.w.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 -1)<br>
@@ -2992,13 +3052,23 @@ declare <32 x i16> @llvm.x86.avx512.mask<br>
 define <32 x i16>@test_int_x86_avx512_mask_pshufl_w_512(<32 x i16> %x0, i8 %x1, <32 x i16> %x2, i32 %x3) {<br>
 ; AVX512BW-LABEL: test_int_x86_avx512_mask_pshufl_w_512:<br>
 ; AVX512BW:    ## BB#0:<br>
-; AVX512BW-NEXT:Â Â kmovd %esi, %k1<br>
-; AVX512BW-NEXT:Â Â vpshuflw $3, %zmm0, %zmm1 {%k1}<br>
-; AVX512BW-NEXT:Â Â vpshuflw $3, %zmm0, %zmm2 {%k1} {z}<br>
-; AVX512BW-NEXT:Â Â vpshuflw $3, %zmm0, %zmm0<br>
-; AVX512BW-NEXT:Â Â vpaddw %zmm2, %zmm1, %zmm1<br>
-; AVX512BW-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
-; AVX512BW-NEXT:Â Â retq<br>
+; AVX512BW-NEXT:Â Â kmovd %esi, %k1<br>
+; AVX512BW-NEXT:Â Â vpshuflw $3, %zmm0, %zmm1 {%k1}<br>
+; AVX512BW-NEXT:Â Â vpshuflw $3, %zmm0, %zmm2 {%k1} {z}<br>
+; AVX512BW-NEXT:Â Â vpshuflw $3, %zmm0, %zmm0<br>
+; AVX512BW-NEXT:Â Â vpaddw %zmm2, %zmm1, %zmm1<br>
+; AVX512BW-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512BW-NEXT:Â Â retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_pshufl_w_512:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpshuflw $3, %zmm0, %zmm1 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpshuflw $3, %zmm0, %zmm2 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpshuflw $3, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm2, %zmm1, %zmm1<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.pshufl.w.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 %x3)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.pshufl.w.512(<32 x i16> %x0, i8 3, <32 x i16> zeroinitializer, i32 %x3)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.pshufl.w.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 -1)<br>
@@ -3019,6 +3089,16 @@ define <32 x i16>@test_int_x86_avx512_ma<br>
 ; AVX512BW-NEXT:  vpaddw %zmm3, %zmm2, %zmm1<br>
 ; AVX512BW-NEXT:  vpaddw %zmm0, %zmm1, %zmm0<br>
 ; AVX512BW-NEXT:  retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_psrav32_hi:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpsravw %zmm1, %zmm0, %zmm2 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpsravw %zmm1, %zmm0, %zmm3 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpsravw %zmm1, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm3, %zmm2, %zmm1<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.psrav32.hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.psrav32.hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.psrav32.hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br>
@@ -3039,6 +3119,16 @@ define <32 x i16>@test_int_x86_avx512_ma<br>
 ; AVX512BW-NEXT:  vpaddw %zmm3, %zmm2, %zmm1<br>
 ; AVX512BW-NEXT:  vpaddw %zmm0, %zmm1, %zmm0<br>
 ; AVX512BW-NEXT:  retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_psll_w_512:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpsllw %xmm1, %zmm0, %zmm2 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpsllw %xmm1, %zmm0, %zmm3 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpsllw %xmm1, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm3, %zmm2, %zmm1<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.psll.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.psll.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.psll.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> %x2, i32 -1)<br>
@@ -3059,6 +3149,16 @@ define <32 x i16>@test_int_x86_avx512_ma<br>
 ; AVX512BW-NEXT:  vpaddw %zmm2, %zmm1, %zmm1<br>
 ; AVX512BW-NEXT:  vpaddw %zmm0, %zmm1, %zmm0<br>
 ; AVX512BW-NEXT:  retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_psll_wi_512:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpsllw $3, %zmm0, %zmm1 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpsllw $3, %zmm0, %zmm2 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpsllw $3, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm2, %zmm1, %zmm1<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.psll.wi.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 %x3)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.psll.wi.512(<32 x i16> %x0, i8 3, <32 x i16> zeroinitializer, i32 %x3)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.psll.wi.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 -1)<br>
@@ -3079,6 +3179,16 @@ define <32 x i16>@test_int_x86_avx512_ma<br>
 ; AVX512BW-NEXT:  vpaddw %zmm3, %zmm2, %zmm1<br>
 ; AVX512BW-NEXT:  vpaddw %zmm0, %zmm1, %zmm0<br>
 ; AVX512BW-NEXT:  retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_psllv32hi:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpsllvw %zmm1, %zmm0, %zmm2 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpsllvw %zmm1, %zmm0, %zmm3 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpsllvw %zmm1, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm3, %zmm2, %zmm1<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.psllv32hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.psllv32hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.psllv32hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br>
@@ -3152,13 +3262,23 @@ declare <32 x i16> @llvm.x86.avx512.mask<br>
 define <32 x i16>@test_int_x86_avx512_mask_pmovzxb_w_512(<32 x i8> %x0, <32 x i16> %x1, i32 %x2) {<br>
 ; AVX512BW-LABEL: test_int_x86_avx512_mask_pmovzxb_w_512:<br>
 ; AVX512BW:    ## BB#0:<br>
-; AVX512BW-NEXT:Â Â kmovd %edi, %k1<br>
-; AVX512BW-NEXT:Â Â vpmovzxbw %ymm0, %zmm1 {%k1}<br>
-; AVX512BW-NEXT:Â Â vpmovzxbw %ymm0, %zmm2 {%k1} {z}<br>
-; AVX512BW-NEXT:Â Â vpmovzxbw %ymm0, %zmm0<br>
-; AVX512BW-NEXT:Â Â vpaddw %zmm2, %zmm1, %zmm1<br>
-; AVX512BW-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
-; AVX512BW-NEXT:Â Â retq<br>
+; AVX512BW-NEXT:Â Â kmovd %edi, %k1<br>
+; AVX512BW-NEXT:Â Â vpmovzxbw %ymm0, %zmm1 {%k1}<br>
+; AVX512BW-NEXT:Â Â vpmovzxbw %ymm0, %zmm2 {%k1} {z}<br>
+; AVX512BW-NEXT:Â Â vpmovzxbw %ymm0, %zmm0<br>
+; AVX512BW-NEXT:Â Â vpaddw %zmm2, %zmm1, %zmm1<br>
+; AVX512BW-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512BW-NEXT:Â Â retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_pmovzxb_w_512:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpmovzxbw %ymm0, %zmm1 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpmovzxbw %ymm0, %zmm2 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpmovzxbw %ymm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm2, %zmm1, %zmm1<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.pmovzxb.w.512(<32 x i8> %x0, <32 x i16> %x1, i32 %x2)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmovzxb.w.512(<32 x i8> %x0, <32 x i16> zeroinitializer, i32 %x2)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.pmovzxb.w.512(<32 x i8> %x0, <32 x i16> %x1, i32 -1)<br>
@@ -3172,13 +3292,23 @@ declare <32 x i16> @llvm.x86.avx512.mask<br>
 define <32 x i16>@test_int_x86_avx512_mask_pmovsxb_w_512(<32 x i8> %x0, <32 x i16> %x1, i32 %x2) {<br>
 ; AVX512BW-LABEL: test_int_x86_avx512_mask_pmovsxb_w_512:<br>
 ; AVX512BW:    ## BB#0:<br>
-; AVX512BW-NEXT:Â Â kmovd %edi, %k1<br>
-; AVX512BW-NEXT:Â Â vpmovsxbw %ymm0, %zmm1 {%k1}<br>
-; AVX512BW-NEXT:Â Â vpmovsxbw %ymm0, %zmm2 {%k1} {z}<br>
-; AVX512BW-NEXT:Â Â vpmovsxbw %ymm0, %zmm0<br>
-; AVX512BW-NEXT:Â Â vpaddw %zmm2, %zmm1, %zmm1<br>
-; AVX512BW-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
-; AVX512BW-NEXT:Â Â retq<br>
+; AVX512BW-NEXT:Â Â kmovd %edi, %k1<br>
+; AVX512BW-NEXT:Â Â vpmovsxbw %ymm0, %zmm1 {%k1}<br>
+; AVX512BW-NEXT:Â Â vpmovsxbw %ymm0, %zmm2 {%k1} {z}<br>
+; AVX512BW-NEXT:Â Â vpmovsxbw %ymm0, %zmm0<br>
+; AVX512BW-NEXT:Â Â vpaddw %zmm2, %zmm1, %zmm1<br>
+; AVX512BW-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512BW-NEXT:Â Â retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_pmovsxb_w_512:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpmovsxbw %ymm0, %zmm1 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpmovsxbw %ymm0, %zmm2 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpmovsxbw %ymm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm2, %zmm1, %zmm1<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.pmovsxb.w.512(<32 x i8> %x0, <32 x i16> %x1, i32 %x2)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmovsxb.w.512(<32 x i8> %x0, <32 x i16> zeroinitializer, i32 %x2)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.pmovsxb.w.512(<32 x i8> %x0, <32 x i16> %x1, i32 -1)<br>
@@ -3192,13 +3322,23 @@ declare <32 x i16> @llvm.x86.avx512.mask<br>
 define <32 x i16>@test_int_x86_avx512_mask_permvar_hi_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br>
 ; AVX512BW-LABEL: test_int_x86_avx512_mask_permvar_hi_512:<br>
 ; AVX512BW:    ## BB#0:<br>
-; AVX512BW-NEXT:Â Â kmovd %edi, %k1<br>
-; AVX512BW-NEXT:Â Â vpermw %zmm1, %zmm0, %zmm2 {%k1}<br>
-; AVX512BW-NEXT:Â Â vpermw %zmm1, %zmm0, %zmm3 {%k1} {z}<br>
-; AVX512BW-NEXT:Â Â vpermw %zmm1, %zmm0, %zmm0<br>
-; AVX512BW-NEXT:Â Â vpaddw %zmm3, %zmm2, %zmm1<br>
-; AVX512BW-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
-; AVX512BW-NEXT:Â Â retq<br>
+; AVX512BW-NEXT:Â Â kmovd %edi, %k1<br>
+; AVX512BW-NEXT:Â Â vpermw %zmm1, %zmm0, %zmm2 {%k1}<br>
+; AVX512BW-NEXT:Â Â vpermw %zmm1, %zmm0, %zmm3 {%k1} {z}<br>
+; AVX512BW-NEXT:Â Â vpermw %zmm1, %zmm0, %zmm0<br>
+; AVX512BW-NEXT:Â Â vpaddw %zmm3, %zmm2, %zmm1<br>
+; AVX512BW-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512BW-NEXT:Â Â retq<br>
+;<br>
+; AVX512F-32-LABEL: test_int_x86_avx512_mask_permvar_hi_512:<br>
+; AVX512F-32:Â Â Â Â # BB#0:<br>
+; AVX512F-32-NEXT:Â Â kmovd {{[0-9]+}}(%esp), %k1<br>
+; AVX512F-32-NEXT:Â Â vpermw %zmm1, %zmm0, %zmm2 {%k1}<br>
+; AVX512F-32-NEXT:Â Â vpermw %zmm1, %zmm0, %zmm3 {%k1} {z}<br>
+; AVX512F-32-NEXT:Â Â vpermw %zmm1, %zmm0, %zmm0<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm3, %zmm2, %zmm1<br>
+; AVX512F-32-NEXT:Â Â vpaddw %zmm0, %zmm1, %zmm0<br>
+; AVX512F-32-NEXT:Â Â retl<br>
  %res = call <32 x i16> @llvm.x86.avx512.mask.permvar.hi.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>
  %res1 = call <32 x i16> @llvm.x86.avx512.mask.permvar.hi.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)<br>
  %res2 = call <32 x i16> @llvm.x86.avx512.mask.permvar.hi.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br>
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature">~Craig</div>
</div>