<div dir="ltr">It's a pipe dream, but maybe we can make x86 suck less. :)<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jan 26, 2016 at 3:16 PM, Eric Christopher <span dir="ltr"><<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Thanks for the cleanup.<div><br></div><div>-eric</div></div><br><div class="gmail_quote"><div dir="ltr">On Tue, Jan 26, 2016 at 2:12 PM Sanjay Patel via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: spatel<br>
Date: Tue Jan 26 16:08:58 2016<br>
New Revision: 258867<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=258867&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=258867&view=rev</a><br>
Log:<br>
[x86] make the subtarget member a const reference, not a pointer ; NFCI<br>
<br>
It's passed in as a reference; it's not optional; it's not a pointer.<br>
<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=258867&r1=258866&r2=258867&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=258867&r1=258866&r2=258867&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jan 26 16:08:58 2016<br>
@@ -71,9 +71,9 @@ static cl::opt<bool> ExperimentalVectorW<br>
<br>
X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,<br>
const X86Subtarget &STI)<br>
- : TargetLowering(TM), Subtarget(&STI) {<br>
- X86ScalarSSEf64 = Subtarget->hasSSE2();<br>
- X86ScalarSSEf32 = Subtarget->hasSSE1();<br>
+ : TargetLowering(TM), Subtarget(STI) {<br>
+ X86ScalarSSEf64 = Subtarget.hasSSE2();<br>
+ X86ScalarSSEf32 = Subtarget.hasSSE1();<br>
MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());<br>
<br>
// Set up the TargetLowering object.<br>
@@ -86,24 +86,24 @@ X86TargetLowering::X86TargetLowering(con<br>
// For 64-bit, since we have so many registers, use the ILP scheduler.<br>
// For 32-bit, use the register pressure specific scheduling.<br>
// For Atom, always use ILP scheduling.<br>
- if (Subtarget->isAtom())<br>
+ if (Subtarget.isAtom())<br>
setSchedulingPreference(Sched::ILP);<br>
- else if (Subtarget->is64Bit())<br>
+ else if (Subtarget.is64Bit())<br>
setSchedulingPreference(Sched::ILP);<br>
else<br>
setSchedulingPreference(Sched::RegPressure);<br>
- const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();<br>
+ const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();<br>
setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());<br>
<br>
// Bypass expensive divides on Atom when compiling with O2.<br>
if (TM.getOptLevel() >= CodeGenOpt::Default) {<br>
- if (Subtarget->hasSlowDivide32())<br>
+ if (Subtarget.hasSlowDivide32())<br>
addBypassSlowDiv(32, 8);<br>
- if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())<br>
+ if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())<br>
addBypassSlowDiv(64, 16);<br>
}<br>
<br>
- if (Subtarget->isTargetKnownWindowsMSVC()) {<br>
+ if (Subtarget.isTargetKnownWindowsMSVC()) {<br>
// Setup Windows compiler runtime calls.<br>
setLibcallName(RTLIB::SDIV_I64, "_alldiv");<br>
setLibcallName(RTLIB::UDIV_I64, "_aulldiv");<br>
@@ -117,11 +117,11 @@ X86TargetLowering::X86TargetLowering(con<br>
setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);<br>
}<br>
<br>
- if (Subtarget->isTargetDarwin()) {<br>
+ if (Subtarget.isTargetDarwin()) {<br>
// Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.<br>
setUseUnderscoreSetJmp(false);<br>
setUseUnderscoreLongJmp(false);<br>
- } else if (Subtarget->isTargetWindowsGNU()) {<br>
+ } else if (Subtarget.isTargetWindowsGNU()) {<br>
// MS runtime is weird: it exports _setjmp, but longjmp!<br>
setUseUnderscoreSetJmp(true);<br>
setUseUnderscoreLongJmp(false);<br>
@@ -134,7 +134,7 @@ X86TargetLowering::X86TargetLowering(con<br>
addRegisterClass(MVT::i8, &X86::GR8RegClass);<br>
addRegisterClass(MVT::i16, &X86::GR16RegClass);<br>
addRegisterClass(MVT::i32, &X86::GR32RegClass);<br>
- if (Subtarget->is64Bit())<br>
+ if (Subtarget.is64Bit())<br>
addRegisterClass(MVT::i64, &X86::GR64RegClass);<br>
<br>
for (MVT VT : MVT::integer_valuetypes())<br>
@@ -164,14 +164,14 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);<br>
setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);<br>
<br>
- if (Subtarget->is64Bit()) {<br>
- if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())<br>
+ if (Subtarget.is64Bit()) {<br>
+ if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512())<br>
// f32/f64 are legal, f80 is custom.<br>
setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);<br>
else<br>
setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);<br>
setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);<br>
- } else if (!Subtarget->useSoftFloat()) {<br>
+ } else if (!Subtarget.useSoftFloat()) {<br>
// We have an algorithm for SSE2->double, and we turn this into a<br>
// 64-bit FILD followed by conditional FADD for other targets.<br>
setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);<br>
@@ -185,7 +185,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);<br>
setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);<br>
<br>
- if (!Subtarget->useSoftFloat()) {<br>
+ if (!Subtarget.useSoftFloat()) {<br>
// SSE has no i16 to fp conversion, only i32<br>
if (X86ScalarSSEf32) {<br>
setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);<br>
@@ -205,7 +205,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);<br>
setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);<br>
<br>
- if (!Subtarget->useSoftFloat()) {<br>
+ if (!Subtarget.useSoftFloat()) {<br>
// In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64<br>
// are Legal, f80 is custom lowered.<br>
setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);<br>
@@ -231,8 +231,8 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);<br>
setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);<br>
<br>
- if (Subtarget->is64Bit()) {<br>
- if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {<br>
+ if (Subtarget.is64Bit()) {<br>
+ if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {<br>
// FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.<br>
setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);<br>
setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);<br>
@@ -240,9 +240,9 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);<br>
setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);<br>
}<br>
- } else if (!Subtarget->useSoftFloat()) {<br>
+ } else if (!Subtarget.useSoftFloat()) {<br>
// Since AVX is a superset of SSE3, only check for SSE here.<br>
- if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())<br>
+ if (Subtarget.hasSSE1() && !Subtarget.hasSSE3())<br>
// Expand FP_TO_UINT into a select.<br>
// FIXME: We would like to use a Custom expander here eventually to do<br>
// the optimal thing for SSE vs. the default expansion in the legalizer.<br>
@@ -260,12 +260,12 @@ X86TargetLowering::X86TargetLowering(con<br>
if (!X86ScalarSSEf64) {<br>
setOperationAction(ISD::BITCAST , MVT::f32 , Expand);<br>
setOperationAction(ISD::BITCAST , MVT::i32 , Expand);<br>
- if (Subtarget->is64Bit()) {<br>
+ if (Subtarget.is64Bit()) {<br>
setOperationAction(ISD::BITCAST , MVT::f64 , Expand);<br>
// Without SSE, i64->f64 goes through memory.<br>
setOperationAction(ISD::BITCAST , MVT::i64 , Expand);<br>
}<br>
- } else if (!Subtarget->is64Bit())<br>
+ } else if (!Subtarget.is64Bit())<br>
setOperationAction(ISD::BITCAST , MVT::i64 , Custom);<br>
<br>
// Scalar integer divide and remainder are lowered to use operations that<br>
@@ -311,14 +311,14 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);<br>
setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);<br>
setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);<br>
- if (Subtarget->is64Bit())<br>
+ if (Subtarget.is64Bit())<br>
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);<br>
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);<br>
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);<br>
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);<br>
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);<br>
<br>
- if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {<br>
+ if (Subtarget.is32Bit() && Subtarget.isTargetKnownWindowsMSVC()) {<br>
// On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`<br>
// is. We should promote the value to 64-bits to solve this.<br>
// This is what the CRT headers do - `fmodf` is an inline header<br>
@@ -338,19 +338,19 @@ X86TargetLowering::X86TargetLowering(con<br>
AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);<br>
setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);<br>
AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);<br>
- if (Subtarget->hasBMI()) {<br>
+ if (Subtarget.hasBMI()) {<br>
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);<br>
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);<br>
- if (Subtarget->is64Bit())<br>
+ if (Subtarget.is64Bit())<br>
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);<br>
} else {<br>
setOperationAction(ISD::CTTZ , MVT::i16 , Custom);<br>
setOperationAction(ISD::CTTZ , MVT::i32 , Custom);<br>
- if (Subtarget->is64Bit())<br>
+ if (Subtarget.is64Bit())<br>
setOperationAction(ISD::CTTZ , MVT::i64 , Custom);<br>
}<br>
<br>
- if (Subtarget->hasLZCNT()) {<br>
+ if (Subtarget.hasLZCNT()) {<br>
// When promoting the i8 variants, force them to i32 for a shorter<br>
// encoding.<br>
setOperationAction(ISD::CTLZ , MVT::i8 , Promote);<br>
@@ -359,7 +359,7 @@ X86TargetLowering::X86TargetLowering(con<br>
AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);<br>
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);<br>
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);<br>
- if (Subtarget->is64Bit())<br>
+ if (Subtarget.is64Bit())<br>
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);<br>
} else {<br>
setOperationAction(ISD::CTLZ , MVT::i8 , Custom);<br>
@@ -368,7 +368,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);<br>
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);<br>
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);<br>
- if (Subtarget->is64Bit()) {<br>
+ if (Subtarget.is64Bit()) {<br>
setOperationAction(ISD::CTLZ , MVT::i64 , Custom);<br>
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);<br>
}<br>
@@ -377,7 +377,7 @@ X86TargetLowering::X86TargetLowering(con<br>
// Special handling for half-precision floating point conversions.<br>
// If we don't have F16C support, then lower half float conversions<br>
// into library calls.<br>
- if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {<br>
+ if (Subtarget.useSoftFloat() || !Subtarget.hasF16C()) {<br>
setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);<br>
setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);<br>
}<br>
@@ -395,19 +395,19 @@ X86TargetLowering::X86TargetLowering(con<br>
setTruncStoreAction(MVT::f64, MVT::f16, Expand);<br>
setTruncStoreAction(MVT::f80, MVT::f16, Expand);<br>
<br>
- if (Subtarget->hasPOPCNT()) {<br>
+ if (Subtarget.hasPOPCNT()) {<br>
setOperationAction(ISD::CTPOP , MVT::i8 , Promote);<br>
} else {<br>
setOperationAction(ISD::CTPOP , MVT::i8 , Expand);<br>
setOperationAction(ISD::CTPOP , MVT::i16 , Expand);<br>
setOperationAction(ISD::CTPOP , MVT::i32 , Expand);<br>
- if (Subtarget->is64Bit())<br>
+ if (Subtarget.is64Bit())<br>
setOperationAction(ISD::CTPOP , MVT::i64 , Expand);<br>
}<br>
<br>
setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);<br>
<br>
- if (!Subtarget->hasMOVBE())<br>
+ if (!Subtarget.hasMOVBE())<br>
setOperationAction(ISD::BSWAP , MVT::i16 , Expand);<br>
<br>
// These should be promoted to a larger select which is supported.<br>
@@ -430,7 +430,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::SETCCE , MVT::i8 , Custom);<br>
setOperationAction(ISD::SETCCE , MVT::i16 , Custom);<br>
setOperationAction(ISD::SETCCE , MVT::i32 , Custom);<br>
- if (Subtarget->is64Bit()) {<br>
+ if (Subtarget.is64Bit()) {<br>
setOperationAction(ISD::SELECT , MVT::i64 , Custom);<br>
setOperationAction(ISD::SETCC , MVT::i64 , Custom);<br>
setOperationAction(ISD::SETCCE , MVT::i64 , Custom);<br>
@@ -450,11 +450,11 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::JumpTable , MVT::i32 , Custom);<br>
setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);<br>
setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);<br>
- if (Subtarget->is64Bit())<br>
+ if (Subtarget.is64Bit())<br>
setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);<br>
setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);<br>
setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);<br>
- if (Subtarget->is64Bit()) {<br>
+ if (Subtarget.is64Bit()) {<br>
setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);<br>
setOperationAction(ISD::JumpTable , MVT::i64 , Custom);<br>
setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);<br>
@@ -465,13 +465,13 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);<br>
setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);<br>
setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);<br>
- if (Subtarget->is64Bit()) {<br>
+ if (Subtarget.is64Bit()) {<br>
setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);<br>
setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);<br>
setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);<br>
}<br>
<br>
- if (Subtarget->hasSSE1())<br>
+ if (Subtarget.hasSSE1())<br>
setOperationAction(ISD::PREFETCH , MVT::Other, Legal);<br>
<br>
setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);<br>
@@ -483,13 +483,13 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::ATOMIC_STORE, VT, Custom);<br>
}<br>
<br>
- if (Subtarget->hasCmpxchg16b()) {<br>
+ if (Subtarget.hasCmpxchg16b()) {<br>
setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);<br>
}<br>
<br>
// FIXME - use subtarget debug flags<br>
- if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&<br>
- !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {<br>
+ if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&<br>
+ !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64()) {<br>
setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);<br>
}<br>
<br>
@@ -505,7 +505,7 @@ X86TargetLowering::X86TargetLowering(con<br>
// VASTART needs to be custom lowered to use the VarArgsFrameIndex<br>
setOperationAction(ISD::VASTART , MVT::Other, Custom);<br>
setOperationAction(ISD::VAEND , MVT::Other, Expand);<br>
- if (Subtarget->is64Bit()) {<br>
+ if (Subtarget.is64Bit()) {<br>
setOperationAction(ISD::VAARG , MVT::Other, Custom);<br>
setOperationAction(ISD::VACOPY , MVT::Other, Custom);<br>
} else {<br>
@@ -523,7 +523,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);<br>
setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);<br>
<br>
- if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {<br>
+ if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {<br>
// f32 and f64 use SSE.<br>
// Set up the FP register classes.<br>
addRegisterClass(MVT::f32, &X86::FR32RegClass);<br>
@@ -557,7 +557,7 @@ X86TargetLowering::X86TargetLowering(con<br>
// cases we handle.<br>
addLegalFPImmediate(APFloat(+0.0)); // xorpd<br>
addLegalFPImmediate(APFloat(+0.0f)); // xorps<br>
- } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {<br>
+ } else if (!Subtarget.useSoftFloat() && X86ScalarSSEf32) {<br>
// Use SSE for f32, x87 for f64.<br>
// Set up the FP register classes.<br>
addRegisterClass(MVT::f32, &X86::FR32RegClass);<br>
@@ -592,7 +592,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::FCOS , MVT::f64, Expand);<br>
setOperationAction(ISD::FSINCOS, MVT::f64, Expand);<br>
}<br>
- } else if (!Subtarget->useSoftFloat()) {<br>
+ } else if (!Subtarget.useSoftFloat()) {<br>
// f32 and f64 in x87.<br>
// Set up the FP register classes.<br>
addRegisterClass(MVT::f64, &X86::RFP64RegClass);<br>
@@ -626,8 +626,8 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::FMA, MVT::f32, Expand);<br>
<br>
// Long double always uses X87, except f128 in MMX.<br>
- if (!Subtarget->useSoftFloat()) {<br>
- if (Subtarget->is64Bit() && Subtarget->hasMMX()) {<br>
+ if (!Subtarget.useSoftFloat()) {<br>
+ if (Subtarget.is64Bit() && Subtarget.hasMMX()) {<br>
addRegisterClass(MVT::f128, &X86::FR128RegClass);<br>
ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);<br>
setOperationAction(ISD::FABS , MVT::f128, Custom);<br>
@@ -774,7 +774,7 @@ X86TargetLowering::X86TargetLowering(con<br>
<br>
// FIXME: In order to prevent SSE instructions being expanded to MMX ones<br>
// with -msoft-float, disable use of MMX as well.<br>
- if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {<br>
+ if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {<br>
addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);<br>
// No operations on x86mmx supported, everything uses intrinsics.<br>
}<br>
@@ -792,7 +792,7 @@ X86TargetLowering::X86TargetLowering(con<br>
}<br>
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);<br>
<br>
- if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {<br>
+ if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {<br>
addRegisterClass(MVT::v4f32, &X86::VR128RegClass);<br>
<br>
setOperationAction(ISD::FADD, MVT::v4f32, Legal);<br>
@@ -811,7 +811,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);<br>
}<br>
<br>
- if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {<br>
+ if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {<br>
addRegisterClass(MVT::v2f64, &X86::VR128RegClass);<br>
<br>
// FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM<br>
@@ -908,7 +908,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);<br>
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);<br>
<br>
- if (Subtarget->is64Bit()) {<br>
+ if (Subtarget.is64Bit()) {<br>
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);<br>
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);<br>
}<br>
@@ -942,7 +942,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);<br>
// As there is no 64-bit GPR available, we need build a special custom<br>
// sequence to convert from v2i32 to v2f32.<br>
- if (!Subtarget->is64Bit())<br>
+ if (!Subtarget.is64Bit())<br>
setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);<br>
<br>
setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);<br>
@@ -956,7 +956,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);<br>
}<br>
<br>
- if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {<br>
+ if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {<br>
for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {<br>
setOperationAction(ISD::FFLOOR, RoundedTy, Legal);<br>
setOperationAction(ISD::FCEIL, RoundedTy, Legal);<br>
@@ -1020,13 +1020,13 @@ X86TargetLowering::X86TargetLowering(con<br>
<br>
// FIXME: these should be Legal, but that's only for the case where<br>
// the index is constant. For now custom expand to deal with that.<br>
- if (Subtarget->is64Bit()) {<br>
+ if (Subtarget.is64Bit()) {<br>
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);<br>
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);<br>
}<br>
}<br>
<br>
- if (Subtarget->hasSSE2()) {<br>
+ if (Subtarget.hasSSE2()) {<br>
setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);<br>
setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);<br>
setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);<br>
@@ -1052,7 +1052,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::SRA, MVT::v4i32, Custom);<br>
}<br>
<br>
- if (Subtarget->hasXOP()) {<br>
+ if (Subtarget.hasXOP()) {<br>
setOperationAction(ISD::ROTL, MVT::v16i8, Custom);<br>
setOperationAction(ISD::ROTL, MVT::v8i16, Custom);<br>
setOperationAction(ISD::ROTL, MVT::v4i32, Custom);<br>
@@ -1063,7 +1063,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::ROTL, MVT::v4i64, Custom);<br>
}<br>
<br>
- if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {<br>
+ if (!Subtarget.useSoftFloat() && Subtarget.hasFp256()) {<br>
addRegisterClass(MVT::v32i8, &X86::VR256RegClass);<br>
addRegisterClass(MVT::v16i16, &X86::VR256RegClass);<br>
addRegisterClass(MVT::v8i32, &X86::VR256RegClass);<br>
@@ -1162,7 +1162,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);<br>
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);<br>
<br>
- if (Subtarget->hasAnyFMA()) {<br>
+ if (Subtarget.hasAnyFMA()) {<br>
setOperationAction(ISD::FMA, MVT::v8f32, Legal);<br>
setOperationAction(ISD::FMA, MVT::v4f64, Legal);<br>
setOperationAction(ISD::FMA, MVT::v4f32, Legal);<br>
@@ -1171,7 +1171,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::FMA, MVT::f64, Legal);<br>
}<br>
<br>
- if (Subtarget->hasInt256()) {<br>
+ if (Subtarget.hasInt256()) {<br>
setOperationAction(ISD::ADD, MVT::v4i64, Legal);<br>
setOperationAction(ISD::ADD, MVT::v8i32, Legal);<br>
setOperationAction(ISD::ADD, MVT::v16i16, Legal);<br>
@@ -1289,7 +1289,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);<br>
}<br>
<br>
- if (Subtarget->hasInt256())<br>
+ if (Subtarget.hasInt256())<br>
setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);<br>
<br>
// Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.<br>
@@ -1307,7 +1307,7 @@ X86TargetLowering::X86TargetLowering(con<br>
}<br>
}<br>
<br>
- if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {<br>
+ if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {<br>
addRegisterClass(MVT::v16i32, &X86::VR512RegClass);<br>
addRegisterClass(MVT::v16f32, &X86::VR512RegClass);<br>
addRegisterClass(MVT::v8i64, &X86::VR512RegClass);<br>
@@ -1388,7 +1388,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);<br>
setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);<br>
setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);<br>
- if (Subtarget->hasVLX()){<br>
+ if (Subtarget.hasVLX()){<br>
setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);<br>
setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);<br>
setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);<br>
@@ -1411,7 +1411,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);<br>
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);<br>
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);<br>
- if (Subtarget->hasDQI()) {<br>
+ if (Subtarget.hasDQI()) {<br>
setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);<br>
setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);<br>
<br>
@@ -1419,7 +1419,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);<br>
setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);<br>
setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);<br>
- if (Subtarget->hasVLX()) {<br>
+ if (Subtarget.hasVLX()) {<br>
setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);<br>
setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);<br>
setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);<br>
@@ -1430,7 +1430,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);<br>
}<br>
}<br>
- if (Subtarget->hasVLX()) {<br>
+ if (Subtarget.hasVLX()) {<br>
setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);<br>
setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);<br>
setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);<br>
@@ -1452,7 +1452,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);<br>
setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);<br>
setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);<br>
- if (Subtarget->hasDQI()) {<br>
+ if (Subtarget.hasDQI()) {<br>
setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);<br>
setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);<br>
}<br>
@@ -1524,7 +1524,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::OR, MVT::v16i32, Legal);<br>
setOperationAction(ISD::XOR, MVT::v16i32, Legal);<br>
<br>
- if (Subtarget->hasCDI()) {<br>
+ if (Subtarget.hasCDI()) {<br>
setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);<br>
setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);<br>
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Expand);<br>
@@ -1542,7 +1542,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);<br>
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);<br>
<br>
- if (Subtarget->hasVLX()) {<br>
+ if (Subtarget.hasVLX()) {<br>
setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);<br>
setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);<br>
setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);<br>
@@ -1566,9 +1566,9 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Expand);<br>
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Expand);<br>
}<br>
- } // Subtarget->hasCDI()<br>
+ } // Subtarget.hasCDI()<br>
<br>
- if (Subtarget->hasDQI()) {<br>
+ if (Subtarget.hasDQI()) {<br>
setOperationAction(ISD::MUL, MVT::v2i64, Legal);<br>
setOperationAction(ISD::MUL, MVT::v4i64, Legal);<br>
setOperationAction(ISD::MUL, MVT::v8i64, Legal);<br>
@@ -1617,7 +1617,7 @@ X86TargetLowering::X86TargetLowering(con<br>
}<br>
}// has AVX-512<br>
<br>
- if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {<br>
+ if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {<br>
addRegisterClass(MVT::v32i16, &X86::VR512RegClass);<br>
addRegisterClass(MVT::v64i8, &X86::VR512RegClass);<br>
<br>
@@ -1678,10 +1678,10 @@ X86TargetLowering::X86TargetLowering(con<br>
<br>
setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);<br>
setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);<br>
- if (Subtarget->hasVLX())<br>
+ if (Subtarget.hasVLX())<br>
setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);<br>
<br>
- if (Subtarget->hasCDI()) {<br>
+ if (Subtarget.hasCDI()) {<br>
setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);<br>
setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);<br>
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Expand);<br>
@@ -1704,7 +1704,7 @@ X86TargetLowering::X86TargetLowering(con<br>
}<br>
}<br>
<br>
- if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {<br>
+ if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {<br>
addRegisterClass(MVT::v4i1, &X86::VK4RegClass);<br>
addRegisterClass(MVT::v2i1, &X86::VK2RegClass);<br>
<br>
@@ -1744,7 +1744,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);<br>
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);<br>
setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);<br>
- if (!Subtarget->is64Bit()) {<br>
+ if (!Subtarget.is64Bit()) {<br>
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);<br>
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);<br>
}<br>
@@ -1756,7 +1756,7 @@ X86TargetLowering::X86TargetLowering(con<br>
// subtraction on x86-32 once PR3203 is fixed. We really can't do much better<br>
// than generic legalization for 64-bit multiplication-with-overflow, though.<br>
for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {<br>
- if (VT == MVT::i64 && !Subtarget->is64Bit())<br>
+ if (VT == MVT::i64 && !Subtarget.is64Bit())<br>
continue;<br>
// Add/Sub/Mul with overflow operations are custom lowered.<br>
setOperationAction(ISD::SADDO, VT, Custom);<br>
@@ -1767,7 +1767,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::UMULO, VT, Custom);<br>
}<br>
<br>
- if (!Subtarget->is64Bit()) {<br>
+ if (!Subtarget.is64Bit()) {<br>
// These libcalls are not available in 32-bit.<br>
setLibcallName(RTLIB::SHL_I128, nullptr);<br>
setLibcallName(RTLIB::SRL_I128, nullptr);<br>
@@ -1775,10 +1775,10 @@ X86TargetLowering::X86TargetLowering(con<br>
}<br>
<br>
// Combine sin / cos into one node or libcall if possible.<br>
- if (Subtarget->hasSinCos()) {<br>
+ if (Subtarget.hasSinCos()) {<br>
setLibcallName(RTLIB::SINCOS_F32, "sincosf");<br>
setLibcallName(RTLIB::SINCOS_F64, "sincos");<br>
- if (Subtarget->isTargetDarwin()) {<br>
+ if (Subtarget.isTargetDarwin()) {<br>
// For MacOSX, we don't want the normal expansion of a libcall to sincos.<br>
// We want to issue a libcall to __sincos_stret to avoid memory traffic.<br>
setOperationAction(ISD::FSINCOS, MVT::f64, Custom);<br>
@@ -1786,7 +1786,7 @@ X86TargetLowering::X86TargetLowering(con<br>
}<br>
}<br>
<br>
- if (Subtarget->isTargetWin64()) {<br>
+ if (Subtarget.isTargetWin64()) {<br>
setOperationAction(ISD::SDIV, MVT::i128, Custom);<br>
setOperationAction(ISD::UDIV, MVT::i128, Custom);<br>
setOperationAction(ISD::SREM, MVT::i128, Custom);<br>
@@ -1832,7 +1832,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setTargetDAGCombine(ISD::MSCATTER);<br>
setTargetDAGCombine(ISD::MGATHER);<br>
<br>
- computeRegisterProperties(Subtarget->getRegisterInfo());<br>
+ computeRegisterProperties(Subtarget.getRegisterInfo());<br>
<br>
MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores<br>
MaxStoresPerMemsetOptSize = 8;<br>
@@ -1844,7 +1844,7 @@ X86TargetLowering::X86TargetLowering(con<br>
<br>
// A predictable cmov does not hurt on an in-order CPU.<br>
// FIXME: Use a CPU attribute to trigger this, not a CPU model.<br>
- PredictableSelectIsExpensive = !Subtarget->isAtom();<br>
+ PredictableSelectIsExpensive = !Subtarget.isAtom();<br>
EnableExtLdPromotion = true;<br>
setPrefFunctionAlignment(4); // 2^4 bytes.<br>
<br>
@@ -1853,7 +1853,7 @@ X86TargetLowering::X86TargetLowering(con<br>
<br>
// This has so far only been implemented for 64-bit MachO.<br>
bool X86TargetLowering::useLoadStackGuardNode() const {<br>
- return Subtarget->isTargetMachO() && Subtarget->is64Bit();<br>
+ return Subtarget.isTargetMachO() && Subtarget.is64Bit();<br>
}<br>
<br>
TargetLoweringBase::LegalizeTypeAction<br>
@@ -1869,21 +1869,21 @@ X86TargetLowering::getPreferredVectorAct<br>
EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,<br>
EVT VT) const {<br>
if (!VT.isVector())<br>
- return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;<br>
+ return Subtarget.hasAVX512() ? MVT::i1: MVT::i8;<br>
<br>
if (VT.isSimple()) {<br>
MVT VVT = VT.getSimpleVT();<br>
const unsigned NumElts = VVT.getVectorNumElements();<br>
const MVT EltVT = VVT.getVectorElementType();<br>
if (VVT.is512BitVector()) {<br>
- if (Subtarget->hasAVX512())<br>
+ if (Subtarget.hasAVX512())<br>
if (EltVT == MVT::i32 || EltVT == MVT::i64 ||<br>
EltVT == MVT::f32 || EltVT == MVT::f64)<br>
switch(NumElts) {<br>
case 8: return MVT::v8i1;<br>
case 16: return MVT::v16i1;<br>
}<br>
- if (Subtarget->hasBWI())<br>
+ if (Subtarget.hasBWI())<br>
if (EltVT == MVT::i8 || EltVT == MVT::i16)<br>
switch(NumElts) {<br>
case 32: return MVT::v32i1;<br>
@@ -1892,7 +1892,7 @@ EVT X86TargetLowering::getSetCCResultTyp<br>
}<br>
<br>
if (VVT.is256BitVector() || VVT.is128BitVector()) {<br>
- if (Subtarget->hasVLX())<br>
+ if (Subtarget.hasVLX())<br>
if (EltVT == MVT::i32 || EltVT == MVT::i64 ||<br>
EltVT == MVT::f32 || EltVT == MVT::f64)<br>
switch(NumElts) {<br>
@@ -1900,7 +1900,7 @@ EVT X86TargetLowering::getSetCCResultTyp<br>
case 4: return MVT::v4i1;<br>
case 8: return MVT::v8i1;<br>
}<br>
- if (Subtarget->hasBWI() && Subtarget->hasVLX())<br>
+ if (Subtarget.hasBWI() && Subtarget.hasVLX())<br>
if (EltVT == MVT::i8 || EltVT == MVT::i16)<br>
switch(NumElts) {<br>
case 8: return MVT::v8i1;<br>
@@ -1944,7 +1944,7 @@ static void getMaxByValAlign(Type *Ty, u<br>
/// are at 4-byte boundaries.<br>
unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,<br>
const DataLayout &DL) const {<br>
- if (Subtarget->is64Bit()) {<br>
+ if (Subtarget.is64Bit()) {<br>
// Max of 8 and alignment of type.<br>
unsigned TyAlign = DL.getABITypeAlignment(Ty);<br>
if (TyAlign > 8)<br>
@@ -1953,7 +1953,7 @@ unsigned X86TargetLowering::getByValType<br>
}<br>
<br>
unsigned Align = 4;<br>
- if (Subtarget->hasSSE1())<br>
+ if (Subtarget.hasSSE1())<br>
getMaxByValAlign(Ty, Align);<br>
return Align;<br>
}<br>
@@ -1979,23 +1979,23 @@ X86TargetLowering::getOptimalMemOpType(u<br>
if ((!IsMemset || ZeroMemset) &&<br>
!F->hasFnAttribute(Attribute::NoImplicitFloat)) {<br>
if (Size >= 16 &&<br>
- (!Subtarget->isUnalignedMem16Slow() ||<br>
+ (!Subtarget.isUnalignedMem16Slow() ||<br>
((DstAlign == 0 || DstAlign >= 16) &&<br>
(SrcAlign == 0 || SrcAlign >= 16)))) {<br>
if (Size >= 32) {<br>
// FIXME: Check if unaligned 32-byte accesses are slow.<br>
- if (Subtarget->hasInt256())<br>
+ if (Subtarget.hasInt256())<br>
return MVT::v8i32;<br>
- if (Subtarget->hasFp256())<br>
+ if (Subtarget.hasFp256())<br>
return MVT::v8f32;<br>
}<br>
- if (Subtarget->hasSSE2())<br>
+ if (Subtarget.hasSSE2())<br>
return MVT::v4i32;<br>
- if (Subtarget->hasSSE1())<br>
+ if (Subtarget.hasSSE1())<br>
return MVT::v4f32;<br>
} else if (!MemcpyStrSrc && Size >= 8 &&<br>
- !Subtarget->is64Bit() &&<br>
- Subtarget->hasSSE2()) {<br>
+ !Subtarget.is64Bit() &&<br>
+ Subtarget.hasSSE2()) {<br>
// Do not use f64 to lower memcpy if source is string constant. It's<br>
// better to use i32 to avoid the loads.<br>
return MVT::f64;<br>
@@ -2004,7 +2004,7 @@ X86TargetLowering::getOptimalMemOpType(u<br>
// This is a compromise. If we reach here, unaligned accesses may be slow on<br>
// this target. However, creating smaller, aligned accesses could be even<br>
// slower and would certainly be a lot more code.<br>
- if (Subtarget->is64Bit() && Size >= 8)<br>
+ if (Subtarget.is64Bit() && Size >= 8)<br>
return MVT::i64;<br>
return MVT::i32;<br>
}<br>
@@ -2029,10 +2029,10 @@ X86TargetLowering::allowsMisalignedMemor<br>
*Fast = true;<br>
break;<br>
case 128:<br>
- *Fast = !Subtarget->isUnalignedMem16Slow();<br>
+ *Fast = !Subtarget.isUnalignedMem16Slow();<br>
break;<br>
case 256:<br>
- *Fast = !Subtarget->isUnalignedMem32Slow();<br>
+ *Fast = !Subtarget.isUnalignedMem32Slow();<br>
break;<br>
// TODO: What about AVX-512 (512-bit) accesses?<br>
}<br>
@@ -2048,7 +2048,7 @@ unsigned X86TargetLowering::getJumpTable<br>
// In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF<br>
// symbol.<br>
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&<br>
- Subtarget->isPICStyleGOT())<br>
+ Subtarget.isPICStyleGOT())<br>
return MachineJumpTableInfo::EK_Custom32;<br>
<br>
// Otherwise, use the normal jump table encoding heuristics.<br>
@@ -2056,7 +2056,7 @@ unsigned X86TargetLowering::getJumpTable<br>
}<br>
<br>
bool X86TargetLowering::useSoftFloat() const {<br>
- return Subtarget->useSoftFloat();<br>
+ return Subtarget.useSoftFloat();<br>
}<br>
<br>
const MCExpr *<br>
@@ -2064,7 +2064,7 @@ X86TargetLowering::LowerCustomJumpTableE<br>
const MachineBasicBlock *MBB,<br>
unsigned uid,MCContext &Ctx) const{<br>
assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&<br>
- Subtarget->isPICStyleGOT());<br>
+ Subtarget.isPICStyleGOT());<br>
// In 32-bit ELF systems, our jump table entries are formed with @GOTOFF<br>
// entries.<br>
return MCSymbolRefExpr::create(MBB->getSymbol(),<br>
@@ -2074,7 +2074,7 @@ X86TargetLowering::LowerCustomJumpTableE<br>
/// Returns relocation base for the given PIC jumptable.<br>
SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,<br>
SelectionDAG &DAG) const {<br>
- if (!Subtarget->is64Bit())<br>
+ if (!Subtarget.is64Bit())<br>
// This doesn't have SDLoc associated with it, but is not really the<br>
// same as a Register.<br>
return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),<br>
@@ -2088,7 +2088,7 @@ const MCExpr *X86TargetLowering::<br>
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,<br>
MCContext &Ctx) const {<br>
// X86-64 uses RIP relative addressing based on the jump table label.<br>
- if (Subtarget->isPICStyleRIPRel())<br>
+ if (Subtarget.isPICStyleRIPRel())<br>
return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);<br>
<br>
// Otherwise, the reference is relative to the PIC base.<br>
@@ -2104,7 +2104,7 @@ X86TargetLowering::findRepresentativeCla<br>
default:<br>
return TargetLowering::findRepresentativeClass(TRI, VT);<br>
case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:<br>
- RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;<br>
+ RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;<br>
break;<br>
case MVT::x86mmx:<br>
RRC = &X86::VR64RegClass;<br>
@@ -2122,10 +2122,10 @@ X86TargetLowering::findRepresentativeCla<br>
<br>
bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,<br>
unsigned &Offset) const {<br>
- if (!Subtarget->isTargetLinux())<br>
+ if (!Subtarget.isTargetLinux())<br>
return false;<br>
<br>
- if (Subtarget->is64Bit()) {<br>
+ if (Subtarget.is64Bit()) {<br>
// %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:<br>
Offset = 0x28;<br>
if (getTargetMachine().getCodeModel() == CodeModel::Kernel)<br>
@@ -2141,14 +2141,14 @@ bool X86TargetLowering::getStackCookieLo<br>
}<br>
<br>
Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {<br>
- if (!Subtarget->isTargetAndroid())<br>
+ if (!Subtarget.isTargetAndroid())<br>
return TargetLowering::getSafeStackPointerLocation(IRB);<br>
<br>
// Android provides a fixed TLS slot for the SafeStack pointer. See the<br>
// definition of TLS_SLOT_SAFESTACK in<br>
// <a href="https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h" rel="noreferrer" target="_blank">https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h</a><br>
unsigned AddressSpace, Offset;<br>
- if (Subtarget->is64Bit()) {<br>
+ if (Subtarget.is64Bit()) {<br>
// %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:<br>
Offset = 0x48;<br>
if (getTargetMachine().getCodeModel() == CodeModel::Kernel)<br>
@@ -2243,14 +2243,14 @@ X86TargetLowering::LowerReturn(SDValue C<br>
// or SSE or MMX vectors.<br>
if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||<br>
VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&<br>
- (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {<br>
+ (Subtarget.is64Bit() && !Subtarget.hasSSE1())) {<br>
report_fatal_error("SSE register return with SSE disabled");<br>
}<br>
// Likewise we can't return F64 values with SSE1 only. gcc does so, but<br>
// llvm-gcc has never done it right and no one has noticed, so this<br>
// should be OK for now.<br>
if (ValVT == MVT::f64 &&<br>
- (Subtarget->is64Bit() && !Subtarget->hasSSE2()))<br>
+ (Subtarget.is64Bit() && !Subtarget.hasSSE2()))<br>
report_fatal_error("SSE2 register return with SSE2 disabled");<br>
<br>
// Returns in ST0/ST1 are handled specially: these are pushed as operands to<br>
@@ -2268,7 +2268,7 @@ X86TargetLowering::LowerReturn(SDValue C<br>
<br>
// 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64<br>
// which is returned in RAX / RDX.<br>
- if (Subtarget->is64Bit()) {<br>
+ if (Subtarget.is64Bit()) {<br>
if (ValVT == MVT::x86mmx) {<br>
if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {<br>
ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);<br>
@@ -2276,7 +2276,7 @@ X86TargetLowering::LowerReturn(SDValue C<br>
ValToCopy);<br>
// If we don't have SSE2 available, convert to v4f32 so the generated<br>
// register is legal.<br>
- if (!Subtarget->hasSSE2())<br>
+ if (!Subtarget.hasSSE2())<br>
ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);<br>
}<br>
}<br>
@@ -2301,7 +2301,7 @@ X86TargetLowering::LowerReturn(SDValue C<br>
getPointerTy(MF.getDataLayout()));<br>
<br>
unsigned RetValReg<br>
- = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?<br>
+ = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?<br>
X86::RAX : X86::EAX;<br>
Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);<br>
Flag = Chain.getValue(1);<br>
@@ -2311,7 +2311,7 @@ X86TargetLowering::LowerReturn(SDValue C<br>
DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));<br>
}<br>
<br>
- const X86RegisterInfo *TRI = Subtarget->getRegisterInfo();<br>
+ const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();<br>
const MCPhysReg *I =<br>
TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());<br>
if (I) {<br>
@@ -2379,7 +2379,7 @@ X86TargetLowering::getTypeForExtArgOrRet<br>
ISD::NodeType ExtendKind) const {<br>
MVT ReturnMVT;<br>
// TODO: Is this also valid on 32-bit?<br>
- if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)<br>
+ if (Subtarget.is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)<br>
ReturnMVT = MVT::i8;<br>
else<br>
ReturnMVT = MVT::i32;<br>
@@ -2400,7 +2400,7 @@ X86TargetLowering::LowerCallResult(SDVal<br>
<br>
// Assign locations to each value returned by this call.<br>
SmallVector<CCValAssign, 16> RVLocs;<br>
- bool Is64Bit = Subtarget->is64Bit();<br>
+ bool Is64Bit = Subtarget.is64Bit();<br>
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,<br>
*DAG.getContext());<br>
CCInfo.AnalyzeCallResult(Ins, RetCC_X86);<br>
@@ -2412,7 +2412,7 @@ X86TargetLowering::LowerCallResult(SDVal<br>
<br>
// If this is x86-64, and we disabled SSE, we can't return FP values<br>
if ((CopyVT == MVT::f32 || CopyVT == MVT::f64 || CopyVT == MVT::f128) &&<br>
- ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {<br>
+ ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget.hasSSE1())) {<br>
report_fatal_error("SSE register return with SSE disabled");<br>
}<br>
<br>
@@ -2618,10 +2618,10 @@ X86TargetLowering::LowerMemArgument(SDVa<br>
<br>
// FIXME: Get this from tablegen.<br>
static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,<br>
- const X86Subtarget *Subtarget) {<br>
- assert(Subtarget->is64Bit());<br>
+ const X86Subtarget &Subtarget) {<br>
+ assert(Subtarget.is64Bit());<br>
<br>
- if (Subtarget->isCallingConvWin64(CallConv)) {<br>
+ if (Subtarget.isCallingConvWin64(CallConv)) {<br>
static const MCPhysReg GPR64ArgRegsWin64[] = {<br>
X86::RCX, X86::RDX, X86::R8, X86::R9<br>
};<br>
@@ -2637,9 +2637,9 @@ static ArrayRef<MCPhysReg> get64BitArgum<br>
// FIXME: Get this from tablegen.<br>
static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,<br>
CallingConv::ID CallConv,<br>
- const X86Subtarget *Subtarget) {<br>
- assert(Subtarget->is64Bit());<br>
- if (Subtarget->isCallingConvWin64(CallConv)) {<br>
+ const X86Subtarget &Subtarget) {<br>
+ assert(Subtarget.is64Bit());<br>
+ if (Subtarget.isCallingConvWin64(CallConv)) {<br>
// The XMM registers which might contain var arg parameters are shadowed<br>
// in their paired GPR. So we only need to save the GPR to their home<br>
// slots.<br>
@@ -2649,10 +2649,10 @@ static ArrayRef<MCPhysReg> get64BitArgum<br>
<br>
const Function *Fn = MF.getFunction();<br>
bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);<br>
- bool isSoftFloat = Subtarget->useSoftFloat();<br>
+ bool isSoftFloat = Subtarget.useSoftFloat();<br>
assert(!(isSoftFloat && NoImplicitFloatOps) &&<br>
"SSE register cannot be used when SSE is disabled!");<br>
- if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())<br>
+ if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1())<br>
// Kernel mode asks for SSE to be disabled, so there are no XMM argument<br>
// registers.<br>
return None;<br>
@@ -2670,17 +2670,17 @@ SDValue X86TargetLowering::LowerFormalAr<br>
SmallVectorImpl<SDValue> &InVals) const {<br>
MachineFunction &MF = DAG.getMachineFunction();<br>
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();<br>
- const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();<br>
+ const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();<br>
<br>
const Function* Fn = MF.getFunction();<br>
if (Fn->hasExternalLinkage() &&<br>
- Subtarget->isTargetCygMing() &&<br>
+ Subtarget.isTargetCygMing() &&<br>
Fn->getName() == "main")<br>
FuncInfo->setForceFramePointer(true);<br>
<br>
MachineFrameInfo *MFI = MF.getFrameInfo();<br>
- bool Is64Bit = Subtarget->is64Bit();<br>
- bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);<br>
+ bool Is64Bit = Subtarget.is64Bit();<br>
+ bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);<br>
<br>
assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&<br>
"Var args not supported with calling convention fastcc, ghc or hipe");<br>
@@ -2818,7 +2818,7 @@ SDValue X86TargetLowering::LowerFormalAr<br>
}<br>
<br>
// Figure out if XMM registers are in use.<br>
- assert(!(Subtarget->useSoftFloat() &&<br>
+ assert(!(Subtarget.useSoftFloat() &&<br>
Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&<br>
"SSE register cannot be used when SSE is disabled!");<br>
<br>
@@ -2830,7 +2830,7 @@ SDValue X86TargetLowering::LowerFormalAr<br>
ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);<br>
unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);<br>
unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);<br>
- assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&<br>
+ assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&<br>
"SSE register cannot be used when SSE is disabled!");<br>
<br>
// Gather all the live in physical registers.<br>
@@ -2912,13 +2912,13 @@ SDValue X86TargetLowering::LowerFormalAr<br>
// Find the largest legal vector type.<br>
MVT VecVT = MVT::Other;<br>
// FIXME: Only some x86_32 calling conventions support AVX512.<br>
- if (Subtarget->hasAVX512() &&<br>
+ if (Subtarget.hasAVX512() &&<br>
(Is64Bit || (CallConv == CallingConv::X86_VectorCall ||<br>
CallConv == CallingConv::Intel_OCL_BI)))<br>
VecVT = MVT::v16f32;<br>
- else if (Subtarget->hasAVX())<br>
+ else if (Subtarget.hasAVX())<br>
VecVT = MVT::v8f32;<br>
- else if (Subtarget->hasSSE2())<br>
+ else if (Subtarget.hasSSE2())<br>
VecVT = MVT::v4f32;<br>
<br>
// We forward some GPRs and some vector types.<br>
@@ -2959,8 +2959,8 @@ SDValue X86TargetLowering::LowerFormalAr<br>
FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.<br>
// If this is an sret function, the return should pop the hidden pointer.<br>
if (!Is64Bit && !canGuaranteeTCO(CallConv) &&<br>
- !Subtarget->getTargetTriple().isOSMSVCRT() &&<br>
- argsAreStructReturn(Ins, Subtarget->isTargetMCU()) == StackStructReturn)<br>
+ !Subtarget.getTargetTriple().isOSMSVCRT() &&<br>
+ argsAreStructReturn(Ins, Subtarget.isTargetMCU()) == StackStructReturn)<br>
FuncInfo->setBytesToPopOnReturn(4);<br>
}<br>
<br>
@@ -3078,9 +3078,9 @@ X86TargetLowering::LowerCall(TargetLower<br>
bool isVarArg = CLI.IsVarArg;<br>
<br>
MachineFunction &MF = DAG.getMachineFunction();<br>
- bool Is64Bit = Subtarget->is64Bit();<br>
- bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);<br>
- StructReturnType SR = callIsStructReturn(Outs, Subtarget->isTargetMCU());<br>
+ bool Is64Bit = Subtarget.is64Bit();<br>
+ bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);<br>
+ StructReturnType SR = callIsStructReturn(Outs, Subtarget.isTargetMCU());<br>
bool IsSibcall = false;<br>
X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();<br>
auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");<br>
@@ -3091,7 +3091,7 @@ X86TargetLowering::LowerCall(TargetLower<br>
if (Attr.getValueAsString() == "true")<br>
isTailCall = false;<br>
<br>
- if (Subtarget->isPICStyleGOT() &&<br>
+ if (Subtarget.isPICStyleGOT() &&<br>
!MF.getTarget().Options.GuaranteedTailCallOpt) {<br>
// If we are using a GOT, disable tail calls to external symbols with<br>
// default visibility. Tail calling such a symbol requires using a GOT<br>
@@ -3194,7 +3194,7 @@ X86TargetLowering::LowerCall(TargetLower<br>
<br>
// Walk the register/memloc assignments, inserting copies/loads. In the case<br>
// of tail call optimization arguments are handle later.<br>
- const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();<br>
+ const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();<br>
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {<br>
// Skip inalloca arguments, they have already been written.<br>
ISD::ArgFlagsTy Flags = Outs[i].Flags;<br>
@@ -3272,7 +3272,7 @@ X86TargetLowering::LowerCall(TargetLower<br>
if (!MemOpChains.empty())<br>
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);<br>
<br>
- if (Subtarget->isPICStyleGOT()) {<br>
+ if (Subtarget.isPICStyleGOT()) {<br>
// ELF / PIC requires GOT in the EBX register before function calls via PLT<br>
// GOT pointer.<br>
if (!isTailCall) {<br>
@@ -3313,7 +3313,7 @@ X86TargetLowering::LowerCall(TargetLower<br>
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7<br>
};<br>
unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);<br>
- assert((Subtarget->hasSSE1() || !NumXMMRegs)<br>
+ assert((Subtarget.hasSSE1() || !NumXMMRegs)<br>
&& "SSE registers cannot be used when SSE is disabled");<br>
<br>
RegsToPass.push_back(std::make_pair(unsigned(X86::AL),<br>
@@ -3423,19 +3423,19 @@ X86TargetLowering::LowerCall(TargetLower<br>
// external symbols most go through the PLT in PIC mode. If the symbol<br>
// has hidden or protected visibility, or if it is static or local, then<br>
// we don't need to use the PLT - we can directly call it.<br>
- if (Subtarget->isTargetELF() &&<br>
+ if (Subtarget.isTargetELF() &&<br>
DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&<br>
GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {<br>
OpFlags = X86II::MO_PLT;<br>
- } else if (Subtarget->isPICStyleStubAny() &&<br>
+ } else if (Subtarget.isPICStyleStubAny() &&<br>
!GV->isStrongDefinitionForLinker() &&<br>
- (!Subtarget->getTargetTriple().isMacOSX() ||<br>
- Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {<br>
+ (!Subtarget.getTargetTriple().isMacOSX() ||<br>
+ Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {<br>
// PC-relative references to external symbols should go through $stub,<br>
// unless we're building with the leopard linker or later, which<br>
// automatically synthesizes these stubs.<br>
OpFlags = X86II::MO_DARWIN_STUB;<br>
- } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&<br>
+ } else if (Subtarget.isPICStyleRIPRel() && isa<Function>(GV) &&<br>
cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {<br>
// If the function is marked as non-lazy, generate an indirect call<br>
// which loads from the GOT directly. This avoids runtime overhead<br>
@@ -3464,12 +3464,12 @@ X86TargetLowering::LowerCall(TargetLower<br>
<br>
// On ELF targets, in either X86-64 or X86-32 mode, direct calls to<br>
// external symbols should go through the PLT.<br>
- if (Subtarget->isTargetELF() &&<br>
+ if (Subtarget.isTargetELF() &&<br>
DAG.getTarget().getRelocationModel() == Reloc::PIC_) {<br>
OpFlags = X86II::MO_PLT;<br>
- } else if (Subtarget->isPICStyleStubAny() &&<br>
- (!Subtarget->getTargetTriple().isMacOSX() ||<br>
- Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {<br>
+ } else if (Subtarget.isPICStyleStubAny() &&<br>
+ (!Subtarget.getTargetTriple().isMacOSX() ||<br>
+ Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {<br>
// PC-relative references to external symbols should go through $stub,<br>
// unless we're building with the leopard linker or later, which<br>
// automatically synthesizes these stubs.<br>
@@ -3478,7 +3478,7 @@ X86TargetLowering::LowerCall(TargetLower<br>
<br>
Callee = DAG.getTargetExternalSymbol(<br>
S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);<br>
- } else if (Subtarget->isTarget64BitILP32() &&<br>
+ } else if (Subtarget.isTarget64BitILP32() &&<br>
Callee->getValueType(0) == MVT::i32) {<br>
// Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI<br>
Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);<br>
@@ -3551,7 +3551,7 @@ X86TargetLowering::LowerCall(TargetLower<br>
DAG.getTarget().Options.GuaranteedTailCallOpt))<br>
NumBytesForCalleeToPop = NumBytes; // Callee pops everything<br>
else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&<br>
- !Subtarget->getTargetTriple().isOSMSVCRT() &&<br>
+ !Subtarget.getTargetTriple().isOSMSVCRT() &&<br>
SR == StackStructReturn)<br>
// If this is a call to a struct-return function, the callee<br>
// pops the hidden struct pointer, so we have to push it back.<br>
@@ -3613,8 +3613,8 @@ X86TargetLowering::LowerCall(TargetLower<br>
unsigned<br>
X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,<br>
SelectionDAG& DAG) const {<br>
- const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();<br>
- const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();<br>
+ const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();<br>
+ const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();<br>
unsigned StackAlignment = TFI.getStackAlignment();<br>
uint64_t AlignMask = StackAlignment - 1;<br>
int64_t Offset = StackSize;<br>
@@ -3707,8 +3707,8 @@ bool X86TargetLowering::IsEligibleForTai<br>
<br>
CallingConv::ID CallerCC = CallerF->getCallingConv();<br>
bool CCMatch = CallerCC == CalleeCC;<br>
- bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);<br>
- bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);<br>
+ bool IsCalleeWin64 = Subtarget.isCallingConvWin64(CalleeCC);<br>
+ bool IsCallerWin64 = Subtarget.isCallingConvWin64(CallerCC);<br>
<br>
// Win64 functions have extra shadow space for argument homing. Don't do the<br>
// sibcall if the caller and callee have mismatched expectations for this<br>
@@ -3727,7 +3727,7 @@ bool X86TargetLowering::IsEligibleForTai<br>
<br>
// Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to<br>
// emit a special epilogue.<br>
- const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();<br>
+ const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();<br>
if (RegInfo->needsStackRealignment(MF))<br>
return false;<br>
<br>
@@ -3829,7 +3829,7 @@ bool X86TargetLowering::IsEligibleForTai<br>
// the caller's fixed stack objects.<br>
MachineFrameInfo *MFI = MF.getFrameInfo();<br>
const MachineRegisterInfo *MRI = &MF.getRegInfo();<br>
- const X86InstrInfo *TII = Subtarget->getInstrInfo();<br>
+ const X86InstrInfo *TII = Subtarget.getInstrInfo();<br>
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {<br>
CCValAssign &VA = ArgLocs[i];<br>
SDValue Arg = OutVals[i];<br>
@@ -3849,7 +3849,7 @@ bool X86TargetLowering::IsEligibleForTai<br>
// only target EAX, EDX, or ECX since the tail call must be scheduled after<br>
// callee-saved registers are restored. These happen to be the same<br>
// registers used to pass 'inreg' arguments so watch out for those.<br>
- if (!Subtarget->is64Bit() &&<br>
+ if (!Subtarget.is64Bit() &&<br>
((!isa<GlobalAddressSDNode>(Callee) &&<br>
!isa<ExternalSymbolSDNode>(Callee)) ||<br>
DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {<br>
@@ -3876,7 +3876,7 @@ bool X86TargetLowering::IsEligibleForTai<br>
}<br>
<br>
bool CalleeWillPop =<br>
- X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,<br>
+ X86::isCalleePop(CalleeCC, Subtarget.is64Bit(), isVarArg,<br>
MF.getTarget().Options.GuaranteedTailCallOpt);<br>
<br>
if (unsigned BytesToPop =<br>
@@ -3978,7 +3978,7 @@ static SDValue getTargetShuffleNode(unsi<br>
<br>
SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {<br>
MachineFunction &MF = DAG.getMachineFunction();<br>
- const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();<br>
+ const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();<br>
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();<br>
int ReturnAddrIndex = FuncInfo->getRAIndex();<br>
<br>
@@ -4289,12 +4289,12 @@ bool X86TargetLowering::isExtractSubvect<br>
<br>
bool X86TargetLowering::isCheapToSpeculateCttz() const {<br>
// Speculate cttz only if we can directly use TZCNT.<br>
- return Subtarget->hasBMI();<br>
+ return Subtarget.hasBMI();<br>
}<br>
<br>
bool X86TargetLowering::isCheapToSpeculateCtlz() const {<br>
// Speculate ctlz only if we can directly use LZCNT.<br>
- return Subtarget->hasLZCNT();<br>
+ return Subtarget.hasLZCNT();<br>
}<br>
<br>
/// Return true if every element in Mask, beginning<br>
@@ -4474,7 +4474,7 @@ static SDValue getConstVector(ArrayRef<i<br>
}<br>
<br>
/// Returns a vector of specified type with all zero elements.<br>
-static SDValue getZeroVector(MVT VT, const X86Subtarget *Subtarget,<br>
+static SDValue getZeroVector(MVT VT, const X86Subtarget &Subtarget,<br>
SelectionDAG &DAG, SDLoc dl) {<br>
assert(VT.isVector() && "Expected a vector type");<br>
<br>
@@ -4482,7 +4482,7 @@ static SDValue getZeroVector(MVT VT, con<br>
// to their dest type. This ensures they get CSE'd.<br>
SDValue Vec;<br>
if (VT.is128BitVector()) { // SSE<br>
- if (Subtarget->hasSSE2()) { // SSE2<br>
+ if (Subtarget.hasSSE2()) { // SSE2<br>
SDValue Cst = DAG.getConstant(0, dl, MVT::i32);<br>
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);<br>
} else { // SSE1<br>
@@ -4490,7 +4490,7 @@ static SDValue getZeroVector(MVT VT, con<br>
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);<br>
}<br>
} else if (VT.is256BitVector()) { // AVX<br>
- if (Subtarget->hasInt256()) { // AVX2<br>
+ if (Subtarget.hasInt256()) { // AVX2<br>
SDValue Cst = DAG.getConstant(0, dl, MVT::i32);<br>
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };<br>
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);<br>
@@ -4508,9 +4508,9 @@ static SDValue getZeroVector(MVT VT, con<br>
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);<br>
} else if (VT.getVectorElementType() == MVT::i1) {<br>
<br>
- assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)<br>
+ assert((Subtarget.hasBWI() || VT.getVectorNumElements() <= 16)<br>
&& "Unexpected vector type");<br>
- assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)<br>
+ assert((Subtarget.hasVLX() || VT.getVectorNumElements() >= 8)<br>
&& "Unexpected vector type");<br>
SDValue Cst = DAG.getConstant(0, dl, MVT::i1);<br>
SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);<br>
@@ -4756,7 +4756,7 @@ static SDValue Concat256BitVectors(SDVal<br>
/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with<br>
/// no AVX2 support, use two <4 x i32> inserted in a <8 x i32> appropriately.<br>
/// Then bitcast to their original type, ensuring they get CSE'd.<br>
-static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,<br>
+static SDValue getOnesVector(EVT VT, const X86Subtarget &Subtarget,<br>
SelectionDAG &DAG, SDLoc dl) {<br>
assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&<br>
"Expected a 128/256/512-bit vector type");<br>
@@ -4764,7 +4764,7 @@ static SDValue getOnesVector(EVT VT, con<br>
APInt Ones = APInt::getAllOnesValue(32);<br>
unsigned NumElts = VT.getSizeInBits() / 32;<br>
SDValue Vec;<br>
- if (!Subtarget->hasInt256() && NumElts == 8) {<br>
+ if (!Subtarget.hasInt256() && NumElts == 8) {<br>
Vec = DAG.getConstant(Ones, dl, MVT::v4i32);<br>
Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);<br>
} else {<br>
@@ -4803,7 +4803,7 @@ static SDValue getUnpackh(SelectionDAG &<br>
/// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).<br>
static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,<br>
bool IsZero,<br>
- const X86Subtarget *Subtarget,<br>
+ const X86Subtarget &Subtarget,<br>
SelectionDAG &DAG) {<br>
MVT VT = V2.getSimpleValueType();<br>
SDValue V1 = IsZero<br>
@@ -5180,7 +5180,7 @@ static SDValue getShuffleScalarElt(SDNod<br>
static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,<br>
unsigned NumNonZero, unsigned NumZero,<br>
SelectionDAG &DAG,<br>
- const X86Subtarget* Subtarget,<br>
+ const X86Subtarget &Subtarget,<br>
const TargetLowering &TLI) {<br>
if (NumNonZero > 8)<br>
return SDValue();<br>
@@ -5190,7 +5190,7 @@ static SDValue LowerBuildVectorv16i8(SDV<br>
bool First = true;<br>
<br>
// SSE4.1 - use PINSRB to insert each byte directly.<br>
- if (Subtarget->hasSSE41()) {<br>
+ if (Subtarget.hasSSE41()) {<br>
for (unsigned i = 0; i < 16; ++i) {<br>
bool isNonZero = (NonZeros & (1 << i)) != 0;<br>
if (isNonZero) {<br>
@@ -5250,7 +5250,7 @@ static SDValue LowerBuildVectorv16i8(SDV<br>
static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,<br>
unsigned NumNonZero, unsigned NumZero,<br>
SelectionDAG &DAG,<br>
- const X86Subtarget* Subtarget,<br>
+ const X86Subtarget &Subtarget,<br>
const TargetLowering &TLI) {<br>
if (NumNonZero > 4)<br>
return SDValue();<br>
@@ -5279,7 +5279,7 @@ static SDValue LowerBuildVectorv8i16(SDV<br>
<br>
/// Custom lower build_vector of v4i32 or v4f32.<br>
static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,<br>
- const X86Subtarget *Subtarget,<br>
+ const X86Subtarget &Subtarget,<br>
const TargetLowering &TLI) {<br>
// Find all zeroable elements.<br>
std::bitset<4> Zeroable;<br>
@@ -5343,7 +5343,7 @@ static SDValue LowerBuildVectorv4x32(SDV<br>
}<br>
<br>
// See if we can lower this build_vector to a INSERTPS.<br>
- if (!Subtarget->hasSSE41())<br>
+ if (!Subtarget.hasSSE41())<br>
return SDValue();<br>
<br>
SDValue V2 = Elt.getOperand(0);<br>
@@ -5624,12 +5624,12 @@ static SDValue EltsFromConsecutiveLoads(<br>
/// a scalar load, or a constant.<br>
/// The VBROADCAST node is returned when a pattern is found,<br>
/// or SDValue() otherwise.<br>
-static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,<br>
+static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget &Subtarget,<br>
SelectionDAG &DAG) {<br>
// VBROADCAST requires AVX.<br>
// TODO: Splats could be generated for non-AVX CPUs using SSE<br>
// instructions, but there's less potential gain for only 128-bit vectors.<br>
- if (!Subtarget->hasAVX())<br>
+ if (!Subtarget.hasAVX())<br>
return SDValue();<br>
<br>
MVT VT = Op.getSimpleValueType();<br>
@@ -5679,7 +5679,7 @@ static SDValue LowerVectorBroadcast(SDVa<br>
if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&<br>
Sc.getOpcode() != ISD::BUILD_VECTOR) {<br>
<br>
- if (!Subtarget->hasInt256())<br>
+ if (!Subtarget.hasInt256())<br>
return SDValue();<br>
<br>
// Use the register form of the broadcast instruction available on AVX2.<br>
@@ -5697,7 +5697,7 @@ static SDValue LowerVectorBroadcast(SDVa<br>
// Constants may have multiple users.<br>
<br>
// AVX-512 has register version of the broadcast<br>
- bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&<br>
+ bool hasRegVer = Subtarget.hasAVX512() && VT.is512BitVector() &&<br>
Ld.getValueType().getSizeInBits() >= 32;<br>
if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&<br>
!hasRegVer))<br>
@@ -5722,7 +5722,7 @@ static SDValue LowerVectorBroadcast(SDVa<br>
// from the constant pool and not to broadcast it from a scalar.<br>
// But override that restriction when optimizing for size.<br>
// TODO: Check if splatting is recommended for other AVX-capable CPUs.<br>
- if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {<br>
+ if (ConstSplatVal && (Subtarget.hasAVX2() || OptForSize)) {<br>
EVT CVT = Ld.getValueType();<br>
assert(!CVT.isVector() && "Must not broadcast a vector type");<br>
<br>
@@ -5731,7 +5731,7 @@ static SDValue LowerVectorBroadcast(SDVa<br>
// with AVX2, also splat i8 and i16.<br>
// With pattern matching, the VBROADCAST node may become a VMOVDDUP.<br>
if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||<br>
- (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {<br>
+ (OptForSize && (ScalarSize == 64 || Subtarget.hasAVX2()))) {<br>
const Constant *C = nullptr;<br>
if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))<br>
C = CI->getConstantIntValue();<br>
@@ -5756,7 +5756,7 @@ static SDValue LowerVectorBroadcast(SDVa<br>
bool IsLoad = ISD::isNormalLoad(Ld.getNode());<br>
<br>
// Handle AVX2 in-regist</blockquote></div>
</blockquote></div><br></div>