<div dir="ltr">The message I actually wrote for this commit went something like this:<div><br></div><div><div> Revert "[ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/Mainline"</div><div><br></div><div> This patch broke test/MC/ARM/simple-fp-encoding.s on Windows:</div><div> <a href="http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/5744">http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/5744</a></div><div><br></div><div> The following revisions depended on it and had to be reverted:</div><div> [ARM] Add new system registers to ARMv8-M Baseline/Mainline</div><div> [ARM] Add DSP build attribute and extension targeting</div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jan 15, 2016 at 10:31 AM, Reid Kleckner via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rnk<br>
Date: Fri Jan 15 12:31:29 2016<br>
New Revision: 257916<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=257916&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=257916&view=rev</a><br>
Log:<br>
# This is a combination of 2 commits.<br>
# The first commit's message is:<br>
<br>
Revert "[ARM] Add DSP build attribute and extension targeting"<br>
<br>
This reverts commit b11cc50c0b4a7c8cdb628abc50b7dc226ff583dc.<br>
<br>
# This is the 2nd commit message:<br>
<br>
Revert "[ARM] Add new system registers to ARMv8-M Baseline/Mainline"<br>
<br>
This reverts commit 837d08454e3e5beb8581951ac26b22fa07df3cd5.<br>
<br>
Removed:<br>
llvm/trunk/test/CodeGen/ARM/special-reg-v8m-base.ll<br>
llvm/trunk/test/CodeGen/ARM/special-reg-v8m-main.ll<br>
llvm/trunk/test/MC/Disassembler/ARM/thumb2-v8m.txt<br>
Modified:<br>
llvm/trunk/include/llvm/Support/ARMBuildAttributes.h<br>
llvm/trunk/include/llvm/Support/ARMTargetParser.def<br>
llvm/trunk/lib/Support/ARMBuildAttrs.cpp<br>
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp<br>
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br>
llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp<br>
llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s<br>
llvm/trunk/test/CodeGen/ARM/build-attributes.ll<br>
llvm/trunk/test/MC/ARM/directive-eabi_attribute.s<br>
llvm/trunk/test/MC/ARM/thumbv8m.s<br>
llvm/trunk/test/tools/llvm-readobj/ARM/attribute-0.s<br>
llvm/trunk/test/tools/llvm-readobj/ARM/attribute-1.s<br>
llvm/trunk/tools/llvm-readobj/ARMAttributeParser.cpp<br>
llvm/trunk/tools/llvm-readobj/ARMAttributeParser.h<br>
<br>
Modified: llvm/trunk/include/llvm/Support/ARMBuildAttributes.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMBuildAttributes.h?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMBuildAttributes.h?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Support/ARMBuildAttributes.h (original)<br>
+++ llvm/trunk/include/llvm/Support/ARMBuildAttributes.h Fri Jan 15 12:31:29 2016<br>
@@ -67,7 +67,6 @@ enum AttrType {<br>
ABI_FP_16bit_format = 38,<br>
MPextension_use = 42, // recoded from 70 (ABI r2.08)<br>
DIV_use = 44,<br>
- DSP_extension = 46,<br>
also_compatible_with = 65,<br>
conformance = 67,<br>
Virtualization_use = 68,<br>
<br>
Modified: llvm/trunk/include/llvm/Support/ARMTargetParser.def<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMTargetParser.def?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMTargetParser.def?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Support/ARMTargetParser.def (original)<br>
+++ llvm/trunk/include/llvm/Support/ARMTargetParser.def Fri Jan 15 12:31:29 2016<br>
@@ -116,7 +116,6 @@ ARM_ARCH_EXT_NAME("invalid", AEK_INVALI<br>
ARM_ARCH_EXT_NAME("none", AEK_NONE, nullptr, nullptr)<br>
ARM_ARCH_EXT_NAME("crc", AEK_CRC, "+crc", "-crc")<br>
ARM_ARCH_EXT_NAME("crypto", AEK_CRYPTO, "+crypto","-crypto")<br>
-ARM_ARCH_EXT_NAME("dsp", AEK_DSP, "+dsp", "-dsp")<br>
ARM_ARCH_EXT_NAME("fp", AEK_FP, nullptr, nullptr)<br>
ARM_ARCH_EXT_NAME("idiv", (AEK_HWDIVARM | AEK_HWDIV), nullptr, nullptr)<br>
ARM_ARCH_EXT_NAME("mp", AEK_MP, nullptr, nullptr)<br>
<br>
Modified: llvm/trunk/lib/Support/ARMBuildAttrs.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/ARMBuildAttrs.cpp?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/ARMBuildAttrs.cpp?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Support/ARMBuildAttrs.cpp (original)<br>
+++ llvm/trunk/lib/Support/ARMBuildAttrs.cpp Fri Jan 15 12:31:29 2016<br>
@@ -54,7 +54,6 @@ const struct {<br>
{ ARMBuildAttrs::ABI_FP_16bit_format, "Tag_ABI_FP_16bit_format" },<br>
{ ARMBuildAttrs::MPextension_use, "Tag_MPextension_use" },<br>
{ ARMBuildAttrs::DIV_use, "Tag_DIV_use" },<br>
- { ARMBuildAttrs::DSP_extension, "Tag_DSP_extension" },<br>
{ ARMBuildAttrs::nodefaults, "Tag_nodefaults" },<br>
{ ARMBuildAttrs::also_compatible_with, "Tag_also_compatible_with" },<br>
{ ARMBuildAttrs::T2EE_use, "Tag_T2EE_use" },<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Jan 15 12:31:29 2016<br>
@@ -807,9 +807,6 @@ void ARMAsmPrinter::emitAttributes() {<br>
if (STI.hasDivideInARMMode() && !STI.hasV8Ops())<br>
ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);<br>
<br>
- if (STI.hasDSP() && isV8M(&STI))<br>
- ATS.emitAttribute(ARMBuildAttrs::DSP_extension, ARMBuildAttrs::Allowed);<br>
-<br>
if (MMI) {<br>
if (const Module *SourceModule = MMI->getModule()) {<br>
// ABI_PCS_wchar_t to indicate wchar_t width<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Jan 15 12:31:29 2016<br>
@@ -3444,9 +3444,6 @@ static inline int getMClassRegisterSYSmV<br>
.Case("basepri_max", 0x12)<br>
.Case("faultmask", 0x13)<br>
.Case("control", 0x14)<br>
- .Case("msplim", 0x0a)<br>
- .Case("psplim", 0x0b)<br>
- .Case("sp", 0x18)<br>
.Default(-1);<br>
}<br>
<br>
@@ -3476,27 +3473,11 @@ static int getMClassRegisterMask(StringR<br>
if (!Subtarget->hasV7Ops() && SYSmvalue >= 0x11 && SYSmvalue <= 0x13)<br>
return -1;<br>
<br>
- if (Subtarget->has8MSecExt() && Flags.lower() == "ns") {<br>
- Flags = "";<br>
- SYSmvalue |= 0x80;<br>
- }<br>
-<br>
- if (!Subtarget->has8MSecExt() &&<br>
- (SYSmvalue == 0xa || SYSmvalue == 0xb || SYSmvalue > 0x14))<br>
- return -1;<br>
-<br>
- if (!Subtarget->hasV8MMainlineOps() &&<br>
- (SYSmvalue == 0x8a || SYSmvalue == 0x8b || SYSmvalue == 0x91 ||<br>
- SYSmvalue == 0x93))<br>
- return -1;<br>
-<br>
// If it was a read then we won't be expecting flags and so at this point<br>
// we can return the mask.<br>
if (IsRead) {<br>
- if (Flags.empty())<br>
- return SYSmvalue;<br>
- else<br>
- return -1;<br>
+ assert (Flags.empty() && "Unexpected flags for reading M class register.");<br>
+ return SYSmvalue;<br>
}<br>
<br>
// We know we are now handling a write so need to get the mask for the flags.<br>
@@ -3655,13 +3636,7 @@ SDNode *ARMDAGToDAGISel::SelectReadRegis<br>
// is an acceptable value, so check that a mask can be constructed from the<br>
// string.<br>
if (Subtarget->isMClass()) {<br>
- StringRef Flags = "", Reg = SpecialReg;<br>
- if (Reg.endswith("_ns")) {<br>
- Flags = "ns";<br>
- Reg = Reg.drop_back(3);<br>
- }<br>
-<br>
- int SYSmValue = getMClassRegisterMask(Reg, Flags, true, Subtarget);<br>
+ int SYSmValue = getMClassRegisterMask(SpecialReg, "", true, Subtarget);<br>
if (SYSmValue == -1)<br>
return nullptr;<br>
<br>
@@ -3755,10 +3730,10 @@ SDNode *ARMDAGToDAGISel::SelectWriteRegi<br>
return CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);<br>
}<br>
<br>
- std::pair<StringRef, StringRef> Fields;<br>
- Fields = StringRef(SpecialReg).rsplit('_');<br>
- std::string Reg = Fields.first.str();<br>
- StringRef Flags = Fields.second;<br>
+ SmallVector<StringRef, 5> Fields;<br>
+ StringRef(SpecialReg).split(Fields, '_', 1, false);<br>
+ std::string Reg = Fields[0].str();<br>
+ StringRef Flags = Fields.size() == 2 ? Fields[1] : "";<br>
<br>
// If the target was M Class then need to validate the special register value<br>
// and retrieve the mask for use in the instruction node.<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Jan 15 12:31:29 2016<br>
@@ -272,12 +272,6 @@ class ARMAsmParser : public MCTargetAsmP<br>
bool hasV8MBaseline() const {<br>
return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];<br>
}<br>
- bool hasV8MMainline() const {<br>
- return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];<br>
- }<br>
- bool has8MSecExt() const {<br>
- return getSTI().getFeatureBits()[ARM::Feature8MSecExt];<br>
- }<br>
bool hasARM() const {<br>
return !getSTI().getFeatureBits()[ARM::FeatureNoARM];<br>
}<br>
@@ -3978,18 +3972,6 @@ ARMAsmParser::parseMSRMaskOperand(Operan<br>
.Case("basepri_max", 0x812)<br>
.Case("faultmask", 0x813)<br>
.Case("control", 0x814)<br>
- .Case("msplim", 0x80a)<br>
- .Case("psplim", 0x80b)<br>
- .Case("msp_ns", 0x888)<br>
- .Case("psp_ns", 0x889)<br>
- .Case("msplim_ns", 0x88a)<br>
- .Case("psplim_ns", 0x88b)<br>
- .Case("primask_ns", 0x890)<br>
- .Case("basepri_ns", 0x891)<br>
- .Case("basepri_max_ns", 0x892)<br>
- .Case("faultmask_ns", 0x893)<br>
- .Case("control_ns", 0x894)<br>
- .Case("sp_ns", 0x898)<br>
.Default(~0U);<br>
<br>
if (FlagsVal == ~0U)<br>
@@ -4004,14 +3986,6 @@ ARMAsmParser::parseMSRMaskOperand(Operan<br>
// basepri, basepri_max and faultmask only valid for V7m.<br>
return MatchOperand_NoMatch;<br>
<br>
- if (!has8MSecExt() && (FlagsVal == 0x80a || FlagsVal == 0x80b ||<br>
- (FlagsVal > 0x814 && FlagsVal < 0xc00)))<br>
- return MatchOperand_NoMatch;<br>
-<br>
- if (!hasV8MMainline() && (FlagsVal == 0x88a || FlagsVal == 0x88b ||<br>
- (FlagsVal > 0x890 && FlagsVal <= 0x893)))<br>
- return MatchOperand_NoMatch;<br>
-<br>
Parser.Lex(); // Eat identifier token.<br>
Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));<br>
return MatchOperand_Success;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Jan 15 12:31:29 2016<br>
@@ -4096,24 +4096,6 @@ static DecodeStatus DecodeMSRMask(MCInst<br>
// Values basepri, basepri_max and faultmask are only valid for v7m.<br>
return MCDisassembler::Fail;<br>
break;<br>
- case 0x8a: // msplim_ns<br>
- case 0x8b: // psplim_ns<br>
- case 0x91: // basepri_ns<br>
- case 0x92: // basepri_max_ns<br>
- case 0x93: // faultmask_ns<br>
- if (!(FeatureBits[ARM::HasV8MMainlineOps]))<br>
- return MCDisassembler::Fail;<br>
- // fall through<br>
- case 10: // msplim<br>
- case 11: // psplim<br>
- case 0x88: // msp_ns<br>
- case 0x89: // psp_ns<br>
- case 0x90: // primask_ns<br>
- case 0x94: // control_ns<br>
- case 0x98: // sp_ns<br>
- if (!(FeatureBits[ARM::Feature8MSecExt]))<br>
- return MCDisassembler::Fail;<br>
- break;<br>
default:<br>
return MCDisassembler::Fail;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Fri Jan 15 12:31:29 2016<br>
@@ -901,42 +901,6 @@ void ARMInstPrinter::printMSRMaskOperand<br>
case 20:<br>
O << "control";<br>
return;<br>
- case 10:<br>
- O << "msplim";<br>
- return;<br>
- case 11:<br>
- O << "psplim";<br>
- return;<br>
- case 0x88:<br>
- O << "msp_ns";<br>
- return;<br>
- case 0x89:<br>
- O << "psp_ns";<br>
- return;<br>
- case 0x8a:<br>
- O << "msplim_ns";<br>
- return;<br>
- case 0x8b:<br>
- O << "psplim_ns";<br>
- return;<br>
- case 0x90:<br>
- O << "primask_ns";<br>
- return;<br>
- case 0x91:<br>
- O << "basepri_ns";<br>
- return;<br>
- case 0x92:<br>
- O << "basepri_max_ns";<br>
- return;<br>
- case 0x93:<br>
- O << "faultmask_ns";<br>
- return;<br>
- case 0x94:<br>
- O << "control_ns";<br>
- return;<br>
- case 0x98:<br>
- O << "sp_ns";<br>
- return;<br>
}<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s Fri Jan 15 12:31:29 2016<br>
@@ -54,9 +54,6 @@<br>
// Tag_DIV_use (=44)<br>
.eabi_attribute 44, 2<br>
<br>
-// Tag_DSP_extension (=46)<br>
-.eabi_attribute 46, 1<br>
-<br>
// Tag_Virtualization_use (=68)<br>
.eabi_attribute 68, 3<br>
<br>
@@ -74,15 +71,15 @@<br>
// CHECK-NEXT: ]<br>
// CHECK-NEXT: Address: 0x0<br>
// CHECK-NEXT: Offset: 0x34<br>
-// CHECK-NEXT: Size: 73<br>
+// CHECK-NEXT: Size: 71<br>
// CHECK-NEXT: Link: 0<br>
// CHECK-NEXT: Info: 0<br>
// CHECK-NEXT: AddressAlignment: 1<br>
// CHECK-NEXT: EntrySize: 0<br>
// CHECK-NEXT: SectionData (<br>
-// CHECK-NEXT: 0000: 41480000 00616561 62690001 3E000000<br>
+// CHECK-NEXT: 0000: 41460000 00616561 62690001 3C000000<br>
// CHECK-NEXT: 0010: 05636F72 7465782D 61380006 0A074108<br>
// CHECK-NEXT: 0020: 0109020A 030C0214 01150117 01180119<br>
-// CHECK-NEXT: 0030: 011B001C 0124012A 012C022E 0144036E<br>
-// CHECK-NEXT: 0040: A0018101 3100FA01 01<br>
+// CHECK-NEXT: 0030: 011B001C 0124012A 012C0244 036EA001<br>
+// CHECK-NEXT: 0040: 81013100 FA0101<br>
// CHECK-NEXT: )<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/build-attributes.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes.ll?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes.ll?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/build-attributes.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/build-attributes.ll Fri Jan 15 12:31:29 2016<br>
@@ -29,7 +29,6 @@<br>
; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO<br>
; RUN: llc < %s -mtriple=thumbv8m.base-linux-gnueabi | FileCheck %s --check-prefix=V8MBASELINE<br>
; RUN: llc < %s -mtriple=thumbv8m.main-linux-gnueabi | FileCheck %s --check-prefix=V8MMAINLINE<br>
-; RUN: llc < %s -mtriple=thumbv8m.main-linux-gnueabi -mattr=+dsp | FileCheck %s --check-prefix=V8MMAINLINE_DSP<br>
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT<br>
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT-FAST<br>
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING<br>
@@ -392,14 +391,6 @@<br>
; V8MMAINLINE: .eabi_attribute 7, 77<br>
; V8MMAINLINE: .eabi_attribute 8, 0<br>
; V8MMAINLINE: .eabi_attribute 9, 3<br>
-; V8MMAINLINE_DSP-NOT: .eabi_attribute 46<br>
-<br>
-; V8MMAINLINE_DSP: .syntax unified<br>
-; V8MBASELINE_DSP: .eabi_attribute 6, 17<br>
-; V8MBASELINE_DSP: .eabi_attribute 7, 77<br>
-; V8MMAINLINE_DSP: .eabi_attribute 8, 0<br>
-; V8MMAINLINE_DSP: .eabi_attribute 9, 3<br>
-; V8MMAINLINE_DSP: .eabi_attribute 46, 1<br>
<br>
; Tag_CPU_unaligned_access<br>
; NO-STRICT-ALIGN: .eabi_attribute 34, 1<br>
@@ -490,9 +481,6 @@<br>
; CORTEX-A7-NOFPU: .eabi_attribute 44, 2<br>
; CORTEX-A7-FPUV4: .eabi_attribute 44, 2<br>
<br>
-; Tag_DSP_extension<br>
-; CORTEX-A7-CHECK-NOT: .eabi_attribute 46<br>
-<br>
; Tag_Virtualization_use<br>
; CORTEX-A7-CHECK: .eabi_attribute 68, 3<br>
; CORTEX-A7-NOFPU: .eabi_attribute 68, 3<br>
<br>
Removed: llvm/trunk/test/CodeGen/ARM/special-reg-v8m-base.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/special-reg-v8m-base.ll?rev=257915&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/special-reg-v8m-base.ll?rev=257915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/special-reg-v8m-base.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/special-reg-v8m-base.ll (removed)<br>
@@ -1,142 +0,0 @@<br>
-; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=V7M<br>
-; RUN: llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s<br>
-<br>
-; V7M: LLVM ERROR: Invalid register name "sp_ns".<br>
-<br>
-define i32 @read_mclass_registers() nounwind {<br>
-entry:<br>
- ; CHECK-LABEL: read_mclass_registers:<br>
- ; CHECK: mrs r0, apsr<br>
- ; CHECK: mrs r1, iapsr<br>
- ; CHECK: mrs r1, eapsr<br>
- ; CHECK: mrs r1, xpsr<br>
- ; CHECK: mrs r1, ipsr<br>
- ; CHECK: mrs r1, epsr<br>
- ; CHECK: mrs r1, iepsr<br>
- ; CHECK: mrs r1, msp<br>
- ; CHECK: mrs r1, psp<br>
- ; CHECK: mrs r1, primask<br>
- ; CHECK: mrs r1, control<br>
- ; CHECK: mrs r1, msplim<br>
- ; CHECK: mrs r1, psplim<br>
- ; CHECK: mrs r1, msp_ns<br>
- ; CHECK: mrs r1, psp_ns<br>
- ; CHECK: mrs r1, primask_ns<br>
- ; CHECK: mrs r1, control_ns<br>
- ; CHECK: mrs r1, sp_ns<br>
-<br>
- %0 = call i32 @llvm.read_register.i32(metadata !0)<br>
- %1 = call i32 @llvm.read_register.i32(metadata !4)<br>
- %add1 = add i32 %1, %0<br>
- %2 = call i32 @llvm.read_register.i32(metadata !8)<br>
- %add2 = add i32 %add1, %2<br>
- %3 = call i32 @llvm.read_register.i32(metadata !12)<br>
- %add3 = add i32 %add2, %3<br>
- %4 = call i32 @llvm.read_register.i32(metadata !16)<br>
- %add4 = add i32 %add3, %4<br>
- %5 = call i32 @llvm.read_register.i32(metadata !17)<br>
- %add5 = add i32 %add4, %5<br>
- %6 = call i32 @llvm.read_register.i32(metadata !18)<br>
- %add6 = add i32 %add5, %6<br>
- %7 = call i32 @llvm.read_register.i32(metadata !19)<br>
- %add7 = add i32 %add6, %7<br>
- %8 = call i32 @llvm.read_register.i32(metadata !20)<br>
- %add8 = add i32 %add7, %8<br>
- %9 = call i32 @llvm.read_register.i32(metadata !21)<br>
- %add9 = add i32 %add8, %9<br>
- %10 = call i32 @llvm.read_register.i32(metadata !25)<br>
- %add10 = add i32 %add9, %10<br>
- %11 = call i32 @llvm.read_register.i32(metadata !26)<br>
- %add11 = add i32 %add10, %11<br>
- %12 = call i32 @llvm.read_register.i32(metadata !27)<br>
- %add12 = add i32 %add11, %12<br>
- %13 = call i32 @llvm.read_register.i32(metadata !28)<br>
- %add13 = add i32 %add12, %13<br>
- %14 = call i32 @llvm.read_register.i32(metadata !29)<br>
- %add14 = add i32 %add13, %14<br>
- %15 = call i32 @llvm.read_register.i32(metadata !32)<br>
- %add15 = add i32 %add14, %15<br>
- %16 = call i32 @llvm.read_register.i32(metadata !35)<br>
- %add16 = add i32 %add15, %16<br>
- %17 = call i32 @llvm.read_register.i32(metadata !36)<br>
- %add17 = add i32 %add16, %17<br>
- ret i32 %add10<br>
-}<br>
-<br>
-define void @write_mclass_registers(i32 %x) nounwind {<br>
-entry:<br>
- ; CHECK-LABEL: write_mclass_registers:<br>
- ; CHECK: msr apsr, r0<br>
- ; CHECK: msr apsr, r0<br>
- ; CHECK: msr iapsr, r0<br>
- ; CHECK: msr iapsr, r0<br>
- ; CHECK: msr eapsr, r0<br>
- ; CHECK: msr eapsr, r0<br>
- ; CHECK: msr xpsr, r0<br>
- ; CHECK: msr xpsr, r0<br>
- ; CHECK: msr ipsr, r0<br>
- ; CHECK: msr epsr, r0<br>
- ; CHECK: msr iepsr, r0<br>
- ; CHECK: msr msp, r0<br>
- ; CHECK: msr psp, r0<br>
- ; CHECK: msr primask, r0<br>
- ; CHECK: msr control, r0<br>
- ; CHECK: msr msplim, r0<br>
- ; CHECK: msr psplim, r0<br>
- ; CHECK: msr msp_ns, r0<br>
- ; CHECK: msr psp_ns, r0<br>
- ; CHECK: msr primask_ns, r0<br>
- ; CHECK: msr control_ns, r0<br>
- ; CHECK: msr sp_ns, r0<br>
-<br>
- call void @llvm.write_register.i32(metadata !0, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !1, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !4, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !5, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !8, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !9, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !12, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !13, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !16, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !17, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !18, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !19, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !20, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !21, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !25, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !26, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !27, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !28, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !29, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !32, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !35, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !36, i32 %x)<br>
- ret void<br>
-}<br>
-<br>
-declare i32 @llvm.read_register.i32(metadata) nounwind<br>
-declare void @llvm.write_register.i32(metadata, i32) nounwind<br>
-<br>
-!0 = !{!"apsr"}<br>
-!1 = !{!"apsr_nzcvq"}<br>
-!4 = !{!"iapsr"}<br>
-!5 = !{!"iapsr_nzcvq"}<br>
-!8 = !{!"eapsr"}<br>
-!9 = !{!"eapsr_nzcvq"}<br>
-!12 = !{!"xpsr"}<br>
-!13 = !{!"xpsr_nzcvq"}<br>
-!16 = !{!"ipsr"}<br>
-!17 = !{!"epsr"}<br>
-!18 = !{!"iepsr"}<br>
-!19 = !{!"msp"}<br>
-!20 = !{!"psp"}<br>
-!21 = !{!"primask"}<br>
-!25 = !{!"control"}<br>
-!26 = !{!"msplim"}<br>
-!27 = !{!"psplim"}<br>
-!28 = !{!"msp_ns"}<br>
-!29 = !{!"psp_ns"}<br>
-!32 = !{!"primask_ns"}<br>
-!35 = !{!"control_ns"}<br>
-!36 = !{!"sp_ns"}<br>
-<br>
<br>
Removed: llvm/trunk/test/CodeGen/ARM/special-reg-v8m-main.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/special-reg-v8m-main.ll?rev=257915&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/special-reg-v8m-main.ll?rev=257915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/special-reg-v8m-main.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/special-reg-v8m-main.ll (removed)<br>
@@ -1,214 +0,0 @@<br>
-; RUN: not llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s --check-prefix=BASELINE<br>
-; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -mattr=+dsp 2>&1 | FileCheck %s --check-prefix=MAINLINE<br>
-<br>
-; BASELINE: LLVM ERROR: Invalid register name "basepri_max_ns".<br>
-<br>
-define i32 @read_mclass_registers() nounwind {<br>
-entry:<br>
- ; MAINLINE-LABEL: read_mclass_registers:<br>
- ; MAINLINE: mrs r0, apsr<br>
- ; MAINLINE: mrs r1, iapsr<br>
- ; MAINLINE: mrs r1, eapsr<br>
- ; MAINLINE: mrs r1, xpsr<br>
- ; MAINLINE: mrs r1, ipsr<br>
- ; MAINLINE: mrs r1, epsr<br>
- ; MAINLINE: mrs r1, iepsr<br>
- ; MAINLINE: mrs r1, msp<br>
- ; MAINLINE: mrs r1, psp<br>
- ; MAINLINE: mrs r1, primask<br>
- ; MAINLINE: mrs r1, basepri<br>
- ; MAINLINE: mrs r1, basepri_max<br>
- ; MAINLINE: mrs r1, faultmask<br>
- ; MAINLINE: mrs r1, control<br>
- ; MAINLINE: mrs r1, msplim<br>
- ; MAINLINE: mrs r1, psplim<br>
- ; MAINLINE: mrs r1, msp_ns<br>
- ; MAINLINE: mrs r1, psp_ns<br>
- ; MAINLINE: mrs r1, msplim_ns<br>
- ; MAINLINE: mrs r1, psplim_ns<br>
- ; MAINLINE: mrs r1, primask_ns<br>
- ; MAINLINE: mrs r1, basepri_ns<br>
- ; MAINLINE: mrs r1, faultmask_ns<br>
- ; MAINLINE: mrs r1, control_ns<br>
- ; MAINLINE: mrs r1, sp_ns<br>
- ; MAINLINE: mrs r1, basepri_max_ns<br>
-<br>
- %0 = call i32 @llvm.read_register.i32(metadata !0)<br>
- %1 = call i32 @llvm.read_register.i32(metadata !4)<br>
- %add1 = add i32 %1, %0<br>
- %2 = call i32 @llvm.read_register.i32(metadata !8)<br>
- %add2 = add i32 %add1, %2<br>
- %3 = call i32 @llvm.read_register.i32(metadata !12)<br>
- %add3 = add i32 %add2, %3<br>
- %4 = call i32 @llvm.read_register.i32(metadata !16)<br>
- %add4 = add i32 %add3, %4<br>
- %5 = call i32 @llvm.read_register.i32(metadata !17)<br>
- %add5 = add i32 %add4, %5<br>
- %6 = call i32 @llvm.read_register.i32(metadata !18)<br>
- %add6 = add i32 %add5, %6<br>
- %7 = call i32 @llvm.read_register.i32(metadata !19)<br>
- %add7 = add i32 %add6, %7<br>
- %8 = call i32 @llvm.read_register.i32(metadata !20)<br>
- %add8 = add i32 %add7, %8<br>
- %9 = call i32 @llvm.read_register.i32(metadata !21)<br>
- %add9 = add i32 %add8, %9<br>
- %10 = call i32 @llvm.read_register.i32(metadata !22)<br>
- %add10 = add i32 %add9, %10<br>
- %11 = call i32 @llvm.read_register.i32(metadata !23)<br>
- %add11 = add i32 %add10, %11<br>
- %12 = call i32 @llvm.read_register.i32(metadata !24)<br>
- %add12 = add i32 %add11, %12<br>
- %13 = call i32 @llvm.read_register.i32(metadata !25)<br>
- %add13 = add i32 %add12, %13<br>
- %14 = call i32 @llvm.read_register.i32(metadata !26)<br>
- %add14 = add i32 %add13, %14<br>
- %15 = call i32 @llvm.read_register.i32(metadata !27)<br>
- %add15 = add i32 %add14, %15<br>
- %16 = call i32 @llvm.read_register.i32(metadata !28)<br>
- %add16 = add i32 %add15, %16<br>
- %17 = call i32 @llvm.read_register.i32(metadata !29)<br>
- %add17 = add i32 %add16, %17<br>
- %18 = call i32 @llvm.read_register.i32(metadata !30)<br>
- %add18 = add i32 %add17, %18<br>
- %19 = call i32 @llvm.read_register.i32(metadata !31)<br>
- %add19 = add i32 %add18, %19<br>
- %20 = call i32 @llvm.read_register.i32(metadata !32)<br>
- %add20 = add i32 %add19, %20<br>
- %21 = call i32 @llvm.read_register.i32(metadata !33)<br>
- %add21 = add i32 %add20, %21<br>
- %22 = call i32 @llvm.read_register.i32(metadata !34)<br>
- %add22 = add i32 %add21, %22<br>
- %23 = call i32 @llvm.read_register.i32(metadata !35)<br>
- %add23 = add i32 %add22, %23<br>
- %24 = call i32 @llvm.read_register.i32(metadata !36)<br>
- %add24 = add i32 %add23, %24<br>
- %25 = call i32 @llvm.read_register.i32(metadata !37)<br>
- %add25 = add i32 %add24, %25<br>
- ret i32 %add25<br>
-}<br>
-<br>
-define void @write_mclass_registers(i32 %x) nounwind {<br>
-entry:<br>
- ; MAINLINE-LABEL: write_mclass_registers:<br>
- ; MAINLINE: msr apsr_nzcvqg, r0<br>
- ; MAINLINE: msr apsr_nzcvq, r0<br>
- ; MAINLINE: msr apsr_g, r0<br>
- ; MAINLINE: msr apsr_nzcvqg, r0<br>
- ; MAINLINE: msr iapsr_nzcvqg, r0<br>
- ; MAINLINE: msr iapsr_nzcvq, r0<br>
- ; MAINLINE: msr iapsr_g, r0<br>
- ; MAINLINE: msr iapsr_nzcvqg, r0<br>
- ; MAINLINE: msr eapsr_nzcvqg, r0<br>
- ; MAINLINE: msr eapsr_nzcvq, r0<br>
- ; MAINLINE: msr eapsr_g, r0<br>
- ; MAINLINE: msr eapsr_nzcvqg, r0<br>
- ; MAINLINE: msr xpsr_nzcvqg, r0<br>
- ; MAINLINE: msr xpsr_nzcvq, r0<br>
- ; MAINLINE: msr xpsr_g, r0<br>
- ; MAINLINE: msr xpsr_nzcvqg, r0<br>
- ; MAINLINE: msr ipsr, r0<br>
- ; MAINLINE: msr epsr, r0<br>
- ; MAINLINE: msr iepsr, r0<br>
- ; MAINLINE: msr msp, r0<br>
- ; MAINLINE: msr psp, r0<br>
- ; MAINLINE: msr primask, r0<br>
- ; MAINLINE: msr basepri, r0<br>
- ; MAINLINE: msr basepri_max, r0<br>
- ; MAINLINE: msr faultmask, r0<br>
- ; MAINLINE: msr control, r0<br>
- ; MAINLINE: msr msplim, r0<br>
- ; MAINLINE: msr psplim, r0<br>
- ; MAINLINE: msr msp_ns, r0<br>
- ; MAINLINE: msr psp_ns, r0<br>
- ; MAINLINE: msr msplim_ns, r0<br>
- ; MAINLINE: msr psplim_ns, r0<br>
- ; MAINLINE: msr primask_ns, r0<br>
- ; MAINLINE: msr basepri_ns, r0<br>
- ; MAINLINE: msr faultmask_ns, r0<br>
- ; MAINLINE: msr control_ns, r0<br>
- ; MAINLINE: msr sp_ns, r0<br>
- ; MAINLINE: msr basepri_max_ns, r0<br>
-<br>
- call void @llvm.write_register.i32(metadata !0, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !1, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !2, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !3, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !4, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !5, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !6, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !7, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !8, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !9, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !10, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !11, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !12, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !13, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !14, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !15, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !16, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !17, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !18, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !19, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !20, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !21, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !22, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !23, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !24, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !25, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !26, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !27, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !28, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !29, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !30, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !31, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !32, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !33, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !34, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !35, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !36, i32 %x)<br>
- call void @llvm.write_register.i32(metadata !37, i32 %x)<br>
- ret void<br>
-}<br>
-<br>
-declare i32 @llvm.read_register.i32(metadata) nounwind<br>
-declare void @llvm.write_register.i32(metadata, i32) nounwind<br>
-<br>
-!0 = !{!"apsr"}<br>
-!1 = !{!"apsr_nzcvq"}<br>
-!2 = !{!"apsr_g"}<br>
-!3 = !{!"apsr_nzcvqg"}<br>
-!4 = !{!"iapsr"}<br>
-!5 = !{!"iapsr_nzcvq"}<br>
-!6 = !{!"iapsr_g"}<br>
-!7 = !{!"iapsr_nzcvqg"}<br>
-!8 = !{!"eapsr"}<br>
-!9 = !{!"eapsr_nzcvq"}<br>
-!10 = !{!"eapsr_g"}<br>
-!11 = !{!"eapsr_nzcvqg"}<br>
-!12 = !{!"xpsr"}<br>
-!13 = !{!"xpsr_nzcvq"}<br>
-!14 = !{!"xpsr_g"}<br>
-!15 = !{!"xpsr_nzcvqg"}<br>
-!16 = !{!"ipsr"}<br>
-!17 = !{!"epsr"}<br>
-!18 = !{!"iepsr"}<br>
-!19 = !{!"msp"}<br>
-!20 = !{!"psp"}<br>
-!21 = !{!"primask"}<br>
-!22 = !{!"basepri"}<br>
-!23 = !{!"basepri_max"}<br>
-!24 = !{!"faultmask"}<br>
-!25 = !{!"control"}<br>
-!26 = !{!"msplim"}<br>
-!27 = !{!"psplim"}<br>
-!28 = !{!"msp_ns"}<br>
-!29 = !{!"psp_ns"}<br>
-!30 = !{!"msplim_ns"}<br>
-!31 = !{!"psplim_ns"}<br>
-!32 = !{!"primask_ns"}<br>
-!33 = !{!"basepri_ns"}<br>
-!34 = !{!"faultmask_ns"}<br>
-!35 = !{!"control_ns"}<br>
-!36 = !{!"sp_ns"}<br>
-!37 = !{!"basepri_max_ns"}<br>
-<br>
<br>
Modified: llvm/trunk/test/MC/ARM/directive-eabi_attribute.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-eabi_attribute.s?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-eabi_attribute.s?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/ARM/directive-eabi_attribute.s (original)<br>
+++ llvm/trunk/test/MC/ARM/directive-eabi_attribute.s Fri Jan 15 12:31:29 2016<br>
@@ -209,12 +209,6 @@<br>
@ CHECK-OBJ-NEXT: Value: 0<br>
@ CHECK-OBJ-NEXT: TagName: DIV_use<br>
@ CHECK-OBJ-NEXT: Description: If Available<br>
- .eabi_attribute Tag_DSP_extension, 0<br>
-@ CHECK: .eabi_attribute 46, 0<br>
-@ CHECK-OBJ: Tag: 46<br>
-@ CHECK-OBJ-NEXT: Value: 0<br>
-@ CHECK-OBJ-NEXT: TagName: DSP_extension<br>
-@ CHECK-OBJ-NEXT: Description: Not Permitted<br>
.eabi_attribute Tag_nodefaults, 0<br>
@ CHECK: .eabi_attribute 64, 0<br>
@ CHECK-OBJ: Tag: 64<br>
<br>
Modified: llvm/trunk/test/MC/ARM/thumbv8m.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumbv8m.s?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumbv8m.s?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/ARM/thumbv8m.s (original)<br>
+++ llvm/trunk/test/MC/ARM/thumbv8m.s Fri Jan 15 12:31:29 2016<br>
@@ -4,30 +4,16 @@<br>
// RUN: not llvm-mc -triple=thumbv8m.main -show-encoding < %s 2>%t \<br>
// RUN: | FileCheck --check-prefix=CHECK-MAINLINE --check-prefix=CHECK %s<br>
// RUN: FileCheck --check-prefix=UNDEF-MAINLINE --check-prefix=UNDEF < %t %s<br>
-// RUN: not llvm-mc -triple=thumbv8m.main -mattr=+dsp,+t2xtpk -show-encoding < %s 2>%t \<br>
-// RUN: | FileCheck --check-prefix=CHECK-MAINLINE_DSP --check-prefix=CHECK %s<br>
-// RUN: FileCheck --check-prefix=UNDEF-MAINLINE_DSP --check-prefix=UNDEF < %t %s<br>
<br>
// Simple check that baseline is v6M and mainline is v7M<br>
// UNDEF-BASELINE: error: instruction requires: thumb2<br>
// UNDEF-MAINLINE-NOT: error: instruction requires:<br>
-// UNDEF-MAINLINE_DSP-NOT: error: instruction requires:<br>
mov.w r0, r0<br>
<br>
// Check that .arm is invalid<br>
// UNDEF: target does not support ARM mode<br>
.arm<br>
<br>
-// And only +dsp,+t2xtpk has DSP and t2xtpk instructions<br>
-// UNDEF-BASELINE: error: instruction requires: arm-mode<br>
-// UNDEF-MAINLINE: error: instruction requires: arm-mode<br>
-// UNDEF-MAINLINE_DSP-NOT: error: instruction requires:<br>
-qadd16 r0, r0, r0<br>
-// UNDEF-BASELINE: error: instruction requires: arm-mode<br>
-// UNDEF-MAINLINE: error: instruction requires: arm-mode<br>
-// UNDEF-MAINLINE_DSP-NOT: error: instruction requires:<br>
-uxtab16 r0, r1, r2<br>
-<br>
// Instruction availibility checks<br>
<br>
// 'Barrier instructions'<br>
@@ -171,50 +157,12 @@ ttat r0, r1<br>
<br>
// UNDEF-BASELINE: error: instruction requires: armv8m.main<br>
// CHECK-MAINLINE: vlldm r5 @ encoding: [0x35,0xec,0x00,0x0a]<br>
-// CHECK-MAINLINE_DSP: vlldm r5 @ encoding: [0x35,0xec,0x00,0x0a]<br>
vlldm r5<br>
<br>
// UNDEF-BASELINE: error: instruction requires: armv8m.main<br>
// CHECK-MAINLINE: vlstm r10 @ encoding: [0x2a,0xec,0x00,0x0a]<br>
-// CHECK-MAINLINE_DSP: vlstm r10 @ encoding: [0x2a,0xec,0x00,0x0a]<br>
vlstm r10<br>
<br>
-// New SYSm's<br>
-<br>
-MRS r1, MSP_NS<br>
-// CHECK: mrs r1, msp_ns @ encoding: [0xef,0xf3,0x88,0x81]<br>
-MSR PSP_NS, r2<br>
-// CHECK: msr psp_ns, r2 @ encoding: [0x82,0xf3,0x89,0x88]<br>
-MRS r3, PRIMASK_NS<br>
-// CHECK: mrs r3, primask_ns @ encoding: [0xef,0xf3,0x90,0x83]<br>
-MSR CONTROL_NS, r4<br>
-// CHECK: msr control_ns, r4 @ encoding: [0x84,0xf3,0x94,0x88]<br>
-MRS r5, SP_NS<br>
-// CHECK: mrs r5, sp_ns @ encoding: [0xef,0xf3,0x98,0x85]<br>
-MRS r6,MSPLIM<br>
-// CHECK: mrs r6, msplim @ encoding: [0xef,0xf3,0x0a,0x86]<br>
-MRS r7,PSPLIM<br>
-// CHECK: mrs r7, psplim @ encoding: [0xef,0xf3,0x0b,0x87]<br>
-MSR MSPLIM,r8<br>
-// CHECK: msr msplim, r8 @ encoding: [0x88,0xf3,0x0a,0x88]<br>
-MSR PSPLIM,r9<br>
-// CHECK: msr psplim, r9 @ encoding: [0x89,0xf3,0x0b,0x88]<br>
-<br>
-MRS r10, MSPLIM_NS<br>
-// CHECK-MAINLINE: mrs r10, msplim_ns @ encoding: [0xef,0xf3,0x8a,0x8a]<br>
-// UNDEF-BASELINE: error: invalid operand for instruction<br>
-MSR PSPLIM_NS, r11<br>
-// CHECK-MAINLINE: msr psplim_ns, r11 @ encoding: [0x8b,0xf3,0x8b,0x88]<br>
-// UNDEF-BASELINE: error: invalid operand for instruction<br>
-MRS r12, BASEPRI_NS<br>
-// CHECK-MAINLINE: mrs r12, basepri_ns @ encoding: [0xef,0xf3,0x91,0x8c]<br>
-// UNDEF-BASELINE: error: invalid operand for instruction<br>
-MRS r12, BASEPRI_MAX_NS<br>
-// CHECK-MAINLINE: mrs r12, basepri_max_ns @ encoding: [0xef,0xf3,0x92,0x8c]<br>
-// UNDEF-BASELINE: error: invalid operand for instruction<br>
-MSR FAULTMASK_NS, r14<br>
-// CHECK-MAINLINE: msr faultmask_ns, lr @ encoding: [0x8e,0xf3,0x93,0x88]<br>
-// UNDEF-BASELINE: error: invalid operand for instruction<br>
<br>
// Invalid operand tests<br>
// UNDEF: error: invalid operand for instruction<br>
<br>
Removed: llvm/trunk/test/MC/Disassembler/ARM/thumb2-v8m.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb2-v8m.txt?rev=257915&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb2-v8m.txt?rev=257915&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/ARM/thumb2-v8m.txt (original)<br>
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb2-v8m.txt (removed)<br>
@@ -1,25 +0,0 @@<br>
-# RUN: llvm-mc -triple=thumbv8m.base -disassemble < %s 2>%t | FileCheck %s<br>
-# RUN: FileCheck < %t %s --check-prefix=CHECK-STDERR<br>
-# RUN: llvm-mc -triple=thumbv8m.main -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MAINLINE<br>
-<br>
-0xef 0xf3 0x0a 0x83<br>
-# CHECK: mrs r3, msplim<br>
-0xef 0xf3 0x0b 0x84<br>
-# CHECK: mrs r4, psplim<br>
-0x8b 0xf3 0x0a 0x88<br>
-# CHECK: msr msplim, r11<br>
-0x8c 0xf3 0x0b 0x88<br>
-# CHECK: msr psplim, r12<br>
-<br>
-0xef 0xf3 0x90 0x86<br>
-# CHECK: mrs r6, primask_ns<br>
-0x88 0xf3 0x98 0x88<br>
-# CHECK: msr sp_ns, r8<br>
-<br>
-0xef 0xf3 0x8a 0x85<br>
-# CHECK-STDERR: warning: invalid instruction encoding<br>
-# CHECK-MAINLINE: mrs r5, msplim_ns<br>
-0x87 0xf3 0x93 0x88<br>
-# CHECK-STDERR: warning: invalid instruction encoding<br>
-# CHECK-MAINLINE: msr faultmask_ns, r7<br>
-<br>
<br>
Modified: llvm/trunk/test/tools/llvm-readobj/ARM/attribute-0.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-readobj/ARM/attribute-0.s?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-readobj/ARM/attribute-0.s?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/tools/llvm-readobj/ARM/attribute-0.s (original)<br>
+++ llvm/trunk/test/tools/llvm-readobj/ARM/attribute-0.s Fri Jan 15 12:31:29 2016<br>
@@ -225,13 +225,6 @@<br>
@CHECK-OBJ-NEXT: TagName: DIV_use<br>
@CHECK-OBJ-NEXT: Description: If Available<br>
<br>
-.eabi_attribute Tag_DSP_extension, 0<br>
-@CHECK: .eabi_attribute 46, 0<br>
-@CHECK-OBJ: Tag: 46<br>
-@CHECK-OBJ-NEXT: Value: 0<br>
-@CHECK-OBJ-NEXT: TagName: DSP_extension<br>
-@CHECK-OBJ-NEXT: Description: Not Permitted<br>
-<br>
.eabi_attribute Tag_Virtualization_use, 0<br>
@CHECK: .eabi_attribute 68, 0<br>
@CHECK-OBJ: Tag: 68<br>
<br>
Modified: llvm/trunk/test/tools/llvm-readobj/ARM/attribute-1.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-readobj/ARM/attribute-1.s?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-readobj/ARM/attribute-1.s?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/tools/llvm-readobj/ARM/attribute-1.s (original)<br>
+++ llvm/trunk/test/tools/llvm-readobj/ARM/attribute-1.s Fri Jan 15 12:31:29 2016<br>
@@ -211,13 +211,6 @@<br>
@CHECK-OBJ-NEXT: TagName: DIV_use<br>
@CHECK-OBJ-NEXT: Description: Not Permitted<br>
<br>
-.eabi_attribute Tag_DSP_extension, 1<br>
-@CHECK: .eabi_attribute 46, 1<br>
-@CHECK-OBJ: Tag: 46<br>
-@CHECK-OBJ-NEXT: Value: 1<br>
-@CHECK-OBJ-NEXT: TagName: DSP_extension<br>
-@CHECK-OBJ-NEXT: Description: Permitted<br>
-<br>
.eabi_attribute Tag_Virtualization_use, 1<br>
@CHECK: .eabi_attribute 68, 1<br>
@CHECK-OBJ: Tag: 68<br>
<br>
Modified: llvm/trunk/tools/llvm-readobj/ARMAttributeParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-readobj/ARMAttributeParser.cpp?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-readobj/ARMAttributeParser.cpp?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/llvm-readobj/ARMAttributeParser.cpp (original)<br>
+++ llvm/trunk/tools/llvm-readobj/ARMAttributeParser.cpp Fri Jan 15 12:31:29 2016<br>
@@ -63,7 +63,6 @@ ARMAttributeParser::DisplayRoutines[] =<br>
ATTRIBUTE_HANDLER(ABI_FP_16bit_format),<br>
ATTRIBUTE_HANDLER(MPextension_use),<br>
ATTRIBUTE_HANDLER(DIV_use),<br>
- ATTRIBUTE_HANDLER(DSP_extension),<br>
ATTRIBUTE_HANDLER(T2EE_use),<br>
ATTRIBUTE_HANDLER(Virtualization_use),<br>
ATTRIBUTE_HANDLER(nodefaults)<br>
@@ -514,16 +513,6 @@ void ARMAttributeParser::DIV_use(AttrTyp<br>
<br>
uint64_t Value = ParseInteger(Data, Offset);<br>
StringRef ValueDesc =<br>
- (Value < array_lengthof(Strings)) ? Strings[Value] : nullptr;<br>
- PrintAttribute(Tag, Value, ValueDesc);<br>
-}<br>
-<br>
-void ARMAttributeParser::DSP_extension(AttrType Tag, const uint8_t *Data,<br>
- uint32_t &Offset) {<br>
- static const char *const Strings[] = { "Not Permitted", "Permitted" };<br>
-<br>
- uint64_t Value = ParseInteger(Data, Offset);<br>
- StringRef ValueDesc =<br>
(Value < array_lengthof(Strings)) ? Strings[Value] : nullptr;<br>
PrintAttribute(Tag, Value, ValueDesc);<br>
}<br>
<br>
Modified: llvm/trunk/tools/llvm-readobj/ARMAttributeParser.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-readobj/ARMAttributeParser.h?rev=257916&r1=257915&r2=257916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-readobj/ARMAttributeParser.h?rev=257916&r1=257915&r2=257916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/llvm-readobj/ARMAttributeParser.h (original)<br>
+++ llvm/trunk/tools/llvm-readobj/ARMAttributeParser.h Fri Jan 15 12:31:29 2016<br>
@@ -100,8 +100,6 @@ class ARMAttributeParser {<br>
uint32_t &Offset);<br>
void DIV_use(ARMBuildAttrs::AttrType Tag, const uint8_t *Data,<br>
uint32_t &Offset);<br>
- void DSP_extension(ARMBuildAttrs::AttrType Tag, const uint8_t *Data,<br>
- uint32_t &Offset);<br>
void T2EE_use(ARMBuildAttrs::AttrType Tag, const uint8_t *Data,<br>
uint32_t &Offset);<br>
void Virtualization_use(ARMBuildAttrs::AttrType Tag, const uint8_t *Data,<br>
<br>
<br>
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</blockquote></div><br></div>