<div dir="ltr">This or one of the other commits in this batch broke the ARM simple-fp-encoding.s test on Windows:<div><a href="http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/5744">http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/5744</a></div><div><br></div><div>I'm looking for a culprit CL </div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jan 15, 2016 at 2:25 AM, Bradley Smith via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: brasmi01<br>
Date: Fri Jan 15 04:25:14 2016<br>
New Revision: 257879<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=257879&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=257879&view=rev</a><br>
Log:<br>
[ARM] Add MOVW/MOVT instructions to ARMv8-M Baseline/Mainline<br>
<br>
Added:<br>
llvm/trunk/test/MC/ARM/thumb-movwt-reloc.s (with props)<br>
Modified:<br>
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td<br>
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp<br>
llvm/trunk/test/CodeGen/ARM/movt.ll<br>
llvm/trunk/test/MC/ARM/thumbv8m.s<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=257879&r1=257878&r2=257879&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=257879&r1=257878&r2=257879&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Jan 15 04:25:14 2016<br>
@@ -1906,7 +1906,8 @@ def : t2InstAlias<"mov${p} $Rd, $imm", (<br>
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in<br>
def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,<br>
"movw", "\t$Rd, $imm",<br>
- [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]> {<br>
+ [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>,<br>
+ Requires<[IsThumb, HasV8MBaseline]> {<br>
let Inst{31-27} = 0b11110;<br>
let Inst{25} = 1;<br>
let Inst{24-21} = 0b0010;<br>
@@ -1924,8 +1925,9 @@ def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins<br>
let DecoderMethod = "DecodeT2MOVTWInstruction";<br>
}<br>
<br>
-def : t2InstAlias<"mov${p} $Rd, $imm",<br>
- (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>;<br>
+def : InstAlias<"mov${p} $Rd, $imm",<br>
+ (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>,<br>
+ Requires<[IsThumb, HasV8MBaseline]>;<br>
<br>
def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),<br>
(ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;<br>
@@ -1936,7 +1938,8 @@ def t2MOVTi16 : T2I<(outs rGPR:$Rd),<br>
"movt", "\t$Rd, $imm",<br>
[(set rGPR:$Rd,<br>
(or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,<br>
- Sched<[WriteALU]> {<br>
+ Sched<[WriteALU]>,<br>
+ Requires<[IsThumb, HasV8MBaseline]> {<br>
let Inst{31-27} = 0b11110;<br>
let Inst{25} = 1;<br>
let Inst{24-21} = 0b0110;<br>
@@ -1956,7 +1959,7 @@ def t2MOVTi16 : T2I<(outs rGPR:$Rd),<br>
<br>
def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),<br>
(ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,<br>
- Sched<[WriteALU]>;<br>
+ Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>;<br>
} // Constraints<br>
<br>
def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;<br>
@@ -3879,7 +3882,7 @@ let isReMaterializable = 1 in {<br>
def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),<br>
IIC_iMOVix2addpc,<br>
[(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,<br>
- Requires<[IsThumb2, UseMovt]>;<br>
+ Requires<[IsThumb, HasV8MBaseline, UseMovt]>;<br>
<br>
}<br>
<br>
@@ -3893,7 +3896,7 @@ def : T2Pat<(ARMWrapper tglobaltlsaddr:$<br>
// ConstantPool, GlobalAddress, and JumpTable<br>
def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;<br>
def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,<br>
- Requires<[IsThumb2, UseMovt]>;<br>
+ Requires<[IsThumb, HasV8MBaseline, UseMovt]>;<br>
<br>
def : T2Pat<(ARMWrapperJT tjumptable:$dst),<br>
(t2LEApcrelJT tjumptable:$dst)>;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=257879&r1=257878&r2=257879&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=257879&r1=257878&r2=257879&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Fri Jan 15 04:25:14 2016<br>
@@ -350,7 +350,7 @@ bool ARMSubtarget::useMovt(const Machine<br>
// NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit<br>
// immediates as it is inherently position independent, and may be out of<br>
// range otherwise.<br>
- return !NoMovt && hasV6T2Ops() &&<br>
+ return !NoMovt && hasV8MBaselineOps() &&<br>
(isTargetWindows() || !MF.getFunction()->optForMinSize());<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=257879&r1=257878&r2=257879&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=257879&r1=257878&r2=257879&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Fri Jan 15 04:25:14 2016<br>
@@ -1049,12 +1049,12 @@ ARMMCCodeEmitter::getHiLo16ImmOpValue(co<br>
switch (ARM16Expr->getKind()) {<br>
default: llvm_unreachable("Unsupported ARMFixup");<br>
case ARMMCExpr::VK_ARM_HI16:<br>
- Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movt_hi16<br>
- : ARM::fixup_arm_movt_hi16);<br>
+ Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16<br>
+ : ARM::fixup_arm_movt_hi16);<br>
break;<br>
case ARMMCExpr::VK_ARM_LO16:<br>
- Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movw_lo16<br>
- : ARM::fixup_arm_movw_lo16);<br>
+ Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16<br>
+ : ARM::fixup_arm_movw_lo16);<br>
break;<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/movt.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/movt.ll?rev=257879&r1=257878&r2=257879&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/movt.ll?rev=257879&r1=257878&r2=257879&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/movt.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/movt.ll Fri Jan 15 04:25:14 2016<br>
@@ -1,9 +1,11 @@<br>
; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s<br>
; rdar://7317664<br>
<br>
+; RUN: llc -mtriple=thumbv8m.base %s -o - | FileCheck %s<br>
+<br>
define i32 @t(i32 %X) nounwind {<br>
; CHECK-LABEL: t:<br>
-; CHECK: movt r0, #65535<br>
+; CHECK: movt r{{[0-9]}}, #65535<br>
entry:<br>
%0 = or i32 %X, -65536<br>
ret i32 %0<br>
@@ -11,7 +13,7 @@ entry:<br>
<br>
define i32 @t2(i32 %X) nounwind {<br>
; CHECK-LABEL: t2:<br>
-; CHECK: movt r0, #65534<br>
+; CHECK: movt r{{[0-9]}}, #65534<br>
entry:<br>
%0 = or i32 %X, -131072<br>
%1 = and i32 %0, -65537<br>
<br>
Added: llvm/trunk/test/MC/ARM/thumb-movwt-reloc.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-movwt-reloc.s?rev=257879&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-movwt-reloc.s?rev=257879&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/ARM/thumb-movwt-reloc.s (added)<br>
+++ llvm/trunk/test/MC/ARM/thumb-movwt-reloc.s Fri Jan 15 04:25:14 2016<br>
@@ -0,0 +1,27 @@<br>
+@ RUN: llvm-mc -triple thumbv8m.base-eabi -filetype asm -o - %s | FileCheck %s<br>
+@ RUN: llvm-mc -triple thumbv8m.base-eabi -filetype obj -o - %s | llvm-readobj -r \<br>
+@ RUN: | FileCheck -check-prefix CHECK-RELOCATIONS %s<br>
+<br>
+ .syntax unified<br>
+<br>
+ .type function,%function<br>
+function:<br>
+ bx lr<br>
+<br>
+ .global external<br>
+ .type external,%function<br>
+<br>
+ .type test,%function<br>
+test:<br>
+ movw r0, :lower16:function<br>
+ movt r0, :upper16:function<br>
+<br>
+@ CHECK-LABEL: test:<br>
+@ CHECK: movw r0, :lower16:function<br>
+@ CHECK: movt r0, :upper16:function<br>
+<br>
+@ CHECK-RELOCATIONS: Relocations [<br>
+@ CHECK-RELOCATIONS: 0x2 R_ARM_THM_MOVW_ABS_NC function 0x0<br>
+@ CHECK-RELOCATIONS: 0x6 R_ARM_THM_MOVT_ABS function 0x0<br>
+@ CHECK-RELOCATIONS: ]<br>
+<br>
<br>
Propchange: llvm/trunk/test/MC/ARM/thumb-movwt-reloc.s<br>
------------------------------------------------------------------------------<br>
svn:eol-style = native<br>
<br>
Propchange: llvm/trunk/test/MC/ARM/thumb-movwt-reloc.s<br>
------------------------------------------------------------------------------<br>
svn:keywords = Rev Date Author URL Id<br>
<br>
Modified: llvm/trunk/test/MC/ARM/thumbv8m.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumbv8m.s?rev=257879&r1=257878&r2=257879&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumbv8m.s?rev=257879&r1=257878&r2=257879&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/ARM/thumbv8m.s (original)<br>
+++ llvm/trunk/test/MC/ARM/thumbv8m.s Fri Jan 15 04:25:14 2016<br>
@@ -20,3 +20,11 @@ mov.w r0, r0<br>
<br>
// CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]<br>
isb sy<br>
+<br>
+// 'XO generation'<br>
+<br>
+// CHECK: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71]<br>
+movw r1, #0xffff<br>
+<br>
+// CHECK: movt r1, #65535 @ encoding: [0xcf,0xf6,0xff,0x71]<br>
+movt r1, #0xffff<br>
<br>
<br>
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</blockquote></div><br></div>