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<p class="MsoNormal"><a name="_MailEndCompose"><span dir="RTL"></span><span lang="HE" dir="RTL"><span dir="RTL"></span>< 
</span>Shouldn't this be qualified with the feature flag?<o:p></o:p></a></p>
<p class="MsoNormal">I don’t know. Backed does not end up with appropriate error message if the feature is not specified.<o:p></o:p></p>
<p class="MsoNormal">Using intrinsics requires –mpku on clang level.<o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
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<![if !supportLists]><span style="font-family:"Calibri",sans-serif;color:#2F5496"><span style="mso-list:Ignore">-<span style="font:7.0pt "Times New Roman"">         
</span></span></span><![endif]><span dir="LTR"></span><b><i><span style="color:#2F5496"> Elena<o:p></o:p></span></i></b></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><a name="_____replyseparator"></a><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> llvm-commits [mailto:llvm-commits-bounces@lists.llvm.org]
<b>On Behalf Of </b>Craig Topper via llvm-commits<br>
<b>Sent:</b> Friday, January 01, 2016 03:30<br>
<b>To:</b> Badouh, Asaf <asaf.badouh@intel.com><br>
<b>Cc:</b> llvm-commits <llvm-commits@lists.llvm.org><br>
<b>Subject:</b> Re: [llvm] r256670 - [X86][PKU] Add {RD,WR}PKRU intrinsics<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Thu, Dec 31, 2015 at 12:31 AM, Asaf Badouh via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm">
<p class="MsoNormal">Author: abadouh<br>
Date: Thu Dec 31 02:31:13 2015<br>
New Revision: 256670<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=256670&view=rev" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=256670&view=rev</a><br>
Log:<br>
[X86][PKU] Add {RD,WR}PKRU intrinsics<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D15808" target="_blank">http://reviews.llvm.org/D15808</a><br>
<br>
Added:<br>
    llvm/trunk/test/CodeGen/X86/pku.ll<br>
Modified:<br>
    llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
    llvm/trunk/lib/Target/X86/X86InstrSystem.td<br>
<br>
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=256670&r1=256669&r2=256670&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=256670&r1=256669&r2=256670&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)<br>
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Thu Dec 31 02:31:13 2015<br>
@@ -3919,9 +3919,9 @@ let TargetPrefix = "x86" in {  // All in<br>
 // Support protection key<br>
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".<br>
   def int_x86_rdpkru : GCCBuiltin <"__builtin_ia32_rdpkru">,<br>
-              Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;<br>
+              Intrinsic<[llvm_i32_ty], [], []>;<br>
   def int_x86_wrpkru : GCCBuiltin<"__builtin_ia32_wrpkru">,<br>
-              Intrinsic<[], [llvm_i32_ty], [IntrNoMem]>;<br>
+              Intrinsic<[], [llvm_i32_ty], []>;<br>
 }<br>
 //===----------------------------------------------------------------------===//<br>
 // Half float conversion<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=256670&r1=256669&r2=256670&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=256670&r1=256669&r2=256670&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Dec 31 02:31:13 2015<br>
@@ -21144,6 +21144,47 @@ static MachineBasicBlock *EmitPCMPSTRI(M<br>
   return BB;<br>
 }<br>
<br>
+static MachineBasicBlock *EmitWRPKRU(MachineInstr *MI, MachineBasicBlock *BB,<br>
+                                     const X86Subtarget *Subtarget) {<br>
+  DebugLoc dl = MI->getDebugLoc();<br>
+  const TargetInstrInfo *TII = Subtarget->getInstrInfo();<br>
+<br>
+  // insert input VAL into EAX<br>
+  BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)<br>
+                           .addReg(MI->getOperand(0).getReg());<br>
+  // insert zero to ECX<br>
+  BuildMI(*BB, MI, dl, TII->get(X86::XOR32rr), X86::ECX)<br>
+                           .addReg(X86::ECX)<br>
+                           .addReg(X86::ECX);<br>
+  // insert zero to EDX<br>
+  BuildMI(*BB, MI, dl, TII->get(X86::XOR32rr), X86::EDX)<br>
+                           .addReg(X86::EDX)<br>
+                           .addReg(X86::EDX);<br>
+  // insert WRPKRU instruction<br>
+  BuildMI(*BB, MI, dl, TII->get(X86::WRPKRUr));<br>
+<br>
+  MI->eraseFromParent(); // The pseudo is gone now.<br>
+  return BB;<br>
+}<br>
+<br>
+static MachineBasicBlock *EmitRDPKRU(MachineInstr *MI, MachineBasicBlock *BB,<br>
+                                     const X86Subtarget *Subtarget) {<br>
+  DebugLoc dl = MI->getDebugLoc();<br>
+  const TargetInstrInfo *TII = Subtarget->getInstrInfo();<br>
+<br>
+  // insert zero to ECX<br>
+  BuildMI(*BB, MI, dl, TII->get(X86::XOR32rr), X86::ECX)<br>
+                           .addReg(X86::ECX)<br>
+                           .addReg(X86::ECX);<br>
+  // insert RDPKRU instruction<br>
+  BuildMI(*BB, MI, dl, TII->get(X86::RDPKRUr));<br>
+  BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())<br>
+                           .addReg(X86::EAX);<br>
+<br>
+  MI->eraseFromParent(); // The pseudo is gone now.<br>
+  return BB;<br>
+}<br>
+<br>
 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,<br>
                                       const X86Subtarget *Subtarget) {<br>
   DebugLoc dl = MI->getDebugLoc();<br>
@@ -22611,7 +22652,11 @@ X86TargetLowering::EmitInstrWithCustomIn<br>
   // Thread synchronization.<br>
   case X86::MONITOR:<br>
     return EmitMonitor(MI, BB, Subtarget);<br>
-<br>
+  // PKU feature<br>
+  case X86::WRPKRU:<br>
+    return EmitWRPKRU(MI, BB, Subtarget);<br>
+  case X86::RDPKRU:<br>
+    return EmitRDPKRU(MI, BB, Subtarget);<br>
   // xbegin<br>
   case X86::XBEGIN:<br>
     return EmitXBegin(MI, BB, Subtarget->getInstrInfo());<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=256670&r1=256669&r2=256670&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=256670&r1=256669&r2=256670&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Thu Dec 31 02:31:13 2015<br>
@@ -551,10 +551,17 @@ let Defs = [RAX, RDX, RSI], Uses = [RAX,<br>
   def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;<br>
 //==-----------------------------------------------------------------------===//<br>
 // PKU  - enable protection key<br>
+let usesCustomInserter = 1 in {<br>
+  def WRPKRU : PseudoI<(outs), (ins GR32:$src),<br>
+                [(int_x86_wrpkru GR32:$src)]>;<br>
+  def RDPKRU : PseudoI<(outs GR32:$dst), (ins),<br>
+                [(set GR32:$dst, (int_x86_rdpkru))]>;<br>
+}<br>
+<br>
 let Defs = [EAX, EDX], Uses = [ECX] in<br>
-  def RDPKRU : I<0x01, MRM_EE, (outs), (ins), "rdpkru", []>, TB;<br>
+  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", []>, TB;<br>
 let Uses = [EAX, ECX, EDX] in<br>
-  def WRPKRU : I<0x01, MRM_EF, (outs), (ins), "wrpkru", []>, TB;<br>
+  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", []>, TB;<o:p></o:p></p>
</blockquote>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Shouldn't this be qualified with the feature flag?<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal"><br>
 //===----------------------------------------------------------------------===//<br>
 // FS/GS Base Instructions<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/pku.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pku.ll?rev=256670&view=auto" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pku.ll?rev=256670&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/pku.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/pku.ll Thu Dec 31 02:31:13 2015<br>
@@ -0,0 +1,25 @@<br>
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s<br>
+declare i32 @llvm.x86.rdpkru()<br>
+declare void @llvm.x86.wrpkru(i32)<br>
+<br>
+define void @test_x86_wrpkru(i32 %src) {<br>
+; CHECK-LABEL: test_x86_wrpkru:<br>
+; CHECK:       ## BB#0:<br>
+; CHECK-NEXT:    xorl    %ecx, %ecx<br>
+; CHECK-NEXT:    xorl    %edx, %edx<br>
+; CHECK-NEXT:    movl    %edi, %eax<br>
+; CHECK-NEXT:    wrpkru<br>
+; CHECK-NEXT:    retq<br>
+  call void @llvm.x86.wrpkru(i32 %src)<br>
+  ret void<br>
+}<br>
+<br>
+define i32 @test_x86_rdpkru() {<br>
+; CHECK-LABEL: test_x86_rdpkru:<br>
+; CHECK:      ## BB#0:<br>
+; CHECK-NEXT: xorl    %ecx, %ecx<br>
+; CHECK-NEXT: rdpkru<br>
+; CHECK-NEXT: retq<br>
+  %res = call i32 @llvm.x86.rdpkru()<br>
+  ret i32 %res<br>
+}<br>
<br>
<br>
_______________________________________________<br>
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</blockquote>
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<p class="MsoNormal"><br>
<br clear="all">
<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
</div>
<p class="MsoNormal">-- <o:p></o:p></p>
<div>
<p class="MsoNormal">~Craig<o:p></o:p></p>
</div>
</div>
</div>
</div>
<p>---------------------------------------------------------------------<br>
Intel Israel (74) Limited</p>

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