<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Dec 15, 2015 at 5:35 AM, Asaf Badouh via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: abadouh<br>
Date: Tue Dec 15 07:35:29 2015<br>
New Revision: 255644<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=255644&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=255644&view=rev</a><br>
Log:<br>
[x86] adding PKU feature flag<br>
<br>
the feature flag is essential for RDPKRU and WRPKRU instruction<br>
more about the instruction can be found in the SDM rev 56, vol 2 from <a href="http://www.intel.com/sdm" rel="noreferrer" target="_blank">http://www.intel.com/sdm</a><br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D15491" rel="noreferrer" target="_blank">http://reviews.llvm.org/D15491</a><br>
<br>
<br>
Modified:<br>
llvm/trunk/lib/Support/Host.cpp<br>
llvm/trunk/lib/Target/X86/X86.td<br>
llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>
llvm/trunk/lib/Target/X86/X86Subtarget.h<br>
<br>
Modified: llvm/trunk/lib/Support/Host.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=255644&r1=255643&r2=255644&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=255644&r1=255643&r2=255644&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Support/Host.cpp (original)<br>
+++ llvm/trunk/lib/Support/Host.cpp Tue Dec 15 07:35:29 2015<br>
@@ -812,6 +812,8 @@ bool sys::getHostCPUFeatures(StringMap<b<br>
Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);<br>
Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);<br>
Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);<br>
+ // Enable protection keys<br>
+ Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);<br>
<br>
// AVX512 is only supported if the OS supports the context save for it.<br>
Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=255644&r1=255643&r2=255644&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=255644&r1=255643&r2=255644&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86.td Tue Dec 15 07:35:29 2015<br>
@@ -134,6 +134,8 @@ def FeatureBWI : SubtargetFeature<"a<br>
def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",<br>
"Enable AVX-512 Vector Length eXtensions",<br>
[FeatureAVX512]>;<br>
+def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true",<br>
+ "Enable protection keys">;<br>
def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",<br>
"Enable packed carry-less multiplication instructions",<br>
[FeatureSSE2]>;<br>
@@ -491,6 +493,7 @@ class SkylakeProc<string Name> : Process<br>
FeatureDQI,<br>
FeatureBWI,<br>
FeatureVLX,<br>
+ FeaturePKU,<br>
FeatureCMPXCHG16B,<br>
FeatureSlowBTMem,<br>
FeaturePOPCNT,<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=255644&r1=255643&r2=255644&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=255644&r1=255643&r2=255644&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Dec 15 07:35:29 2015<br>
@@ -771,6 +771,7 @@ def HasVLX : Predicate<"Subtarget-<br>
def NoVLX : Predicate<"!Subtarget->hasVLX()">;<br>
def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">;<br>
def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">;<br>
+def PKU : Predicate<"!Subtarget->hasPKU()">;<br></blockquote><div><br></div><div>Should that be HasPKU or NoPKU? I'm confused because its not named like any of other flags and the predicate has an '!' in it.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;<br>
def HasAES : Predicate<"Subtarget->hasAES()">;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=255644&r1=255643&r2=255644&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=255644&r1=255643&r2=255644&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Tue Dec 15 07:35:29 2015<br>
@@ -270,6 +270,7 @@ void X86Subtarget::initializeEnvironment<br>
HasBWI = false;<br>
HasVLX = false;<br>
HasADX = false;<br>
+ HasPKU = false;<br>
HasSHA = false;<br>
HasPRFCHW = false;<br>
HasRDSEED = false;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=255644&r1=255643&r2=255644&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=255644&r1=255643&r2=255644&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Tue Dec 15 07:35:29 2015<br>
@@ -223,6 +223,9 @@ protected:<br>
/// Processor has AVX-512 Vector Length eXtenstions<br>
bool HasVLX;<br>
<br>
+ /// Processor has PKU extenstions<br>
+ bool HasPKU;<br>
+<br>
/// Processot supports MPX - Memory Protection Extensions<br>
bool HasMPX;<br>
<br>
@@ -398,6 +401,7 @@ public:<br>
bool hasDQI() const { return HasDQI; }<br>
bool hasBWI() const { return HasBWI; }<br>
bool hasVLX() const { return HasVLX; }<br>
+ bool hasPKU() const { return HasPKU; }<br>
bool hasMPX() const { return HasMPX; }<br>
<br>
bool isAtom() const { return X86ProcFamily == IntelAtom; }<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature">~Craig</div>
</div></div>