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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Hi Eric,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">First, thanks for fixing this.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">I can be more careful and can notice such change with a little effort from my side.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">I just did not know that this is not a wanted change!<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">I will be more careful next time.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Thanks again for pointing this issue out.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Amjad<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></a></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Eric Christopher [mailto:echristo@gmail.com]
<br>
<b>Sent:</b> Tuesday, December 22, 2015 00:57<br>
<b>To:</b> Aboud, Amjad; llvm-commits@lists.llvm.org; Nadav Rotem; klimek@google.com<br>
<b>Subject:</b> Re: [llvm] r256155 - Implemented Support of IA interrupt and exception handlers:<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hi Amjad,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">You just changed all of the line endings in X86ExpandPseudos.cpp, it's only obvious via phab if you look at the number of lines changed versus the diff, but is a pretty strict no-no.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">I'm going to fix it, but do be more careful in the future.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Manuel: Can you think of any way to highlight this in phab?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">-eric<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Mon, Dec 21, 2015 at 6:10 AM Amjad Aboud via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal">Author: aaboud<br>
Date: Mon Dec 21 08:07:14 2015<br>
New Revision: 256155<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=256155&view=rev" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=256155&view=rev</a><br>
Log:<br>
Implemented Support of IA interrupt and exception handlers:<br>
<a href="http://lists.llvm.org/pipermail/cfe-dev/2015-September/045171.html" target="_blank">http://lists.llvm.org/pipermail/cfe-dev/2015-September/045171.html</a><br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D15567" target="_blank">http://reviews.llvm.org/D15567</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/x86-32-intrcc.ll<br>
llvm/trunk/test/CodeGen/X86/x86-64-intrcc.ll<br>
Modified:<br>
llvm/trunk/include/llvm/IR/CallingConv.h<br>
llvm/trunk/lib/AsmParser/LLLexer.cpp<br>
llvm/trunk/lib/AsmParser/LLParser.cpp<br>
llvm/trunk/lib/AsmParser/LLToken.h<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
llvm/trunk/lib/IR/AsmWriter.cpp<br>
llvm/trunk/lib/Target/X86/X86CallingConv.td<br>
llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
llvm/trunk/lib/Target/X86/X86InstrControl.td<br>
llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
llvm/trunk/lib/Target/X86/X86InstrSystem.td<br>
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/IR/CallingConv.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/CallingConv.h?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/CallingConv.h?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IR/CallingConv.h (original)<br>
+++ llvm/trunk/include/llvm/IR/CallingConv.h Mon Dec 21 08:07:14 2015<br>
@@ -161,6 +161,13 @@ namespace CallingConv {<br>
/// \brief HHVM calling convention for invoking C/C++ helpers.<br>
HHVM_C = 82,<br>
<br>
+ /// X86_INTR - x86 hardware interrupt context. Callee may take one or two<br>
+ /// parameters, where the 1st represents a pointer to hardware context frame<br>
+ /// and the 2nd represents hardware error code, the presence of the later<br>
+ /// depends on the interrupt vector taken. Valid for both 32- and 64-bit<br>
+ /// subtargets.<br>
+ X86_INTR = 83,<br>
+<br>
/// The highest possible calling convention ID. Must be some 2^k - 1.<br>
MaxID = 1023<br>
};<br>
<br>
Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/AsmParser/LLLexer.cpp (original)<br>
+++ llvm/trunk/lib/AsmParser/LLLexer.cpp Mon Dec 21 08:07:14 2015<br>
@@ -591,6 +591,7 @@ lltok::Kind LLLexer::LexIdentifier() {<br>
KEYWORD(preserve_mostcc);<br>
KEYWORD(preserve_allcc);<br>
KEYWORD(ghccc);<br>
+ KEYWORD(x86_intrcc);<br>
KEYWORD(hhvmcc);<br>
KEYWORD(hhvm_ccc);<br>
KEYWORD(cxx_fast_tlscc);<br>
<br>
Modified: llvm/trunk/lib/AsmParser/LLParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)<br>
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Dec 21 08:07:14 2015<br>
@@ -1546,6 +1546,7 @@ bool LLParser::ParseOptionalDLLStorageCl<br>
/// ::= 'preserve_mostcc'<br>
/// ::= 'preserve_allcc'<br>
/// ::= 'ghccc'<br>
+/// ::= 'x86_intrcc'<br>
/// ::= 'hhvmcc'<br>
/// ::= 'hhvm_ccc'<br>
/// ::= 'cxx_fast_tlscc'<br>
@@ -1577,6 +1578,7 @@ bool LLParser::ParseOptionalCallingConv(<br>
case lltok::kw_preserve_mostcc:CC = CallingConv::PreserveMost; break;<br>
case lltok::kw_preserve_allcc: CC = CallingConv::PreserveAll; break;<br>
case lltok::kw_ghccc: CC = CallingConv::GHC; break;<br>
+ case lltok::kw_x86_intrcc: CC = CallingConv::X86_INTR; break;<br>
case lltok::kw_hhvmcc: CC = CallingConv::HHVM; break;<br>
case lltok::kw_hhvm_ccc: CC = CallingConv::HHVM_C; break;<br>
case lltok::kw_cxx_fast_tlscc: CC = CallingConv::CXX_FAST_TLS; break;<br>
<br>
Modified: llvm/trunk/lib/AsmParser/LLToken.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/AsmParser/LLToken.h (original)<br>
+++ llvm/trunk/lib/AsmParser/LLToken.h Mon Dec 21 08:07:14 2015<br>
@@ -100,6 +100,7 @@ namespace lltok {<br>
kw_webkit_jscc, kw_anyregcc,<br>
kw_preserve_mostcc, kw_preserve_allcc,<br>
kw_ghccc,<br>
+ kw_x86_intrcc,<br>
kw_hhvmcc, kw_hhvm_ccc,<br>
kw_cxx_fast_tlscc,<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Dec 21 08:07:14 2015<br>
@@ -7361,6 +7361,11 @@ void SelectionDAGISel::LowerArguments(co<br>
// in the various CC lowering callbacks.<br>
Flags.setByVal();<br>
}<br>
+ if (F.getCallingConv() == CallingConv::X86_INTR) {<br>
+ // IA Interrupt passes frame (1st parameter) by value in the stack.<br>
+ if (Idx == 1)<br>
+ Flags.setByVal();<br>
+ }<br>
if (Flags.isByVal() || Flags.isInAlloca()) {<br>
PointerType *Ty = cast<PointerType>(I->getType());<br>
Type *ElementTy = Ty->getElementType();<br>
<br>
Modified: llvm/trunk/lib/IR/AsmWriter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AsmWriter.cpp?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AsmWriter.cpp?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/IR/AsmWriter.cpp (original)<br>
+++ llvm/trunk/lib/IR/AsmWriter.cpp Mon Dec 21 08:07:14 2015<br>
@@ -313,6 +313,7 @@ static void PrintCallingConv(unsigned cc<br>
case CallingConv::X86_64_Win64: Out << "x86_64_win64cc"; break;<br>
case CallingConv::SPIR_FUNC: Out << "spir_func"; break;<br>
case CallingConv::SPIR_KERNEL: Out << "spir_kernel"; break;<br>
+ case CallingConv::X86_INTR: Out << "x86_intrcc"; break;<br>
case CallingConv::HHVM: Out << "hhvmcc"; break;<br>
case CallingConv::HHVM_C: Out << "hhvm_ccc"; break;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86CallingConv.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallingConv.td?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallingConv.td?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86CallingConv.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86CallingConv.td Mon Dec 21 08:07:14 2015<br>
@@ -739,6 +739,14 @@ def CC_Intel_OCL_BI : CallingConv<[<br>
CCDelegateTo<CC_X86_32_C><br>
]>;<br>
<br>
+def CC_X86_32_Intr : CallingConv<[<br>
+ CCAssignToStack<4, 4><br>
+]>;<br>
+<br>
+def CC_X86_64_Intr : CallingConv<[<br>
+ CCAssignToStack<8, 8><br>
+]>;<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// X86 Root Argument Calling Conventions<br>
//===----------------------------------------------------------------------===//<br>
@@ -751,6 +759,7 @@ def CC_X86_32 : CallingConv<[<br>
CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,<br>
CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,<br>
CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,<br>
+ CCIfCC<"CallingConv::X86_INTR", CCDelegateTo<CC_X86_32_Intr>>,<br>
<br>
// Otherwise, drop to normal X86-32 CC<br>
CCDelegateTo<CC_X86_32_C><br>
@@ -767,6 +776,7 @@ def CC_X86_64 : CallingConv<[<br>
CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>,<br>
CCIfCC<"CallingConv::HHVM", CCDelegateTo<CC_X86_64_HHVM>>,<br>
CCIfCC<"CallingConv::HHVM_C", CCDelegateTo<CC_X86_64_HHVM_C>>,<br>
+ CCIfCC<"CallingConv::X86_INTR", CCDelegateTo<CC_X86_64_Intr>>,<br>
<br>
// Mingw64 and native Win64 use Win64 CC<br>
CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,<br>
@@ -817,6 +827,11 @@ def CSR_64_MostRegs : CalleeSavedRegs<(a<br>
R11, R12, R13, R14, R15, RBP,<br>
(sequence "XMM%u", 0, 15))>;<br>
<br>
+def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI,<br>
+ EDI, ESP)>;<br>
+def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs,<br>
+ (sequence "XMM%u", 0, 7))>;<br>
+<br>
def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP,<br>
(sequence "XMM%u", 16, 31))>;<br>
def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP,<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp Mon Dec 21 08:07:14 2015<br>
@@ -1,189 +1,198 @@<br>
-//===------- X86ExpandPseudo.cpp - Expand pseudo instructions -------------===//<br>
-//<br>
-// The LLVM Compiler Infrastructure<br>
-//<br>
-// This file is distributed under the University of Illinois Open Source<br>
-// License. See LICENSE.TXT for details.<br>
-//<br>
-//===----------------------------------------------------------------------===//<br>
-//<br>
-// This file contains a pass that expands pseudo instructions into target<br>
-// instructions to allow proper scheduling, if-conversion, other late<br>
-// optimizations, or simply the encoding of the instructions.<br>
-//<br>
-//===----------------------------------------------------------------------===//<br>
-<br>
-#include "X86.h"<br>
-#include "X86FrameLowering.h"<br>
-#include "X86InstrBuilder.h"<br>
-#include "X86InstrInfo.h"<br>
-#include "X86MachineFunctionInfo.h"<br>
-#include "X86Subtarget.h"<br>
-#include "llvm/Analysis/EHPersonalities.h"<br>
-#include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.<br>
-#include "llvm/CodeGen/MachineFunctionPass.h"<br>
-#include "llvm/CodeGen/MachineInstrBuilder.h"<br>
-#include "llvm/IR/GlobalValue.h"<br>
-using namespace llvm;<br>
-<br>
-#define DEBUG_TYPE "x86-pseudo"<br>
-<br>
-namespace {<br>
-class X86ExpandPseudo : public MachineFunctionPass {<br>
-public:<br>
- static char ID;<br>
- X86ExpandPseudo() : MachineFunctionPass(ID) {}<br>
-<br>
- void getAnalysisUsage(AnalysisUsage &AU) const override {<br>
- AU.setPreservesCFG();<br>
- AU.addPreservedID(MachineLoopInfoID);<br>
- AU.addPreservedID(MachineDominatorsID);<br>
- MachineFunctionPass::getAnalysisUsage(AU);<br>
- }<br>
-<br>
- const X86Subtarget *STI;<br>
- const X86InstrInfo *TII;<br>
- const X86RegisterInfo *TRI;<br>
- const X86FrameLowering *X86FL;<br>
-<br>
- bool runOnMachineFunction(MachineFunction &Fn) override;<br>
-<br>
- const char *getPassName() const override {<br>
- return "X86 pseudo instruction expansion pass";<br>
- }<br>
-<br>
-private:<br>
- bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);<br>
- bool ExpandMBB(MachineBasicBlock &MBB);<br>
-};<br>
-char X86ExpandPseudo::ID = 0;<br>
-} // End anonymous namespace.<br>
-<br>
-/// If \p MBBI is a pseudo instruction, this method expands<br>
-/// it to the corresponding (sequence of) actual instruction(s).<br>
-/// \returns true if \p MBBI has been expanded.<br>
-bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,<br>
- MachineBasicBlock::iterator MBBI) {<br>
- MachineInstr &MI = *MBBI;<br>
- unsigned Opcode = MI.getOpcode();<br>
- DebugLoc DL = MBBI->getDebugLoc();<br>
- switch (Opcode) {<br>
- default:<br>
- return false;<br>
- case X86::TCRETURNdi:<br>
- case X86::TCRETURNri:<br>
- case X86::TCRETURNmi:<br>
- case X86::TCRETURNdi64:<br>
- case X86::TCRETURNri64:<br>
- case X86::TCRETURNmi64: {<br>
- bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64;<br>
- MachineOperand &JumpTarget = MBBI->getOperand(0);<br>
- MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);<br>
- assert(StackAdjust.isImm() && "Expecting immediate value.");<br>
-<br>
- // Adjust stack pointer.<br>
- int StackAdj = StackAdjust.getImm();<br>
-<br>
- if (StackAdj) {<br>
- // Check for possible merge with preceding ADD instruction.<br>
- StackAdj += X86FL->mergeSPUpdates(MBB, MBBI, true);<br>
- X86FL->emitSPUpdate(MBB, MBBI, StackAdj, /*InEpilogue=*/true);<br>
- }<br>
-<br>
- // Jump to label or value in register.<br>
- bool IsWin64 = STI->isTargetWin64();<br>
- if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdi64) {<br>
- unsigned Op = (Opcode == X86::TCRETURNdi)<br>
- ? X86::TAILJMPd<br>
- : (IsWin64 ? X86::TAILJMPd64_REX : X86::TAILJMPd64);<br>
- MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));<br>
- if (JumpTarget.isGlobal())<br>
- MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),<br>
- JumpTarget.getTargetFlags());<br>
- else {<br>
- assert(JumpTarget.isSymbol());<br>
- MIB.addExternalSymbol(JumpTarget.getSymbolName(),<br>
- JumpTarget.getTargetFlags());<br>
- }<br>
- } else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64) {<br>
- unsigned Op = (Opcode == X86::TCRETURNmi)<br>
- ? X86::TAILJMPm<br>
- : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);<br>
- MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));<br>
- for (unsigned i = 0; i != 5; ++i)<br>
- MIB.addOperand(MBBI->getOperand(i));<br>
- } else if (Opcode == X86::TCRETURNri64) {<br>
- BuildMI(MBB, MBBI, DL,<br>
- TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))<br>
- .addReg(JumpTarget.getReg(), RegState::Kill);<br>
- } else {<br>
- BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))<br>
- .addReg(JumpTarget.getReg(), RegState::Kill);<br>
- }<br>
-<br>
- MachineInstr *NewMI = std::prev(MBBI);<br>
- NewMI->copyImplicitOps(*MBBI->getParent()->getParent(), MBBI);<br>
-<br>
- // Delete the pseudo instruction TCRETURN.<br>
- MBB.erase(MBBI);<br>
-<br>
- return true;<br>
- }<br>
- case X86::EH_RETURN:<br>
- case X86::EH_RETURN64: {<br>
- MachineOperand &DestAddr = MBBI->getOperand(0);<br>
- assert(DestAddr.isReg() && "Offset should be in register!");<br>
- const bool Uses64BitFramePtr =<br>
- STI->isTarget64BitLP64() || STI->isTargetNaCl64();<br>
- unsigned StackPtr = TRI->getStackRegister();<br>
- BuildMI(MBB, MBBI, DL,<br>
- TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)<br>
- .addReg(DestAddr.getReg());<br>
- // The EH_RETURN pseudo is really removed during the MC Lowering.<br>
- return true;<br>
- }<br>
-<br>
- case X86::EH_RESTORE: {<br>
- // Restore ESP and EBP, and optionally ESI if required.<br>
- bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(<br>
- MBB.getParent()->getFunction()->getPersonalityFn()));<br>
- X86FL->restoreWin32EHStackPointers(MBB, MBBI, DL, /*RestoreSP=*/IsSEH);<br>
- MBBI->eraseFromParent();<br>
- return true;<br>
- }<br>
- }<br>
- llvm_unreachable("Previous switch has a fallthrough?");<br>
-}<br>
-<br>
-/// Expand all pseudo instructions contained in \p MBB.<br>
-/// \returns true if any expansion occurred for \p MBB.<br>
-bool X86ExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {<br>
- bool Modified = false;<br>
-<br>
- // MBBI may be invalidated by the expansion.<br>
- MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();<br>
- while (MBBI != E) {<br>
- MachineBasicBlock::iterator NMBBI = std::next(MBBI);<br>
- Modified |= ExpandMI(MBB, MBBI);<br>
- MBBI = NMBBI;<br>
- }<br>
-<br>
- return Modified;<br>
-}<br>
-<br>
-bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {<br>
- STI = &static_cast<const X86Subtarget &>(MF.getSubtarget());<br>
- TII = STI->getInstrInfo();<br>
- TRI = STI->getRegisterInfo();<br>
- X86FL = STI->getFrameLowering();<br>
-<br>
- bool Modified = false;<br>
- for (MachineBasicBlock &MBB : MF)<br>
- Modified |= ExpandMBB(MBB);<br>
- return Modified;<br>
-}<br>
-<br>
-/// Returns an instance of the pseudo instruction expansion pass.<br>
-FunctionPass *llvm::createX86ExpandPseudoPass() {<br>
- return new X86ExpandPseudo();<br>
-}<br>
+//===------- X86ExpandPseudo.cpp - Expand pseudo instructions -------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file contains a pass that expands pseudo instructions into target<br>
+// instructions to allow proper scheduling, if-conversion, other late<br>
+// optimizations, or simply the encoding of the instructions.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "X86.h"<br>
+#include "X86FrameLowering.h"<br>
+#include "X86InstrBuilder.h"<br>
+#include "X86InstrInfo.h"<br>
+#include "X86MachineFunctionInfo.h"<br>
+#include "X86Subtarget.h"<br>
+#include "llvm/Analysis/EHPersonalities.h"<br>
+#include "llvm/CodeGen/MachineFunctionPass.h"<br>
+#include "llvm/CodeGen/MachineInstrBuilder.h"<br>
+#include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.<br>
+#include "llvm/IR/GlobalValue.h"<br>
+using namespace llvm;<br>
+<br>
+#define DEBUG_TYPE "x86-pseudo"<br>
+<br>
+namespace {<br>
+class X86ExpandPseudo : public MachineFunctionPass {<br>
+public:<br>
+ static char ID;<br>
+ X86ExpandPseudo() : MachineFunctionPass(ID) {}<br>
+<br>
+ void getAnalysisUsage(AnalysisUsage &AU) const override {<br>
+ AU.setPreservesCFG();<br>
+ AU.addPreservedID(MachineLoopInfoID);<br>
+ AU.addPreservedID(MachineDominatorsID);<br>
+ MachineFunctionPass::getAnalysisUsage(AU);<br>
+ }<br>
+<br>
+ const X86Subtarget *STI;<br>
+ const X86InstrInfo *TII;<br>
+ const X86RegisterInfo *TRI;<br>
+ const X86FrameLowering *X86FL;<br>
+<br>
+ bool runOnMachineFunction(MachineFunction &Fn) override;<br>
+<br>
+ const char *getPassName() const override {<br>
+ return "X86 pseudo instruction expansion pass";<br>
+ }<br>
+<br>
+private:<br>
+ bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);<br>
+ bool ExpandMBB(MachineBasicBlock &MBB);<br>
+};<br>
+char X86ExpandPseudo::ID = 0;<br>
+} // End anonymous namespace.<br>
+<br>
+/// If \p MBBI is a pseudo instruction, this method expands<br>
+/// it to the corresponding (sequence of) actual instruction(s).<br>
+/// \returns true if \p MBBI has been expanded.<br>
+bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,<br>
+ MachineBasicBlock::iterator MBBI) {<br>
+ MachineInstr &MI = *MBBI;<br>
+ unsigned Opcode = MI.getOpcode();<br>
+ DebugLoc DL = MBBI->getDebugLoc();<br>
+ switch (Opcode) {<br>
+ default:<br>
+ return false;<br>
+ case X86::TCRETURNdi:<br>
+ case X86::TCRETURNri:<br>
+ case X86::TCRETURNmi:<br>
+ case X86::TCRETURNdi64:<br>
+ case X86::TCRETURNri64:<br>
+ case X86::TCRETURNmi64: {<br>
+ bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64;<br>
+ MachineOperand &JumpTarget = MBBI->getOperand(0);<br>
+ MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);<br>
+ assert(StackAdjust.isImm() && "Expecting immediate value.");<br>
+<br>
+ // Adjust stack pointer.<br>
+ int StackAdj = StackAdjust.getImm();<br>
+<br>
+ if (StackAdj) {<br>
+ // Check for possible merge with preceding ADD instruction.<br>
+ StackAdj += X86FL->mergeSPUpdates(MBB, MBBI, true);<br>
+ X86FL->emitSPUpdate(MBB, MBBI, StackAdj, /*InEpilogue=*/true);<br>
+ }<br>
+<br>
+ // Jump to label or value in register.<br>
+ bool IsWin64 = STI->isTargetWin64();<br>
+ if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdi64) {<br>
+ unsigned Op = (Opcode == X86::TCRETURNdi)<br>
+ ? X86::TAILJMPd<br>
+ : (IsWin64 ? X86::TAILJMPd64_REX : X86::TAILJMPd64);<br>
+ MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));<br>
+ if (JumpTarget.isGlobal())<br>
+ MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),<br>
+ JumpTarget.getTargetFlags());<br>
+ else {<br>
+ assert(JumpTarget.isSymbol());<br>
+ MIB.addExternalSymbol(JumpTarget.getSymbolName(),<br>
+ JumpTarget.getTargetFlags());<br>
+ }<br>
+ } else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64) {<br>
+ unsigned Op = (Opcode == X86::TCRETURNmi)<br>
+ ? X86::TAILJMPm<br>
+ : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);<br>
+ MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));<br>
+ for (unsigned i = 0; i != 5; ++i)<br>
+ MIB.addOperand(MBBI->getOperand(i));<br>
+ } else if (Opcode == X86::TCRETURNri64) {<br>
+ BuildMI(MBB, MBBI, DL,<br>
+ TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))<br>
+ .addReg(JumpTarget.getReg(), RegState::Kill);<br>
+ } else {<br>
+ BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))<br>
+ .addReg(JumpTarget.getReg(), RegState::Kill);<br>
+ }<br>
+<br>
+ MachineInstr *NewMI = std::prev(MBBI);<br>
+ NewMI->copyImplicitOps(*MBBI->getParent()->getParent(), MBBI);<br>
+<br>
+ // Delete the pseudo instruction TCRETURN.<br>
+ MBB.erase(MBBI);<br>
+<br>
+ return true;<br>
+ }<br>
+ case X86::EH_RETURN:<br>
+ case X86::EH_RETURN64: {<br>
+ MachineOperand &DestAddr = MBBI->getOperand(0);<br>
+ assert(DestAddr.isReg() && "Offset should be in register!");<br>
+ const bool Uses64BitFramePtr =<br>
+ STI->isTarget64BitLP64() || STI->isTargetNaCl64();<br>
+ unsigned StackPtr = TRI->getStackRegister();<br>
+ BuildMI(MBB, MBBI, DL,<br>
+ TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)<br>
+ .addReg(DestAddr.getReg());<br>
+ // The EH_RETURN pseudo is really removed during the MC Lowering.<br>
+ return true;<br>
+ }<br>
+ case X86::IRET: {<br>
+ // Adjust stack to erase error code<br>
+ int64_t StackAdj = MBBI->getOperand(0).getImm();<br>
+ X86FL->emitSPUpdate(MBB, MBBI, StackAdj, true);<br>
+ // Replace pseudo with machine iret<br>
+ BuildMI(MBB, MBBI, DL,<br>
+ TII->get(STI->is64Bit() ? X86::IRET64 : X86::IRET32));<br>
+ MBB.erase(MBBI);<br>
+ return true;<br>
+ }<br>
+ case X86::EH_RESTORE: {<br>
+ // Restore ESP and EBP, and optionally ESI if required.<br>
+ bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(<br>
+ MBB.getParent()->getFunction()->getPersonalityFn()));<br>
+ X86FL->restoreWin32EHStackPointers(MBB, MBBI, DL, /*RestoreSP=*/IsSEH);<br>
+ MBBI->eraseFromParent();<br>
+ return true;<br>
+ }<br>
+ }<br>
+ llvm_unreachable("Previous switch has a fallthrough?");<br>
+}<br>
+<br>
+/// Expand all pseudo instructions contained in \p MBB.<br>
+/// \returns true if any expansion occurred for \p MBB.<br>
+bool X86ExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {<br>
+ bool Modified = false;<br>
+<br>
+ // MBBI may be invalidated by the expansion.<br>
+ MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();<br>
+ while (MBBI != E) {<br>
+ MachineBasicBlock::iterator NMBBI = std::next(MBBI);<br>
+ Modified |= ExpandMI(MBB, MBBI);<br>
+ MBBI = NMBBI;<br>
+ }<br>
+<br>
+ return Modified;<br>
+}<br>
+<br>
+bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {<br>
+ STI = &static_cast<const X86Subtarget &>(MF.getSubtarget());<br>
+ TII = STI->getInstrInfo();<br>
+ TRI = STI->getRegisterInfo();<br>
+ X86FL = STI->getFrameLowering();<br>
+<br>
+ bool Modified = false;<br>
+ for (MachineBasicBlock &MBB : MF)<br>
+ Modified |= ExpandMBB(MBB);<br>
+ return Modified;<br>
+}<br>
+<br>
+/// Returns an instance of the pseudo instruction expansion pass.<br>
+FunctionPass *llvm::createX86ExpandPseudoPass() {<br>
+ return new X86ExpandPseudo();<br>
+}<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Dec 21 08:07:14 2015<br>
@@ -2188,6 +2188,9 @@ X86TargetLowering::LowerReturn(SDValue C<br>
MachineFunction &MF = DAG.getMachineFunction();<br>
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();<br>
<br>
+ if (CallConv == CallingConv::X86_INTR && !Outs.empty())<br>
+ report_fatal_error("X86 interrupts may not return any value");<br>
+<br>
SmallVector<CCValAssign, 16> RVLocs;<br>
CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());<br>
CCInfo.AnalyzeReturn(Outs, RetCC_X86);<br>
@@ -2301,7 +2304,10 @@ X86TargetLowering::LowerReturn(SDValue C<br>
if (Flag.getNode())<br>
RetOps.push_back(Flag);<br>
<br>
- return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);<br>
+ X86ISD::NodeType opcode = X86ISD::RET_FLAG;<br>
+ if (CallConv == CallingConv::X86_INTR)<br>
+ opcode = X86ISD::IRET;<br>
+ return DAG.getNode(opcode, dl, MVT::Other, RetOps);<br>
}<br>
<br>
bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {<br>
@@ -2541,6 +2547,19 @@ X86TargetLowering::LowerMemArgument(SDVa<br>
else<br>
ValVT = VA.getValVT();<br>
<br>
+ // Calculate SP offset of interrupt parameter, re-arrange the slot normally<br>
+ // taken by a return address.<br>
+ int Offset = 0;<br>
+ if (CallConv == CallingConv::X86_INTR) {<br>
+ const X86Subtarget& Subtarget =<br>
+ static_cast<const X86Subtarget&>(DAG.getSubtarget());<br>
+ // X86 interrupts may take one or two arguments.<br>
+ // On the stack there will be no return address as in regular call.<br>
+ // Offset of last argument need to be set to -4/-8 bytes.<br>
+ // Where offset of the first argument out of two, should be set to 0 bytes.<br>
+ Offset = (Subtarget.is64Bit() ? 8 : 4) * ((i + 1) % Ins.size() - 1);<br>
+ }<br>
+<br>
// FIXME: For now, all byval parameter objects are marked mutable. This can be<br>
// changed with more analysis.<br>
// In case of tail call optimization mark all arguments mutable. Since they<br>
@@ -2549,10 +2568,19 @@ X86TargetLowering::LowerMemArgument(SDVa<br>
unsigned Bytes = Flags.getByValSize();<br>
if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.<br>
int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);<br>
+ // Adjust SP offset of interrupt parameter.<br>
+ if (CallConv == CallingConv::X86_INTR) {<br>
+ MFI->setObjectOffset(FI, Offset);<br>
+ }<br>
return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));<br>
} else {<br>
int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,<br>
VA.getLocMemOffset(), isImmutable);<br>
+ // Adjust SP offset of interrupt parameter.<br>
+ if (CallConv == CallingConv::X86_INTR) {<br>
+ MFI->setObjectOffset(FI, Offset);<br>
+ }<br>
+<br>
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));<br>
SDValue Val = DAG.getLoad(<br>
ValVT, dl, Chain, FIN,<br>
@@ -2632,6 +2660,14 @@ SDValue X86TargetLowering::LowerFormalAr<br>
assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&<br>
"Var args not supported with calling convention fastcc, ghc or hipe");<br>
<br>
+ if (CallConv == CallingConv::X86_INTR) {<br>
+ bool isLegal = Ins.size() == 1 ||<br>
+ (Ins.size() == 2 && ((Is64Bit && Ins[1].VT == MVT::i64) ||<br>
+ (!Is64Bit && Ins[1].VT == MVT::i32)));<br>
+ if (!isLegal)<br>
+ report_fatal_error("X86 interrupts may take one or two arguments");<br>
+ }<br>
+<br>
// Assign locations to all of the incoming arguments.<br>
SmallVector<CCValAssign, 16> ArgLocs;<br>
CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());<br>
@@ -2891,6 +2927,9 @@ SDValue X86TargetLowering::LowerFormalAr<br>
if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,<br>
MF.getTarget().Options.GuaranteedTailCallOpt)) {<br>
FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.<br>
+ } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {<br>
+ // X86 interrupts must pop the error code if present<br>
+ FuncInfo->setBytesToPopOnReturn(Is64Bit ? 8 : 4);<br>
} else {<br>
FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.<br>
// If this is an sret function, the return should pop the hidden pointer.<br>
@@ -3021,6 +3060,9 @@ X86TargetLowering::LowerCall(TargetLower<br>
X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();<br>
auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");<br>
<br>
+ if (CallConv == CallingConv::X86_INTR)<br>
+ report_fatal_error("X86 interrupts may not be called directly");<br>
+<br>
if (Attr.getValueAsString() == "true")<br>
isTailCall = false;<br>
<br>
@@ -20392,6 +20434,7 @@ const char *X86TargetLowering::getTarget<br>
case X86ISD::CMOV: return "X86ISD::CMOV";<br>
case X86ISD::BRCOND: return "X86ISD::BRCOND";<br>
case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";<br>
+ case X86ISD::IRET: return "X86ISD::IRET";<br>
case X86ISD::REP_STOS: return "X86ISD::REP_STOS";<br>
case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";<br>
case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Dec 21 08:07:14 2015<br>
@@ -126,6 +126,9 @@ namespace llvm {<br>
/// 1 is the number of bytes of stack to pop.<br>
RET_FLAG,<br>
<br>
+ /// Return from interrupt. Operand 0 is the number of bytes to pop.<br>
+ IRET,<br>
+<br>
/// Repeat fill, corresponds to X86::REP_STOSx.<br>
REP_STOS,<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrControl.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrControl.td?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrControl.td?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrControl.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrControl.td Mon Dec 21 08:07:14 2015<br>
@@ -53,6 +53,19 @@ let isTerminator = 1, isReturn = 1, isBa<br>
"{l}ret{|f}q\t$amt", [], IIC_RET>, Requires<[In64BitMode]>;<br>
def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),<br>
"{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize16;<br>
+<br>
+ // The machine return from interrupt instruction, but sometimes we need to<br>
+ // perform a post-epilogue stack adjustment. Codegen emits the pseudo form<br>
+ // which expands to include an SP adjustment if necessary.<br>
+ def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>,<br>
+ OpSize16;<br>
+ def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", [],<br>
+ IIC_IRET>, OpSize32;<br>
+ def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", [],<br>
+ IIC_IRET>, Requires<[In64BitMode]>;<br>
+ let isCodeGenOnly = 1 in<br>
+ def IRET : PseudoI<(outs), (ins i16imm:$adj), [(X86iret timm:$adj)]>;<br>
+<br>
}<br>
<br>
// Unconditional branches.<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Dec 21 08:07:14 2015<br>
@@ -156,6 +156,8 @@ def X86cas16 : SDNode<"X86ISD::LCMPXCHG1<br>
<br>
def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,<br>
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;<br>
+def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret,<br>
+ [SDNPHasChain, SDNPOptInGlue]>;<br>
<br>
def X86vastart_save_xmm_regs :<br>
SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Mon Dec 21 08:07:14 2015<br>
@@ -60,12 +60,6 @@ def SYSEXIT : I<0x35, RawFrm, (outs),<br>
IIC_SYS_ENTER_EXIT>, TB;<br>
def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [],<br>
IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;<br>
-<br>
-def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize16;<br>
-def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>,<br>
- OpSize32;<br>
-def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,<br>
- Requires<[In64BitMode]>;<br>
} // SchedRW<br>
<br>
def : Pat<(debugtrap),<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=256155&r1=256154&r2=256155&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=256155&r1=256154&r2=256155&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Dec 21 08:07:14 2015<br>
@@ -229,6 +229,7 @@ X86RegisterInfo::getRegPressureLimit(con<br>
const MCPhysReg *<br>
X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {<br>
const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();<br>
+ bool HasSSE = Subtarget.hasSSE1();<br>
bool HasAVX = Subtarget.hasAVX();<br>
bool HasAVX512 = Subtarget.hasAVX512();<br>
bool CallsEHReturn = MF->getMMI().callsEHReturn();<br>
@@ -277,6 +278,18 @@ X86RegisterInfo::getCalleeSavedRegs(cons<br>
if (CallsEHReturn)<br>
return CSR_64EHRet_SaveList;<br>
return CSR_64_SaveList;<br>
+ case CallingConv::X86_INTR:<br>
+ if (Is64Bit) {<br>
+ if (HasAVX)<br>
+ return CSR_64_AllRegs_AVX_SaveList;<br>
+ else<br>
+ return CSR_64_AllRegs_SaveList;<br>
+ } else {<br>
+ if (HasSSE)<br>
+ return CSR_32_AllRegs_SSE_SaveList;<br>
+ else<br>
+ return CSR_32_AllRegs_SaveList;<br>
+ }<br>
default:<br>
break;<br>
}<br>
@@ -297,6 +310,7 @@ const uint32_t *<br>
X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,<br>
CallingConv::ID CC) const {<br>
const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();<br>
+ bool HasSSE = Subtarget.hasSSE1();<br>
bool HasAVX = Subtarget.hasAVX();<br>
bool HasAVX512 = Subtarget.hasAVX512();<br>
<br>
@@ -337,12 +351,24 @@ X86RegisterInfo::getCallPreservedMask(co<br>
if (Is64Bit)<br>
return CSR_64_MostRegs_RegMask;<br>
break;<br>
- default:<br>
- break;<br>
case CallingConv::X86_64_Win64:<br>
return CSR_Win64_RegMask;<br>
case CallingConv::X86_64_SysV:<br>
return CSR_64_RegMask;<br>
+ case CallingConv::X86_INTR:<br>
+ if (Is64Bit) {<br>
+ if (HasAVX)<br>
+ return CSR_64_AllRegs_AVX_RegMask;<br>
+ else<br>
+ return CSR_64_AllRegs_RegMask;<br>
+ } else {<br>
+ if (HasSSE)<br>
+ return CSR_32_AllRegs_SSE_RegMask;<br>
+ else<br>
+ return CSR_32_AllRegs_RegMask;<br>
+ }<br>
+ default:<br>
+ break;<br>
}<br>
<br>
// Unlike getCalleeSavedRegs(), we don't have MMI so we can't check<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/x86-32-intrcc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-32-intrcc.ll?rev=256155&view=auto" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-32-intrcc.ll?rev=256155&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/x86-32-intrcc.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/x86-32-intrcc.ll Mon Dec 21 08:07:14 2015<br>
@@ -0,0 +1,79 @@<br>
+; RUN: llc -mtriple=i686-unknown-unknown < %s | FileCheck %s<br>
+; RUN: llc -mtriple=i686-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0<br>
+<br>
+%struct.interrupt_frame = type { i32, i32, i32, i32, i32 }<br>
+<br>
<a href="mailto:+@llvm.used">+@llvm.used</a> = appending global [3 x i8*] [i8* bitcast (void (%struct.interrupt_frame*)* @test_isr_no_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i32)* @test_isr_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*,
i32)* @test_isr_clobbers to i8*)], section "llvm.metadata"<br>
+<br>
+; Spills eax, putting original esp at +4.<br>
+; No stack adjustment if declared with no error code<br>
+define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) {<br>
+ ; CHECK-LABEL: test_isr_no_ecode:<br>
+ ; CHECK: pushl %eax<br>
+ ; CHECK: movl 12(%esp), %eax<br>
+ ; CHECK: popl %eax<br>
+ ; CHECK: iretl<br>
+ ; CHECK0-LABEL: test_isr_no_ecode:<br>
+ ; CHECK0: pushl %eax<br>
+ ; CHECK0: leal 4(%esp), %eax<br>
+ ; CHECK0: movl 8(%eax), %eax<br>
+ ; CHECK0: popl %eax<br>
+ ; CHECK0: iretl<br>
+ %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2<br>
+ %flags = load i32, i32* %pflags, align 4<br>
+ call void asm sideeffect "", "r"(i32 %flags)<br>
+ ret void<br>
+}<br>
+<br>
+; Spills eax and ecx, putting original esp at +8. Stack is adjusted up another 4 bytes<br>
+; before return, popping the error code.<br>
+define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i32 %ecode) {<br>
+ ; CHECK-LABEL: test_isr_ecode<br>
+ ; CHECK: pushl %ecx<br>
+ ; CHECK: pushl %eax<br>
+ ; CHECK: movl 8(%esp), %eax<br>
+ ; CHECK: movl 20(%esp), %ecx<br>
+ ; CHECK: popl %eax<br>
+ ; CHECK: popl %ecx<br>
+ ; CHECK: addl $4, %esp<br>
+ ; CHECK: iretl<br>
+ ; CHECK0-LABEL: test_isr_ecode<br>
+ ; CHECK0: pushl %ecx<br>
+ ; CHECK0: pushl %eax<br>
+ ; CHECK0: movl 8(%esp), %eax<br>
+ ; CHECK0: leal 12(%esp), %ecx<br>
+ ; CHECK0: movl 8(%ecx), %ecx<br>
+ ; CHECK0: popl %eax<br>
+ ; CHECK0: popl %ecx<br>
+ ; CHECK0: addl $4, %esp<br>
+ ; CHECK0: iretl<br>
+ %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2<br>
+ %flags = load i32, i32* %pflags, align 4<br>
+ call x86_fastcallcc void asm sideeffect "", "r,r"(i32 %flags, i32 %ecode)<br>
+ ret void<br>
+}<br>
+<br>
+; All clobbered registers must be saved<br>
+define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i32 %ecode) {<br>
+ call void asm sideeffect "", "~{eax},~{ebx},~{ebp}"()<br>
+ ; CHECK-LABEL: test_isr_clobbers<br>
+ ; CHECK-SSE-NEXT: pushl %ebp<br>
+ ; CHECK-SSE-NEXT: pushl %ebx<br>
+ ; CHECK-SSE-NEXT; pushl %eax<br>
+ ; CHECK-SSE-NEXT: popl %eax<br>
+ ; CHECK-SSE-NEXT: popl %ebx<br>
+ ; CHECK-SSE-NEXT: popl %ebp<br>
+ ; CHECK-SSE-NEXT: addl $4, %esp<br>
+ ; CHECK-SSE-NEXT: iretl<br>
+ ; CHECK0-LABEL: test_isr_clobbers<br>
+ ; CHECK0-SSE-NEXT: pushl %ebp<br>
+ ; CHECK0-SSE-NEXT: pushl %ebx<br>
+ ; CHECK0-SSE-NEXT; pushl %eax<br>
+ ; CHECK0-SSE-NEXT: popl %eax<br>
+ ; CHECK0-SSE-NEXT: popl %ebx<br>
+ ; CHECK0-SSE-NEXT: popl %ebp<br>
+ ; CHECK0-SSE-NEXT: addl $4, %esp<br>
+ ; CHECK0-SSE-NEXT: iretl<br>
+ ret void<br>
+}<br>
+<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/x86-64-intrcc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-intrcc.ll?rev=256155&view=auto" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-intrcc.ll?rev=256155&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/x86-64-intrcc.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/x86-64-intrcc.ll Mon Dec 21 08:07:14 2015<br>
@@ -0,0 +1,86 @@<br>
+; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s<br>
+; RUN: llc -mtriple=x86_64-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0<br>
+<br>
+%struct.interrupt_frame = type { i64, i64, i64, i64, i64 }<br>
+<br>
<a href="mailto:+@llvm.used">+@llvm.used</a> = appending global [3 x i8*] [i8* bitcast (void (%struct.interrupt_frame*)* @test_isr_no_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*,
i64)* @test_isr_clobbers to i8*)], section "llvm.metadata"<br>
+<br>
+; Spills rax, putting original esp at +8.<br>
+; No stack adjustment if declared with no error code<br>
+define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) {<br>
+ ; CHECK-LABEL: test_isr_no_ecode:<br>
+ ; CHECK: pushq %rax<br>
+ ; CHECK: movq 24(%rsp), %rax<br>
+ ; CHECK: popq %rax<br>
+ ; CHECK: iretq<br>
+ ; CHECK0-LABEL: test_isr_no_ecode:<br>
+ ; CHECK0: pushq %rax<br>
+ ; CHECK0: leaq 8(%rsp), %rax<br>
+ ; CHECK0: movq 16(%rax), %rax<br>
+ ; CHECK0: popq %rax<br>
+ ; CHECK0: iretq<br>
+ %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2<br>
+ %flags = load i64, i64* %pflags, align 4<br>
+ call void asm sideeffect "", "r"(i64 %flags)<br>
+ ret void<br>
+}<br>
+<br>
+; Spills rax and rcx, putting original rsp at +16. Stack is adjusted up another 8 bytes<br>
+; before return, popping the error code.<br>
+define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i64 %ecode) {<br>
+ ; CHECK-LABEL: test_isr_ecode<br>
+ ; CHECK: pushq %rax<br>
+ ; CHECK: pushq %rcx<br>
+ ; CHECK: movq 16(%rsp), %rax<br>
+ ; CHECK: movq 40(%rsp), %rcx<br>
+ ; CHECK: popq %rcx<br>
+ ; CHECK: popq %rax<br>
+ ; CHECK: addq $8, %rsp<br>
+ ; CHECK: iretq<br>
+ ; CHECK0-LABEL: test_isr_ecode<br>
+ ; CHECK0: pushq %rax<br>
+ ; CHECK0: pushq %rcx<br>
+ ; CHECK0: movq 16(%rsp), %rax<br>
+ ; CHECK0: leaq 24(%rsp), %rcx<br>
+ ; CHECK0: movq 16(%rcx), %rcx<br>
+ ; CHECK0: popq %rcx<br>
+ ; CHECK0: popq %rax<br>
+ ; CHECK0: addq $8, %rsp<br>
+ ; CHECK0: iretq<br>
+ %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2<br>
+ %flags = load i64, i64* %pflags, align 4<br>
+ call void asm sideeffect "", "r,r"(i64 %flags, i64 %ecode)<br>
+ ret void<br>
+}<br>
+<br>
+; All clobbered registers must be saved<br>
+define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i64 %ecode) {<br>
+ call void asm sideeffect "", "~{rax},~{rbx},~{rbp},~{r11},~{xmm0}"()<br>
+ ; CHECK-LABEL: test_isr_clobbers<br>
+ ; CHECK-SSE-NEXT: pushq %rax<br>
+ ; CHECK-SSE-NEXT; pushq %r11<br>
+ ; CHECK-SSE-NEXT: pushq %rbp<br>
+ ; CHECK-SSE-NEXT: pushq %rbx<br>
+ ; CHECK-SSE-NEXT: movaps %xmm0<br>
+ ; CHECK-SSE-NEXT: movaps %xmm0<br>
+ ; CHECK-SSE-NEXT: popq %rbx<br>
+ ; CHECK-SSE-NEXT: popq %rbp<br>
+ ; CHECK-SSE-NEXT: popq %r11<br>
+ ; CHECK-SSE-NEXT: popq %rax<br>
+ ; CHECK-SSE-NEXT: addq $8, %rsp<br>
+ ; CHECK-SSE-NEXT: iretq<br>
+ ; CHECK0-LABEL: test_isr_clobbers<br>
+ ; CHECK0-SSE-NEXT: pushq %rax<br>
+ ; CHECK0-SSE-NEXT; pushq %r11<br>
+ ; CHECK0-SSE-NEXT: pushq %rbp<br>
+ ; CHECK0-SSE-NEXT: pushq %rbx<br>
+ ; CHECK0-SSE-NEXT: movaps %xmm0<br>
+ ; CHECK0-SSE-NEXT: movaps %xmm0<br>
+ ; CHECK0-SSE-NEXT: popq %rbx<br>
+ ; CHECK0-SSE-NEXT: popq %rbp<br>
+ ; CHECK0-SSE-NEXT: popq %r11<br>
+ ; CHECK0-SSE-NEXT: popq %rax<br>
+ ; CHECK0-SSE-NEXT: addq $8, %rsp<br>
+ ; CHECK0-SSE-NEXT: iretq<br>
+ ret void<br>
+}<br>
\ No newline at end of file<br>
<br>
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