That makes sense to me. LGTM!<br><div class="gmail_quote"><div dir="ltr">On Wed, 16 Dec 2015 at 16:10, Matthew Simpson via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">mssimpso updated this revision to Diff 43012.<br>
mssimpso added a comment.<br>
<br>
Type checking.<br>
<br>
<br>
<a href="http://reviews.llvm.org/D15515" rel="noreferrer" target="_blank">http://reviews.llvm.org/D15515</a><br>
<br>
Files:<br>
lib/Target/AArch64/AArch64ISelLowering.cpp<br>
test/CodeGen/AArch64/arm64-neon-copy.ll<br>
<br>
Index: test/CodeGen/AArch64/arm64-neon-copy.ll<br>
===================================================================<br>
--- test/CodeGen/AArch64/arm64-neon-copy.ll<br>
+++ test/CodeGen/AArch64/arm64-neon-copy.ll<br>
@@ -320,21 +320,20 @@<br>
ret i32 %tmp5<br>
}<br>
<br>
-define i32 @smovx16b(<16 x i8> %tmp1) {<br>
+define i64 @smovx16b(<16 x i8> %tmp1) {<br>
; CHECK-LABEL: smovx16b:<br>
-; CHECK: smov {{[xw][0-9]+}}, {{v[0-9]+}}.b[8]<br>
+; CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.b[8]<br>
%tmp3 = extractelement <16 x i8> %tmp1, i32 8<br>
- %tmp4 = sext i8 %tmp3 to i32<br>
- %tmp5 = add i32 %tmp4, %tmp4<br>
- ret i32 %tmp5<br>
+ %tmp4 = sext i8 %tmp3 to i64<br>
+ ret i64 %tmp4<br>
}<br>
<br>
-define i32 @smovx8h(<8 x i16> %tmp1) {<br>
+define i64 @smovx8h(<8 x i16> %tmp1) {<br>
; CHECK-LABEL: smovx8h:<br>
-; CHECK: smov {{[xw][0-9]+}}, {{v[0-9]+}}.h[2]<br>
+; CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.h[2]<br>
%tmp3 = extractelement <8 x i16> %tmp1, i32 2<br>
- %tmp4 = sext i16 %tmp3 to i32<br>
- ret i32 %tmp4<br>
+ %tmp4 = sext i16 %tmp3 to i64<br>
+ ret i64 %tmp4<br>
}<br>
<br>
define i64 @smovx4s(<4 x i32> %tmp1) {<br>
Index: lib/Target/AArch64/AArch64ISelLowering.cpp<br>
===================================================================<br>
--- lib/Target/AArch64/AArch64ISelLowering.cpp<br>
+++ lib/Target/AArch64/AArch64ISelLowering.cpp<br>
@@ -8437,6 +8437,25 @@<br>
}<br>
}<br>
<br>
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();<br>
+<br>
+ // If we see (any_extend (extract_vector_element v, i)), we can potentially<br>
+ // remove the extend and promote the extract. We can do this if the vector<br>
+ // type is legal and if the result is sign extended from the element type.<br>
+ if (DCI.isAfterLegalizeVectorOps() && N->getOpcode() == ISD::ANY_EXTEND &&<br>
+ N->hasOneUse() && N->use_begin()->getOpcode() == ISD::SIGN_EXTEND_INREG) {<br>
+ const SDValue &M = N->getOperand(0);<br>
+ if (M.getNode()->hasOneUse() && M.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {<br>
+ EVT DstTy = N->getValueType(0);<br>
+ EVT SrcTy = cast<VTSDNode>(N->use_begin()->getOperand(1))->getVT();<br>
+ EVT VecTy = M.getOperand(0).getValueType();<br>
+ EVT ElmTy = VecTy.getScalarType();<br>
+ if (TLI.isTypeLegal(VecTy) && SrcTy == ElmTy)<br>
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), DstTy,<br>
+ M.getOperand(0), M.getOperand(1));<br>
+ }<br>
+ }<br>
+<br>
// This is effectively a custom type legalization for AArch64.<br>
//<br>
// Type legalization will split an extend of a small, legal, type to a larger<br>
@@ -8467,7 +8486,6 @@<br>
// We're only interested in cleaning things up for non-legal vector types<br>
// here. If both the source and destination are legal, things will just<br>
// work naturally without any fiddling.<br>
- const TargetLowering &TLI = DAG.getTargetLoweringInfo();<br>
EVT ResVT = N->getValueType(0);<br>
if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))<br>
return SDValue();<br>
<br>
<br>
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</blockquote></div>