<div dir="ltr">This broke an ARM encoding test on some Windows bots:<div><a href="http://bb.pgr.jp/builders/ninja-clang-i686-msc18-R/builds/4722">http://bb.pgr.jp/builders/ninja-clang-i686-msc18-R/builds/4722</a><br></div><div><a href="http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/5140">http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/5140</a><br></div><div><br></div><div>The first bot indicates that the test fails with MSVC alone, and the second indicates that it fails with a self-hosted clang-cl. The test passes on MinGW, so the failure is probably somehow MSVC-related, either in the C runtime libraries, or in the C++ ABI. This could be a different unstable sorting algorithm, different bitfield behavior, or different argument evaluation order.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Dec 16, 2015 at 3:35 AM, Oliver Stannard via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: olista01<br>
Date: Wed Dec 16 05:35:44 2015<br>
New Revision: 255762<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=255762&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=255762&view=rev</a><br>
Log:<br>
[ARM] Add ARMv8.2-A FP16 scalar instructions<br>
<br>
ARMv8.2-A adds 16-bit floating point versions of all existing VFP<br>
floating-point instructions. This is an optional extension, so all of<br>
these instructions require the FeatureFullFP16 subtarget feature.<br>
<br>
The assembly for these instructions uses S registers (AArch32 does not<br>
have H registers), but the instructions have ".f16" type specifiers<br>
rather than ".f32" or ".f64". The top 16 bits of each source register<br>
are ignored, and the top 16 bits of the destination register are set to<br>
zero.<br>
<br>
These instructions are mostly the same as the 32- and 64-bit versions,<br>
but they use coprocessor 9 rather than 10 and 11.<br>
<br>
Two new instructions, VMOVX and VINS, have been added to allow packing<br>
and extracting two 16-bit floats stored in the top and bottom halves of<br>
an S register.<br>
<br>
New fixup kinds have been added for the PC-relative load and store<br>
instructions, but no ELF relocations have been added as they have a<br>
range of 512 bytes.<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D15038" rel="noreferrer" target="_blank">http://reviews.llvm.org/D15038</a><br>
<br>
<br>
Added:<br>
    llvm/trunk/test/MC/ARM/fullfp16-neg.s<br>
    llvm/trunk/test/MC/ARM/fullfp16.s<br>
    llvm/trunk/test/MC/Disassembler/ARM/fullfp16-arm-neg.txt<br>
    llvm/trunk/test/MC/Disassembler/ARM/fullfp16-arm.txt<br>
    llvm/trunk/test/MC/Disassembler/ARM/fullfp16-thumb-neg.txt<br>
    llvm/trunk/test/MC/Disassembler/ARM/fullfp16-thumb.txt<br>
Modified:<br>
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td<br>
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td<br>
    llvm/trunk/lib/Target/ARM/ARMSchedule.td<br>
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br>
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp<br>
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h<br>
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h<br>
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp<br>
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h<br>
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=255762&r1=255761&r2=255762&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=255762&r1=255761&r2=255762&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Dec 16 05:35:44 2015<br>
@@ -1495,6 +1495,32 @@ class ASI5<bits<4> opcod1, bits<2> opcod<br>
   let D = VFPNeonDomain;<br>
 }<br>
<br>
+class AHI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,<br>
+           InstrItinClass itin,<br>
+           string opc, string asm, list<dag> pattern><br>
+  : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,<br>
+         VFPLdStFrm, itin, opc, asm, "", pattern> {<br>
+  list<Predicate> Predicates = [HasFullFP16];<br>
+<br>
+  // Instruction operands.<br>
+  bits<5>  Sd;<br>
+  bits<13> addr;<br>
+<br>
+  // Encode instruction operands.<br>
+  let Inst{23}    = addr{8};      // U (add = (U == '1'))<br>
+  let Inst{22}    = Sd{0};<br>
+  let Inst{19-16} = addr{12-9};   // Rn<br>
+  let Inst{15-12} = Sd{4-1};<br>
+  let Inst{7-0}   = addr{7-0};    // imm8<br>
+<br>
+  let Inst{27-24} = opcod1;<br>
+  let Inst{21-20} = opcod2;<br>
+  let Inst{11-8}  = 0b1001;     // Half precision<br>
+<br>
+  // Loads & stores operate on both NEON and VFP pipelines.<br>
+  let D = VFPNeonDomain;<br>
+}<br>
+<br>
 // VFP Load / store multiple pseudo instructions.<br>
 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,<br>
                      list<dag> pattern><br>
@@ -1817,6 +1843,114 @@ class ASbIn<bits<5> opcod1, bits<2> opco<br>
   let Inst{22}    = Sd{0};<br>
 }<br>
<br>
+// Half precision, unary, predicated<br>
+class AHuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,<br>
+           bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,<br>
+           string asm, list<dag> pattern><br>
+  : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {<br>
+  list<Predicate> Predicates = [HasFullFP16];<br>
+<br>
+  // Instruction operands.<br>
+  bits<5> Sd;<br>
+  bits<5> Sm;<br>
+<br>
+  // Encode instruction operands.<br>
+  let Inst{3-0}   = Sm{4-1};<br>
+  let Inst{5}     = Sm{0};<br>
+  let Inst{15-12} = Sd{4-1};<br>
+  let Inst{22}    = Sd{0};<br>
+<br>
+  let Inst{27-23} = opcod1;<br>
+  let Inst{21-20} = opcod2;<br>
+  let Inst{19-16} = opcod3;<br>
+  let Inst{11-8}  = 0b1001;   // Half precision<br>
+  let Inst{7-6}   = opcod4;<br>
+  let Inst{4}     = opcod5;<br>
+}<br>
+<br>
+// Half precision, unary, non-predicated<br>
+class AHuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,<br>
+             bit opcod5, dag oops, dag iops, InstrItinClass itin,<br>
+             string asm, list<dag> pattern><br>
+  : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,<br>
+          VFPUnaryFrm, itin, asm, "", pattern> {<br>
+  list<Predicate> Predicates = [HasFullFP16];<br>
+<br>
+  // Instruction operands.<br>
+  bits<5> Sd;<br>
+  bits<5> Sm;<br>
+<br>
+  let Inst{31-28} = 0b1111;<br>
+<br>
+  // Encode instruction operands.<br>
+  let Inst{3-0}   = Sm{4-1};<br>
+  let Inst{5}     = Sm{0};<br>
+  let Inst{15-12} = Sd{4-1};<br>
+  let Inst{22}    = Sd{0};<br>
+<br>
+  let Inst{27-23} = opcod1;<br>
+  let Inst{21-20} = opcod2;<br>
+  let Inst{19-16} = opcod3;<br>
+  let Inst{11-8}  = 0b1001;   // Half precision<br>
+  let Inst{7-6}   = opcod4;<br>
+  let Inst{4}     = opcod5;<br>
+}<br>
+<br>
+// Half precision, binary<br>
+class AHbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,<br>
+           InstrItinClass itin, string opc, string asm, list<dag> pattern><br>
+  : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {<br>
+  list<Predicate> Predicates = [HasFullFP16];<br>
+<br>
+  // Instruction operands.<br>
+  bits<5> Sd;<br>
+  bits<5> Sn;<br>
+  bits<5> Sm;<br>
+<br>
+  // Encode instruction operands.<br>
+  let Inst{3-0}   = Sm{4-1};<br>
+  let Inst{5}     = Sm{0};<br>
+  let Inst{19-16} = Sn{4-1};<br>
+  let Inst{7}     = Sn{0};<br>
+  let Inst{15-12} = Sd{4-1};<br>
+  let Inst{22}    = Sd{0};<br>
+<br>
+  let Inst{27-23} = opcod1;<br>
+  let Inst{21-20} = opcod2;<br>
+  let Inst{11-8}  = 0b1001;   // Half precision<br>
+  let Inst{6}     = op6;<br>
+  let Inst{4}     = op4;<br>
+}<br>
+<br>
+// Half precision, binary, not predicated<br>
+class AHbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,<br>
+           InstrItinClass itin, string asm, list<dag> pattern><br>
+  : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,<br>
+          VFPBinaryFrm, itin, asm, "", pattern> {<br>
+  list<Predicate> Predicates = [HasFullFP16];<br>
+<br>
+  // Instruction operands.<br>
+  bits<5> Sd;<br>
+  bits<5> Sn;<br>
+  bits<5> Sm;<br>
+<br>
+  let Inst{31-28} = 0b1111;<br>
+<br>
+  // Encode instruction operands.<br>
+  let Inst{3-0}   = Sm{4-1};<br>
+  let Inst{5}     = Sm{0};<br>
+  let Inst{19-16} = Sn{4-1};<br>
+  let Inst{7}     = Sn{0};<br>
+  let Inst{15-12} = Sd{4-1};<br>
+  let Inst{22}    = Sd{0};<br>
+<br>
+  let Inst{27-23} = opcod1;<br>
+  let Inst{21-20} = opcod2;<br>
+  let Inst{11-8}  = 0b1001;   // Half precision<br>
+  let Inst{6}     = opcod3;<br>
+  let Inst{4}     = 0;<br>
+}<br>
+<br>
 // VFP conversion instructions<br>
 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,<br>
                dag oops, dag iops, InstrItinClass itin, string opc, string asm,<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=255762&r1=255761&r2=255762&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=255762&r1=255761&r2=255762&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Dec 16 05:35:44 2015<br>
@@ -981,6 +981,21 @@ def addrmode5_pre : AddrMode5 {<br>
    let PrintMethod = "printAddrMode5Operand<true>";<br>
 }<br>
<br>
+// addrmode5fp16 := reg +/- imm8*2<br>
+//<br>
+def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; }<br>
+class AddrMode5FP16 : Operand<i32>,<br>
+                      ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> {<br>
+  let EncoderMethod = "getAddrMode5FP16OpValue";<br>
+  let DecoderMethod = "DecodeAddrMode5FP16Operand";<br>
+  let ParserMatchClass = AddrMode5FP16AsmOperand;<br>
+  let MIOperandInfo = (ops GPR:$base, i32imm);<br>
+}<br>
+<br>
+def addrmode5fp16 : AddrMode5FP16 {<br>
+   let PrintMethod = "printAddrMode5FP16Operand<false>";<br>
+}<br>
+<br>
 // addrmode6 := reg with optional alignment<br>
 //<br>
 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=255762&r1=255761&r2=255762&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=255762&r1=255761&r2=255762&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Wed Dec 16 05:35:44 2015<br>
@@ -30,6 +30,18 @@ def FPImmOperand : AsmOperandClass {<br>
   let ParserMethod = "parseFPImm";<br>
 }<br>
<br>
+def vfp_f16imm : Operand<f16>,<br>
+                 PatLeaf<(f16 fpimm), [{<br>
+      return ARM_AM::getFP16Imm(N->getValueAPF()) != -1;<br>
+    }], SDNodeXForm<fpimm, [{<br>
+      APFloat InVal = N->getValueAPF();<br>
+      uint32_t enc = ARM_AM::getFP16Imm(InVal);<br>
+      return CurDAG->getTargetConstant(enc, MVT::i32);<br>
+    }]>> {<br>
+  let PrintMethod = "printFPImmOperand";<br>
+  let ParserMatchClass = FPImmOperand;<br>
+}<br>
+<br>
 def vfp_f32imm : Operand<f32>,<br>
                  PatLeaf<(f32 fpimm), [{<br>
       return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;<br>
@@ -98,6 +110,11 @@ def VLDRS : ASI5<0b1101, 0b01, (outs SPR<br>
   let D = VFPNeonDomain;<br>
 }<br>
<br>
+def VLDRH : AHI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5fp16:$addr),<br>
+                 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr",<br>
+                 []>,<br>
+            Requires<[HasFullFP16]>;<br>
+<br>
 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'<br>
<br>
 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),<br>
@@ -112,6 +129,11 @@ def VSTRS : ASI5<0b1101, 0b00, (outs), (<br>
   let D = VFPNeonDomain;<br>
 }<br>
<br>
+def VSTRH : AHI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5fp16:$addr),<br>
+                 IIC_fpStore16, "vstr", ".16\t$Sd, $addr",<br>
+                 []>,<br>
+            Requires<[HasFullFP16]>;<br>
+<br>
 //===----------------------------------------------------------------------===//<br>
 //  Load / store multiple Instructions.<br>
 //<br>
@@ -295,6 +317,12 @@ def VADDS  : ASbIn<0b11100, 0b11, 0, 0,<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
<br>
+let TwoOperandAliasConstraint = "$Sn = $Sd" in<br>
+def VADDH  : AHbI<0b11100, 0b11, 0, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm",<br>
+                  []>;<br>
+<br>
 let TwoOperandAliasConstraint = "$Dn = $Dd" in<br>
 def VSUBD  : ADbI<0b11100, 0b11, 1, 0,<br>
                   (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),<br>
@@ -311,6 +339,12 @@ def VSUBS  : ASbIn<0b11100, 0b11, 1, 0,<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
<br>
+let TwoOperandAliasConstraint = "$Sn = $Sd" in<br>
+def VSUBH  : AHbI<0b11100, 0b11, 1, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",<br>
+                  []>;<br>
+<br>
 let TwoOperandAliasConstraint = "$Dn = $Dd" in<br>
 def VDIVD  : ADbI<0b11101, 0b00, 0, 0,<br>
                   (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),<br>
@@ -323,6 +357,12 @@ def VDIVS  : ASbI<0b11101, 0b00, 0, 0,<br>
                   IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",<br>
                   [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;<br>
<br>
+let TwoOperandAliasConstraint = "$Sn = $Sd" in<br>
+def VDIVH  : AHbI<0b11101, 0b00, 0, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm",<br>
+                  []>;<br>
+<br>
 let TwoOperandAliasConstraint = "$Dn = $Dd" in<br>
 def VMULD  : ADbI<0b11100, 0b10, 0, 0,<br>
                   (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),<br>
@@ -339,6 +379,12 @@ def VMULS  : ASbIn<0b11100, 0b10, 0, 0,<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
<br>
+let TwoOperandAliasConstraint = "$Sn = $Sd" in<br>
+def VMULH  : AHbI<0b11100, 0b10, 0, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm",<br>
+                  []>;<br>
+<br>
 def VNMULD : ADbI<0b11100, 0b10, 1, 0,<br>
                   (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),<br>
                   IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",<br>
@@ -353,9 +399,20 @@ def VNMULS : ASbI<0b11100, 0b10, 1, 0,<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
<br>
+def VNMULH : AHbI<0b11100, 0b10, 1, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",<br>
+                  []>;<br>
+<br>
 multiclass vsel_inst<string op, bits<2> opc, int CC> {<br>
   let DecoderNamespace = "VFPV8", PostEncoderMethod = "",<br>
       Uses = [CPSR], AddedComplexity = 4 in {<br>
+    def H : AHbInp<0b11100, opc, 0,<br>
+                   (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),<br>
+                   NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),<br>
+                   []>,<br>
+                   Requires<[HasFullFP16]>;<br>
+<br>
     def S : ASbInp<0b11100, opc, 0,<br>
                    (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),<br>
                    NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),<br>
@@ -378,6 +435,12 @@ defm VSELVS : vsel_inst<"vs", 0b01, 6>;<br>
<br>
 multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {<br>
   let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {<br>
+    def H : AHbInp<0b11101, 0b00, opc,<br>
+                   (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),<br>
+                   NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"),<br>
+                   []>,<br>
+                   Requires<[HasFullFP16]>;<br>
+<br>
     def S : ASbInp<0b11101, 0b00, opc,<br>
                    (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),<br>
                    NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),<br>
@@ -418,6 +481,12 @@ def VCMPES : ASuI<0b11101, 0b11, 0b0100,<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
<br>
+def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0,<br>
+                  (outs), (ins SPR:$Sd, SPR:$Sm),<br>
+                  IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",<br>
+                  []>;<br>
+<br>
+<br>
 // FIXME: Verify encoding after integrated assembler is working.<br>
 def VCMPD  : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,<br>
                   (outs), (ins DPR:$Dd, DPR:$Dm),<br>
@@ -432,6 +501,11 @@ def VCMPS  : ASuI<0b11101, 0b11, 0b0100,<br>
   // VFP pipelines on A8.<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
+<br>
+def VCMPH  : AHuI<0b11101, 0b11, 0b0100, 0b01, 0,<br>
+                  (outs), (ins SPR:$Sd, SPR:$Sm),<br>
+                  IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm",<br>
+                  []>;<br>
 } // Defs = [FPSCR_NZCV]<br>
<br>
 //===----------------------------------------------------------------------===//<br>
@@ -452,6 +526,11 @@ def VABSS  : ASuIn<0b11101, 0b11, 0b0000<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
<br>
+def VABSH  : AHuI<0b11101, 0b11, 0b0000, 0b11, 0,<br>
+                   (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                   IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm",<br>
+                   []>;<br>
+<br>
 let Defs = [FPSCR_NZCV] in {<br>
 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,<br>
                    (outs), (ins DPR:$Dd),<br>
@@ -473,6 +552,14 @@ def VCMPEZS : ASuI<0b11101, 0b11, 0b0101<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
<br>
+def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0,<br>
+                   (outs), (ins SPR:$Sd),<br>
+                   IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0",<br>
+                   []> {<br>
+  let Inst{3-0} = 0b0000;<br>
+  let Inst{5}   = 0;<br>
+}<br>
+<br>
 // FIXME: Verify encoding after integrated assembler is working.<br>
 def VCMPZD  : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,<br>
                    (outs), (ins DPR:$Dd),<br>
@@ -493,6 +580,14 @@ def VCMPZS  : ASuI<0b11101, 0b11, 0b0101<br>
   // VFP pipelines on A8.<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
+<br>
+def VCMPZH  : AHuI<0b11101, 0b11, 0b0101, 0b01, 0,<br>
+                   (outs), (ins SPR:$Sd),<br>
+                   IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0",<br>
+                   []> {<br>
+  let Inst{3-0} = 0b0000;<br>
+  let Inst{5}   = 0;<br>
+}<br>
 } // Defs = [FPSCR_NZCV]<br>
<br>
 def VCVTDS  : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,<br>
@@ -627,6 +722,22 @@ def : Pat<(f64 (f16_to_fp GPR:$a)),<br>
 multiclass vcvt_inst<string opc, bits<2> rm,<br>
                      SDPatternOperator node = null_frag> {<br>
   let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {<br>
+    def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0,<br>
+                    (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                    NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"),<br>
+                    []>,<br>
+                    Requires<[HasFullFP16]> {<br>
+      let Inst{17-16} = rm;<br>
+    }<br>
+<br>
+    def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0,<br>
+                    (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                    NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"),<br>
+                    []>,<br>
+                    Requires<[HasFullFP16]> {<br>
+      let Inst{17-16} = rm;<br>
+    }<br>
+<br>
     def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,<br>
                     (outs SPR:$Sd), (ins SPR:$Sm),<br>
                     NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),<br>
@@ -715,7 +826,21 @@ def VNEGS  : ASuIn<0b11101, 0b11, 0b0001<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
<br>
+def VNEGH  : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                  IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",<br>
+                  []>;<br>
+<br>
 multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {<br>
+  def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0,<br>
+               (outs SPR:$Sd), (ins SPR:$Sm),<br>
+               NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",<br>
+               []>,<br>
+               Requires<[HasFullFP16]> {<br>
+    let Inst{7} = op2;<br>
+    let Inst{16} = op;<br>
+  }<br>
+<br>
   def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,<br>
                (outs SPR:$Sd), (ins SPR:$Sm),<br>
                NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",<br>
@@ -733,6 +858,9 @@ multiclass vrint_inst_zrx<string opc, bi<br>
     let Inst{16} = op;<br>
   }<br>
<br>
+  def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"),<br>
+                  (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p)>,<br>
+        Requires<[HasFullFP16]>;<br>
   def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),<br>
                   (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,<br>
         Requires<[HasFPARMv8]>;<br>
@@ -748,6 +876,13 @@ defm VRINTX : vrint_inst_zrx<"x", 1, 0,<br>
 multiclass vrint_inst_anpm<string opc, bits<2> rm,<br>
                            SDPatternOperator node = null_frag> {<br>
   let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {<br>
+    def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0,<br>
+                   (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                   NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),<br>
+                   []>,<br>
+                   Requires<[HasFullFP16]> {<br>
+      let Inst{17-16} = rm;<br>
+    }<br>
     def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,<br>
                    (outs SPR:$Sd), (ins SPR:$Sm),<br>
                    NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),<br>
@@ -787,6 +922,11 @@ def VSQRTS : ASuI<0b11101, 0b11, 0b0001,<br>
                   IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",<br>
                   [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;<br>
<br>
+def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                  IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm",<br>
+                  []>;<br>
+<br>
 let hasSideEffects = 0 in {<br>
 def VMOVD  : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,<br>
                   (outs DPR:$Dd), (ins DPR:$Dm),<br>
@@ -795,6 +935,18 @@ def VMOVD  : ADuI<0b11101, 0b11, 0b0000,<br>
 def VMOVS  : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,<br>
                   (outs SPR:$Sd), (ins SPR:$Sm),<br>
                   IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;<br>
+<br>
+let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {<br>
+def VMOVH  : ASuInp<0b11101, 0b11, 0b0000, 0b01, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                  IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>,<br>
+             Requires<[HasFullFP16]>;<br>
+<br>
+def VINSH  : ASuInp<0b11101, 0b11, 0b0000, 0b11, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                  IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>,<br>
+             Requires<[HasFullFP16]>;<br>
+} // PostEncoderMethod<br>
 } // hasSideEffects<br>
<br>
 //===----------------------------------------------------------------------===//<br>
@@ -966,6 +1118,44 @@ def VMOVSRR : AVConv5I<0b11000100, 0b101<br>
   let DecoderMethod = "DecodeVMOVSRR";<br>
 }<br>
<br>
+// Move H->R, clearing top 16 bits<br>
+def VMOVRH : AVConv2I<0b11100001, 0b1001,<br>
+                      (outs GPR:$Rt), (ins SPR:$Sn),<br>
+                      IIC_fpMOVSI, "vmov", ".f16\t$Rt, $Sn",<br>
+                      []>,<br>
+             Requires<[HasFullFP16]> {<br>
+  // Instruction operands.<br>
+  bits<4> Rt;<br>
+  bits<5> Sn;<br>
+<br>
+  // Encode instruction operands.<br>
+  let Inst{19-16} = Sn{4-1};<br>
+  let Inst{7}     = Sn{0};<br>
+  let Inst{15-12} = Rt;<br>
+<br>
+  let Inst{6-5}   = 0b00;<br>
+  let Inst{3-0}   = 0b0000;<br>
+}<br>
+<br>
+// Move R->H, clearing top 16 bits<br>
+def VMOVHR : AVConv4I<0b11100000, 0b1001,<br>
+                      (outs SPR:$Sn), (ins GPR:$Rt),<br>
+                      IIC_fpMOVIS, "vmov", ".f16\t$Sn, $Rt",<br>
+                      []>,<br>
+             Requires<[HasFullFP16]> {<br>
+  // Instruction operands.<br>
+  bits<5> Sn;<br>
+  bits<4> Rt;<br>
+<br>
+  // Encode instruction operands.<br>
+  let Inst{19-16} = Sn{4-1};<br>
+  let Inst{7}     = Sn{0};<br>
+  let Inst{15-12} = Rt;<br>
+<br>
+  let Inst{6-5}   = 0b00;<br>
+  let Inst{3-0}   = 0b0000;<br>
+}<br>
+<br>
 // FMRDH: SPR -> GPR<br>
 // FMRDL: SPR -> GPR<br>
 // FMRRS: SPR -> GPR<br>
@@ -1011,6 +1201,25 @@ class AVConv1InSs_Encode<bits<5> opcod1,<br>
   let Inst{22}    = Sd{0};<br>
 }<br>
<br>
+class AVConv1IHs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,<br>
+                        bits<4> opcod4, dag oops, dag iops,<br>
+                        InstrItinClass itin, string opc, string asm,<br>
+                        list<dag> pattern><br>
+  : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,<br>
+             pattern> {<br>
+  // Instruction operands.<br>
+  bits<5> Sd;<br>
+  bits<5> Sm;<br>
+<br>
+  // Encode instruction operands.<br>
+  let Inst{3-0}   = Sm{4-1};<br>
+  let Inst{5}     = Sm{0};<br>
+  let Inst{15-12} = Sd{4-1};<br>
+  let Inst{22}    = Sd{0};<br>
+<br>
+  let Predicates = [HasFullFP16];<br>
+}<br>
+<br>
 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,<br>
                                (outs DPR:$Dd), (ins SPR:$Sm),<br>
                                IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",<br>
@@ -1043,6 +1252,13 @@ def : VFPNoNEONPat<(f32 (sint_to_fp GPR:<br>
 def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))),<br>
                    (VSITOS (VLDRS addrmode5:$a))>;<br>
<br>
+def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,<br>
+                               (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                               IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm",<br>
+                               []> {<br>
+  let Inst{7} = 1; // s32<br>
+}<br>
+<br>
 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,<br>
                                (outs DPR:$Dd), (ins SPR:$Sm),<br>
                                IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",<br>
@@ -1075,6 +1291,13 @@ def : VFPNoNEONPat<(f32 (uint_to_fp GPR:<br>
 def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))),<br>
                    (VUITOS (VLDRS addrmode5:$a))>;<br>
<br>
+def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,<br>
+                                (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                                IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm",<br>
+                                []> {<br>
+  let Inst{7} = 0; // u32<br>
+}<br>
+<br>
 // FP -> Int:<br>
<br>
 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,<br>
@@ -1113,6 +1336,25 @@ class AVConv1InsS_Encode<bits<5> opcod1,<br>
   let Inst{22}    = Sd{0};<br>
 }<br>
<br>
+class AVConv1IsH_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,<br>
+                         bits<4> opcod4, dag oops, dag iops,<br>
+                         InstrItinClass itin, string opc, string asm,<br>
+                         list<dag> pattern><br>
+  : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,<br>
+              pattern> {<br>
+  // Instruction operands.<br>
+  bits<5> Sd;<br>
+  bits<5> Sm;<br>
+<br>
+  // Encode instruction operands.<br>
+  let Inst{3-0}   = Sm{4-1};<br>
+  let Inst{5}     = Sm{0};<br>
+  let Inst{15-12} = Sd{4-1};<br>
+  let Inst{22}    = Sd{0};<br>
+<br>
+  let Predicates = [HasFullFP16];<br>
+}<br>
+<br>
 // Always set Z bit in the instruction, i.e. "round towards zero" variants.<br>
 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,<br>
                                 (outs SPR:$Sd), (ins DPR:$Dm),<br>
@@ -1147,6 +1389,13 @@ def : VFPNoNEONPat<(alignedstore32 (i32<br>
                                    addrmode5:$ptr),<br>
                    (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;<br>
<br>
+def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,<br>
+                                 (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                                 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",<br>
+                                 []> {<br>
+  let Inst{7} = 1; // Z bit<br>
+}<br>
+<br>
 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,<br>
                                (outs SPR:$Sd), (ins DPR:$Dm),<br>
                                IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",<br>
@@ -1180,6 +1429,13 @@ def : VFPNoNEONPat<(alignedstore32 (i32<br>
                                    addrmode5:$ptr),<br>
                   (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;<br>
<br>
+def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,<br>
+                                 (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                                 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",<br>
+                                 []> {<br>
+  let Inst{7} = 1; // Z bit<br>
+}<br>
+<br>
 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.<br>
 let Uses = [FPSCR] in {<br>
 // FIXME: Verify encoding after integrated assembler is working.<br>
@@ -1197,6 +1453,13 @@ def VTOSIRS : AVConv1InsS_Encode<0b11101<br>
   let Inst{7} = 0; // Z bit<br>
 }<br>
<br>
+def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,<br>
+                                 (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                                 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm",<br>
+                                 []> {<br>
+  let Inst{7} = 0; // Z bit<br>
+}<br>
+<br>
 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,<br>
                                 (outs SPR:$Sd), (ins DPR:$Dm),<br>
                                 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",<br>
@@ -1210,6 +1473,13 @@ def VTOUIRS : AVConv1InsS_Encode<0b11101<br>
                                  [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {<br>
   let Inst{7} = 0; // Z bit<br>
 }<br>
+<br>
+def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,<br>
+                                 (outs SPR:$Sd), (ins SPR:$Sm),<br>
+                                 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm",<br>
+                                 []> {<br>
+  let Inst{7} = 0; // Z bit<br>
+}<br>
 }<br>
<br>
 // Convert between floating-point and fixed-point<br>
@@ -1249,6 +1519,26 @@ class AVConv1XInsD_Encode<bits<5> op1, b<br>
   let Predicates = [HasVFP2, HasDPVFP];<br>
 }<br>
<br>
+def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,<br>
+                       (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),<br>
+                 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>,<br>
+             Requires<[HasFullFP16]>;<br>
+<br>
+def VTOUHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 0,<br>
+                       (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),<br>
+                 IIC_fpCVTHI, "vcvt", ".u16.f16\t$dst, $a, $fbits", []>,<br>
+             Requires<[HasFullFP16]>;<br>
+<br>
+def VTOSLH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 1,<br>
+                       (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),<br>
+                 IIC_fpCVTHI, "vcvt", ".s32.f16\t$dst, $a, $fbits", []>,<br>
+             Requires<[HasFullFP16]>;<br>
+<br>
+def VTOULH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 1,<br>
+                       (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),<br>
+                 IIC_fpCVTHI, "vcvt", ".u32.f16\t$dst, $a, $fbits", []>,<br>
+             Requires<[HasFullFP16]>;<br>
+<br>
 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,<br>
                        (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),<br>
                  IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {<br>
@@ -1299,6 +1589,26 @@ def VTOULD : AVConv1XInsD_Encode<0b11101<br>
<br>
 // Fixed-Point to FP:<br>
<br>
+def VSHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 0,<br>
+                       (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),<br>
+                 IIC_fpCVTIH, "vcvt", ".f16.s16\t$dst, $a, $fbits", []>,<br>
+             Requires<[HasFullFP16]>;<br>
+<br>
+def VUHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 0,<br>
+                       (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),<br>
+                 IIC_fpCVTIH, "vcvt", ".f16.u16\t$dst, $a, $fbits", []>,<br>
+             Requires<[HasFullFP16]>;<br>
+<br>
+def VSLTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 1,<br>
+                       (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),<br>
+                 IIC_fpCVTIH, "vcvt", ".f16.s32\t$dst, $a, $fbits", []>,<br>
+             Requires<[HasFullFP16]>;<br>
+<br>
+def VULTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 1,<br>
+                       (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),<br>
+                 IIC_fpCVTIH, "vcvt", ".f16.u32\t$dst, $a, $fbits", []>,<br>
+             Requires<[HasFullFP16]>;<br>
+<br>
 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,<br>
                        (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),<br>
                  IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {<br>
@@ -1373,6 +1683,13 @@ def VMLAS : ASbIn<0b11100, 0b00, 0, 0,<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
<br>
+def VMLAH : AHbI<0b11100, 0b00, 0, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm",<br>
+                  []>,<br>
+              RegConstraint<"$Sdin = $Sd">,<br>
+              Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;<br>
+<br>
 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),<br>
           (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,<br>
           Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;<br>
@@ -1400,6 +1717,13 @@ def VMLSS : ASbIn<0b11100, 0b00, 1, 0,<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
<br>
+def VMLSH : AHbI<0b11100, 0b00, 1, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm",<br>
+                  []>,<br>
+              RegConstraint<"$Sdin = $Sd">,<br>
+              Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;<br>
+<br>
 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),<br>
           (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,<br>
           Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;<br>
@@ -1427,6 +1751,13 @@ def VNMLAS : ASbI<0b11100, 0b01, 1, 0,<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
<br>
+def VNMLAH : AHbI<0b11100, 0b01, 1, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm",<br>
+                  []>,<br>
+                RegConstraint<"$Sdin = $Sd">,<br>
+                Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;<br>
+<br>
 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),<br>
           (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,<br>
           Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;<br>
@@ -1453,6 +1784,13 @@ def VNMLSS : ASbI<0b11100, 0b01, 0, 0,<br>
   let D = VFPNeonA8Domain;<br>
 }<br>
<br>
+def VNMLSH : AHbI<0b11100, 0b01, 0, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm",<br>
+             []>,<br>
+                         RegConstraint<"$Sdin = $Sd">,<br>
+                Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;<br>
+<br>
 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),<br>
           (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,<br>
           Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;<br>
@@ -1482,6 +1820,13 @@ def VFMAS : ASbIn<0b11101, 0b10, 0, 0,<br>
   // VFP pipelines.<br>
 }<br>
<br>
+def VFMAH : AHbI<0b11101, 0b10, 0, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm",<br>
+                  []>,<br>
+              RegConstraint<"$Sdin = $Sd">,<br>
+              Requires<[HasFullFP16,UseFusedMAC]>;<br>
+<br>
 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),<br>
           (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,<br>
           Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;<br>
@@ -1517,6 +1862,13 @@ def VFMSS : ASbIn<0b11101, 0b10, 1, 0,<br>
   // VFP pipelines.<br>
 }<br>
<br>
+def VFMSH : AHbI<0b11101, 0b10, 1, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm",<br>
+                  []>,<br>
+              RegConstraint<"$Sdin = $Sd">,<br>
+              Requires<[HasFullFP16,UseFusedMAC]>;<br>
+<br>
 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),<br>
           (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,<br>
           Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;<br>
@@ -1559,6 +1911,13 @@ def VFNMAS : ASbI<0b11101, 0b01, 1, 0,<br>
   // VFP pipelines.<br>
 }<br>
<br>
+def VFNMAH : AHbI<0b11101, 0b01, 1, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm",<br>
+                  []>,<br>
+                RegConstraint<"$Sdin = $Sd">,<br>
+                Requires<[HasFullFP16,UseFusedMAC]>;<br>
+<br>
 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),<br>
           (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,<br>
           Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;<br>
@@ -1600,6 +1959,13 @@ def VFNMSS : ASbI<0b11101, 0b01, 0, 0,<br>
   // VFP pipelines.<br>
 }<br>
<br>
+def VFNMSH : AHbI<0b11101, 0b01, 0, 0,<br>
+                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),<br>
+                  IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm",<br>
+             []>,<br>
+                         RegConstraint<"$Sdin = $Sd">,<br>
+                  Requires<[HasFullFP16,UseFusedMAC]>;<br>
+<br>
 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),<br>
           (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,<br>
           Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;<br>
@@ -1780,6 +2146,23 @@ def FCONSTS : VFPAI<(outs SPR:$Sd), (ins<br>
   let Inst{7-4}   = 0b0000;<br>
   let Inst{3-0}   = imm{3-0};<br>
 }<br>
+<br>
+def FCONSTH : VFPAI<(outs SPR:$Sd), (ins vfp_f16imm:$imm),<br>
+                     VFPMiscFrm, IIC_fpUNA16,<br>
+                     "vmov", ".f16\t$Sd, $imm",<br>
+                     []>, Requires<[HasFullFP16]> {<br>
+  bits<5> Sd;<br>
+  bits<8> imm;<br>
+<br>
+  let Inst{27-23} = 0b11101;<br>
+  let Inst{22}    = Sd{0};<br>
+  let Inst{21-20} = 0b11;<br>
+  let Inst{19-16} = imm{7-4};<br>
+  let Inst{15-12} = Sd{4-1};<br>
+  let Inst{11-8}  = 0b1001;     // Half precision<br>
+  let Inst{7-4}   = 0b0000;<br>
+  let Inst{3-0}   = imm{3-0};<br>
+}<br>
 }<br>
<br>
 //===----------------------------------------------------------------------===//<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=255762&r1=255761&r2=255762&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=255762&r1=255761&r2=255762&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Wed Dec 16 05:35:44 2015<br>
@@ -186,38 +186,50 @@ def IIC_iStore_mu  : InstrItinClass;<br>
 def IIC_Preload    : InstrItinClass;<br>
 def IIC_Br         : InstrItinClass;<br>
 def IIC_fpSTAT     : InstrItinClass;<br>
+def IIC_fpUNA16    : InstrItinClass;<br>
 def IIC_fpUNA32    : InstrItinClass;<br>
 def IIC_fpUNA64    : InstrItinClass;<br>
+def IIC_fpCMP16    : InstrItinClass;<br>
 def IIC_fpCMP32    : InstrItinClass;<br>
 def IIC_fpCMP64    : InstrItinClass;<br>
 def IIC_fpCVTSD    : InstrItinClass;<br>
 def IIC_fpCVTDS    : InstrItinClass;<br>
 def IIC_fpCVTSH    : InstrItinClass;<br>
 def IIC_fpCVTHS    : InstrItinClass;<br>
+def IIC_fpCVTIH    : InstrItinClass;<br>
 def IIC_fpCVTIS    : InstrItinClass;<br>
 def IIC_fpCVTID    : InstrItinClass;<br>
+def IIC_fpCVTHI    : InstrItinClass;<br>
 def IIC_fpCVTSI    : InstrItinClass;<br>
 def IIC_fpCVTDI    : InstrItinClass;<br>
 def IIC_fpMOVIS    : InstrItinClass;<br>
 def IIC_fpMOVID    : InstrItinClass;<br>
 def IIC_fpMOVSI    : InstrItinClass;<br>
 def IIC_fpMOVDI    : InstrItinClass;<br>
+def IIC_fpALU16    : InstrItinClass;<br>
 def IIC_fpALU32    : InstrItinClass;<br>
 def IIC_fpALU64    : InstrItinClass;<br>
+def IIC_fpMUL16    : InstrItinClass;<br>
 def IIC_fpMUL32    : InstrItinClass;<br>
 def IIC_fpMUL64    : InstrItinClass;<br>
+def IIC_fpMAC16    : InstrItinClass;<br>
 def IIC_fpMAC32    : InstrItinClass;<br>
 def IIC_fpMAC64    : InstrItinClass;<br>
+def IIC_fpFMAC16   : InstrItinClass;<br>
 def IIC_fpFMAC32   : InstrItinClass;<br>
 def IIC_fpFMAC64   : InstrItinClass;<br>
+def IIC_fpDIV16    : InstrItinClass;<br>
 def IIC_fpDIV32    : InstrItinClass;<br>
 def IIC_fpDIV64    : InstrItinClass;<br>
+def IIC_fpSQRT16   : InstrItinClass;<br>
 def IIC_fpSQRT32   : InstrItinClass;<br>
 def IIC_fpSQRT64   : InstrItinClass;<br>
+def IIC_fpLoad16   : InstrItinClass;<br>
 def IIC_fpLoad32   : InstrItinClass;<br>
 def IIC_fpLoad64   : InstrItinClass;<br>
 def IIC_fpLoad_m   : InstrItinClass;<br>
 def IIC_fpLoad_mu  : InstrItinClass;<br>
+def IIC_fpStore16  : InstrItinClass;<br>
 def IIC_fpStore32  : InstrItinClass;<br>
 def IIC_fpStore64  : InstrItinClass;<br>
 def IIC_fpStore_m  : InstrItinClass;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=255762&r1=255761&r2=255762&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=255762&r1=255761&r2=255762&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Dec 16 05:35:44 2015<br>
@@ -1183,6 +1183,20 @@ public:<br>
     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||<br>
       Val == INT32_MIN;<br>
   }<br>
+  bool isAddrMode5FP16() const {<br>
+    // If we have an immediate that's not a constant, treat it as a label<br>
+    // reference needing a fixup. If it is a constant, it's something else<br>
+    // and we reject it.<br>
+    if (isImm() && !isa<MCConstantExpr>(getImm()))<br>
+      return true;<br>
+    if (!isMem() || Memory.Alignment != 0) return false;<br>
+    // Check for register offset.<br>
+    if (Memory.OffsetRegNum) return false;<br>
+    // Immediate offset in range [-510, 510] and a multiple of 2.<br>
+    if (!Memory.OffsetImm) return true;<br>
+    int64_t Val = Memory.OffsetImm->getValue();<br>
+    return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || Val == INT32_MIN;<br>
+  }<br>
   bool isMemTBB() const {<br>
     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||<br>
         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)<br>
@@ -2145,6 +2159,28 @@ public:<br>
     Inst.addOperand(MCOperand::createImm(Val));<br>
   }<br>
<br>
+  void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {<br>
+    assert(N == 2 && "Invalid number of operands!");<br>
+    // If we have an immediate that's not a constant, treat it as a label<br>
+    // reference needing a fixup. If it is a constant, it's something else<br>
+    // and we reject it.<br>
+    if (isImm()) {<br>
+      Inst.addOperand(MCOperand::createExpr(getImm()));<br>
+      Inst.addOperand(MCOperand::createImm(0));<br>
+      return;<br>
+    }<br>
+<br>
+    // The lower bit is always zero and as such is not encoded.<br>
+    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;<br>
+    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;<br>
+    // Special case for #-0<br>
+    if (Val == INT32_MIN) Val = 0;<br>
+    if (Val < 0) Val = -Val;<br>
+    Val = ARM_AM::getAM5FP16Opc(AddSub, Val);<br>
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));<br>
+    Inst.addOperand(MCOperand::createImm(Val));<br>
+  }<br>
+<br>
   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {<br>
     assert(N == 2 && "Invalid number of operands!");<br>
     // If we have an immediate that's not a constant, treat it as a label<br>
@@ -4973,7 +5009,8 @@ ARMAsmParser::parseFPImm(OperandVector &<br>
   // vmov.i{8|16|32|64} <dreg|qreg>, #imm<br>
   ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);<br>
   bool isVmovf = TyOp.isToken() &&<br>
-                 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");<br>
+                 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||<br>
+                  TyOp.getToken() == ".f16");<br>
   ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);<br>
   bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||<br>
                                          Mnemonic.getToken() == "fconsts");<br>
@@ -5265,7 +5302,7 @@ StringRef ARMAsmParser::splitMnemonic(St<br>
       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||<br>
       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||<br>
       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||<br>
-      Mnemonic.startswith("vsel"))<br>
+      Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx")<br>
     return Mnemonic;<br>
<br>
   // First, split out any predication code. Ignore mnemonics we know aren't<br>
@@ -5369,7 +5406,8 @@ void ARMAsmParser::getMnemonicAcceptInfo<br>
       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||<br>
       Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||<br>
       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||<br>
-      (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {<br>
+      (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||<br>
+      Mnemonic == "vmovx" || Mnemonic == "vins") {<br>
     // These mnemonics are never predicable<br>
     CanAcceptPredicationCode = false;<br>
   } else if (!isThumb()) {<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=255762&r1=255761&r2=255762&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=255762&r1=255761&r2=255762&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Dec 16 05:35:44 2015<br>
@@ -222,6 +222,8 @@ static DecodeStatus DecodeAddrModeImm12O<br>
                                uint64_t Address, const void *Decoder);<br>
 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,<br>
                                uint64_t Address, const void *Decoder);<br>
+static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,<br>
+                               uint64_t Address, const void *Decoder);<br>
 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,<br>
                                uint64_t Address, const void *Decoder);<br>
 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,<br>
@@ -2183,6 +2185,7 @@ static DecodeStatus DecodeAddrMode5Opera<br>
   DecodeStatus S = MCDisassembler::Success;<br>
<br>
   unsigned Rn = fieldFromInstruction(Val, 9, 4);<br>
+  // U == 1 to add imm, 0 to subtract it.<br>
   unsigned U = fieldFromInstruction(Val, 8, 1);<br>
   unsigned imm = fieldFromInstruction(Val, 0, 8);<br>
<br>
@@ -2196,6 +2199,26 @@ static DecodeStatus DecodeAddrMode5Opera<br>
<br>
   return S;<br>
 }<br>
+<br>
+static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,<br>
+                                   uint64_t Address, const void *Decoder) {<br>
+  DecodeStatus S = MCDisassembler::Success;<br>
+<br>
+  unsigned Rn = fieldFromInstruction(Val, 9, 4);<br>
+  // U == 1 to add imm, 0 to subtract it.<br>
+  unsigned U = fieldFromInstruction(Val, 8, 1);<br>
+  unsigned imm = fieldFromInstruction(Val, 0, 8);<br>
+<br>
+  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))<br>
+    return MCDisassembler::Fail;<br>
+<br>
+  if (U)<br>
+    Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));<br>
+  else<br>
+    Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));<br>
+<br>
+  return S;<br>
+}<br>
<br>
 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,<br>
                                    uint64_t Address, const void *Decoder) {<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=255762&r1=255761&r2=255762&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=255762&r1=255761&r2=255762&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Dec 16 05:35:44 2015<br>
@@ -644,6 +644,34 @@ void ARMInstPrinter::printAddrMode5Opera<br>
   O << "]" << markup(">");<br>
 }<br>
<br>
+template <bool AlwaysPrintImm0><br>
+void ARMInstPrinter::printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum,<br>
+                                               const MCSubtargetInfo &STI,<br>
+                                               raw_ostream &O) {<br>
+  const MCOperand &MO1 = MI->getOperand(OpNum);<br>
+  const MCOperand &MO2 = MI->getOperand(OpNum+1);<br>
+<br>
+  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.<br>
+    printOperand(MI, OpNum, STI, O);<br>
+    return;<br>
+  }<br>
+<br>
+  O << markup("<mem:") << "[";<br>
+  printRegName(O, MO1.getReg());<br>
+<br>
+  unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());<br>
+  unsigned Op = ARM_AM::getAM5FP16Op(MO2.getImm());<br>
+  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {<br>
+    O << ", "<br>
+      << markup("<imm:")<br>
+      << "#"<br>
+      << ARM_AM::getAddrOpcStr(ARM_AM::getAM5FP16Op(MO2.getImm()))<br>
+      << ImmOffs * 2<br>
+      << markup(">");<br>
+  }<br>
+  O << "]" << markup(">");<br>
+}<br>
+<br>
 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,<br>
                                            const MCSubtargetInfo &STI,<br>
                                            raw_ostream &O) {<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=255762&r1=255761&r2=255762&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=255762&r1=255761&r2=255762&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Wed Dec 16 05:35:44 2015<br>
@@ -74,6 +74,9 @@ public:<br>
   template <bool AlwaysPrintImm0><br>
   void printAddrMode5Operand(const MCInst *MI, unsigned OpNum,<br>
                              const MCSubtargetInfo &STI, raw_ostream &O);<br>
+  template <bool AlwaysPrintImm0><br>
+  void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum,<br>
+                                 const MCSubtargetInfo &STI, raw_ostream &O);<br>
   void printAddrMode6Operand(const MCInst *MI, unsigned OpNum,<br>
                              const MCSubtargetInfo &STI, raw_ostream &O);<br>
   void printAddrMode7Operand(const MCInst *MI, unsigned OpNum,<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h?rev=255762&r1=255761&r2=255762&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h?rev=255762&r1=255761&r2=255762&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h Wed Dec 16 05:35:44 2015<br>
@@ -486,7 +486,7 @@ namespace ARM_AM {<br>
   // addrmode5 := reg +/- imm8*4<br>
   //<br>
   // The first operand is always a Reg.  The second operand encodes the<br>
-  // operation in bit 8 and the immediate in bits 0-7.<br>
+  // operation (add or subtract) in bit 8 and the immediate in bits 0-7.<br>
<br>
   /// getAM5Opc - This function encodes the addrmode5 opc field.<br>
   static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {<br>
@@ -501,6 +501,29 @@ namespace ARM_AM {<br>
   }<br>
<br>
   //===--------------------------------------------------------------------===//<br>
+  // Addressing Mode #5 FP16<br>
+  //===--------------------------------------------------------------------===//<br>
+  //<br>
+  // This is used for coprocessor instructions, such as 16-bit FP load/stores.<br>
+  //<br>
+  // addrmode5fp16 := reg +/- imm8*2<br>
+  //<br>
+  // The first operand is always a Reg.  The second operand encodes the<br>
+  // operation (add or subtract) in bit 8 and the immediate in bits 0-7.<br>
+<br>
+  /// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.<br>
+  static inline unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset) {<br>
+    bool isSub = Opc == sub;<br>
+    return ((int)isSub << 8) | Offset;<br>
+  }<br>
+  static inline unsigned char getAM5FP16Offset(unsigned AM5Opc) {<br>
+    return AM5Opc & 0xFF;<br>
+  }<br>
+  static inline AddrOpc getAM5FP16Op(unsigned AM5Opc) {<br>
+    return ((AM5Opc >> 8) & 1) ? sub : add;<br>
+  }<br>
+<br>
+  //===--------------------------------------------------------------------===//<br>
   // Addressing Mode #6<br>
   //===--------------------------------------------------------------------===//<br>
   //<br>
@@ -650,6 +673,32 @@ namespace ARM_AM {<br>
     return FPUnion.F;<br>
   }<br>
<br>
+  /// getFP16Imm - Return an 8-bit floating-point version of the 16-bit<br>
+  /// floating-point value. If the value cannot be represented as an 8-bit<br>
+  /// floating-point value, then return -1.<br>
+  static inline int getFP16Imm(const APInt &Imm) {<br>
+    uint32_t Sign = Imm.lshr(15).getZExtValue() & 1;<br>
+    int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15;  // -14 to 15<br>
+    int64_t Mantissa = Imm.getZExtValue() & 0x3ff;  // 10 bits<br>
+<br>
+    // We can handle 4 bits of mantissa.<br>
+    // mantissa = (16+UInt(e:f:g:h))/16.<br>
+    if (Mantissa & 0x3f)<br>
+      return -1;<br>
+    Mantissa >>= 6;<br>
+<br>
+    // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3<br>
+    if (Exp < -3 || Exp > 4)<br>
+      return -1;<br>
+    Exp = ((Exp+3) & 0x7) ^ 4;<br>
+<br>
+    return ((int)Sign << 7) | (Exp << 4) | Mantissa;<br>
+  }<br>
+<br>
+  static inline int getFP16Imm(const APFloat &FPImm) {<br>
+    return getFP16Imm(FPImm.bitcastToAPInt());<br>
+  }<br>
+<br>
   /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit<br>
   /// floating-point value. If the value cannot be represented as an 8-bit<br>
   /// floating-point value, then return -1.<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=255762&r1=255761&r2=255762&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=255762&r1=255761&r2=255762&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Wed Dec 16 05:35:44 2015<br>
@@ -62,6 +62,10 @@ const MCFixupKindInfo &ARMAsmBackend::ge<br>
       {"fixup_t2_pcrel_10", 0, 32,<br>
        MCFixupKindInfo::FKF_IsPCRel |<br>
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},<br>
+      {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},<br>
+      {"fixup_t2_pcrel_9", 0, 32,<br>
+       MCFixupKindInfo::FKF_IsPCRel |<br>
+           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},<br>
       {"fixup_thumb_adr_pcrel_10", 0, 8,<br>
        MCFixupKindInfo::FKF_IsPCRel |<br>
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},<br>
@@ -105,6 +109,10 @@ const MCFixupKindInfo &ARMAsmBackend::ge<br>
       {"fixup_t2_pcrel_10", 0, 32,<br>
        MCFixupKindInfo::FKF_IsPCRel |<br>
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},<br>
+      {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},<br>
+      {"fixup_t2_pcrel_9", 0, 32,<br>
+       MCFixupKindInfo::FKF_IsPCRel |<br>
+           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},<br>
       {"fixup_thumb_adr_pcrel_10", 8, 8,<br>
        MCFixupKindInfo::FKF_IsPCRel |<br>
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},<br>
@@ -624,6 +632,37 @@ unsigned ARMAsmBackend::adjustFixupValue<br>
<br>
     return Value;<br>
   }<br>
+  case ARM::fixup_arm_pcrel_9:<br>
+    Value = Value - 4; // ARM fixups offset by an additional word and don't<br>
+                       // need to adjust for the half-word ordering.<br>
+                       // Fall through.<br>
+  case ARM::fixup_t2_pcrel_9: {<br>
+    // Offset by 4, adjusted by two due to the half-word ordering of thumb.<br>
+    Value = Value - 4;<br>
+    bool isAdd = true;<br>
+    if ((int64_t)Value < 0) {<br>
+      Value = -Value;<br>
+      isAdd = false;<br>
+    }<br>
+    // These values don't encode the low bit since it's always zero.<br>
+    if (Ctx && (Value & 1)) {<br>
+      Ctx->reportError(Fixup.getLoc(), "invalid value for this fixup");<br>
+      return 0;<br>
+    }<br>
+    Value >>= 1;<br>
+    if (Ctx && Value >= 256) {<br>
+      Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value");<br>
+      return 0;<br>
+    }<br>
+    Value |= isAdd << 23;<br>
+<br>
+    // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords<br>
+    // swapped.<br>
+    if (Kind == ARM::fixup_t2_pcrel_9)<br>
+      return swapHalfWords(Value, IsLittleEndian);<br>
+<br>
+    return Value;<br>
+  }<br>
   }<br>
 }<br>
<br>
@@ -695,6 +734,7 @@ static unsigned getFixupKindNumBytes(uns<br>
   case ARM::fixup_arm_pcrel_10_unscaled:<br>
   case ARM::fixup_arm_ldst_pcrel_12:<br>
   case ARM::fixup_arm_pcrel_10:<br>
+  case ARM::fixup_arm_pcrel_9:<br>
   case ARM::fixup_arm_adr_pcrel_12:<br>
   case ARM::fixup_arm_uncondbl:<br>
   case ARM::fixup_arm_condbl:<br>
@@ -708,6 +748,7 @@ static unsigned getFixupKindNumBytes(uns<br>
   case ARM::fixup_t2_condbranch:<br>
   case ARM::fixup_t2_uncondbranch:<br>
   case ARM::fixup_t2_pcrel_10:<br>
+  case ARM::fixup_t2_pcrel_9:<br>
   case ARM::fixup_t2_adr_pcrel_12:<br>
   case ARM::fixup_arm_thumb_bl:<br>
   case ARM::fixup_arm_thumb_blx:<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h?rev=255762&r1=255761&r2=255762&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h?rev=255762&r1=255761&r2=255762&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h Wed Dec 16 05:35:44 2015<br>
@@ -33,6 +33,13 @@ enum Fixups {<br>
   // fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for<br>
   // the short-swapped encoding of Thumb2 instructions.<br>
   fixup_t2_pcrel_10,<br>
+  // fixup_arm_pcrel_9 - 9-bit PC relative relocation for symbol addresses<br>
+  // used in VFP instructions where bit 0 not encoded (so it's encoded as an<br>
+  // 8-bit immediate).<br>
+  fixup_arm_pcrel_9,<br>
+  // fixup_t2_pcrel_9 - Equivalent to fixup_arm_pcrel_9, accounting for<br>
+  // the short-swapped encoding of Thumb2 instructions.<br>
+  fixup_t2_pcrel_9,<br>
   // fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol<br>
   // addresses where the lower 2 bits are not encoded (so it's encoded as an<br>
   // 8-bit immediate).<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=255762&r1=255761&r2=255762&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=255762&r1=255761&r2=255762&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Wed Dec 16 05:35:44 2015<br>
@@ -255,11 +255,16 @@ public:<br>
                                 SmallVectorImpl<MCFixup> &Fixups,<br>
                                 const MCSubtargetInfo &STI) const;<br>
<br>
-  /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.<br>
+  /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.<br>
   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,<br>
                                SmallVectorImpl<MCFixup> &Fixups,<br>
                                const MCSubtargetInfo &STI) const;<br>
<br>
+  /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.<br>
+  uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,<br>
+                               SmallVectorImpl<MCFixup> &Fixups,<br>
+                               const MCSubtargetInfo &STI) const;<br>
+<br>
   /// getCCOutOpValue - Return encoding of the 's' bit.<br>
   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,<br>
                            SmallVectorImpl<MCFixup> &Fixups,<br>
@@ -1252,7 +1257,7 @@ getAddrModePCOpValue(const MCInst &MI, u<br>
   return (MO.getImm() >> 2);<br>
 }<br>
<br>
-/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.<br>
+/// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.<br>
 uint32_t ARMMCCodeEmitter::<br>
 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,<br>
                     SmallVectorImpl<MCFixup> &Fixups,<br>
@@ -1279,6 +1284,46 @@ getAddrMode5OpValue(const MCInst &MI, un<br>
     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));<br>
<br>
     ++MCNumCPRelocations;<br>
+  } else {<br>
+    EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);<br>
+    isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;<br>
+  }<br>
+<br>
+  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);<br>
+  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.<br>
+  if (isAdd)<br>
+    Binary |= (1 << 8);<br>
+  Binary |= (Reg << 9);<br>
+  return Binary;<br>
+}<br>
+<br>
+/// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.<br>
+uint32_t ARMMCCodeEmitter::<br>
+getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,<br>
+                    SmallVectorImpl<MCFixup> &Fixups,<br>
+                    const MCSubtargetInfo &STI) const {<br>
+  // {12-9} = reg<br>
+  // {8}    = (U)nsigned (add == '1', sub == '0')<br>
+  // {7-0}  = imm8<br>
+  unsigned Reg, Imm8;<br>
+  bool isAdd;<br>
+  // If The first operand isn't a register, we have a label reference.<br>
+  const MCOperand &MO = MI.getOperand(OpIdx);<br>
+  if (!MO.isReg()) {<br>
+    Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.<br>
+    Imm8 = 0;<br>
+    isAdd = false; // 'U' bit is handled as part of the fixup.<br>
+<br>
+    assert(MO.isExpr() && "Unexpected machine operand type!");<br>
+    const MCExpr *Expr = MO.getExpr();<br>
+    MCFixupKind Kind;<br>
+    if (isThumb2(STI))<br>
+      Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);<br>
+    else<br>
+      Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);<br>
+    Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));<br>
+<br>
+    ++MCNumCPRelocations;<br>
   } else {<br>
     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);<br>
     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;<br>
<br>
Added: llvm/trunk/test/MC/ARM/fullfp16-neg.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/fullfp16-neg.s?rev=255762&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/fullfp16-neg.s?rev=255762&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/ARM/fullfp16-neg.s (added)<br>
+++ llvm/trunk/test/MC/ARM/fullfp16-neg.s Wed Dec 16 05:35:44 2015<br>
@@ -0,0 +1,189 @@<br>
+@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16 -show-encoding < %s 2>&1 | FileCheck %s<br>
+@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+thumb-mode -show-encoding < %s 2>&1 | FileCheck %s<br>
+<br>
+         vadd.f16  s0, s1, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vsub.f16  s0, s1, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vdiv.f16  s0, s1, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vmul.f16  s0, s1, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vnmul.f16       s0, s1, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vmla.f16        s1, s2, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vmls.f16        s1, s2, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vnmla.f16       s1, s2, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vnmls.f16       s1, s2, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vcmp.f16 s0, s1<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vcmp.f16 s2, #0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vcmpe.f16       s1, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vcmpe.f16       s0, #0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vabs.f16        s0, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vneg.f16        s0, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vsqrt.f16       s0, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vcvt.f16.s32    s0, s0<br>
+         vcvt.f16.u32    s0, s0<br>
+         vcvt.s32.f16    s0, s0<br>
+         vcvt.u32.f16    s0, s0<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vcvtr.s32.f16  s0, s1<br>
+         vcvtr.u32.f16  s0, s1<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+         vcvt.f16.u32 s0, s0, #20<br>
+         vcvt.f16.u16 s0, s0, #1<br>
+         vcvt.f16.s32 s1, s1, #20<br>
+         vcvt.f16.s16 s17, s17, #1<br>
+         vcvt.u32.f16 s12, s12, #20<br>
+         vcvt.u16.f16 s28, s28, #1<br>
+         vcvt.s32.f16 s1, s1, #20<br>
+         vcvt.s16.f16 s17, s17, #1<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vcvta.s32.f16 s2, s3<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vcvtn.s32.f16 s6, s23<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vcvtp.s32.f16 s0, s4<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vcvtm.s32.f16 s17, s8<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vcvta.u32.f16 s2, s3<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vcvtn.u32.f16 s6, s23<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vcvtp.u32.f16 s0, s4<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vcvtm.u32.f16 s17, s8<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vselge.f16 s4, s1, s23<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vselgt.f16 s0, s1, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vseleq.f16 s30, s28, s23<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vselvs.f16 s21, s16, s14<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vmaxnm.f16 s5, s12, s0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vminnm.f16 s0, s0, s12<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vrintz.f16 s3, s24<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vrintr.f16 s0, s9<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vrintx.f16 s10, s14<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vrinta.f16 s12, s1<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vrintn.f16 s12, s1<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vrintp.f16 s12, s1<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vrintm.f16 s12, s1<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vfma.f16 s2, s7, s4<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vfms.f16 s2, s7, s4<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vfnma.f16 s2, s7, s4<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vfnms.f16 s2, s7, s4<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vmovx.f16 s2, s5<br>
+  vins.f16 s2, s5<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+<br>
+  vldr.16 s1, [pc, #6]<br>
+  vldr.16 s2, [pc, #510]<br>
+  vldr.16 s3, [pc, #-510]<br>
+  vldr.16 s4, [r4, #-18]<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+<br>
+  vstr.16 s1, [pc, #6]<br>
+  vstr.16 s2, [pc, #510]<br>
+  vstr.16 s3, [pc, #-510]<br>
+  vstr.16 s4, [r4, #-18]<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vmov.f16 s0, #1.0<br>
+@ CHECK: error: instruction requires:<br>
+<br>
+  vmov.f16 s1, r2<br>
+  vmov.f16 r3, s4<br>
+@ CHECK: error: instruction requires:<br>
+@ CHECK: error: instruction requires:<br>
<br>
Added: llvm/trunk/test/MC/ARM/fullfp16.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/fullfp16.s?rev=255762&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/fullfp16.s?rev=255762&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/ARM/fullfp16.s (added)<br>
+++ llvm/trunk/test/MC/ARM/fullfp16.s Wed Dec 16 05:35:44 2015<br>
@@ -0,0 +1,257 @@<br>
+@ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16 -show-encoding < %s | FileCheck %s --check-prefix=ARM<br>
+@ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,+thumb-mode -show-encoding < %s | FileCheck %s --check-prefix=THUMB<br>
+<br>
+         vadd.f16  s0, s1, s0<br>
+@ ARM:    vadd.f16 s0, s1, s0        @ encoding: [0x80,0x09,0x30,0xee]<br>
+@ THUMB:  vadd.f16 s0, s1, s0        @ encoding: [0x30,0xee,0x80,0x09]<br>
+<br>
+         vsub.f16  s0, s1, s0<br>
+@ ARM:   vsub.f16 s0, s1, s0         @ encoding: [0xc0,0x09,0x30,0xee]<br>
+@ THUMB: vsub.f16 s0, s1, s0         @ encoding: [0x30,0xee,0xc0,0x09]<br>
+<br>
+         vdiv.f16  s0, s1, s0<br>
+@ ARM:   vdiv.f16 s0, s1, s0         @ encoding: [0x80,0x09,0x80,0xee]<br>
+@ THUMB: vdiv.f16 s0, s1, s0         @ encoding: [0x80,0xee,0x80,0x09]<br>
+<br>
+         vmul.f16  s0, s1, s0<br>
+@ ARM:   vmul.f16 s0, s1, s0         @ encoding: [0x80,0x09,0x20,0xee]<br>
+@ THUMB: vmul.f16 s0, s1, s0         @ encoding: [0x20,0xee,0x80,0x09]<br>
+<br>
+         vnmul.f16       s0, s1, s0<br>
+@ ARM:   vnmul.f16 s0, s1, s0        @ encoding: [0xc0,0x09,0x20,0xee]<br>
+@ THUMB: vnmul.f16 s0, s1, s0        @ encoding: [0x20,0xee,0xc0,0x09]<br>
+<br>
+         vmla.f16        s1, s2, s0<br>
+@ ARM:   vmla.f16 s1, s2, s0         @ encoding: [0x00,0x09,0x41,0xee]<br>
+@ THUMB: vmla.f16 s1, s2, s0         @ encoding: [0x41,0xee,0x00,0x09]<br>
+<br>
+         vmls.f16        s1, s2, s0<br>
+@ ARM:   vmls.f16 s1, s2, s0         @ encoding: [0x40,0x09,0x41,0xee]<br>
+@ THUMB: vmls.f16 s1, s2, s0         @ encoding: [0x41,0xee,0x40,0x09]<br>
+<br>
+         vnmla.f16       s1, s2, s0<br>
+@ ARM:   vnmla.f16 s1, s2, s0        @ encoding: [0x40,0x09,0x51,0xee]<br>
+@ THUMB: vnmla.f16 s1, s2, s0        @ encoding: [0x51,0xee,0x40,0x09]<br>
+<br>
+         vnmls.f16       s1, s2, s0<br>
+@ ARM:   vnmls.f16 s1, s2, s0        @ encoding: [0x00,0x09,0x51,0xee]<br>
+@ THUMB: vnmls.f16 s1, s2, s0        @ encoding: [0x51,0xee,0x00,0x09]<br>
+<br>
+         vcmp.f16 s0, s1<br>
+@ ARM:   vcmp.f16        s0, s1      @ encoding: [0x60,0x09,0xb4,0xee]<br>
+@ THUMB: vcmp.f16        s0, s1      @ encoding: [0xb4,0xee,0x60,0x09]<br>
+<br>
+         vcmp.f16 s2, #0<br>
+@ ARM:   vcmp.f16        s2, #0      @ encoding: [0x40,0x19,0xb5,0xee]<br>
+@ THUMB: vcmp.f16        s2, #0      @ encoding: [0xb5,0xee,0x40,0x19]<br>
+<br>
+         vcmpe.f16       s1, s0<br>
+@ ARM:   vcmpe.f16 s1, s0            @ encoding: [0xc0,0x09,0xf4,0xee]<br>
+@ THUMB: vcmpe.f16 s1, s0            @ encoding: [0xf4,0xee,0xc0,0x09]<br>
+<br>
+         vcmpe.f16       s0, #0<br>
+@ ARM:   vcmpe.f16 s0, #0            @ encoding: [0xc0,0x09,0xb5,0xee]<br>
+@ THUMB: vcmpe.f16 s0, #0            @ encoding: [0xb5,0xee,0xc0,0x09]<br>
+<br>
+         vabs.f16        s0, s0<br>
+@ ARM:   vabs.f16 s0, s0             @ encoding: [0xc0,0x09,0xb0,0xee]<br>
+@ THUMB: vabs.f16 s0, s0             @ encoding: [0xb0,0xee,0xc0,0x09]<br>
+<br>
+         vneg.f16        s0, s0<br>
+@ ARM:   vneg.f16 s0, s0             @ encoding: [0x40,0x09,0xb1,0xee]<br>
+@ THUMB: vneg.f16 s0, s0             @ encoding: [0xb1,0xee,0x40,0x09]<br>
+<br>
+         vsqrt.f16       s0, s0<br>
+@ ARM:   vsqrt.f16 s0, s0            @ encoding: [0xc0,0x09,0xb1,0xee]<br>
+@ THUMB: vsqrt.f16 s0, s0            @ encoding: [0xb1,0xee,0xc0,0x09]<br>
+<br>
+         vcvt.f16.s32    s0, s0<br>
+         vcvt.f16.u32    s0, s0<br>
+         vcvt.s32.f16    s0, s0<br>
+         vcvt.u32.f16    s0, s0<br>
+@ ARM:   vcvt.f16.s32 s0, s0         @ encoding: [0xc0,0x09,0xb8,0xee]<br>
+@ ARM:   vcvt.f16.u32 s0, s0         @ encoding: [0x40,0x09,0xb8,0xee]<br>
+@ ARM:   vcvt.s32.f16 s0, s0         @ encoding: [0xc0,0x09,0xbd,0xee]<br>
+@ ARM:   vcvt.u32.f16 s0, s0         @ encoding: [0xc0,0x09,0xbc,0xee]<br>
+@ THUMB: vcvt.f16.s32 s0, s0         @ encoding: [0xb8,0xee,0xc0,0x09]<br>
+@ THUMB: vcvt.f16.u32 s0, s0         @ encoding: [0xb8,0xee,0x40,0x09]<br>
+@ THUMB: vcvt.s32.f16 s0, s0         @ encoding: [0xbd,0xee,0xc0,0x09]<br>
+@ THUMB: vcvt.u32.f16 s0, s0         @ encoding: [0xbc,0xee,0xc0,0x09]<br>
+<br>
+         vcvtr.s32.f16  s0, s1<br>
+         vcvtr.u32.f16  s0, s1<br>
+@ ARM:   vcvtr.s32.f16  s0, s1       @ encoding: [0x60,0x09,0xbd,0xee]<br>
+@ ARM:   vcvtr.u32.f16  s0, s1       @ encoding: [0x60,0x09,0xbc,0xee]<br>
+@ THUMB: vcvtr.s32.f16  s0, s1       @ encoding: [0xbd,0xee,0x60,0x09]<br>
+@ THUMB: vcvtr.u32.f16  s0, s1       @ encoding: [0xbc,0xee,0x60,0x09]<br>
+<br>
+         vcvt.f16.u32 s0, s0, #20<br>
+         vcvt.f16.u16 s0, s0, #1<br>
+         vcvt.f16.s32 s1, s1, #20<br>
+         vcvt.f16.s16 s17, s17, #1<br>
+         vcvt.u32.f16 s12, s12, #20<br>
+         vcvt.u16.f16 s28, s28, #1<br>
+         vcvt.s32.f16 s1, s1, #20<br>
+         vcvt.s16.f16 s17, s17, #1<br>
+@ ARM:   vcvt.f16.u32   s0, s0, #20     @ encoding: [0xc6,0x09,0xbb,0xee]<br>
+@ ARM:   vcvt.f16.u16   s0, s0, #1      @ encoding: [0x67,0x09,0xbb,0xee]<br>
+@ ARM:   vcvt.f16.s32   s1, s1, #20     @ encoding: [0xc6,0x09,0xfa,0xee]<br>
+@ ARM:   vcvt.f16.s16   s17, s17, #1    @ encoding: [0x67,0x89,0xfa,0xee]<br>
+@ ARM:   vcvt.u32.f16   s12, s12, #20   @ encoding: [0xc6,0x69,0xbf,0xee]<br>
+@ ARM:   vcvt.u16.f16   s28, s28, #1    @ encoding: [0x67,0xe9,0xbf,0xee]<br>
+@ ARM:   vcvt.s32.f16   s1, s1, #20     @ encoding: [0xc6,0x09,0xfe,0xee]<br>
+@ ARM:   vcvt.s16.f16   s17, s17, #1    @ encoding: [0x67,0x89,0xfe,0xee]<br>
+@ THUMB: vcvt.f16.u32   s0, s0, #20     @ encoding: [0xbb,0xee,0xc6,0x09]<br>
+@ THUMB: vcvt.f16.u16   s0, s0, #1      @ encoding: [0xbb,0xee,0x67,0x09]<br>
+@ THUMB: vcvt.f16.s32   s1, s1, #20     @ encoding: [0xfa,0xee,0xc6,0x09]<br>
+@ THUMB: vcvt.f16.s16   s17, s17, #1    @ encoding: [0xfa,0xee,0x67,0x89]<br>
+@ THUMB: vcvt.u32.f16   s12, s12, #20   @ encoding: [0xbf,0xee,0xc6,0x69]<br>
+@ THUMB: vcvt.u16.f16   s28, s28, #1    @ encoding: [0xbf,0xee,0x67,0xe9]<br>
+@ THUMB: vcvt.s32.f16   s1, s1, #20     @ encoding: [0xfe,0xee,0xc6,0x09]<br>
+@ THUMB: vcvt.s16.f16   s17, s17, #1    @ encoding: [0xfe,0xee,0x67,0x89]<br>
+<br>
+  vcvta.s32.f16 s2, s3<br>
+@ ARM:   vcvta.s32.f16 s2, s3     @ encoding: [0xe1,0x19,0xbc,0xfe]<br>
+@ THUMB: vcvta.s32.f16 s2, s3     @ encoding: [0xbc,0xfe,0xe1,0x19]<br>
+<br>
+  vcvtn.s32.f16 s6, s23<br>
+@ ARM:   vcvtn.s32.f16 s6, s23     @ encoding: [0xeb,0x39,0xbd,0xfe]<br>
+@ THUMB: vcvtn.s32.f16 s6, s23     @ encoding: [0xbd,0xfe,0xeb,0x39]<br>
+<br>
+  vcvtp.s32.f16 s0, s4<br>
+@ ARM:   vcvtp.s32.f16 s0, s4     @ encoding: [0xc2,0x09,0xbe,0xfe]<br>
+@ THUMB: vcvtp.s32.f16 s0, s4     @ encoding: [0xbe,0xfe,0xc2,0x09]<br>
+<br>
+  vcvtm.s32.f16 s17, s8<br>
+@ ARM:   vcvtm.s32.f16 s17, s8     @ encoding: [0xc4,0x89,0xff,0xfe]<br>
+@ THUMB: vcvtm.s32.f16 s17, s8     @ encoding: [0xff,0xfe,0xc4,0x89]<br>
+<br>
+  vcvta.u32.f16 s2, s3<br>
+@ ARM:   vcvta.u32.f16 s2, s3     @ encoding: [0x61,0x19,0xbc,0xfe]<br>
+@ THUMB: vcvta.u32.f16 s2, s3     @ encoding: [0xbc,0xfe,0x61,0x19]<br>
+<br>
+  vcvtn.u32.f16 s6, s23<br>
+@ ARM:   vcvtn.u32.f16 s6, s23     @ encoding: [0x6b,0x39,0xbd,0xfe]<br>
+@ THUMB: vcvtn.u32.f16 s6, s23     @ encoding: [0xbd,0xfe,0x6b,0x39]<br>
+<br>
+  vcvtp.u32.f16 s0, s4<br>
+@ ARM:   vcvtp.u32.f16 s0, s4     @ encoding: [0x42,0x09,0xbe,0xfe]<br>
+@ THUMB: vcvtp.u32.f16 s0, s4     @ encoding: [0xbe,0xfe,0x42,0x09]<br>
+<br>
+  vcvtm.u32.f16 s17, s8<br>
+@ ARM:   vcvtm.u32.f16 s17, s8     @ encoding: [0x44,0x89,0xff,0xfe]<br>
+@ THUMB: vcvtm.u32.f16 s17, s8     @ encoding: [0xff,0xfe,0x44,0x89]<br>
+<br>
+  vselge.f16 s4, s1, s23<br>
+@ ARM:   vselge.f16 s4, s1, s23    @ encoding: [0xab,0x29,0x20,0xfe]<br>
+@ THUMB: vselge.f16 s4, s1, s23    @ encoding: [0x20,0xfe,0xab,0x29]<br>
+<br>
+  vselgt.f16 s0, s1, s0<br>
+@ ARM:   vselgt.f16 s0, s1, s0    @ encoding: [0x80,0x09,0x30,0xfe]<br>
+@ THUMB: vselgt.f16 s0, s1, s0    @ encoding: [0x30,0xfe,0x80,0x09]<br>
+<br>
+  vseleq.f16 s30, s28, s23<br>
+@ ARM:   vseleq.f16 s30, s28, s23 @ encoding: [0x2b,0xf9,0x0e,0xfe]<br>
+@ THUMB: vseleq.f16 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xf9]<br>
+<br>
+  vselvs.f16 s21, s16, s14<br>
+@ ARM:   vselvs.f16 s21, s16, s14 @ encoding: [0x07,0xa9,0x58,0xfe]<br>
+@ THUMB: vselvs.f16 s21, s16, s14 @ encoding: [0x58,0xfe,0x07,0xa9]<br>
+<br>
+  vmaxnm.f16 s5, s12, s0<br>
+@ ARM:   vmaxnm.f16 s5, s12, s0    @ encoding: [0x00,0x29,0xc6,0xfe]<br>
+@ THUMB: vmaxnm.f16 s5, s12, s0    @ encoding: [0xc6,0xfe,0x00,0x29]<br>
+<br>
+  vminnm.f16 s0, s0, s12<br>
+@ ARM:   vminnm.f16 s0, s0, s12    @ encoding: [0x46,0x09,0x80,0xfe]<br>
+@ THUMB: vminnm.f16 s0, s0, s12    @ encoding: [0x80,0xfe,0x46,0x09]<br>
+<br>
+  vrintz.f16 s3, s24<br>
+@ ARM:   vrintz.f16 s3, s24     @ encoding: [0xcc,0x19,0xf6,0xee]<br>
+@ THUMB: vrintz.f16 s3, s24     @ encoding: [0xf6,0xee,0xcc,0x19]<br>
+<br>
+  vrintr.f16 s0, s9<br>
+@ ARM:   vrintr.f16 s0, s9      @ encoding: [0x64,0x09,0xb6,0xee]<br>
+@ THUMB: vrintr.f16 s0, s9      @ encoding: [0xb6,0xee,0x64,0x09]<br>
+<br>
+  vrintx.f16 s10, s14<br>
+@ ARM:   vrintx.f16 s10, s14  @ encoding: [0x47,0x59,0xb7,0xee]<br>
+@ THUMB: vrintx.f16 s10, s14  @ encoding: [0xb7,0xee,0x47,0x59]<br>
+<br>
+  vrinta.f16 s12, s1<br>
+@ ARM:   vrinta.f16 s12, s1    @ encoding: [0x60,0x69,0xb8,0xfe]<br>
+@ THUMB: vrinta.f16 s12, s1    @ encoding: [0xb8,0xfe,0x60,0x69]<br>
+<br>
+  vrintn.f16 s12, s1<br>
+@ ARM:   vrintn.f16 s12, s1    @ encoding: [0x60,0x69,0xb9,0xfe]<br>
+@ THUMB: vrintn.f16 s12, s1    @ encoding: [0xb9,0xfe,0x60,0x69]<br>
+<br>
+  vrintp.f16 s12, s1<br>
+@ ARM:   vrintp.f16 s12, s1    @ encoding: [0x60,0x69,0xba,0xfe]<br>
+@ THUMB: vrintp.f16 s12, s1    @ encoding: [0xba,0xfe,0x60,0x69]<br>
+<br>
+  vrintm.f16 s12, s1<br>
+@ ARM:   vrintm.f16 s12, s1    @ encoding: [0x60,0x69,0xbb,0xfe]<br>
+@ THUMB: vrintm.f16 s12, s1    @ encoding: [0xbb,0xfe,0x60,0x69]<br>
+<br>
+  vfma.f16 s2, s7, s4<br>
+@ ARM:   vfma.f16        s2, s7, s4      @ encoding: [0x82,0x19,0xa3,0xee]<br>
+@ THUMB: vfma.f16        s2, s7, s4      @ encoding: [0xa3,0xee,0x82,0x19]<br>
+<br>
+  vfms.f16 s2, s7, s4<br>
+@ ARM:   vfms.f16        s2, s7, s4      @ encoding: [0xc2,0x19,0xa3,0xee]<br>
+@ THUMB: vfms.f16        s2, s7, s4      @ encoding: [0xa3,0xee,0xc2,0x19]<br>
+<br>
+  vfnma.f16 s2, s7, s4<br>
+@ ARM:   vfnma.f16       s2, s7, s4      @ encoding: [0xc2,0x19,0x93,0xee]<br>
+@ THUMB: vfnma.f16       s2, s7, s4      @ encoding: [0x93,0xee,0xc2,0x19]<br>
+<br>
+  vfnms.f16 s2, s7, s4<br>
+@ ARM:   vfnms.f16       s2, s7, s4      @ encoding: [0x82,0x19,0x93,0xee]<br>
+@ THUMB: vfnms.f16       s2, s7, s4      @ encoding: [0x93,0xee,0x82,0x19]<br>
+<br>
+  vmovx.f16 s2, s5<br>
+  vins.f16 s2, s5<br>
+@ ARM:   vmovx.f16       s2, s5          @ encoding: [0x62,0x1a,0xb0,0xfe]<br>
+@ ARM:   vins.f16        s2, s5          @ encoding: [0xe2,0x1a,0xb0,0xfe]<br>
+@ THUMB: vmovx.f16       s2, s5          @ encoding: [0xb0,0xfe,0x62,0x1a]<br>
+@ THUMB: vins.f16        s2, s5          @ encoding: [0xb0,0xfe,0xe2,0x1a]<br>
+<br>
+<br>
+  vldr.16 s1, [pc, #6]<br>
+  vldr.16 s2, [pc, #510]<br>
+  vldr.16 s3, [pc, #-510]<br>
+  vldr.16 s4, [r4, #-18]<br>
+@ ARM:   vldr.16 s1, [pc, #6]          @ encoding: [0x03,0x09,0xdf,0xed]<br>
+@ ARM:   vldr.16 s2, [pc, #510]        @ encoding: [0xff,0x19,0x9f,0xed]<br>
+@ ARM:   vldr.16 s3, [pc, #-510]       @ encoding: [0xff,0x19,0x5f,0xed]<br>
+@ ARM:   vldr.16 s4, [r4, #-18]        @ encoding: [0x09,0x29,0x14,0xed]<br>
+@ THUMB: vldr.16 s1, [pc, #6]          @ encoding: [0xdf,0xed,0x03,0x09]<br>
+@ THUMB: vldr.16 s2, [pc, #510]        @ encoding: [0x9f,0xed,0xff,0x19]<br>
+@ THUMB: vldr.16 s3, [pc, #-510]       @ encoding: [0x5f,0xed,0xff,0x19]<br>
+@ THUMB: vldr.16 s4, [r4, #-18]        @ encoding: [0x14,0xed,0x09,0x29]<br>
+<br>
+<br>
+  vstr.16 s1, [pc, #6]<br>
+  vstr.16 s2, [pc, #510]<br>
+  vstr.16 s3, [pc, #-510]<br>
+  vstr.16 s4, [r4, #-18]<br>
+@ ARM:   vstr.16 s1, [pc, #6]          @ encoding: [0x03,0x09,0xcf,0xed]<br>
+@ ARM:   vstr.16 s2, [pc, #510]        @ encoding: [0xff,0x19,0x8f,0xed]<br>
+@ ARM:   vstr.16 s3, [pc, #-510]       @ encoding: [0xff,0x19,0x4f,0xed]<br>
+@ ARM:   vstr.16 s4, [r4, #-18]        @ encoding: [0x09,0x29,0x04,0xed]<br>
+@ THUMB: vstr.16 s1, [pc, #6]          @ encoding: [0xcf,0xed,0x03,0x09]<br>
+@ THUMB: vstr.16 s2, [pc, #510]        @ encoding: [0x8f,0xed,0xff,0x19]<br>
+@ THUMB: vstr.16 s3, [pc, #-510]       @ encoding: [0x4f,0xed,0xff,0x19]<br>
+@ THUMB: vstr.16 s4, [r4, #-18]        @ encoding: [0x04,0xed,0x09,0x29]<br>
+<br>
+  vmov.f16 s0, #1.0<br>
+@ ARM:   vmov.f16        s0, #1.000000e+00 @ encoding: [0x00,0x09,0xb7,0xee]<br>
+@ THUMB: vmov.f16        s0, #1.000000e+00 @ encoding: [0xb7,0xee,0x00,0x09]<br>
+<br>
+  vmov.f16 s1, r2<br>
+  vmov.f16 r3, s4<br>
+@ ARM:   vmov.f16        s1, r2          @ encoding: [0x90,0x29,0x00,0xee]<br>
+@ ARM:   vmov.f16        r3, s4          @ encoding: [0x10,0x39,0x12,0xee]<br>
+@ THUMB: vmov.f16       s1, r2          @ encoding: [0x00,0xee,0x90,0x29]<br>
+@ THUMB: vmov.f16       r3, s4          @ encoding: [0x12,0xee,0x10,0x39]<br>
<br>
Added: llvm/trunk/test/MC/Disassembler/ARM/fullfp16-arm-neg.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/fullfp16-arm-neg.txt?rev=255762&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/fullfp16-arm-neg.txt?rev=255762&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/ARM/fullfp16-arm-neg.txt (added)<br>
+++ llvm/trunk/test/MC/Disassembler/ARM/fullfp16-arm-neg.txt Wed Dec 16 05:35:44 2015<br>
@@ -0,0 +1,188 @@<br>
+# RUN: not llvm-mc -disassemble -triple armv8a-none-eabi -mattr=-fullfp16 -show-encoding < %s 2>&1 | FileCheck %s<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x80,0x09,0x30,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc0,0x09,0x30,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x80,0x09,0x80,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x80,0x09,0x20,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc0,0x09,0x20,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x00,0x09,0x41,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x40,0x09,0x41,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x40,0x09,0x51,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x00,0x09,0x51,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x60,0x09,0xb4,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x40,0x19,0xb5,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc0,0x09,0xf4,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc0,0x09,0xb5,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc0,0x09,0xb0,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x40,0x09,0xb1,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc0,0x09,0xb1,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc0,0x09,0xb8,0xee]<br>
+[0x40,0x09,0xb8,0xee]<br>
+[0xc0,0x09,0xbd,0xee]<br>
+[0xc0,0x09,0xbc,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x60,0x09,0xbd,0xee]<br>
+[0x60,0x09,0xbc,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc6,0x09,0xbb,0xee]<br>
+[0x67,0x09,0xbb,0xee]<br>
+[0xc6,0x09,0xfa,0xee]<br>
+[0x67,0x89,0xfa,0xee]<br>
+[0xc6,0x69,0xbf,0xee]<br>
+[0x67,0xe9,0xbf,0xee]<br>
+[0xc6,0x09,0xfe,0xee]<br>
+[0x67,0x89,0xfe,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xe1,0x19,0xbc,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xeb,0x39,0xbd,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc2,0x09,0xbe,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc4,0x89,0xff,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x61,0x19,0xbc,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x6b,0x39,0xbd,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x42,0x09,0xbe,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x44,0x89,0xff,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xab,0x29,0x20,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x80,0x09,0x30,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x2b,0xf9,0x0e,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x07,0xa9,0x58,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x00,0x29,0xc6,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x46,0x09,0x80,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xcc,0x19,0xf6,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x64,0x09,0xb6,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x47,0x59,0xb7,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x60,0x69,0xb8,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x60,0x69,0xb9,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x60,0x69,0xba,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x60,0x69,0xbb,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x82,0x19,0xa3,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc2,0x19,0xa3,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc2,0x19,0x93,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x82,0x19,0x93,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x62,0x1a,0xb0,0xfe]<br>
+[0xe2,0x1a,0xb0,0xfe]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x03,0x09,0xdf,0xed]<br>
+[0xff,0x19,0x9f,0xed]<br>
+[0xff,0x19,0x5f,0xed]<br>
+[0x09,0x29,0x14,0xed]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x03,0x09,0xcf,0xed]<br>
+[0xff,0x19,0x8f,0xed]<br>
+[0xff,0x19,0x4f,0xed]<br>
+[0x09,0x29,0x04,0xed]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x00,0x09,0xb7,0xee]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x90,0x29,0x00,0xee]<br>
+[0x10,0x39,0x12,0xee]<br>
+<br>
+# CHECK-NOT: warning: invalid instruction encoding<br>
<br>
Added: llvm/trunk/test/MC/Disassembler/ARM/fullfp16-arm.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/fullfp16-arm.txt?rev=255762&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/fullfp16-arm.txt?rev=255762&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/ARM/fullfp16-arm.txt (added)<br>
+++ llvm/trunk/test/MC/Disassembler/ARM/fullfp16-arm.txt Wed Dec 16 05:35:44 2015<br>
@@ -0,0 +1,186 @@<br>
+# RUN: llvm-mc -disassemble -triple armv8a-none-eabi -mattr=+fullfp16 -show-encoding < %s | FileCheck %s<br>
+<br>
+# CHECK:        vadd.f16  s0, s1, s0<br>
+[0x80,0x09,0x30,0xee]<br>
+<br>
+# CHECK:        vsub.f16  s0, s1, s0<br>
+[0xc0,0x09,0x30,0xee]<br>
+<br>
+# CHECK:        vdiv.f16  s0, s1, s0<br>
+[0x80,0x09,0x80,0xee]<br>
+<br>
+# CHECK:        vmul.f16  s0, s1, s0<br>
+[0x80,0x09,0x20,0xee]<br>
+<br>
+# CHECK:        vnmul.f16       s0, s1, s0<br>
+[0xc0,0x09,0x20,0xee]<br>
+<br>
+# CHECK:        vmla.f16        s1, s2, s0<br>
+[0x00,0x09,0x41,0xee]<br>
+<br>
+# CHECK:        vmls.f16        s1, s2, s0<br>
+[0x40,0x09,0x41,0xee]<br>
+<br>
+# CHECK:        vnmla.f16       s1, s2, s0<br>
+[0x40,0x09,0x51,0xee]<br>
+<br>
+# CHECK:        vnmls.f16       s1, s2, s0<br>
+[0x00,0x09,0x51,0xee]<br>
+<br>
+# CHECK:        vcmp.f16 s0, s1<br>
+[0x60,0x09,0xb4,0xee]<br>
+<br>
+# CHECK:        vcmp.f16 s2, #0<br>
+[0x40,0x19,0xb5,0xee]<br>
+<br>
+# CHECK:        vcmpe.f16       s1, s0<br>
+[0xc0,0x09,0xf4,0xee]<br>
+<br>
+# CHECK:        vcmpe.f16       s0, #0<br>
+[0xc0,0x09,0xb5,0xee]<br>
+<br>
+# CHECK:        vabs.f16        s0, s0<br>
+[0xc0,0x09,0xb0,0xee]<br>
+<br>
+# CHECK:        vneg.f16        s0, s0<br>
+[0x40,0x09,0xb1,0xee]<br>
+<br>
+# CHECK:        vsqrt.f16       s0, s0<br>
+[0xc0,0x09,0xb1,0xee]<br>
+<br>
+# CHECK:        vcvt.f16.s32    s0, s0<br>
+# CHECK:        vcvt.f16.u32    s0, s0<br>
+# CHECK:        vcvt.s32.f16    s0, s0<br>
+# CHECK:        vcvt.u32.f16    s0, s0<br>
+[0xc0,0x09,0xb8,0xee]<br>
+[0x40,0x09,0xb8,0xee]<br>
+[0xc0,0x09,0xbd,0xee]<br>
+[0xc0,0x09,0xbc,0xee]<br>
+<br>
+# CHECK:        vcvtr.s32.f16  s0, s1<br>
+# CHECK:        vcvtr.u32.f16  s0, s1<br>
+[0x60,0x09,0xbd,0xee]<br>
+[0x60,0x09,0xbc,0xee]<br>
+<br>
+# CHECK:        vcvt.f16.u32 s0, s0, #20<br>
+# CHECK:        vcvt.f16.u16 s0, s0, #1<br>
+# CHECK:        vcvt.f16.s32 s1, s1, #20<br>
+# CHECK:        vcvt.f16.s16 s17, s17, #1<br>
+# CHECK:        vcvt.u32.f16 s12, s12, #20<br>
+# CHECK:        vcvt.u16.f16 s28, s28, #1<br>
+# CHECK:        vcvt.s32.f16 s1, s1, #20<br>
+# CHECK:        vcvt.s16.f16 s17, s17, #1<br>
+[0xc6,0x09,0xbb,0xee]<br>
+[0x67,0x09,0xbb,0xee]<br>
+[0xc6,0x09,0xfa,0xee]<br>
+[0x67,0x89,0xfa,0xee]<br>
+[0xc6,0x69,0xbf,0xee]<br>
+[0x67,0xe9,0xbf,0xee]<br>
+[0xc6,0x09,0xfe,0xee]<br>
+[0x67,0x89,0xfe,0xee]<br>
+<br>
+# CHECK: vcvta.s32.f16 s2, s3<br>
+[0xe1,0x19,0xbc,0xfe]<br>
+<br>
+# CHECK: vcvtn.s32.f16 s6, s23<br>
+[0xeb,0x39,0xbd,0xfe]<br>
+<br>
+# CHECK: vcvtp.s32.f16 s0, s4<br>
+[0xc2,0x09,0xbe,0xfe]<br>
+<br>
+# CHECK: vcvtm.s32.f16 s17, s8<br>
+[0xc4,0x89,0xff,0xfe]<br>
+<br>
+# CHECK: vcvta.u32.f16 s2, s3<br>
+[0x61,0x19,0xbc,0xfe]<br>
+<br>
+# CHECK: vcvtn.u32.f16 s6, s23<br>
+[0x6b,0x39,0xbd,0xfe]<br>
+<br>
+# CHECK: vcvtp.u32.f16 s0, s4<br>
+[0x42,0x09,0xbe,0xfe]<br>
+<br>
+# CHECK: vcvtm.u32.f16 s17, s8<br>
+[0x44,0x89,0xff,0xfe]<br>
+<br>
+# CHECK: vselge.f16 s4, s1, s23<br>
+[0xab,0x29,0x20,0xfe]<br>
+<br>
+# CHECK: vselgt.f16 s0, s1, s0<br>
+[0x80,0x09,0x30,0xfe]<br>
+<br>
+# CHECK: vseleq.f16 s30, s28, s23<br>
+[0x2b,0xf9,0x0e,0xfe]<br>
+<br>
+# CHECK: vselvs.f16 s21, s16, s14<br>
+[0x07,0xa9,0x58,0xfe]<br>
+<br>
+# CHECK: vmaxnm.f16 s5, s12, s0<br>
+[0x00,0x29,0xc6,0xfe]<br>
+<br>
+# CHECK: vminnm.f16 s0, s0, s12<br>
+[0x46,0x09,0x80,0xfe]<br>
+<br>
+# CHECK: vrintz.f16 s3, s24<br>
+[0xcc,0x19,0xf6,0xee]<br>
+<br>
+# CHECK: vrintr.f16 s0, s9<br>
+[0x64,0x09,0xb6,0xee]<br>
+<br>
+# CHECK: vrintx.f16 s10, s14<br>
+[0x47,0x59,0xb7,0xee]<br>
+<br>
+# CHECK: vrinta.f16 s12, s1<br>
+[0x60,0x69,0xb8,0xfe]<br>
+<br>
+# CHECK: vrintn.f16 s12, s1<br>
+[0x60,0x69,0xb9,0xfe]<br>
+<br>
+# CHECK: vrintp.f16 s12, s1<br>
+[0x60,0x69,0xba,0xfe]<br>
+<br>
+# CHECK: vrintm.f16 s12, s1<br>
+[0x60,0x69,0xbb,0xfe]<br>
+<br>
+# CHECK: vfma.f16 s2, s7, s4<br>
+[0x82,0x19,0xa3,0xee]<br>
+<br>
+# CHECK: vfms.f16 s2, s7, s4<br>
+[0xc2,0x19,0xa3,0xee]<br>
+<br>
+# CHECK: vfnma.f16 s2, s7, s4<br>
+[0xc2,0x19,0x93,0xee]<br>
+<br>
+# CHECK: vfnms.f16 s2, s7, s4<br>
+[0x82,0x19,0x93,0xee]<br>
+<br>
+# CHECK: vmovx.f16 s2, s5<br>
+# CHECK: vins.f16 s2, s5<br>
+[0x62,0x1a,0xb0,0xfe]<br>
+[0xe2,0x1a,0xb0,0xfe]<br>
+<br>
+# CHECK: vldr.16 s1, [pc, #6]<br>
+# CHECK: vldr.16 s2, [pc, #510]<br>
+# CHECK: vldr.16 s3, [pc, #-510]<br>
+# CHECK: vldr.16 s4, [r4, #-18]<br>
+[0x03,0x09,0xdf,0xed]<br>
+[0xff,0x19,0x9f,0xed]<br>
+[0xff,0x19,0x5f,0xed]<br>
+[0x09,0x29,0x14,0xed]<br>
+<br>
+# CHECK: vstr.16 s1, [pc, #6]<br>
+# CHECK: vstr.16 s2, [pc, #510]<br>
+# CHECK: vstr.16 s3, [pc, #-510]<br>
+# CHECK: vstr.16 s4, [r4, #-18]<br>
+[0x03,0x09,0xcf,0xed]<br>
+[0xff,0x19,0x8f,0xed]<br>
+[0xff,0x19,0x4f,0xed]<br>
+[0x09,0x29,0x04,0xed]<br>
+<br>
+# CHECK: vmov.f16 s0, #1.0<br>
+[0x00,0x09,0xb7,0xee]<br>
+<br>
+# CHECK: vmov.f16 s1, r2<br>
+# CHECK: vmov.f16 r3, s4<br>
+[0x90,0x29,0x00,0xee]<br>
+[0x10,0x39,0x12,0xee]<br>
<br>
Added: llvm/trunk/test/MC/Disassembler/ARM/fullfp16-thumb-neg.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/fullfp16-thumb-neg.txt?rev=255762&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/fullfp16-thumb-neg.txt?rev=255762&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/ARM/fullfp16-thumb-neg.txt (added)<br>
+++ llvm/trunk/test/MC/Disassembler/ARM/fullfp16-thumb-neg.txt Wed Dec 16 05:35:44 2015<br>
@@ -0,0 +1,186 @@<br>
+# RUN: not llvm-mc -disassemble -triple thumbv8a-none-eabi -mattr=-fullfp16,+thumb-mode -show-encoding < %s 2>&1 | FileCheck %s<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x30,0xee,0x80,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x30,0xee,0xc0,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x80,0xee,0x80,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x20,0xee,0x80,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x20,0xee,0xc0,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x41,0xee,0x00,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x41,0xee,0x40,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x51,0xee,0x40,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x51,0xee,0x00,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb4,0xee,0x60,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb5,0xee,0x40,0x19]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xf4,0xee,0xc0,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb5,0xee,0xc0,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb0,0xee,0xc0,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb1,0xee,0x40,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb1,0xee,0xc0,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb8,0xee,0xc0,0x09]<br>
+[0xb8,0xee,0x40,0x09]<br>
+[0xbd,0xee,0xc0,0x09]<br>
+[0xbc,0xee,0xc0,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xbd,0xee,0x60,0x09]<br>
+[0xbc,0xee,0x60,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xbb,0xee,0xc6,0x09]<br>
+[0xbb,0xee,0x67,0x09]<br>
+[0xfa,0xee,0xc6,0x09]<br>
+[0xfa,0xee,0x67,0x89]<br>
+[0xbf,0xee,0xc6,0x69]<br>
+[0xbf,0xee,0x67,0xe9]<br>
+[0xfe,0xee,0xc6,0x09]<br>
+[0xfe,0xee,0x67,0x89]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xbc,0xfe,0xe1,0x19]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xbd,0xfe,0xeb,0x39]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xbe,0xfe,0xc2,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xff,0xfe,0xc4,0x89]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xbc,0xfe,0x61,0x19]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xbd,0xfe,0x6b,0x39]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xbe,0xfe,0x42,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xff,0xfe,0x44,0x89]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x20,0xfe,0xab,0x29]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x30,0xfe,0x80,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x0e,0xfe,0x2b,0xf9]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x58,0xfe,0x07,0xa9]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xc6,0xfe,0x00,0x29]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x80,0xfe,0x46,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xf6,0xee,0xcc,0x19]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb6,0xee,0x64,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb7,0xee,0x47,0x59]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb8,0xfe,0x60,0x69]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb9,0xfe,0x60,0x69]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xba,0xfe,0x60,0x69]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xbb,0xfe,0x60,0x69]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xa3,0xee,0x82,0x19]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xa3,0xee,0xc2,0x19]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x93,0xee,0xc2,0x19]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x93,0xee,0x82,0x19]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb0,0xfe,0x62,0x1a]<br>
+[0xb0,0xfe,0xe2,0x1a]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xdf,0xed,0x03,0x09]<br>
+[0x9f,0xed,0xff,0x19]<br>
+[0x5f,0xed,0xff,0x19]<br>
+[0x14,0xed,0x09,0x29]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xcf,0xed,0x03,0x09]<br>
+[0x8f,0xed,0xff,0x19]<br>
+[0x4f,0xed,0xff,0x19]<br>
+[0x04,0xed,0x09,0x29]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0xb7,0xee,0x00,0x09]<br>
+<br>
+# CHECK: warning: invalid instruction encoding<br>
+# CHECK: warning: invalid instruction encoding<br>
+[0x00,0xee,0x90,0x29]<br>
+[0x12,0xee,0x10,0x39]<br>
<br>
Added: llvm/trunk/test/MC/Disassembler/ARM/fullfp16-thumb.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/fullfp16-thumb.txt?rev=255762&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/fullfp16-thumb.txt?rev=255762&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/ARM/fullfp16-thumb.txt (added)<br>
+++ llvm/trunk/test/MC/Disassembler/ARM/fullfp16-thumb.txt Wed Dec 16 05:35:44 2015<br>
@@ -0,0 +1,186 @@<br>
+# RUN: llvm-mc -disassemble -triple thumbv8a-none-eabi -mattr=+fullfp16,+thumb-mode -show-encoding < %s | FileCheck %s<br>
+<br>
+# CHECK:        vadd.f16  s0, s1, s0<br>
+[0x30,0xee,0x80,0x09]<br>
+<br>
+# CHECK:        vsub.f16  s0, s1, s0<br>
+[0x30,0xee,0xc0,0x09]<br>
+<br>
+# CHECK:        vdiv.f16  s0, s1, s0<br>
+[0x80,0xee,0x80,0x09]<br>
+<br>
+# CHECK:        vmul.f16  s0, s1, s0<br>
+[0x20,0xee,0x80,0x09]<br>
+<br>
+# CHECK:        vnmul.f16       s0, s1, s0<br>
+[0x20,0xee,0xc0,0x09]<br>
+<br>
+# CHECK:        vmla.f16        s1, s2, s0<br>
+[0x41,0xee,0x00,0x09]<br>
+<br>
+# CHECK:        vmls.f16        s1, s2, s0<br>
+[0x41,0xee,0x40,0x09]<br>
+<br>
+# CHECK:        vnmla.f16       s1, s2, s0<br>
+[0x51,0xee,0x40,0x09]<br>
+<br>
+# CHECK:        vnmls.f16       s1, s2, s0<br>
+[0x51,0xee,0x00,0x09]<br>
+<br>
+# CHECK:        vcmp.f16 s0, s1<br>
+[0xb4,0xee,0x60,0x09]<br>
+<br>
+# CHECK:        vcmp.f16 s2, #0<br>
+[0xb5,0xee,0x40,0x19]<br>
+<br>
+# CHECK:        vcmpe.f16       s1, s0<br>
+[0xf4,0xee,0xc0,0x09]<br>
+<br>
+# CHECK:        vcmpe.f16       s0, #0<br>
+[0xb5,0xee,0xc0,0x09]<br>
+<br>
+# CHECK:        vabs.f16        s0, s0<br>
+[0xb0,0xee,0xc0,0x09]<br>
+<br>
+# CHECK:        vneg.f16        s0, s0<br>
+[0xb1,0xee,0x40,0x09]<br>
+<br>
+# CHECK:        vsqrt.f16       s0, s0<br>
+[0xb1,0xee,0xc0,0x09]<br>
+<br>
+# CHECK:        vcvt.f16.s32    s0, s0<br>
+# CHECK:        vcvt.f16.u32    s0, s0<br>
+# CHECK:        vcvt.s32.f16    s0, s0<br>
+# CHECK:        vcvt.u32.f16    s0, s0<br>
+[0xb8,0xee,0xc0,0x09]<br>
+[0xb8,0xee,0x40,0x09]<br>
+[0xbd,0xee,0xc0,0x09]<br>
+[0xbc,0xee,0xc0,0x09]<br>
+<br>
+# CHECK:        vcvtr.s32.f16  s0, s1<br>
+# CHECK:        vcvtr.u32.f16  s0, s1<br>
+[0xbd,0xee,0x60,0x09]<br>
+[0xbc,0xee,0x60,0x09]<br>
+<br>
+# CHECK:        vcvt.f16.u32 s0, s0, #20<br>
+# CHECK:        vcvt.f16.u16 s0, s0, #1<br>
+# CHECK:        vcvt.f16.s32 s1, s1, #20<br>
+# CHECK:        vcvt.f16.s16 s17, s17, #1<br>
+# CHECK:        vcvt.u32.f16 s12, s12, #20<br>
+# CHECK:        vcvt.u16.f16 s28, s28, #1<br>
+# CHECK:        vcvt.s32.f16 s1, s1, #20<br>
+# CHECK:        vcvt.s16.f16 s17, s17, #1<br>
+[0xbb,0xee,0xc6,0x09]<br>
+[0xbb,0xee,0x67,0x09]<br>
+[0xfa,0xee,0xc6,0x09]<br>
+[0xfa,0xee,0x67,0x89]<br>
+[0xbf,0xee,0xc6,0x69]<br>
+[0xbf,0xee,0x67,0xe9]<br>
+[0xfe,0xee,0xc6,0x09]<br>
+[0xfe,0xee,0x67,0x89]<br>
+<br>
+# CHECK: vcvta.s32.f16 s2, s3<br>
+[0xbc,0xfe,0xe1,0x19]<br>
+<br>
+# CHECK: vcvtn.s32.f16 s6, s23<br>
+[0xbd,0xfe,0xeb,0x39]<br>
+<br>
+# CHECK: vcvtp.s32.f16 s0, s4<br>
+[0xbe,0xfe,0xc2,0x09]<br>
+<br>
+# CHECK: vcvtm.s32.f16 s17, s8<br>
+[0xff,0xfe,0xc4,0x89]<br>
+<br>
+# CHECK: vcvta.u32.f16 s2, s3<br>
+[0xbc,0xfe,0x61,0x19]<br>
+<br>
+# CHECK: vcvtn.u32.f16 s6, s23<br>
+[0xbd,0xfe,0x6b,0x39]<br>
+<br>
+# CHECK: vcvtp.u32.f16 s0, s4<br>
+[0xbe,0xfe,0x42,0x09]<br>
+<br>
+# CHECK: vcvtm.u32.f16 s17, s8<br>
+[0xff,0xfe,0x44,0x89]<br>
+<br>
+# CHECK: vselge.f16 s4, s1, s23<br>
+[0x20,0xfe,0xab,0x29]<br>
+<br>
+# CHECK: vselgt.f16 s0, s1, s0<br>
+[0x30,0xfe,0x80,0x09]<br>
+<br>
+# CHECK: vseleq.f16 s30, s28, s23<br>
+[0x0e,0xfe,0x2b,0xf9]<br>
+<br>
+# CHECK: vselvs.f16 s21, s16, s14<br>
+[0x58,0xfe,0x07,0xa9]<br>
+<br>
+# CHECK: vmaxnm.f16 s5, s12, s0<br>
+[0xc6,0xfe,0x00,0x29]<br>
+<br>
+# CHECK: vminnm.f16 s0, s0, s12<br>
+[0x80,0xfe,0x46,0x09]<br>
+<br>
+# CHECK: vrintz.f16 s3, s24<br>
+[0xf6,0xee,0xcc,0x19]<br>
+<br>
+# CHECK: vrintr.f16 s0, s9<br>
+[0xb6,0xee,0x64,0x09]<br>
+<br>
+# CHECK: vrintx.f16 s10, s14<br>
+[0xb7,0xee,0x47,0x59]<br>
+<br>
+# CHECK: vrinta.f16 s12, s1<br>
+[0xb8,0xfe,0x60,0x69]<br>
+<br>
+# CHECK: vrintn.f16 s12, s1<br>
+[0xb9,0xfe,0x60,0x69]<br>
+<br>
+# CHECK: vrintp.f16 s12, s1<br>
+[0xba,0xfe,0x60,0x69]<br>
+<br>
+# CHECK: vrintm.f16 s12, s1<br>
+[0xbb,0xfe,0x60,0x69]<br>
+<br>
+# CHECK: vfma.f16 s2, s7, s4<br>
+[0xa3,0xee,0x82,0x19]<br>
+<br>
+# CHECK: vfms.f16 s2, s7, s4<br>
+[0xa3,0xee,0xc2,0x19]<br>
+<br>
+# CHECK: vfnma.f16 s2, s7, s4<br>
+[0x93,0xee,0xc2,0x19]<br>
+<br>
+# CHECK: vfnms.f16 s2, s7, s4<br>
+[0x93,0xee,0x82,0x19]<br>
+<br>
+# CHECK: vmovx.f16 s2, s5<br>
+# CHECK: vins.f16 s2, s5<br>
+[0xb0,0xfe,0x62,0x1a]<br>
+[0xb0,0xfe,0xe2,0x1a]<br>
+<br>
+# CHECK: vldr.16 s1, [pc, #6]<br>
+# CHECK: vldr.16 s2, [pc, #510]<br>
+# CHECK: vldr.16 s3, [pc, #-510]<br>
+# CHECK: vldr.16 s4, [r4, #-18]<br>
+[0xdf,0xed,0x03,0x09]<br>
+[0x9f,0xed,0xff,0x19]<br>
+[0x5f,0xed,0xff,0x19]<br>
+[0x14,0xed,0x09,0x29]<br>
+<br>
+# CHECK: vstr.16 s1, [pc, #6]<br>
+# CHECK: vstr.16 s2, [pc, #510]<br>
+# CHECK: vstr.16 s3, [pc, #-510]<br>
+# CHECK: vstr.16 s4, [r4, #-18]<br>
+[0xcf,0xed,0x03,0x09]<br>
+[0x8f,0xed,0xff,0x19]<br>
+[0x4f,0xed,0xff,0x19]<br>
+[0x04,0xed,0x09,0x29]<br>
+<br>
+# CHECK: vmov.f16 s0, #1.0<br>
+[0xb7,0xee,0x00,0x09]<br>
+<br>
+# CHECK: vmov.f16 s1, r2<br>
+# CHECK: vmov.f16 r3, s4<br>
+[0x00,0xee,0x90,0x29]<br>
+[0x12,0xee,0x10,0x39]<br>
<br>
<br>
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</blockquote></div><br></div>