<div dir="ltr">What about SBB?</div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Dec 14, 2015 at 3:12 PM, Quentin Colombet via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: qcolombet<br>
Date: Mon Dec 14 17:12:40 2015<br>
New Revision: 255570<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=255570&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=255570&view=rev</a><br>
Log:<br>
[X86] Add relaxtion logic for ADC instructions.<br>
<br>
Prior to this patch, we would wrongly stick to the variant with imm8 encoding<br>
even when the relocation could not fit that size.<br>
<br>
rdar://problem/23785506<br>
<br>
Modified:<br>
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp<br>
    llvm/trunk/test/MC/ELF/relax-arith.s<br>
<br>
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=255570&r1=255569&r2=255570&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=255570&r1=255569&r2=255570&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Mon Dec 14 17:12:40 2015<br>
@@ -204,6 +204,14 @@ static unsigned getRelaxedOpcodeArith(un<br>
   case X86::ADD64ri8: return X86::ADD64ri32;<br>
   case X86::ADD64mi8: return X86::ADD64mi32;<br>
<br>
+   // ADC<br>
+  case X86::ADC16ri8: return X86::ADC16ri;<br>
+  case X86::ADC16mi8: return X86::ADC16mi;<br>
+  case X86::ADC32ri8: return X86::ADC32ri;<br>
+  case X86::ADC32mi8: return X86::ADC32mi;<br>
+  case X86::ADC64ri8: return X86::ADC64ri32;<br>
+  case X86::ADC64mi8: return X86::ADC64mi32;<br>
+<br>
     // SUB<br>
   case X86::SUB16ri8: return X86::SUB16ri;<br>
   case X86::SUB16mi8: return X86::SUB16mi;<br>
<br>
Modified: llvm/trunk/test/MC/ELF/relax-arith.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relax-arith.s?rev=255570&r1=255569&r2=255570&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relax-arith.s?rev=255570&r1=255569&r2=255570&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/ELF/relax-arith.s (original)<br>
+++ llvm/trunk/test/MC/ELF/relax-arith.s Mon Dec 14 17:12:40 2015<br>
@@ -123,3 +123,19 @@ bar:<br>
         .section push,"x"<br>
         pushw $foo<br>
         push  $foo<br>
+<br>
+// CHECK:      Disassembly of section adc:<br>
+// CHECK-NEXT: adc:<br>
+// CHECK-NEXT:   0: 66 81 d3 00 00                       adcw $0, %bx<br>
+// CHECK-NEXT:   5: 66 81 14 25 00 00 00 00 00 00        adcw $0, 0<br>
+// CHECK-NEXT:   f: 81 d3 00 00 00 00                    adcl $0, %ebx<br>
+// CHECK-NEXT:  15: 81 14 25 00 00 00 00 00 00 00 00     adcl $0, 0<br>
+// CHECK-NEXT:  20: 48 81 d3 00 00 00 00                 adcq $0, %rbx<br>
+// CHECK-NEXT:  27: 48 81 14 25 00 00 00 00 00 00 00 00  adcq $0, 0<br>
+        .section adc,"x"<br>
+        adc  $foo, %bx<br>
+        adcw $foo, bar<br>
+        adc  $foo, %ebx<br>
+        adcl $foo, bar<br>
+        adc  $foo, %rbx<br>
+        adcq $foo, bar<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br>
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature">~Craig</div>
</div>