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<div class="moz-cite-prefix">On 12/04/2015 06:16 PM, Sean Silva
wrote:<br>
</div>
<blockquote
cite="mid:CAHnXoa=0zhsxmfPpTUaGfXP3B1QNpnBegN+04tnh8oiuUKqsSQ@mail.gmail.com"
type="cite">
<div dir="ltr"><br>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Fri, Dec 4, 2015 at 4:18 PM,
Philip Reames via llvm-commits <span dir="ltr"><<a
moz-do-not-send="true"
href="mailto:llvm-commits@lists.llvm.org"
target="_blank"><a class="moz-txt-link-abbreviated" href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a></a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">Author:
reames<br>
Date: Fri Dec 4 18:18:33 2015<br>
New Revision: 254805<br>
<br>
URL: <a moz-do-not-send="true"
href="http://llvm.org/viewvc/llvm-project?rev=254805&view=rev"
rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=254805&view=rev</a><br>
Log:<br>
[EarlyCSE] IsSimple vs IsVolatile naming clarification
(NFC)<br>
<br>
When the notion of target specific memory intrinsics was
introduced to EarlyCSE, the commit confused the notions of
volatile and simple memory access. Since I'm about to
start working on this area, cleanup the naming so that
patches aren't horribly confusing. Note that the actual
implementation was always bailing if the load or store
wasn't simple.<br>
<br>
Reminder:<br>
- "volatile" - C++ volatile, can't remove any memory
operations, but in principal unordered<br>
- "ordered" - imposes ordering constraints on other nearby
memory operations<br>
- "atomic" - can't be split or sheared. In LLVM terms,
all "ordered" operations are also atomic so the predicate
"isAtomic" is often used.<br>
</blockquote>
<div><br>
</div>
<div>What does "sheared" mean in this context? Widened?</div>
</div>
</div>
</div>
</blockquote>
Any operation which can result in less than the original bit-width
being issued all the way through the memory system. Though, looking
around, I can't find a precise quotable definition either. I'll
have to dig a bit further. In practice, the following types of
things tend to be problematic:<br>
<br>
Splitting is a problem - so, you can't value forward half a load and
reload the other half. Nor can you do two i32 loads to build an
i64. On some platforms, this implies a major cost. <br>
<br>
Widening would be a problem if the widened load was then split
without restoring the atomic marker. Widening or merging is not
inherently problematic assuming all the individual constraints are
obeyed. (Treating widening as canonicalization becomes quite a bit
harder though due to profitability questions.)<br>
<br>
RMW operations have to be performed at the original bitwidth. i.e.
an OR to set the low bit can't be reduced from i64 to i8. This is
essentially just a special application of splitting. It also
implies that narrow the bitwidth of any chain of operations has to
stop at the memory access. <br>
<br>
Depending on your hardware, you might need to worry about splitting
done within the hardware itself. For instance, some split vector
loads into two cycles and don't ensure atomicity of the two reads.
So, even if you issue the appropriate load type, you might get a
sheared value. x86 is fairly lenient on this. Other architectures,
not so much. <br>
<br>
<br>
(Fair warning - I wrote the above off the cuff without thinking it
through in detail - that pretty much guarantees I'm wrong about
_something_ in the above.)<br>
<br>
<br>
<blockquote
cite="mid:CAHnXoa=0zhsxmfPpTUaGfXP3B1QNpnBegN+04tnh8oiuUKqsSQ@mail.gmail.com"
type="cite">
<div dir="ltr">
<div class="gmail_extra">
<div class="gmail_quote">
<div><br>
</div>
<div>-- Sean Silva</div>
<div> </div>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
- "simple" - a load which is none of the above. These are
normal loads and what most of the optimizer works with.<br>
<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h<br>
llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp<br>
llvm/trunk/lib/Transforms/Scalar/EarlyCSE.cpp<br>
<br>
Modified:
llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h<br>
URL: <a moz-do-not-send="true"
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h?rev=254805&r1=254804&r2=254805&view=diff"
rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h?rev=254805&r1=254804&r2=254805&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h
(original)<br>
+++ llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h
Fri Dec 4 18:18:33 2015<br>
@@ -42,11 +42,13 @@ class Value;<br>
/// \brief Information about a load/store intrinsic
defined by the target.<br>
struct MemIntrinsicInfo {<br>
MemIntrinsicInfo()<br>
- : ReadMem(false), WriteMem(false), Vol(false),
MatchingId(0),<br>
+ : ReadMem(false), WriteMem(false), IsSimple(false),
MatchingId(0),<br>
NumMemRefs(0), PtrVal(nullptr) {}<br>
bool ReadMem;<br>
bool WriteMem;<br>
- bool Vol;<br>
+ /// True only if this memory operation is non-volatile,
non-atomic, and<br>
+ /// unordered. (See LoadInst/StoreInst for details on
each)<br>
+ bool IsSimple;<br>
// Same Id is set by the target for corresponding
load/store intrinsics.<br>
unsigned short MatchingId;<br>
int NumMemRefs;<br>
<br>
Modified:
llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp<br>
URL: <a moz-do-not-send="true"
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp?rev=254805&r1=254804&r2=254805&view=diff"
rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp?rev=254805&r1=254804&r2=254805&view=diff</a><br>
==============================================================================<br>
---
llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
(original)<br>
+++
llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Fri Dec 4 18:18:33 2015<br>
@@ -538,7 +538,7 @@ bool
AArch64TTIImpl::getTgtMemIntrinsic(<br>
case Intrinsic::aarch64_neon_ld4:<br>
Info.ReadMem = true;<br>
Info.WriteMem = false;<br>
- Info.Vol = false;<br>
+ Info.IsSimple = true;<br>
Info.NumMemRefs = 1;<br>
Info.PtrVal = Inst->getArgOperand(0);<br>
break;<br>
@@ -547,7 +547,7 @@ bool
AArch64TTIImpl::getTgtMemIntrinsic(<br>
case Intrinsic::aarch64_neon_st4:<br>
Info.ReadMem = false;<br>
Info.WriteMem = true;<br>
- Info.Vol = false;<br>
+ Info.IsSimple = true;<br>
Info.NumMemRefs = 1;<br>
Info.PtrVal =
Inst->getArgOperand(Inst->getNumArgOperands() - 1);<br>
break;<br>
<br>
Modified: llvm/trunk/lib/Transforms/Scalar/EarlyCSE.cpp<br>
URL: <a moz-do-not-send="true"
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/EarlyCSE.cpp?rev=254805&r1=254804&r2=254805&view=diff"
rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/EarlyCSE.cpp?rev=254805&r1=254804&r2=254805&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Scalar/EarlyCSE.cpp
(original)<br>
+++ llvm/trunk/lib/Transforms/Scalar/EarlyCSE.cpp Fri Dec
4 18:18:33 2015<br>
@@ -388,8 +388,8 @@ private:<br>
class ParseMemoryInst {<br>
public:<br>
ParseMemoryInst(Instruction *Inst, const
TargetTransformInfo &TTI)<br>
- : Load(false), Store(false), Vol(false),
MayReadFromMemory(false),<br>
- MayWriteToMemory(false), MatchingId(-1),
Ptr(nullptr) {<br>
+ : Load(false), Store(false), IsSimple(true),
MayReadFromMemory(false),<br>
+ MayWriteToMemory(false), MatchingId(-1),
Ptr(nullptr) {<br>
MayReadFromMemory = Inst->mayReadFromMemory();<br>
MayWriteToMemory = Inst->mayWriteToMemory();<br>
if (IntrinsicInst *II =
dyn_cast<IntrinsicInst>(Inst)) {<br>
@@ -402,22 +402,22 @@ private:<br>
MatchingId = Info.MatchingId;<br>
MayReadFromMemory = Info.ReadMem;<br>
MayWriteToMemory = Info.WriteMem;<br>
- Vol = Info.Vol;<br>
+ IsSimple = Info.IsSimple;<br>
Ptr = Info.PtrVal;<br>
}<br>
} else if (LoadInst *LI =
dyn_cast<LoadInst>(Inst)) {<br>
Load = true;<br>
- Vol = !LI->isSimple();<br>
+ IsSimple = LI->isSimple();<br>
Ptr = LI->getPointerOperand();<br>
} else if (StoreInst *SI =
dyn_cast<StoreInst>(Inst)) {<br>
Store = true;<br>
- Vol = !SI->isSimple();<br>
+ IsSimple = SI->isSimple();<br>
Ptr = SI->getPointerOperand();<br>
}<br>
}<br>
bool isLoad() const { return Load; }<br>
bool isStore() const { return Store; }<br>
- bool isVolatile() const { return Vol; }<br>
+ bool isSimple() const { return IsSimple; }<br>
bool isMatchingMemLoc(const ParseMemoryInst
&Inst) const {<br>
return Ptr == Inst.Ptr && MatchingId ==
Inst.MatchingId;<br>
}<br>
@@ -430,7 +430,7 @@ private:<br>
private:<br>
bool Load;<br>
bool Store;<br>
- bool Vol;<br>
+ bool IsSimple;<br>
bool MayReadFromMemory;<br>
bool MayWriteToMemory;<br>
// For regular (non-intrinsic) loads/stores, this is
set to -1. For<br>
@@ -554,8 +554,8 @@ bool EarlyCSE::processNode(DomTreeNode
*<br>
ParseMemoryInst MemInst(Inst, TTI);<br>
// If this is a non-volatile load, process it.<br>
if (MemInst.isValid() && MemInst.isLoad()) {<br>
- // Ignore volatile loads.<br>
- if (MemInst.isVolatile()) {<br>
+ // Ignore volatile or ordered loads.<br>
+ if (!MemInst.isSimple()) {<br>
LastStore = nullptr;<br>
// Don't CSE across synchronization boundaries.<br>
if (Inst->mayWriteToMemory())<br>
@@ -662,8 +662,8 @@ bool EarlyCSE::processNode(DomTreeNode
*<br>
MemInst.getPtr(),<br>
LoadValue(Inst, CurrentGeneration,
MemInst.getMatchingId()));<br>
<br>
- // Remember that this was the last store we saw
for DSE.<br>
- if (!MemInst.isVolatile())<br>
+ // Remember that this was the last normal store
we saw for DSE.<br>
+ if (MemInst.isSimple())<br>
LastStore = Inst;<br>
}<br>
}<br>
<br>
<br>
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