<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Dec 1, 2015 at 2:49 AM, Oliver Stannard via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Author: olista01<br>
Date: Tue Dec 1 04:48:51 2015<br>
New Revision: 254401<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=254401&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=254401&view=rev</a><br>
Log:<br>
[AArch64] Add ARMv8.2-A Statistical Profiling Extension<br></blockquote><div><br></div><div>A quick googling doesn't seem to find info on this. Can you add a link with info about it to <a href="http://llvm.org/docs/CompilerWriterInfo.html">http://llvm.org/docs/CompilerWriterInfo.html</a> ? (docs/CompilerWriterInfo.rst)</div><div><br></div><div>-- Sean Silva</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<br>
The Statistical Profiling Extension is an optional extension to<br>
ARMv8.2-A. Since it is an optional extension, I have added the<br>
FeatureSPE subtarget feature to control it. The assembler-visible parts<br>
of this extension are the new "psb csync" instruction, which is<br>
equivalent to "hint #17", and a number of system registers.<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D15021" rel="noreferrer" target="_blank">http://reviews.llvm.org/D15021</a><br>
<br>
<br>
Added:<br>
llvm/trunk/test/MC/AArch64/armv8.2a-statistical-profiling.s<br>
llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-statistical-profiling.txt<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/AArch64.td<br>
llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td<br>
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td<br>
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h<br>
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp<br>
llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp<br>
llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h<br>
llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp<br>
llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h<br>
llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=254401&r1=254400&r2=254401&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=254401&r1=254400&r2=254401&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Tue Dec 1 04:48:51 2015<br>
@@ -38,6 +38,9 @@ def FeaturePerfMon : SubtargetFeature<"p<br>
def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",<br>
"Full FP16", [FeatureFPARMv8]>;<br>
<br>
+def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",<br>
+ "Enable Statistical Profiling extension">;<br>
+<br>
/// Cyclone has register move instructions which are "free".<br>
def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",<br>
"Has zero-cycle register moves">;<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=254401&r1=254400&r2=254401&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=254401&r1=254400&r2=254401&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Tue Dec 1 04:48:51 2015<br>
@@ -911,6 +911,25 @@ def msr_sysreg_op : Operand<i32> {<br>
let PrintMethod = "printMSRSystemRegister";<br>
}<br>
<br>
+def PSBHintOperand : AsmOperandClass {<br>
+ let Name = "PSBHint";<br>
+ let ParserMethod = "tryParsePSBHint";<br>
+}<br>
+def psbhint_op : Operand<i32> {<br>
+ let ParserMatchClass = PSBHintOperand;<br>
+ let PrintMethod = "printPSBHintOp";<br>
+ let MCOperandPredicate = [{<br>
+ // Check, if operand is valid, to fix exhaustive aliasing in disassembly.<br>
+ // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.<br>
+ if (!MCOp.isImm())<br>
+ return false;<br>
+ bool ValidNamed;<br>
+ (void)AArch64PSBHint::PSBHintMapper().toString(MCOp.getImm(),<br>
+ STI.getFeatureBits(), ValidNamed);<br>
+ return ValidNamed;<br>
+ }];<br>
+}<br>
+<br>
class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),<br>
"mrs", "\t$Rt, $systemreg"> {<br>
bits<16> systemreg;<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=254401&r1=254400&r2=254401&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=254401&r1=254400&r2=254401&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Tue Dec 1 04:48:51 2015<br>
@@ -29,6 +29,8 @@ def HasCRC : Predicate<"Subtar<br>
def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">;<br>
def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,<br>
AssemblerPredicate<"FeatureFullFP16", "fullfp16">;<br>
+def HasSPE : Predicate<"Subtarget->hasSPE()">,<br>
+ AssemblerPredicate<"FeatureSPE", "spe">;<br>
<br>
def IsLE : Predicate<"Subtarget->isLittleEndian()">;<br>
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;<br>
@@ -382,6 +384,9 @@ def : InstAlias<"wfi", (HINT 0b011)>;<br>
def : InstAlias<"sev", (HINT 0b100)>;<br>
def : InstAlias<"sevl", (HINT 0b101)>;<br>
<br>
+// v8.2a Statistical Profiling extension<br>
+def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>;<br>
+<br>
// As far as LLVM is concerned this writes to the system's exclusive monitors.<br>
let mayLoad = 1, mayStore = 1 in<br>
def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=254401&r1=254400&r2=254401&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=254401&r1=254400&r2=254401&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Tue Dec 1 04:48:51 2015<br>
@@ -47,6 +47,7 @@ protected:<br>
bool HasCRC;<br>
bool HasPerfMon;<br>
bool HasFullFP16;<br>
+ bool HasSPE;<br>
<br>
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.<br>
bool HasZeroCycleRegMove;<br>
@@ -124,6 +125,7 @@ public:<br>
<br>
bool hasPerfMon() const { return HasPerfMon; }<br>
bool hasFullFP16() const { return HasFullFP16; }<br>
+ bool hasSPE() const { return HasSPE; }<br>
<br>
bool isLittleEndian() const { return IsLittle; }<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=254401&r1=254400&r2=254401&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=254401&r1=254400&r2=254401&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Tue Dec 1 04:48:51 2015<br>
@@ -100,6 +100,7 @@ private:<br>
OperandMatchResultTy tryParseSysReg(OperandVector &Operands);<br>
OperandMatchResultTy tryParseSysCROperand(OperandVector &Operands);<br>
OperandMatchResultTy tryParsePrefetch(OperandVector &Operands);<br>
+ OperandMatchResultTy tryParsePSBHint(OperandVector &Operands);<br>
OperandMatchResultTy tryParseAdrpLabel(OperandVector &Operands);<br>
OperandMatchResultTy tryParseAdrLabel(OperandVector &Operands);<br>
OperandMatchResultTy tryParseFPImm(OperandVector &Operands);<br>
@@ -159,7 +160,8 @@ private:<br>
k_Prefetch,<br>
k_ShiftExtend,<br>
k_FPImm,<br>
- k_Barrier<br>
+ k_Barrier,<br>
+ k_PSBHint,<br>
} Kind;<br>
<br>
SMLoc StartLoc, EndLoc;<br>
@@ -227,6 +229,12 @@ private:<br>
unsigned Length;<br>
};<br>
<br>
+ struct PSBHintOp {<br>
+ unsigned Val;<br>
+ const char *Data;<br>
+ unsigned Length;<br>
+ };<br>
+<br>
struct ShiftExtendOp {<br>
AArch64_AM::ShiftExtendType Type;<br>
unsigned Amount;<br>
@@ -250,6 +258,7 @@ private:<br>
struct SysRegOp SysReg;<br>
struct SysCRImmOp SysCRImm;<br>
struct PrefetchOp Prefetch;<br>
+ struct PSBHintOp PSBHint;<br>
struct ShiftExtendOp ShiftExtend;<br>
};<br>
<br>
@@ -301,6 +310,9 @@ public:<br>
case k_Prefetch:<br>
Prefetch = o.Prefetch;<br>
break;<br>
+ case k_PSBHint:<br>
+ PSBHint = o.PSBHint;<br>
+ break;<br>
case k_ShiftExtend:<br>
ShiftExtend = o.ShiftExtend;<br>
break;<br>
@@ -392,6 +404,16 @@ public:<br>
return Prefetch.Val;<br>
}<br>
<br>
+ unsigned getPSBHint() const {<br>
+ assert(Kind == k_PSBHint && "Invalid access!");<br>
+ return PSBHint.Val;<br>
+ }<br>
+<br>
+ StringRef getPSBHintName() const {<br>
+ assert(Kind == k_PSBHint && "Invalid access!");<br>
+ return StringRef(PSBHint.Data, PSBHint.Length);<br>
+ }<br>
+<br>
StringRef getPrefetchName() const {<br>
assert(Kind == k_Prefetch && "Invalid access!");<br>
return StringRef(Prefetch.Data, Prefetch.Length);<br>
@@ -961,6 +983,7 @@ public:<br>
}<br>
bool isSysCR() const { return Kind == k_SysCR; }<br>
bool isPrefetch() const { return Kind == k_Prefetch; }<br>
+ bool isPSBHint() const { return Kind == k_PSBHint; }<br>
bool isShiftExtend() const { return Kind == k_ShiftExtend; }<br>
bool isShifter() const {<br>
if (!isShiftExtend())<br>
@@ -1534,6 +1557,11 @@ public:<br>
Inst.addOperand(MCOperand::createImm(getPrefetch()));<br>
}<br>
<br>
+ void addPSBHintOperands(MCInst &Inst, unsigned N) const {<br>
+ assert(N == 1 && "Invalid number of operands!");<br>
+ Inst.addOperand(MCOperand::createImm(getPSBHint()));<br>
+ }<br>
+<br>
void addShifterOperands(MCInst &Inst, unsigned N) const {<br>
assert(N == 1 && "Invalid number of operands!");<br>
unsigned Imm =<br>
@@ -1730,6 +1758,19 @@ public:<br>
return Op;<br>
}<br>
<br>
+ static std::unique_ptr<AArch64Operand> CreatePSBHint(unsigned Val,<br>
+ StringRef Str,<br>
+ SMLoc S,<br>
+ MCContext &Ctx) {<br>
+ auto Op = make_unique<AArch64Operand>(k_PSBHint, Ctx);<br>
+ Op->PSBHint.Val = Val;<br>
+ Op->PSBHint.Data = Str.data();<br>
+ Op->PSBHint.Length = Str.size();<br>
+ Op->StartLoc = S;<br>
+ Op->EndLoc = S;<br>
+ return Op;<br>
+ }<br>
+<br>
static std::unique_ptr<AArch64Operand><br>
CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val,<br>
bool HasExplicitAmount, SMLoc S, SMLoc E, MCContext &Ctx) {<br>
@@ -1803,6 +1844,10 @@ void AArch64Operand::print(raw_ostream &<br>
OS << "<prfop invalid #" << getPrefetch() << ">";<br>
break;<br>
}<br>
+ case k_PSBHint: {<br>
+ OS << getPSBHintName();<br>
+ break;<br>
+ }<br>
case k_ShiftExtend: {<br>
OS << "<" << AArch64_AM::getShiftExtendName(getShiftExtendType()) << " #"<br>
<< getShiftExtendAmount();<br>
@@ -2069,6 +2114,32 @@ AArch64AsmParser::tryParsePrefetch(Opera<br>
return MatchOperand_Success;<br>
}<br>
<br>
+/// tryParsePSBHint - Try to parse a PSB operand, mapped to Hint command<br>
+AArch64AsmParser::OperandMatchResultTy<br>
+AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) {<br>
+ MCAsmParser &Parser = getParser();<br>
+ SMLoc S = getLoc();<br>
+ const AsmToken &Tok = Parser.getTok();<br>
+ if (Tok.isNot(AsmToken::Identifier)) {<br>
+ TokError("invalid operand for instruction");<br>
+ return MatchOperand_ParseFail;<br>
+ }<br>
+<br>
+ bool Valid;<br>
+ auto Mapper = AArch64PSBHint::PSBHintMapper();<br>
+ unsigned psbhint =<br>
+ Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid);<br>
+ if (!Valid) {<br>
+ TokError("invalid operand for instruction");<br>
+ return MatchOperand_ParseFail;<br>
+ }<br>
+<br>
+ Parser.Lex(); // Eat identifier token.<br>
+ Operands.push_back(AArch64Operand::CreatePSBHint(psbhint, Tok.getString(),<br>
+ S, getContext()));<br>
+ return MatchOperand_Success;<br>
+}<br>
+<br>
/// tryParseAdrpLabel - Parse and validate a source label for the ADRP<br>
/// instruction.<br>
AArch64AsmParser::OperandMatchResultTy<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp?rev=254401&r1=254400&r2=254401&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp?rev=254401&r1=254400&r2=254401&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp Tue Dec 1 04:48:51 2015<br>
@@ -1144,6 +1144,19 @@ void AArch64InstPrinter::printPrefetchOp<br>
O << '#' << prfop;<br>
}<br>
<br>
+void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,<br>
+ const MCSubtargetInfo &STI,<br>
+ raw_ostream &O) {<br>
+ unsigned psbhintop = MI->getOperand(OpNum).getImm();<br>
+ bool Valid;<br>
+ StringRef Name =<br>
+ AArch64PSBHint::PSBHintMapper().toString(psbhintop, STI.getFeatureBits(), Valid);<br>
+ if (Valid)<br>
+ O << Name;<br>
+ else<br>
+ O << '#' << psbhintop;<br>
+}<br>
+<br>
void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,<br>
const MCSubtargetInfo &STI,<br>
raw_ostream &O) {<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h?rev=254401&r1=254400&r2=254401&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h?rev=254401&r1=254400&r2=254401&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h Tue Dec 1 04:48:51 2015<br>
@@ -123,6 +123,9 @@ protected:<br>
void printPrefetchOp(const MCInst *MI, unsigned OpNum,<br>
const MCSubtargetInfo &STI, raw_ostream &O);<br>
<br>
+ void printPSBHintOp(const MCInst *MI, unsigned OpNum,<br>
+ const MCSubtargetInfo &STI, raw_ostream &O);<br>
+<br>
void printFPImmOperand(const MCInst *MI, unsigned OpNum,<br>
const MCSubtargetInfo &STI, raw_ostream &O);<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp?rev=254401&r1=254400&r2=254401&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp?rev=254401&r1=254400&r2=254401&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp Tue Dec 1 04:48:51 2015<br>
@@ -154,6 +154,14 @@ const AArch64NamedImmMapper::Mapping AAr<br>
AArch64PState::PStateMapper::PStateMapper()<br>
: AArch64NamedImmMapper(PStateMappings, 0) {}<br>
<br>
+const AArch64NamedImmMapper::Mapping AArch64PSBHint::PSBHintMapper::PSBHintMappings[] = {<br>
+ // v8.2a "Statistical Profiling" extension-specific PSB operand<br>
+ {"csync", CSync, {AArch64::FeatureSPE}},<br>
+};<br>
+<br>
+AArch64PSBHint::PSBHintMapper::PSBHintMapper()<br>
+ : AArch64NamedImmMapper(PSBHintMappings, 0) {}<br>
+<br>
const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {<br>
{"mdccsr_el0", MDCCSR_EL0, {}},<br>
{"dbgdtrrx_el0", DBGDTRRX_EL0, {}},<br>
@@ -808,6 +816,21 @@ const AArch64NamedImmMapper::Mapping AAr<br>
<br>
// v8.2a registers<br>
{"uao", UAO, {AArch64::HasV8_2aOps}},<br>
+<br>
+ // v8.2a "Statistical Profiling extension" registers<br>
+ {"pmblimitr_el1", PMBLIMITR_EL1, {AArch64::FeatureSPE}},<br>
+ {"pmbptr_el1", PMBPTR_EL1, {AArch64::FeatureSPE}},<br>
+ {"pmbsr_el1", PMBSR_EL1, {AArch64::FeatureSPE}},<br>
+ {"pmbidr_el1", PMBIDR_EL1, {AArch64::FeatureSPE}},<br>
+ {"pmscr_el2", PMSCR_EL2, {AArch64::FeatureSPE}},<br>
+ {"pmscr_el12", PMSCR_EL12, {AArch64::FeatureSPE}},<br>
+ {"pmscr_el1", PMSCR_EL1, {AArch64::FeatureSPE}},<br>
+ {"pmsicr_el1", PMSICR_EL1, {AArch64::FeatureSPE}},<br>
+ {"pmsirr_el1", PMSIRR_EL1, {AArch64::FeatureSPE}},<br>
+ {"pmsfcr_el1", PMSFCR_EL1, {AArch64::FeatureSPE}},<br>
+ {"pmsevfr_el1", PMSEVFR_EL1, {AArch64::FeatureSPE}},<br>
+ {"pmslatfr_el1", PMSLATFR_EL1, {AArch64::FeatureSPE}},<br>
+ {"pmsidr_el1", PMSIDR_EL1, {AArch64::FeatureSPE}},<br>
};<br>
<br>
uint32_t<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h?rev=254401&r1=254400&r2=254401&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h?rev=254401&r1=254400&r2=254401&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h Tue Dec 1 04:48:51 2015<br>
@@ -478,6 +478,21 @@ namespace AArch64PState {<br>
<br>
}<br>
<br>
+namespace AArch64PSBHint {<br>
+ enum PSBHintValues {<br>
+ Invalid = -1,<br>
+ // v8.2a "Statistical Profiling" extension-specific PSB operands<br>
+ CSync = 0x11, // psb csync = hint #0x11<br>
+ };<br>
+<br>
+ struct PSBHintMapper : AArch64NamedImmMapper {<br>
+ const static Mapping PSBHintMappings[];<br>
+<br>
+ PSBHintMapper();<br>
+ };<br>
+<br>
+}<br>
+<br>
namespace AArch64SE {<br>
enum ShiftExtSpecifiers {<br>
Invalid = -1,<br>
@@ -1199,6 +1214,21 @@ namespace AArch64SysReg {<br>
// v8.2a registers<br>
UAO = 0xc214, // 11 000 0100 0010 100<br>
<br>
+ // v8.2a "Statistical Profiling extension" registers<br>
+ PMBLIMITR_EL1 = 0xc4d0, // 11 000 1001 1010 000<br>
+ PMBPTR_EL1 = 0xc4d1, // 11 000 1001 1010 001<br>
+ PMBSR_EL1 = 0xc4d3, // 11 000 1001 1010 011<br>
+ PMBIDR_EL1 = 0xc4d7, // 11 000 1001 1010 111<br>
+ PMSCR_EL2 = 0xe4c8, // 11 100 1001 1001 000<br>
+ PMSCR_EL12 = 0xecc8, // 11 101 1001 1001 000<br>
+ PMSCR_EL1 = 0xc4c8, // 11 000 1001 1001 000<br>
+ PMSICR_EL1 = 0xc4ca, // 11 000 1001 1001 010<br>
+ PMSIRR_EL1 = 0xc4cb, // 11 000 1001 1001 011<br>
+ PMSFCR_EL1 = 0xc4cc, // 11 000 1001 1001 100<br>
+ PMSEVFR_EL1 = 0xc4cd, // 11 000 1001 1001 101<br>
+ PMSLATFR_EL1 = 0xc4ce, // 11 000 1001 1001 110<br>
+ PMSIDR_EL1 = 0xc4cf, // 11 000 1001 1001 111<br>
+<br>
// Cyclone specific system registers<br>
CPM_IOACC_CTL_EL3 = 0xff90,<br>
};<br>
<br>
Added: llvm/trunk/test/MC/AArch64/armv8.2a-statistical-profiling.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-statistical-profiling.s?rev=254401&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-statistical-profiling.s?rev=254401&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/armv8.2a-statistical-profiling.s (added)<br>
+++ llvm/trunk/test/MC/AArch64/armv8.2a-statistical-profiling.s Tue Dec 1 04:48:51 2015<br>
@@ -0,0 +1,87 @@<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+spe < %s | FileCheck %s<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2>&1 | FileCheck --check-prefix=NO_SPE %s<br>
+<br>
+ psb csync<br>
+// CHECK: psb csync // encoding: [0x3f,0x22,0x03,0xd5]<br>
+// NO_SPE: invalid operand for instruction<br>
+<br>
+ msr pmblimitr_el1, x0<br>
+ msr pmbptr_el1, x0<br>
+ msr pmbsr_el1, x0<br>
+ msr pmbidr_el1, x0<br>
+ msr pmscr_el2, x0<br>
+ msr pmscr_el12, x0<br>
+ msr pmscr_el1, x0<br>
+ msr pmsicr_el1, x0<br>
+ msr pmsirr_el1, x0<br>
+ msr pmsfcr_el1, x0<br>
+ msr pmsevfr_el1, x0<br>
+ msr pmslatfr_el1, x0<br>
+ msr pmsidr_el1, x0<br>
+// CHECK: msr PMBLIMITR_EL1, x0 // encoding: [0x00,0x9a,0x18,0xd5]<br>
+// CHECK: msr PMBPTR_EL1, x0 // encoding: [0x20,0x9a,0x18,0xd5]<br>
+// CHECK: msr PMBSR_EL1, x0 // encoding: [0x60,0x9a,0x18,0xd5]<br>
+// CHECK: msr PMBIDR_EL1, x0 // encoding: [0xe0,0x9a,0x18,0xd5]<br>
+// CHECK: msr PMSCR_EL2, x0 // encoding: [0x00,0x99,0x1c,0xd5]<br>
+// CHECK: msr PMSCR_EL12, x0 // encoding: [0x00,0x99,0x1d,0xd5]<br>
+// CHECK: msr PMSCR_EL1, x0 // encoding: [0x00,0x99,0x18,0xd5]<br>
+// CHECK: msr PMSICR_EL1, x0 // encoding: [0x40,0x99,0x18,0xd5]<br>
+// CHECK: msr PMSIRR_EL1, x0 // encoding: [0x60,0x99,0x18,0xd5]<br>
+// CHECK: msr PMSFCR_EL1, x0 // encoding: [0x80,0x99,0x18,0xd5]<br>
+// CHECK: msr PMSEVFR_EL1, x0 // encoding: [0xa0,0x99,0x18,0xd5]<br>
+// CHECK: msr PMSLATFR_EL1, x0 // encoding: [0xc0,0x99,0x18,0xd5]<br>
+// CHECK: msr PMSIDR_EL1, x0 // encoding: [0xe0,0x99,0x18,0xd5]<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+// NO_SPE: error: expected writable system register or pstate<br>
+<br>
+mrs x0, pmblimitr_el1<br>
+ mrs x0, pmbptr_el1<br>
+ mrs x0, pmbsr_el1<br>
+ mrs x0, pmbidr_el1<br>
+ mrs x0, pmscr_el2<br>
+ mrs x0, pmscr_el12<br>
+ mrs x0, pmscr_el1<br>
+ mrs x0, pmsicr_el1<br>
+ mrs x0, pmsirr_el1<br>
+ mrs x0, pmsfcr_el1<br>
+ mrs x0, pmsevfr_el1<br>
+ mrs x0, pmslatfr_el1<br>
+ mrs x0, pmsidr_el1<br>
+<br>
+// CHECK: mrs x0, PMBLIMITR_EL1 // encoding: [0x00,0x9a,0x38,0xd5]<br>
+// CHECK: mrs x0, PMBPTR_EL1 // encoding: [0x20,0x9a,0x38,0xd5]<br>
+// CHECK: mrs x0, PMBSR_EL1 // encoding: [0x60,0x9a,0x38,0xd5]<br>
+// CHECK: mrs x0, PMBIDR_EL1 // encoding: [0xe0,0x9a,0x38,0xd5]<br>
+// CHECK: mrs x0, PMSCR_EL2 // encoding: [0x00,0x99,0x3c,0xd5]<br>
+// CHECK: mrs x0, PMSCR_EL12 // encoding: [0x00,0x99,0x3d,0xd5]<br>
+// CHECK: mrs x0, PMSCR_EL1 // encoding: [0x00,0x99,0x38,0xd5]<br>
+// CHECK: mrs x0, PMSICR_EL1 // encoding: [0x40,0x99,0x38,0xd5]<br>
+// CHECK: mrs x0, PMSIRR_EL1 // encoding: [0x60,0x99,0x38,0xd5]<br>
+// CHECK: mrs x0, PMSFCR_EL1 // encoding: [0x80,0x99,0x38,0xd5]<br>
+// CHECK: mrs x0, PMSEVFR_EL1 // encoding: [0xa0,0x99,0x38,0xd5]<br>
+// CHECK: mrs x0, PMSLATFR_EL1 // encoding: [0xc0,0x99,0x38,0xd5]<br>
+// CHECK: mrs x0, PMSIDR_EL1 // encoding: [0xe0,0x99,0x38,0xd5]<br>
+// NO_SPE: error: expected readable system register<br>
+// NO_SPE: error: expected readable system register<br>
+// NO_SPE: error: expected readable system register<br>
+// NO_SPE: error: expected readable system register<br>
+// NO_SPE: error: expected readable system register<br>
+// NO_SPE: error: expected readable system register<br>
+// NO_SPE: error: expected readable system register<br>
+// NO_SPE: error: expected readable system register<br>
+// NO_SPE: error: expected readable system register<br>
+// NO_SPE: error: expected readable system register<br>
+// NO_SPE: error: expected readable system register<br>
+// NO_SPE: error: expected readable system register<br>
+// NO_SPE: error: expected readable system register<br>
<br>
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-statistical-profiling.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-statistical-profiling.txt?rev=254401&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-statistical-profiling.txt?rev=254401&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-statistical-profiling.txt (added)<br>
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-statistical-profiling.txt Tue Dec 1 04:48:51 2015<br>
@@ -0,0 +1,91 @@<br>
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+spe --disassemble < %s | FileCheck %s<br>
+# RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s | FileCheck --check-prefix=NO_SPE %s<br>
+<br>
+[0x1f,0x22,0x03,0xd5]<br>
+# CHECK: hint #0x10<br>
+# NO_SPE: hint #0x10<br>
+<br>
+[0x3f,0x22,0x03,0xd5]<br>
+# CHECK: psb csync<br>
+# NO_SPE: hint #0x11<br>
+<br>
+[0x00,0x9a,0x18,0xd5]<br>
+[0x20,0x9a,0x18,0xd5]<br>
+[0x60,0x9a,0x18,0xd5]<br>
+[0xe0,0x9a,0x18,0xd5]<br>
+[0x00,0x99,0x1c,0xd5]<br>
+[0x00,0x99,0x1d,0xd5]<br>
+[0x00,0x99,0x18,0xd5]<br>
+[0x40,0x99,0x18,0xd5]<br>
+[0x60,0x99,0x18,0xd5]<br>
+[0x80,0x99,0x18,0xd5]<br>
+[0xa0,0x99,0x18,0xd5]<br>
+[0xc0,0x99,0x18,0xd5]<br>
+[0xe0,0x99,0x18,0xd5]<br>
+# CHECK: msr PMBLIMITR_EL1, x0<br>
+# NO_SPE: msr S3_0_C9_C10_0, x0<br>
+# CHECK: msr PMBPTR_EL1, x0<br>
+# NO_SPE: msr S3_0_C9_C10_1, x0<br>
+# CHECK: msr PMBSR_EL1, x0<br>
+# NO_SPE: msr S3_0_C9_C10_3, x0<br>
+# CHECK: msr PMBIDR_EL1, x0<br>
+# NO_SPE: msr S3_0_C9_C10_7, x0<br>
+# CHECK: msr PMSCR_EL2, x0<br>
+# NO_SPE: msr S3_4_C9_C9_0, x0<br>
+# CHECK: msr PMSCR_EL12, x0<br>
+# NO_SPE: msr S3_5_C9_C9_0, x0<br>
+# CHECK: msr PMSCR_EL1, x0<br>
+# NO_SPE: msr S3_0_C9_C9_0, x0<br>
+# CHECK: msr PMSICR_EL1, x0<br>
+# NO_SPE: msr S3_0_C9_C9_2, x0<br>
+# CHECK: msr PMSIRR_EL1, x0<br>
+# NO_SPE: msr S3_0_C9_C9_3, x0<br>
+# CHECK: msr PMSFCR_EL1, x0<br>
+# NO_SPE: msr S3_0_C9_C9_4, x0<br>
+# CHECK: msr PMSEVFR_EL1, x0<br>
+# NO_SPE: msr S3_0_C9_C9_5, x0<br>
+# CHECK: msr PMSLATFR_EL1, x0<br>
+# NO_SPE: msr S3_0_C9_C9_6, x0<br>
+# CHECK: msr PMSIDR_EL1, x0<br>
+# NO_SPE: msr S3_0_C9_C9_7, x0<br>
+<br>
+[0x00,0x9a,0x38,0xd5]<br>
+[0x20,0x9a,0x38,0xd5]<br>
+[0x60,0x9a,0x38,0xd5]<br>
+[0xe0,0x9a,0x38,0xd5]<br>
+[0x00,0x99,0x3c,0xd5]<br>
+[0x00,0x99,0x3d,0xd5]<br>
+[0x00,0x99,0x38,0xd5]<br>
+[0x40,0x99,0x38,0xd5]<br>
+[0x60,0x99,0x38,0xd5]<br>
+[0x80,0x99,0x38,0xd5]<br>
+[0xa0,0x99,0x38,0xd5]<br>
+[0xc0,0x99,0x38,0xd5]<br>
+[0xe0,0x99,0x38,0xd5]<br>
+<br>
+# CHECK: mrs x0, PMBLIMITR_EL1<br>
+# NO_SPE: mrs x0, S3_0_C9_C10_0<br>
+# CHECK: mrs x0, PMBPTR_EL1<br>
+# NO_SPE: mrs x0, S3_0_C9_C10_1<br>
+# CHECK: mrs x0, PMBSR_EL1<br>
+# NO_SPE: mrs x0, S3_0_C9_C10_3<br>
+# CHECK: mrs x0, PMBIDR_EL1<br>
+# NO_SPE: mrs x0, S3_0_C9_C10_7<br>
+# CHECK: mrs x0, PMSCR_EL2<br>
+# NO_SPE: mrs x0, S3_4_C9_C9_0<br>
+# CHECK: mrs x0, PMSCR_EL12<br>
+# NO_SPE: mrs x0, S3_5_C9_C9_0<br>
+# CHECK: mrs x0, PMSCR_EL1<br>
+# NO_SPE: mrs x0, S3_0_C9_C9_0<br>
+# CHECK: mrs x0, PMSICR_EL1<br>
+# NO_SPE: mrs x0, S3_0_C9_C9_2<br>
+# CHECK: mrs x0, PMSIRR_EL1<br>
+# NO_SPE: mrs x0, S3_0_C9_C9_3<br>
+# CHECK: mrs x0, PMSFCR_EL1<br>
+# NO_SPE: mrs x0, S3_0_C9_C9_4<br>
+# CHECK: mrs x0, PMSEVFR_EL1<br>
+# NO_SPE: mrs x0, S3_0_C9_C9_5<br>
+# CHECK: mrs x0, PMSLATFR_EL1<br>
+# NO_SPE: mrs x0, S3_0_C9_C9_6<br>
+# CHECK: mrs x0, PMSIDR_EL1<br>
+# NO_SPE: mrs x0, S3_0_C9_C9_7<br>
<br>
Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=254401&r1=254400&r2=254401&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=254401&r1=254400&r2=254401&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Tue Dec 1 04:48:51 2015<br>
@@ -901,7 +901,7 @@ void AsmWriterEmitter::EmitPrintAliasIns<br>
break; // No conditions on this operand at all<br>
}<br>
Cond = Target.getName() + ClassName + "ValidateMCOperand(" +<br>
- Op + ", " + llvm::utostr(Entry) + ")";<br>
+ Op + ", STI, " + llvm::utostr(Entry) + ")";<br>
}<br>
// for all subcases of ResultOperand::K_Record:<br>
IAP.addCond(Cond);<br>
@@ -996,8 +996,9 @@ void AsmWriterEmitter::EmitPrintAliasIns<br>
<br>
if (!MCOpPredicates.empty())<br>
O << "static bool " << Target.getName() << ClassName<br>
- << "ValidateMCOperand(\n"<br>
- << " const MCOperand &MCOp, unsigned PredicateIndex);\n";<br>
+ << "ValidateMCOperand(const MCOperand &MCOp,\n"<br>
+ << " const MCSubtargetInfo &STI,\n"<br>
+ << " unsigned PredicateIndex);\n";<br>
<br>
O << HeaderO.str();<br>
O.indent(2) << "const char *AsmString;\n";<br>
@@ -1069,8 +1070,9 @@ void AsmWriterEmitter::EmitPrintAliasIns<br>
<br>
if (!MCOpPredicates.empty()) {<br>
O << "static bool " << Target.getName() << ClassName<br>
- << "ValidateMCOperand(\n"<br>
- << " const MCOperand &MCOp, unsigned PredicateIndex) {\n"<br>
+ << "ValidateMCOperand(const MCOperand &MCOp,\n"<br>
+ << " const MCSubtargetInfo &STI,\n"<br>
+ << " unsigned PredicateIndex) {\n"<br>
<< " switch (PredicateIndex) {\n"<br>
<< " default:\n"<br>
<< " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"<br>
<br>
<br>
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</blockquote></div><br></div></div>