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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>I sent an email to who appears to be the maintainer 'gkistanova@gmail.com'<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>I think the bot needs to be cleaned, ASM parsing was enabled with that commit and other builders seem to have taken it.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'> David Blaikie [mailto:dblaikie@gmail.com] <br><b>Sent:</b> Monday, November 09, 2015 10:08 AM<br><b>To:</b> Colin LeMahieu<br><b>Cc:</b> llvm-commits<br><b>Subject:</b> Re: [llvm] r252443 - [Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission.<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>This seems to have broken a bot ( <a href="http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/26199">http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/26199</a> ) even after a fix in r252447 ( <a href="http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/26202">http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/26202</a> )<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>On Sun, Nov 8, 2015 at 8:07 PM, Colin LeMahieu via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<o:p></o:p></p><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt'><p class=MsoNormal>Author: colinl<br>Date: Sun Nov 8 22:07:48 2015<br>New Revision: 252443<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=252443&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=252443&view=rev</a><br>Log:<br>[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission.<br><br>Added:<br> llvm/trunk/lib/Target/Hexagon/AsmParser/<br> llvm/trunk/lib/Target/Hexagon/AsmParser/CMakeLists.txt<br> llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp<br> llvm/trunk/lib/Target/Hexagon/AsmParser/LLVMBuild.txt<br> llvm/trunk/lib/Target/Hexagon/AsmParser/Makefile<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h<br> llvm/trunk/test/MC/Disassembler/Hexagon/invalid_packet.txt<br> llvm/trunk/test/MC/Disassembler/Hexagon/too_many_instructions.txt<br> llvm/trunk/test/MC/Disassembler/Hexagon/too_many_loop_ends.txt<br> llvm/trunk/test/MC/Disassembler/Hexagon/unextendable.txt<br> llvm/trunk/test/MC/Hexagon/instructions/<br> llvm/trunk/test/MC/Hexagon/instructions/alu32_alu.s<br> llvm/trunk/test/MC/Hexagon/instructions/alu32_perm.s<br> llvm/trunk/test/MC/Hexagon/instructions/alu32_pred.s<br> llvm/trunk/test/MC/Hexagon/instructions/cr.s<br> llvm/trunk/test/MC/Hexagon/instructions/j.s<br> llvm/trunk/test/MC/Hexagon/instructions/jr.s<br> llvm/trunk/test/MC/Hexagon/instructions/ld.s<br> llvm/trunk/test/MC/Hexagon/instructions/memop.s<br> llvm/trunk/test/MC/Hexagon/instructions/nv_j.s<br> llvm/trunk/test/MC/Hexagon/instructions/nv_st.s<br> llvm/trunk/test/MC/Hexagon/instructions/st.s<br> llvm/trunk/test/MC/Hexagon/instructions/system_user.s<br> llvm/trunk/test/MC/Hexagon/instructions/xtype_alu.s<br> llvm/trunk/test/MC/Hexagon/instructions/xtype_bit.s<br> llvm/trunk/test/MC/Hexagon/instructions/xtype_complex.s<br> llvm/trunk/test/MC/Hexagon/instructions/xtype_fp.s<br> llvm/trunk/test/MC/Hexagon/instructions/xtype_mpy.s<br> llvm/trunk/test/MC/Hexagon/instructions/xtype_perm.s<br> llvm/trunk/test/MC/Hexagon/instructions/xtype_pred.s<br> llvm/trunk/test/MC/Hexagon/instructions/xtype_shift.s<br>Modified:<br> llvm/trunk/lib/Target/Hexagon/CMakeLists.txt<br> llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp<br> llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt<br> llvm/trunk/lib/Target/Hexagon/Hexagon.td<br> llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp<br> llvm/trunk/lib/Target/Hexagon/HexagonOperands.td<br> llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td<br> llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h<br> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h<br> llvm/trunk/test/CodeGen/Hexagon/absaddr-store.ll<br> llvm/trunk/test/CodeGen/Hexagon/absimm.ll<br> llvm/trunk/test/CodeGen/Hexagon/always-ext.ll<br> llvm/trunk/test/CodeGen/Hexagon/compound.ll<br> llvm/trunk/test/CodeGen/Hexagon/static.ll<br> llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll<br> llvm/trunk/test/MC/Disassembler/Hexagon/j.txt<br> llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt<br> llvm/trunk/test/MC/Disassembler/Hexagon/lit.local.cfg<br> llvm/trunk/test/MC/Disassembler/Hexagon/nv_j.txt<br> llvm/trunk/test/MC/Disassembler/Hexagon/nv_st.txt<br> llvm/trunk/test/MC/Disassembler/Hexagon/st.txt<br><br>Added: llvm/trunk/lib/Target/Hexagon/AsmParser/CMakeLists.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/CMakeLists.txt?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/CMakeLists.txt?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/AsmParser/CMakeLists.txt (added)<br>+++ llvm/trunk/lib/Target/Hexagon/AsmParser/CMakeLists.txt Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,7 @@<br>+include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )<br>+<br>+add_llvm_library(LLVMHexagonAsmParser<br>+ HexagonAsmParser.cpp<br>+ )<br>+<br>+add_dependencies( LLVMHexagonAsmParser HexagonCommonTableGen )<br><br>Added: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (added)<br>+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,2152 @@<br>+//===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//<br>+//<br>+// The LLVM Compiler Infrastructure<br>+//<br>+// This file is distributed under the University of Illinois Open Source<br>+// License. See LICENSE.TXT for details.<br>+//<br>+//===----------------------------------------------------------------------===//<br>+<br>+#define DEBUG_TYPE "mcasmparser"<br>+<br>+#include "Hexagon.h"<br>+#include "HexagonRegisterInfo.h"<br>+#include "HexagonTargetStreamer.h"<br>+#include "MCTargetDesc/HexagonBaseInfo.h"<br>+#include "MCTargetDesc/HexagonMCELFStreamer.h"<br>+#include "MCTargetDesc/HexagonMCChecker.h"<br>+#include "MCTargetDesc/HexagonMCExpr.h"<br>+#include "MCTargetDesc/HexagonMCShuffler.h"<br>+#include "MCTargetDesc/HexagonMCTargetDesc.h"<br>+#include "MCTargetDesc/HexagonMCAsmInfo.h"<br>+#include "MCTargetDesc/HexagonShuffler.h"<br>+#include "llvm/ADT/SmallString.h"<br>+#include "llvm/ADT/SmallVector.h"<br>+#include "llvm/ADT/StringExtras.h"<br>+#include "llvm/ADT/Twine.h"<br>+#include "llvm/MC/MCContext.h"<br>+#include "llvm/MC/MCELFStreamer.h"<br>+#include "llvm/MC/MCExpr.h"<br>+#include "llvm/MC/MCInst.h"<br>+#include "llvm/MC/MCParser/MCAsmLexer.h"<br>+#include "llvm/MC/MCParser/MCAsmParser.h"<br>+#include "llvm/MC/MCParser/MCParsedAsmOperand.h"<br>+#include "llvm/MC/MCStreamer.h"<br>+#include "llvm/MC/MCSectionELF.h"<br>+#include "llvm/MC/MCSubtargetInfo.h"<br>+#include "llvm/MC/MCTargetAsmParser.h"<br>+#include "llvm/Support/CommandLine.h"<br>+#include "llvm/Support/Debug.h"<br>+#include "llvm/Support/ELF.h"<br>+#include "llvm/Support/SourceMgr.h"<br>+#include "llvm/Support/MemoryBuffer.h"<br>+#include "llvm/Support/TargetRegistry.h"<br>+#include "llvm/Support/raw_ostream.h"<br>+#include <sstream><br>+<br>+using namespace llvm;<br>+<br>+static cl::opt<bool> EnableFutureRegs("mfuture-regs",<br>+ cl::desc("Enable future registers"));<br>+<br>+static cl::opt<bool> WarnMissingParenthesis("mwarn-missing-parenthesis",<br>+cl::desc("Warn for missing parenthesis around predicate registers"),<br>+cl::init(true));<br>+static cl::opt<bool> ErrorMissingParenthesis("merror-missing-parenthesis",<br>+cl::desc("Error for missing parenthesis around predicate registers"),<br>+cl::init(false));<br>+static cl::opt<bool> WarnSignedMismatch("mwarn-sign-mismatch",<br>+cl::desc("Warn for mismatching a signed and unsigned value"),<br>+cl::init(true));<br>+static cl::opt<bool> WarnNoncontigiousRegister("mwarn-noncontigious-register",<br>+cl::desc("Warn for register names that arent contigious"),<br>+cl::init(true));<br>+static cl::opt<bool> ErrorNoncontigiousRegister("merror-noncontigious-register",<br>+cl::desc("Error for register names that aren't contigious"),<br>+cl::init(false));<br>+<br>+<br>+namespace {<br>+struct HexagonOperand;<br>+<br>+class HexagonAsmParser : public MCTargetAsmParser {<br>+<br>+ HexagonTargetStreamer &getTargetStreamer() {<br>+ MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();<br>+ return static_cast<HexagonTargetStreamer &>(TS);<br>+ }<br>+<br>+ MCSubtargetInfo &STI;<br>+ MCAsmParser &Parser;<br>+ MCAssembler *Assembler;<br>+ MCInstrInfo const &MCII;<br>+ MCInst MCB;<br>+ bool InBrackets;<br>+<br>+ MCAsmParser &getParser() const { return Parser; }<br>+ MCAssembler *getAssembler() const { return Assembler; }<br>+ MCAsmLexer &getLexer() const { return Parser.getLexer(); }<br>+<br>+ unsigned ArchVersion;<br>+<br>+ bool equalIsAsmAssignment() override { return false; }<br>+ bool isLabel(AsmToken &Token) override;<br>+<br>+ void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }<br>+ bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }<br>+ bool ParseDirectiveFalign(unsigned Size, SMLoc L);<br>+<br>+ virtual bool ParseRegister(unsigned &RegNo,<br>+ SMLoc &StartLoc,<br>+ SMLoc &EndLoc) override;<br>+ bool ParseDirectiveSubsection(SMLoc L);<br>+ bool ParseDirectiveValue(unsigned Size, SMLoc L);<br>+ bool ParseDirectiveComm(bool IsLocal, SMLoc L);<br>+ bool RegisterMatchesArch(unsigned MatchNum) const;<br>+<br>+ bool matchBundleOptions();<br>+ bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc);<br>+ bool finishBundle(SMLoc IDLoc, MCStreamer &Out);<br>+ void canonicalizeImmediates(MCInst &MCI);<br>+ bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,<br>+ OperandVector &InstOperands, uint64_t &ErrorInfo,<br>+ bool MatchingInlineAsm, bool &MustExtend);<br>+<br>+ bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,<br>+ OperandVector &Operands, MCStreamer &Out,<br>+ uint64_t &ErrorInfo, bool MatchingInlineAsm);<br>+<br>+ unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override;<br>+ void OutOfRange(SMLoc IDLoc, long long Val, long long Max);<br>+ int processInstruction(MCInst &Inst, OperandVector const &Operands,<br>+ SMLoc IDLoc, bool &MustExtend);<br>+<br>+ // Check if we have an assembler and, if so, set the ELF e_header flags.<br>+ void chksetELFHeaderEFlags(unsigned flags) {<br>+ if (getAssembler())<br>+ getAssembler()->setELFHeaderEFlags(flags);<br>+ }<br>+<br>+/// @name Auto-generated Match Functions<br>+/// {<br>+<br>+#define GET_ASSEMBLER_HEADER<br>+#include "HexagonGenAsmMatcher.inc"<br>+<br>+ /// }<br>+<br>+public:<br>+ HexagonAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,<br>+ const MCInstrInfo &MII, const MCTargetOptions &Options)<br>+ : MCTargetAsmParser(Options), STI(_STI), Parser(_Parser),<br>+ MCII (MII), InBrackets(false) {<br>+ MCB.setOpcode(Hexagon::BUNDLE);<br>+ setAvailableFeatures(<br>+ ComputeAvailableFeatures(_STI.getFeatureBits()));<br>+<br>+ MCAsmParserExtension::Initialize(_Parser);<br>+<br>+ Assembler = nullptr;<br>+ // FIXME: need better way to detect AsmStreamer (upstream removed getKind())<br>+ if (!Parser.getStreamer().hasRawTextSupport()) {<br>+ MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());<br>+ Assembler = &MES->getAssembler();<br>+ }<br>+ }<br>+<br>+ bool mustExtend(OperandVector &Operands);<br>+ bool splitIdentifier(OperandVector &Operands);<br>+ bool parseOperand(OperandVector &Operands);<br>+ bool parseInstruction(OperandVector &Operands);<br>+ bool implicitExpressionLocation(OperandVector &Operands);<br>+ bool parseExpressionOrOperand(OperandVector &Operands);<br>+ bool parseExpression(MCExpr const *& Expr);<br>+ virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,<br>+ SMLoc NameLoc, OperandVector &Operands) {<br>+ llvm_unreachable("Unimplemented");<br>+ }<br>+ virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,<br>+ AsmToken ID, OperandVector &Operands);<br>+<br>+ virtual bool ParseDirective(AsmToken DirectiveID);<br>+};<br>+<br>+/// HexagonOperand - Instances of this class represent a parsed Hexagon machine<br>+/// instruction.<br>+struct HexagonOperand : public MCParsedAsmOperand {<br>+ enum KindTy { Token, Immediate, Register } Kind;<br>+<br>+ SMLoc StartLoc, EndLoc;<br>+<br>+ struct TokTy {<br>+ const char *Data;<br>+ unsigned Length;<br>+ };<br>+<br>+ struct RegTy {<br>+ unsigned RegNum;<br>+ };<br>+<br>+ struct ImmTy {<br>+ const MCExpr *Val;<br>+ bool MustExtend;<br>+ };<br>+<br>+ struct InstTy {<br>+ OperandVector *SubInsts;<br>+ };<br>+<br>+ union {<br>+ struct TokTy Tok;<br>+ struct RegTy Reg;<br>+ struct ImmTy Imm;<br>+ };<br>+<br>+ HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}<br>+<br>+public:<br>+ HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() {<br>+ Kind = o.Kind;<br>+ StartLoc = o.StartLoc;<br>+ EndLoc = o.EndLoc;<br>+ switch (Kind) {<br>+ case Register:<br>+ Reg = o.Reg;<br>+ break;<br>+ case Immediate:<br>+ Imm = o.Imm;<br>+ break;<br>+ case Token:<br>+ Tok = o.Tok;<br>+ break;<br>+ }<br>+ }<br>+<br>+ /// getStartLoc - Get the location of the first token of this operand.<br>+ SMLoc getStartLoc() const { return StartLoc; }<br>+<br>+ /// getEndLoc - Get the location of the last token of this operand.<br>+ SMLoc getEndLoc() const { return EndLoc; }<br>+<br>+ unsigned getReg() const {<br>+ assert(Kind == Register && "Invalid access!");<br>+ return Reg.RegNum;<br>+ }<br>+<br>+ const MCExpr *getImm() const {<br>+ assert(Kind == Immediate && "Invalid access!");<br>+ return Imm.Val;<br>+ }<br>+<br>+ bool isToken() const { return Kind == Token; }<br>+ bool isImm() const { return Kind == Immediate; }<br>+ bool isMem() const { llvm_unreachable("No isMem"); }<br>+ bool isReg() const { return Kind == Register; }<br>+<br>+ bool CheckImmRange(int immBits, int zeroBits, bool isSigned,<br>+ bool isRelocatable, bool Extendable) const {<br>+ if (Kind == Immediate) {<br>+ const MCExpr *myMCExpr = getImm();<br>+ if (Imm.MustExtend && !Extendable)<br>+ return false;<br>+ int64_t Res;<br>+ if (myMCExpr->evaluateAsAbsolute(Res)) {<br>+ int bits = immBits + zeroBits;<br>+ // Field bit range is zerobits + bits<br>+ // zeroBits must be 0<br>+ if (Res & ((1 << zeroBits) - 1))<br>+ return false;<br>+ if (isSigned) {<br>+ if (Res < (1LL << (bits - 1)) && Res >= -(1LL << (bits - 1)))<br>+ return true;<br>+ } else {<br>+ if (bits == 64)<br>+ return true;<br>+ if (Res >= 0)<br>+ return ((uint64_t)Res < (uint64_t)(1ULL << bits)) ? true : false;<br>+ else {<br>+ const int64_t high_bit_set = 1ULL << 63;<br>+ const uint64_t mask = (high_bit_set >> (63 - bits));<br>+ return (((uint64_t)Res & mask) == mask) ? true : false;<br>+ }<br>+ }<br>+ } else if (myMCExpr->getKind() == MCExpr::SymbolRef && isRelocatable)<br>+ return true;<br>+ else if (myMCExpr->getKind() == MCExpr::Binary ||<br>+ myMCExpr->getKind() == MCExpr::Unary)<br>+ return true;<br>+ }<br>+ return false;<br>+ }<br>+<br>+ bool isf32Ext() const { return false; }<br>+ bool iss32Imm() const { return CheckImmRange(32, 0, true, true, false); }<br>+ bool iss8Imm() const { return CheckImmRange(8, 0, true, false, false); }<br>+ bool iss8Imm64() const { return CheckImmRange(8, 0, true, true, false); }<br>+ bool iss7Imm() const { return CheckImmRange(7, 0, true, false, false); }<br>+ bool iss6Imm() const { return CheckImmRange(6, 0, true, false, false); }<br>+ bool iss4Imm() const { return CheckImmRange(4, 0, true, false, false); }<br>+ bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); }<br>+ bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); }<br>+ bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); }<br>+ bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); }<br>+ bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); }<br>+ bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); }<br>+ bool iss3Imm() const { return CheckImmRange(3, 0, true, false, false); }<br>+<br>+ bool isu64Imm() const { return CheckImmRange(64, 0, false, true, true); }<br>+ bool isu32Imm() const { return CheckImmRange(32, 0, false, true, false); }<br>+ bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); }<br>+ bool isu16Imm() const { return CheckImmRange(16, 0, false, true, false); }<br>+ bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); }<br>+ bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); }<br>+ bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); }<br>+ bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); }<br>+ bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); }<br>+ bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }<br>+ bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); }<br>+ bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); }<br>+ bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); }<br>+ bool isu10Imm() const { return CheckImmRange(10, 0, false, false, false); }<br>+ bool isu9Imm() const { return CheckImmRange(9, 0, false, false, false); }<br>+ bool isu8Imm() const { return CheckImmRange(8, 0, false, false, false); }<br>+ bool isu7Imm() const { return CheckImmRange(7, 0, false, false, false); }<br>+ bool isu6Imm() const { return CheckImmRange(6, 0, false, false, false); }<br>+ bool isu5Imm() const { return CheckImmRange(5, 0, false, false, false); }<br>+ bool isu4Imm() const { return CheckImmRange(4, 0, false, false, false); }<br>+ bool isu3Imm() const { return CheckImmRange(3, 0, false, false, false); }<br>+ bool isu2Imm() const { return CheckImmRange(2, 0, false, false, false); }<br>+ bool isu1Imm() const { return CheckImmRange(1, 0, false, false, false); }<br>+<br>+ bool ism6Imm() const { return CheckImmRange(6, 0, false, false, false); }<br>+ bool isn8Imm() const { return CheckImmRange(8, 0, false, false, false); }<br>+<br>+ bool iss16Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); }<br>+ bool iss12Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); }<br>+ bool iss10Ext() const { return CheckImmRange(10 + 26, 0, true, true, true); }<br>+ bool iss9Ext() const { return CheckImmRange(9 + 26, 0, true, true, true); }<br>+ bool iss8Ext() const { return CheckImmRange(8 + 26, 0, true, true, true); }<br>+ bool iss7Ext() const { return CheckImmRange(7 + 26, 0, true, true, true); }<br>+ bool iss6Ext() const { return CheckImmRange(6 + 26, 0, true, true, true); }<br>+ bool iss11_0Ext() const {<br>+ return CheckImmRange(11 + 26, 0, true, true, true);<br>+ }<br>+ bool iss11_1Ext() const {<br>+ return CheckImmRange(11 + 26, 1, true, true, true);<br>+ }<br>+ bool iss11_2Ext() const {<br>+ return CheckImmRange(11 + 26, 2, true, true, true);<br>+ }<br>+ bool iss11_3Ext() const {<br>+ return CheckImmRange(11 + 26, 3, true, true, true);<br>+ }<br>+<br>+ bool isu6Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }<br>+ bool isu7Ext() const { return CheckImmRange(7 + 26, 0, false, true, true); }<br>+ bool isu8Ext() const { return CheckImmRange(8 + 26, 0, false, true, true); }<br>+ bool isu9Ext() const { return CheckImmRange(9 + 26, 0, false, true, true); }<br>+ bool isu10Ext() const { return CheckImmRange(10 + 26, 0, false, true, true); }<br>+ bool isu6_0Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }<br>+ bool isu6_1Ext() const { return CheckImmRange(6 + 26, 1, false, true, true); }<br>+ bool isu6_2Ext() const { return CheckImmRange(6 + 26, 2, false, true, true); }<br>+ bool isu6_3Ext() const { return CheckImmRange(6 + 26, 3, false, true, true); }<br>+ bool isu32MustExt() const { return isImm() && Imm.MustExtend; }<br>+<br>+ void addRegOperands(MCInst &Inst, unsigned N) const {<br>+ assert(N == 1 && "Invalid number of operands!");<br>+ Inst.addOperand(MCOperand::createReg(getReg()));<br>+ }<br>+<br>+ void addImmOperands(MCInst &Inst, unsigned N) const {<br>+ assert(N == 1 && "Invalid number of operands!");<br>+ Inst.addOperand(MCOperand::createExpr(getImm()));<br>+ }<br>+<br>+ void addSignedImmOperands(MCInst &Inst, unsigned N) const {<br>+ assert(N == 1 && "Invalid number of operands!");<br>+ MCExpr const *Expr = getImm();<br>+ int64_t Value;<br>+ if (!Expr->evaluateAsAbsolute(Value)) {<br>+ Inst.addOperand(MCOperand::createExpr(Expr));<br>+ return;<br>+ }<br>+ int64_t Extended = SignExtend64 (Value, 32);<br>+ if ((Extended < 0) == (Value < 0)) {<br>+ Inst.addOperand(MCOperand::createExpr(Expr));<br>+ return;<br>+ }<br>+ // Flip bit 33 to signal signed unsigned mismatch<br>+ Extended ^= 0x100000000;<br>+ Inst.addOperand(MCOperand::createImm(Extended));<br>+ }<br>+<br>+ void addf32ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+<br>+ void adds32ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds8ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds8Imm64Operands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds6ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds4ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds4_0ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds4_1ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds4_2ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds4_3ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds3ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+<br>+ void addu64ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu32ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu26_6ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu16ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu16_0ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu16_1ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu16_2ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu16_3ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu11_3ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu10ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu9ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu8ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu7ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu6ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu6_0ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu6_1ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu6_2ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu6_3ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu5ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu4ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu3ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu2ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu1ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+<br>+ void addm6ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addn8ImmOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+<br>+ void adds16ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds12ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds10ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds9ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds8ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds6ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds11_0ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds11_1ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds11_2ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+ void adds11_3ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addSignedImmOperands(Inst, N);<br>+ }<br>+<br>+ void addu6ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu7ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu8ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu9ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu10ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu6_0ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu6_1ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu6_2ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu6_3ExtOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+ void addu32MustExtOperands(MCInst &Inst, unsigned N) const {<br>+ addImmOperands(Inst, N);<br>+ }<br>+<br>+ void adds4_6ImmOperands(MCInst &Inst, unsigned N) const {<br>+ assert(N == 1 && "Invalid number of operands!");<br>+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());<br>+ Inst.addOperand(MCOperand::createImm(CE->getValue() << 6));<br>+ }<br>+<br>+ void adds3_6ImmOperands(MCInst &Inst, unsigned N) const {<br>+ assert(N == 1 && "Invalid number of operands!");<br>+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());<br>+ Inst.addOperand(MCOperand::createImm(CE->getValue() << 6));<br>+ }<br>+<br>+ StringRef getToken() const {<br>+ assert(Kind == Token && "Invalid access!");<br>+ return StringRef(Tok.Data, Tok.Length);<br>+ }<br>+<br>+ virtual void print(raw_ostream &OS) const;<br>+<br>+ static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc S) {<br>+ HexagonOperand *Op = new HexagonOperand(Token);<br>+ Op->Tok.Data = Str.data();<br>+ Op->Tok.Length = Str.size();<br>+ Op->StartLoc = S;<br>+ Op->EndLoc = S;<br>+ return std::unique_ptr<HexagonOperand>(Op);<br>+ }<br>+<br>+ static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S,<br>+ SMLoc E) {<br>+ HexagonOperand *Op = new HexagonOperand(Register);<br>+ Op->Reg.RegNum = RegNum;<br>+ Op->StartLoc = S;<br>+ Op->EndLoc = E;<br>+ return std::unique_ptr<HexagonOperand>(Op);<br>+ }<br>+<br>+ static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val, SMLoc S,<br>+ SMLoc E) {<br>+ HexagonOperand *Op = new HexagonOperand(Immediate);<br>+ Op->Imm.Val = Val;<br>+ Op->Imm.MustExtend = false;<br>+ Op->StartLoc = S;<br>+ Op->EndLoc = E;<br>+ return std::unique_ptr<HexagonOperand>(Op);<br>+ }<br>+};<br>+<br>+} // end anonymous namespace.<br>+<br>+void HexagonOperand::print(raw_ostream &OS) const {<br>+ switch (Kind) {<br>+ case Immediate:<br>+ getImm()->print(OS, nullptr);<br>+ break;<br>+ case Register:<br>+ OS << "<register R";<br>+ OS << getReg() << ">";<br>+ break;<br>+ case Token:<br>+ OS << "'" << getToken() << "'";<br>+ break;<br>+ }<br>+}<br>+<br>+/// @name Auto-generated Match Functions<br>+static unsigned MatchRegisterName(StringRef Name);<br>+<br>+bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {<br>+ DEBUG(dbgs() << "Bundle:");<br>+ DEBUG(MCB.dump_pretty(dbgs()));<br>+ DEBUG(dbgs() << "--\n");<br>+<br>+ // Check the bundle for errors.<br>+ const MCRegisterInfo *RI = getContext().getRegisterInfo();<br>+ HexagonMCChecker Check(MCII, STI, MCB, MCB, *RI);<br>+<br>+ bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, STI, getContext(),<br>+ MCB, &Check);<br>+<br>+ while (Check.getNextErrInfo() == true) {<br>+ unsigned Reg = Check.getErrRegister();<br>+ Twine R(RI->getName(Reg));<br>+<br>+ uint64_t Err = Check.getError();<br>+ if (Err != HexagonMCErrInfo::CHECK_SUCCESS) {<br>+ if (HexagonMCErrInfo::CHECK_ERROR_BRANCHES & Err)<br>+ Error(IDLoc,<br>+ "unconditional branch cannot precede another branch in packet");<br>+<br>+ if (HexagonMCErrInfo::CHECK_ERROR_NEWP & Err ||<br>+ HexagonMCErrInfo::CHECK_ERROR_NEWV & Err)<br>+ Error(IDLoc, "register `" + R +<br>+ "' used with `.new' "<br>+ "but not validly modified in the same packet");<br>+<br>+ if (HexagonMCErrInfo::CHECK_ERROR_REGISTERS & Err)<br>+ Error(IDLoc, "register `" + R + "' modified more than once");<br>+<br>+ if (HexagonMCErrInfo::CHECK_ERROR_READONLY & Err)<br>+ Error(IDLoc, "cannot write to read-only register `" + R + "'");<br>+<br>+ if (HexagonMCErrInfo::CHECK_ERROR_LOOP & Err)<br>+ Error(IDLoc, "loop-setup and some branch instructions "<br>+ "cannot be in the same packet");<br>+<br>+ if (HexagonMCErrInfo::CHECK_ERROR_ENDLOOP & Err) {<br>+ Twine N(HexagonMCInstrInfo::isInnerLoop(MCB) ? '0' : '1');<br>+ Error(IDLoc, "packet marked with `:endloop" + N + "' " +<br>+ "cannot contain instructions that modify register " +<br>+ "`" + R + "'");<br>+ }<br>+<br>+ if (HexagonMCErrInfo::CHECK_ERROR_SOLO & Err)<br>+ Error(IDLoc,<br>+ "instruction cannot appear in packet with other instructions");<br>+<br>+ if (HexagonMCErrInfo::CHECK_ERROR_NOSLOTS & Err)<br>+ Error(IDLoc, "too many slots used in packet");<br>+<br>+ if (Err & HexagonMCErrInfo::CHECK_ERROR_SHUFFLE) {<br>+ uint64_t Erm = Check.getShuffleError();<br>+<br>+ if (HexagonShuffler::SHUFFLE_ERROR_INVALID == Erm)<br>+ Error(IDLoc, "invalid instruction packet");<br>+ else if (HexagonShuffler::SHUFFLE_ERROR_STORES == Erm)<br>+ Error(IDLoc, "invalid instruction packet: too many stores");<br>+ else if (HexagonShuffler::SHUFFLE_ERROR_LOADS == Erm)<br>+ Error(IDLoc, "invalid instruction packet: too many loads");<br>+ else if (HexagonShuffler::SHUFFLE_ERROR_BRANCHES == Erm)<br>+ Error(IDLoc, "too many branches in packet");<br>+ else if (HexagonShuffler::SHUFFLE_ERROR_NOSLOTS == Erm)<br>+ Error(IDLoc, "invalid instruction packet: out of slots");<br>+ else if (HexagonShuffler::SHUFFLE_ERROR_SLOTS == Erm)<br>+ Error(IDLoc, "invalid instruction packet: slot error");<br>+ else if (HexagonShuffler::SHUFFLE_ERROR_ERRATA2 == Erm)<br>+ Error(IDLoc, "v60 packet violation");<br>+ else if (HexagonShuffler::SHUFFLE_ERROR_STORE_LOAD_CONFLICT == Erm)<br>+ Error(IDLoc, "slot 0 instruction does not allow slot 1 store");<br>+ else<br>+ Error(IDLoc, "unknown error in instruction packet");<br>+ }<br>+ }<br>+<br>+ unsigned Warn = Check.getWarning();<br>+ if (Warn != HexagonMCErrInfo::CHECK_SUCCESS) {<br>+ if (HexagonMCErrInfo::CHECK_WARN_CURRENT & Warn)<br>+ Warning(IDLoc, "register `" + R + "' used with `.cur' "<br>+ "but not used in the same packet");<br>+ else if (HexagonMCErrInfo::CHECK_WARN_TEMPORARY & Warn)<br>+ Warning(IDLoc, "register `" + R + "' used with `.tmp' "<br>+ "but not used in the same packet");<br>+ }<br>+ }<br>+<br>+ if (CheckOk) {<br>+ MCB.setLoc(IDLoc);<br>+ if (HexagonMCInstrInfo::bundleSize(MCB) == 0) {<br>+ assert(!HexagonMCInstrInfo::isInnerLoop(MCB));<br>+ assert(!HexagonMCInstrInfo::isOuterLoop(MCB));<br>+ // Empty packets are valid yet aren't emitted<br>+ return false;<br>+ }<br>+ Out.EmitInstruction(MCB, STI);<br>+ } else {<br>+ // If compounding and duplexing didn't reduce the size below<br>+ // 4 or less we have a packet that is too big.<br>+ if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) {<br>+ Error(IDLoc, "invalid instruction packet: out of slots");<br>+ return true; // Error<br>+ }<br>+ }<br>+<br>+ return false; // No error<br>+}<br>+<br>+bool HexagonAsmParser::matchBundleOptions() {<br>+ MCAsmParser &Parser = getParser();<br>+ MCAsmLexer &Lexer = getLexer();<br>+ while (true) {<br>+ if (!Parser.getTok().is(AsmToken::Colon))<br>+ return false;<br>+ Lexer.Lex();<br>+ StringRef Option = Parser.getTok().getString();<br>+ if (Option.compare_lower("endloop0") == 0)<br>+ HexagonMCInstrInfo::setInnerLoop(MCB);<br>+ else if (Option.compare_lower("endloop1") == 0)<br>+ HexagonMCInstrInfo::setOuterLoop(MCB);<br>+ else if (Option.compare_lower("mem_noshuf") == 0)<br>+ HexagonMCInstrInfo::setMemReorderDisabled(MCB);<br>+ else if (Option.compare_lower("mem_shuf") == 0)<br>+ HexagonMCInstrInfo::setMemStoreReorderEnabled(MCB);<br>+ else<br>+ return true;<br>+ Lexer.Lex();<br>+ }<br>+}<br>+<br>+// For instruction aliases, immediates are generated rather than<br>+// MCConstantExpr. Convert them for uniform MCExpr.<br>+// Also check for signed/unsigned mismatches and warn<br>+void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {<br>+ MCInst NewInst;<br>+ NewInst.setOpcode(MCI.getOpcode());<br>+ for (MCOperand &I : MCI)<br>+ if (I.isImm()) {<br>+ int64_t Value (I.getImm());<br>+ if ((Value & 0x100000000) != (Value & 0x80000000)) {<br>+ // Detect flipped bit 33 wrt bit 32 and signal warning<br>+ Value ^= 0x100000000;<br>+ if (WarnSignedMismatch)<br>+ Warning (MCI.getLoc(), "Signed/Unsigned mismatch");<br>+ }<br>+ NewInst.addOperand(MCOperand::createExpr(<br>+ MCConstantExpr::create(Value, getContext())));<br>+ }<br>+ else<br>+ NewInst.addOperand(I);<br>+ MCI = NewInst;<br>+}<br>+<br>+bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,<br>+ OperandVector &InstOperands,<br>+ uint64_t &ErrorInfo,<br>+ bool MatchingInlineAsm,<br>+ bool &MustExtend) {<br>+ // Perform matching with tablegen asmmatcher generated function<br>+ int result =<br>+ MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm);<br>+ if (result == Match_Success) {<br>+ MCI.setLoc(IDLoc);<br>+ MustExtend = mustExtend(InstOperands);<br>+ canonicalizeImmediates(MCI);<br>+ result = processInstruction(MCI, InstOperands, IDLoc, MustExtend);<br>+<br>+ DEBUG(dbgs() << "Insn:");<br>+ DEBUG(MCI.dump_pretty(dbgs()));<br>+ DEBUG(dbgs() << "\n\n");<br>+<br>+ MCI.setLoc(IDLoc);<br>+ }<br>+<br>+ // Create instruction operand for bundle instruction<br>+ // Break this into a separate function Code here is less readable<br>+ // Think about how to get an instruction error to report correctly.<br>+ // SMLoc will return the "{"<br>+ switch (result) {<br>+ default:<br>+ break;<br>+ case Match_Success:<br>+ return false;<br>+ case Match_MissingFeature:<br>+ return Error(IDLoc, "invalid instruction");<br>+ case Match_MnemonicFail:<br>+ return Error(IDLoc, "unrecognized instruction");<br>+ case Match_InvalidOperand:<br>+ SMLoc ErrorLoc = IDLoc;<br>+ if (ErrorInfo != ~0U) {<br>+ if (ErrorInfo >= InstOperands.size())<br>+ return Error(IDLoc, "too few operands for instruction");<br>+<br>+ ErrorLoc = (static_cast<HexagonOperand *>(InstOperands[ErrorInfo].get()))<br>+ ->getStartLoc();<br>+ if (ErrorLoc == SMLoc())<br>+ ErrorLoc = IDLoc;<br>+ }<br>+ return Error(ErrorLoc, "invalid operand for instruction");<br>+ }<br>+ llvm_unreachable("Implement any new match types added!");<br>+}<br>+<br>+bool HexagonAsmParser::mustExtend(OperandVector &Operands) {<br>+ unsigned Count = 0;<br>+ for (std::unique_ptr<MCParsedAsmOperand> &i : Operands)<br>+ if (i->isImm())<br>+ if (static_cast<HexagonOperand *>(i.get())->Imm.MustExtend)<br>+ ++Count;<br>+ // Multiple extenders should have been filtered by iss9Ext et. al.<br>+ assert(Count < 2 && "Multiple extenders");<br>+ return Count == 1;<br>+}<br>+<br>+bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,<br>+ OperandVector &Operands,<br>+ MCStreamer &Out,<br>+ uint64_t &ErrorInfo,<br>+ bool MatchingInlineAsm) {<br>+ if (!InBrackets) {<br>+ MCB.clear();<br>+ MCB.addOperand(MCOperand::createImm(0));<br>+ }<br>+ HexagonOperand &FirstOperand = static_cast<HexagonOperand &>(*Operands[0]);<br>+ if (FirstOperand.isToken() && FirstOperand.getToken() == "{") {<br>+ assert(Operands.size() == 1 && "Brackets should be by themselves");<br>+ if (InBrackets) {<br>+ getParser().Error(IDLoc, "Already in a packet");<br>+ return true;<br>+ }<br>+ InBrackets = true;<br>+ return false;<br>+ }<br>+ if (FirstOperand.isToken() && FirstOperand.getToken() == "}") {<br>+ assert(Operands.size() == 1 && "Brackets should be by themselves");<br>+ if (!InBrackets) {<br>+ getParser().Error(IDLoc, "Not in a packet");<br>+ return true;<br>+ }<br>+ InBrackets = false;<br>+ if (matchBundleOptions())<br>+ return true;<br>+ return finishBundle(IDLoc, Out);<br>+ }<br>+ MCInst *SubInst = new (getParser().getContext()) MCInst;<br>+ bool MustExtend = false;<br>+ if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,<br>+ MatchingInlineAsm, MustExtend))<br>+ return true;<br>+ HexagonMCInstrInfo::extendIfNeeded(<br>+ MCII, MCB, *SubInst,<br>+ HexagonMCInstrInfo::isExtended(MCII, *SubInst) || MustExtend);<br>+ MCB.addOperand(MCOperand::createInst(SubInst));<br>+ if (!InBrackets)<br>+ return finishBundle(IDLoc, Out);<br>+ return false;<br>+}<br>+<br>+/// ParseDirective parses the Hexagon specific directives<br>+bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) {<br>+ StringRef IDVal = DirectiveID.getIdentifier();<br>+ if ((IDVal.lower() == ".word") || (IDVal.lower() == ".4byte"))<br>+ return ParseDirectiveValue(4, DirectiveID.getLoc());<br>+ if (IDVal.lower() == ".short" || IDVal.lower() == ".hword" ||<br>+ IDVal.lower() == ".half")<br>+ return ParseDirectiveValue(2, DirectiveID.getLoc());<br>+ if (IDVal.lower() == ".falign")<br>+ return ParseDirectiveFalign(256, DirectiveID.getLoc());<br>+ if ((IDVal.lower() == ".lcomm") || (IDVal.lower() == ".lcommon"))<br>+ return ParseDirectiveComm(true, DirectiveID.getLoc());<br>+ if ((IDVal.lower() == ".comm") || (IDVal.lower() == ".common"))<br>+ return ParseDirectiveComm(false, DirectiveID.getLoc());<br>+ if (IDVal.lower() == ".subsection")<br>+ return ParseDirectiveSubsection(DirectiveID.getLoc());<br>+<br>+ return true;<br>+}<br>+bool HexagonAsmParser::ParseDirectiveSubsection(SMLoc L) {<br>+ const MCExpr *Subsection = 0;<br>+ int64_t Res;<br>+<br>+ assert((getLexer().isNot(AsmToken::EndOfStatement)) &&<br>+ "Invalid subsection directive");<br>+ getParser().parseExpression(Subsection);<br>+<br>+ if (!Subsection->evaluateAsAbsolute(Res))<br>+ return Error(L, "Cannot evaluate subsection number");<br>+<br>+ if (getLexer().isNot(AsmToken::EndOfStatement))<br>+ return TokError("unexpected token in directive");<br>+<br>+ // 0-8192 is the hard-coded range in MCObjectStreamper.cpp, this keeps the<br>+ // negative subsections together and in the same order but at the opposite<br>+ // end of the section. Only legacy hexagon-gcc created assembly code<br>+ // used negative subsections.<br>+ if ((Res < 0) && (Res > -8193))<br>+ Subsection = MCConstantExpr::create(8192 + Res, this->getContext());<br>+<br>+ getStreamer().SubSection(Subsection);<br>+ return false;<br>+}<br>+<br>+/// ::= .falign [expression]<br>+bool HexagonAsmParser::ParseDirectiveFalign(unsigned Size, SMLoc L) {<br>+<br>+ int64_t MaxBytesToFill = 15;<br>+<br>+ // if there is an arguement<br>+ if (getLexer().isNot(AsmToken::EndOfStatement)) {<br>+ const MCExpr *Value;<br>+ SMLoc ExprLoc = L;<br>+<br>+ // Make sure we have a number (false is returned if expression is a number)<br>+ if (getParser().parseExpression(Value) == false) {<br>+ // Make sure this is a number that is in range<br>+ const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value);<br>+ uint64_t IntValue = MCE->getValue();<br>+ if (!isUIntN(Size, IntValue) && !isIntN(Size, IntValue))<br>+ return Error(ExprLoc, "literal value out of range (256) for falign");<br>+ MaxBytesToFill = IntValue;<br>+ Lex();<br>+ } else {<br>+ return Error(ExprLoc, "not a valid expression for falign directive");<br>+ }<br>+ }<br>+<br>+ getTargetStreamer().emitFAlign(16, MaxBytesToFill);<br>+ Lex();<br>+<br>+ return false;<br>+}<br>+<br>+/// ::= .word [ expression (, expression)* ]<br>+bool HexagonAsmParser::ParseDirectiveValue(unsigned Size, SMLoc L) {<br>+ if (getLexer().isNot(AsmToken::EndOfStatement)) {<br>+<br>+ for (;;) {<br>+ const MCExpr *Value;<br>+ SMLoc ExprLoc = L;<br>+ if (getParser().parseExpression(Value))<br>+ return true;<br>+<br>+ // Special case constant expressions to match code generator.<br>+ if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value)) {<br>+ assert(Size <= 8 && "Invalid size");<br>+ uint64_t IntValue = MCE->getValue();<br>+ if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))<br>+ return Error(ExprLoc, "literal value out of range for directive");<br>+ getStreamer().EmitIntValue(IntValue, Size);<br>+ } else<br>+ getStreamer().EmitValue(Value, Size);<br>+<br>+ if (getLexer().is(AsmToken::EndOfStatement))<br>+ break;<br>+<br>+ // FIXME: Improve diagnostic.<br>+ if (getLexer().isNot(AsmToken::Comma))<br>+ return TokError("unexpected token in directive");<br>+ Lex();<br>+ }<br>+ }<br>+<br>+ Lex();<br>+ return false;<br>+}<br>+<br>+// This is largely a copy of AsmParser's ParseDirectiveComm extended to<br>+// accept a 3rd argument, AccessAlignment which indicates the smallest<br>+// memory access made to the symbol, expressed in bytes. If no<br>+// AccessAlignment is specified it defaults to the Alignment Value.<br>+// Hexagon's .lcomm:<br>+// .lcomm Symbol, Length, Alignment, AccessAlignment<br>+bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) {<br>+ // FIXME: need better way to detect if AsmStreamer (upstream removed<br>+ // getKind())<br>+ if (getStreamer().hasRawTextSupport())<br>+ return true; // Only object file output requires special treatment.<br>+<br>+ StringRef Name;<br>+ if (getParser().parseIdentifier(Name))<br>+ return TokError("expected identifier in directive");<br>+ // Handle the identifier as the key symbol.<br>+ MCSymbol *Sym = getContext().getOrCreateSymbol(Name);<br>+<br>+ if (getLexer().isNot(AsmToken::Comma))<br>+ return TokError("unexpected token in directive");<br>+ Lex();<br>+<br>+ int64_t Size;<br>+ SMLoc SizeLoc = getLexer().getLoc();<br>+ if (getParser().parseAbsoluteExpression(Size))<br>+ return true;<br>+<br>+ int64_t ByteAlignment = 1;<br>+ SMLoc ByteAlignmentLoc;<br>+ if (getLexer().is(AsmToken::Comma)) {<br>+ Lex();<br>+ ByteAlignmentLoc = getLexer().getLoc();<br>+ if (getParser().parseAbsoluteExpression(ByteAlignment))<br>+ return true;<br>+ if (!isPowerOf2_64(ByteAlignment))<br>+ return Error(ByteAlignmentLoc, "alignment must be a power of 2");<br>+ }<br>+<br>+ int64_t AccessAlignment = 0;<br>+ if (getLexer().is(AsmToken::Comma)) {<br>+ // The optional access argument specifies the size of the smallest memory<br>+ // access to be made to the symbol, expressed in bytes.<br>+ SMLoc AccessAlignmentLoc;<br>+ Lex();<br>+ AccessAlignmentLoc = getLexer().getLoc();<br>+ if (getParser().parseAbsoluteExpression(AccessAlignment))<br>+ return true;<br>+<br>+ if (!isPowerOf2_64(AccessAlignment))<br>+ return Error(AccessAlignmentLoc, "access alignment must be a power of 2");<br>+ }<br>+<br>+ if (getLexer().isNot(AsmToken::EndOfStatement))<br>+ return TokError("unexpected token in '.comm' or '.lcomm' directive");<br>+<br>+ Lex();<br>+<br>+ // NOTE: a size of zero for a .comm should create a undefined symbol<br>+ // but a size of .lcomm creates a bss symbol of size zero.<br>+ if (Size < 0)<br>+ return Error(SizeLoc, "invalid '.comm' or '.lcomm' directive size, can't "<br>+ "be less than zero");<br>+<br>+ // NOTE: The alignment in the directive is a power of 2 value, the assembler<br>+ // may internally end up wanting an alignment in bytes.<br>+ // FIXME: Diagnose overflow.<br>+ if (ByteAlignment < 0)<br>+ return Error(ByteAlignmentLoc, "invalid '.comm' or '.lcomm' directive "<br>+ "alignment, can't be less than zero");<br>+<br>+ if (!Sym->isUndefined())<br>+ return Error(Loc, "invalid symbol redefinition");<br>+<br>+ HexagonMCELFStreamer &HexagonELFStreamer =<br>+ static_cast<HexagonMCELFStreamer &>(getStreamer());<br>+ if (IsLocal) {<br>+ HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(Sym, Size, ByteAlignment,<br>+ AccessAlignment);<br>+ return false;<br>+ }<br>+<br>+ HexagonELFStreamer.HexagonMCEmitCommonSymbol(Sym, Size, ByteAlignment,<br>+ AccessAlignment);<br>+ return false;<br>+}<br>+<br>+// validate register against architecture<br>+bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {<br>+ return true;<br>+}<br>+<br>+// extern "C" void LLVMInitializeHexagonAsmLexer();<br>+<br>+/// Force static initialization.<br>+extern "C" void LLVMInitializeHexagonAsmParser() {<br>+ RegisterMCAsmParser<HexagonAsmParser> X(TheHexagonTarget);<br>+}<br>+<br>+#define GET_MATCHER_IMPLEMENTATION<br>+#define GET_REGISTER_MATCHER<br>+#include "HexagonGenAsmMatcher.inc"<br>+<br>+namespace {<br>+bool previousEqual(OperandVector &Operands, size_t Index, StringRef String) {<br>+ if (Index >= Operands.size())<br>+ return false;<br>+ MCParsedAsmOperand &Operand = *Operands[Operands.size() - Index - 1];<br>+ if (!Operand.isToken())<br>+ return false;<br>+ return static_cast<HexagonOperand &>(Operand).getToken().equals_lower(String);<br>+}<br>+bool previousIsLoop(OperandVector &Operands, size_t Index) {<br>+ return previousEqual(Operands, Index, "loop0") ||<br>+ previousEqual(Operands, Index, "loop1") ||<br>+ previousEqual(Operands, Index, "sp1loop0") ||<br>+ previousEqual(Operands, Index, "sp2loop0") ||<br>+ previousEqual(Operands, Index, "sp3loop0");<br>+}<br>+}<br>+<br>+bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) {<br>+ AsmToken const &Token = getParser().getTok();<br>+ StringRef String = Token.getString();<br>+ SMLoc Loc = Token.getLoc();<br>+ getLexer().Lex();<br>+ do {<br>+ std::pair<StringRef, StringRef> HeadTail = String.split('.');<br>+ if (!HeadTail.first.empty())<br>+ Operands.push_back(HexagonOperand::CreateToken(HeadTail.first, Loc));<br>+ if (!HeadTail.second.empty())<br>+ Operands.push_back(HexagonOperand::CreateToken(<br>+ String.substr(HeadTail.first.size(), 1), Loc));<br>+ String = HeadTail.second;<br>+ } while (!String.empty());<br>+ return false;<br>+}<br>+<br>+bool HexagonAsmParser::parseOperand(OperandVector &Operands) {<br>+ unsigned Register;<br>+ SMLoc Begin;<br>+ SMLoc End;<br>+ MCAsmLexer &Lexer = getLexer();<br>+ if (!ParseRegister(Register, Begin, End)) {<br>+ if (!ErrorMissingParenthesis)<br>+ switch (Register) {<br>+ default:<br>+ break;<br>+ case Hexagon::P0:<br>+ case Hexagon::P1:<br>+ case Hexagon::P2:<br>+ case Hexagon::P3:<br>+ if (previousEqual(Operands, 0, "if")) {<br>+ if (WarnMissingParenthesis)<br>+ Warning (Begin, "Missing parenthesis around predicate register");<br>+ static char const *LParen = "(";<br>+ static char const *RParen = ")";<br>+ Operands.push_back(HexagonOperand::CreateToken(LParen, Begin));<br>+ Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));<br>+ AsmToken MaybeDotNew = Lexer.getTok();<br>+ if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&<br>+ MaybeDotNew.getString().equals_lower(".new"))<br>+ splitIdentifier(Operands);<br>+ Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));<br>+ return false;<br>+ }<br>+ if (previousEqual(Operands, 0, "!") &&<br>+ previousEqual(Operands, 1, "if")) {<br>+ if (WarnMissingParenthesis)<br>+ Warning (Begin, "Missing parenthesis around predicate register");<br>+ static char const *LParen = "(";<br>+ static char const *RParen = ")";<br>+ Operands.insert(Operands.end () - 1,<br>+ HexagonOperand::CreateToken(LParen, Begin));<br>+ Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));<br>+ AsmToken MaybeDotNew = Lexer.getTok();<br>+ if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&<br>+ MaybeDotNew.getString().equals_lower(".new"))<br>+ splitIdentifier(Operands);<br>+ Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));<br>+ return false;<br>+ }<br>+ break;<br>+ }<br>+ Operands.push_back(HexagonOperand::CreateReg(<br>+ Register, Begin, End));<br>+ return false;<br>+ }<br>+ return splitIdentifier(Operands);<br>+}<br>+<br>+bool HexagonAsmParser::isLabel(AsmToken &Token) {<br>+ MCAsmLexer &Lexer = getLexer();<br>+ AsmToken const &Second = Lexer.getTok();<br>+ AsmToken Third = Lexer.peekTok();<br>+ StringRef String = Token.getString();<br>+ if (Token.is(AsmToken::TokenKind::LCurly) ||<br>+ Token.is(AsmToken::TokenKind::RCurly))<br>+ return false;<br>+ if (!Token.is(AsmToken::TokenKind::Identifier))<br>+ return true;<br>+ if (!MatchRegisterName(String.lower()))<br>+ return true;<br>+ assert(Second.is(AsmToken::Colon));<br>+ StringRef Raw (String.data(), Third.getString().data() - String.data() +<br>+ Third.getString().size());<br>+ std::string Collapsed = Raw;<br>+ Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace),<br>+ Collapsed.end());<br>+ StringRef Whole = Collapsed;<br>+ std::pair<StringRef, StringRef> DotSplit = Whole.split('.');<br>+ if (!MatchRegisterName(DotSplit.first.lower()))<br>+ return true;<br>+ return false;<br>+}<br>+<br>+bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) {<br>+ if (!Contigious && ErrorNoncontigiousRegister) {<br>+ Error(Loc, "Register name is not contigious");<br>+ return true;<br>+ }<br>+ if (!Contigious && WarnNoncontigiousRegister)<br>+ Warning(Loc, "Register name is not contigious");<br>+ return false;<br>+}<br>+<br>+bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {<br>+ MCAsmLexer &Lexer = getLexer();<br>+ StartLoc = getLexer().getLoc();<br>+ SmallVector<AsmToken, 5> Lookahead;<br>+ StringRef RawString(Lexer.getTok().getString().data(), 0);<br>+ bool Again = Lexer.is(AsmToken::Identifier);<br>+ bool NeededWorkaround = false;<br>+ while (Again) {<br>+ AsmToken const &Token = Lexer.getTok();<br>+ RawString = StringRef(RawString.data(),<br>+ Token.getString().data() - RawString.data () +<br>+ Token.getString().size());<br>+ Lookahead.push_back(Token);<br>+ Lexer.Lex();<br>+ bool Contigious = Lexer.getTok().getString().data() ==<br>+ Lookahead.back().getString().data() +<br>+ Lookahead.back().getString().size();<br>+ bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) ||<br>+ Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||<br>+ Lexer.is(AsmToken::Colon);<br>+ bool Workaround = Lexer.is(AsmToken::Colon) ||<br>+ Lookahead.back().is(AsmToken::Colon);<br>+ Again = (Contigious && Type) || (Workaround && Type);<br>+ NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type));<br>+ }<br>+ std::string Collapsed = RawString;<br>+ Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace),<br>+ Collapsed.end());<br>+ StringRef FullString = Collapsed;<br>+ std::pair<StringRef, StringRef> DotSplit = FullString.split('.');<br>+ unsigned DotReg = MatchRegisterName(DotSplit.first.lower());<br>+ if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {<br>+ if (DotSplit.second.empty()) {<br>+ RegNo = DotReg;<br>+ EndLoc = Lexer.getLoc();<br>+ if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))<br>+ return true;<br>+ return false;<br>+ } else {<br>+ RegNo = DotReg;<br>+ size_t First = RawString.find('.');<br>+ StringRef DotString (RawString.data() + First, RawString.size() - First);<br>+ Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString));<br>+ EndLoc = Lexer.getLoc();<br>+ if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))<br>+ return true;<br>+ return false;<br>+ }<br>+ }<br>+ std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');<br>+ unsigned ColonReg = MatchRegisterName(ColonSplit.first.lower());<br>+ if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {<br>+ Lexer.UnLex(Lookahead.back());<br>+ Lookahead.pop_back();<br>+ Lexer.UnLex(Lookahead.back());<br>+ Lookahead.pop_back();<br>+ RegNo = ColonReg;<br>+ EndLoc = Lexer.getLoc();<br>+ if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))<br>+ return true;<br>+ return false;<br>+ }<br>+ while (!Lookahead.empty()) {<br>+ Lexer.UnLex(Lookahead.back());<br>+ Lookahead.pop_back();<br>+ }<br>+ return true;<br>+}<br>+<br>+bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) {<br>+ if (previousEqual(Operands, 0, "call"))<br>+ return true;<br>+ if (previousEqual(Operands, 0, "jump"))<br>+ if (!getLexer().getTok().is(AsmToken::Colon))<br>+ return true;<br>+ if (previousEqual(Operands, 0, "(") && previousIsLoop(Operands, 1))<br>+ return true;<br>+ if (previousEqual(Operands, 1, ":") && previousEqual(Operands, 2, "jump") &&<br>+ (previousEqual(Operands, 0, "nt") || previousEqual(Operands, 0, "t")))<br>+ return true;<br>+ return false;<br>+}<br>+<br>+bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) {<br>+ llvm::SmallVector<AsmToken, 4> Tokens;<br>+ MCAsmLexer &Lexer = getLexer();<br>+ bool Done = false;<br>+ static char const * Comma = ",";<br>+ do {<br>+ Tokens.emplace_back (Lexer.getTok());<br>+ Lexer.Lex();<br>+ switch (Tokens.back().getKind())<br>+ {<br>+ case AsmToken::TokenKind::Hash:<br>+ if (Tokens.size () > 1)<br>+ if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) {<br>+ Tokens.insert(Tokens.end() - 2,<br>+ AsmToken(AsmToken::TokenKind::Comma, Comma));<br>+ Done = true;<br>+ }<br>+ break;<br>+ case AsmToken::TokenKind::RCurly:<br>+ case AsmToken::TokenKind::EndOfStatement:<br>+ case AsmToken::TokenKind::Eof:<br>+ Done = true;<br>+ break;<br>+ default:<br>+ break;<br>+ }<br>+ } while (!Done);<br>+ while (!Tokens.empty()) {<br>+ Lexer.UnLex(Tokens.back());<br>+ Tokens.pop_back();<br>+ }<br>+ return getParser().parseExpression(Expr);<br>+}<br>+<br>+bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {<br>+ if (implicitExpressionLocation(Operands)) {<br>+ MCAsmParser &Parser = getParser();<br>+ SMLoc Loc = Parser.getLexer().getLoc();<br>+ std::unique_ptr<HexagonOperand> Expr =<br>+ HexagonOperand::CreateImm(nullptr, Loc, Loc);<br>+ MCExpr const *& Val = Expr->Imm.Val;<br>+ Operands.push_back(std::move(Expr));<br>+ return parseExpression(Val);<br>+ }<br>+ return parseOperand(Operands);<br>+}<br>+<br>+/// Parse an instruction.<br>+bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {<br>+ MCAsmParser &Parser = getParser();<br>+ MCAsmLexer &Lexer = getLexer();<br>+ while (true) {<br>+ AsmToken const &Token = Parser.getTok();<br>+ switch (Token.getKind()) {<br>+ case AsmToken::EndOfStatement: {<br>+ Lexer.Lex();<br>+ return false;<br>+ }<br>+ case AsmToken::LCurly: {<br>+ if (!Operands.empty())<br>+ return true;<br>+ Operands.push_back(<br>+ HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));<br>+ Lexer.Lex();<br>+ return false;<br>+ }<br>+ case AsmToken::RCurly: {<br>+ if (Operands.empty()) {<br>+ Operands.push_back(<br>+ HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));<br>+ Lexer.Lex();<br>+ }<br>+ return false;<br>+ }<br>+ case AsmToken::Comma: {<br>+ Lexer.Lex();<br>+ continue;<br>+ }<br>+ case AsmToken::EqualEqual:<br>+ case AsmToken::ExclaimEqual:<br>+ case AsmToken::GreaterEqual:<br>+ case AsmToken::GreaterGreater:<br>+ case AsmToken::LessEqual:<br>+ case AsmToken::LessLess: {<br>+ Operands.push_back(HexagonOperand::CreateToken(<br>+ Token.getString().substr(0, 1), Token.getLoc()));<br>+ Operands.push_back(HexagonOperand::CreateToken(<br>+ Token.getString().substr(1, 1), Token.getLoc()));<br>+ Lexer.Lex();<br>+ continue;<br>+ }<br>+ case AsmToken::Hash: {<br>+ bool MustNotExtend = false;<br>+ bool ImplicitExpression = implicitExpressionLocation(Operands);<br>+ std::unique_ptr<HexagonOperand> Expr = HexagonOperand::CreateImm(<br>+ nullptr, Lexer.getLoc(), Lexer.getLoc());<br>+ if (!ImplicitExpression)<br>+ Operands.push_back(<br>+ HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));<br>+ Lexer.Lex();<br>+ bool MustExtend = false;<br>+ bool HiOnly = false;<br>+ bool LoOnly = false;<br>+ if (Lexer.is(AsmToken::Hash)) {<br>+ Lexer.Lex();<br>+ MustExtend = true;<br>+ } else if (ImplicitExpression)<br>+ MustNotExtend = true;<br>+ AsmToken const &Token = Parser.getTok();<br>+ if (Token.is(AsmToken::Identifier)) {<br>+ StringRef String = Token.getString();<br>+ AsmToken IDToken = Token;<br>+ if (String.lower() == "hi") {<br>+ HiOnly = true;<br>+ } else if (String.lower() == "lo") {<br>+ LoOnly = true;<br>+ }<br>+ if (HiOnly || LoOnly) {<br>+ AsmToken LParen = Lexer.peekTok();<br>+ if (!LParen.is(AsmToken::LParen)) {<br>+ HiOnly = false;<br>+ LoOnly = false;<br>+ } else {<br>+ Lexer.Lex();<br>+ }<br>+ }<br>+ }<br>+ if (parseExpression(Expr->Imm.Val))<br>+ return true;<br>+ int64_t Value;<br>+ MCContext &Context = Parser.getContext();<br>+ assert(Expr->Imm.Val != nullptr);<br>+ if (Expr->Imm.Val->evaluateAsAbsolute(Value)) {<br>+ if (HiOnly)<br>+ Expr->Imm.Val = MCBinaryExpr::createLShr(<br>+ Expr->Imm.Val, MCConstantExpr::create(16, Context), Context);<br>+ if (HiOnly || LoOnly)<br>+ Expr->Imm.Val = MCBinaryExpr::createAnd(<br>+ Expr->Imm.Val, MCConstantExpr::create(0xffff, Context), Context);<br>+ }<br>+ if (MustNotExtend)<br>+ Expr->Imm.Val = HexagonNoExtendOperand::Create(Expr->Imm.Val, Context);<br>+ Expr->Imm.MustExtend = MustExtend;<br>+ Operands.push_back(std::move(Expr));<br>+ continue;<br>+ }<br>+ default:<br>+ break;<br>+ }<br>+ if (parseExpressionOrOperand(Operands))<br>+ return true;<br>+ }<br>+}<br>+<br>+bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,<br>+ StringRef Name,<br>+ AsmToken ID,<br>+ OperandVector &Operands) {<br>+ getLexer().UnLex(ID);<br>+ return parseInstruction(Operands);<br>+}<br>+<br>+namespace {<br>+MCInst makeCombineInst(int opCode, MCOperand &Rdd,<br>+ MCOperand &MO1, MCOperand &MO2) {<br>+ MCInst TmpInst;<br>+ TmpInst.setOpcode(opCode);<br>+ TmpInst.addOperand(Rdd);<br>+ TmpInst.addOperand(MO1);<br>+ TmpInst.addOperand(MO2);<br>+<br>+ return TmpInst;<br>+}<br>+}<br>+<br>+// Define this matcher function after the auto-generated include so we<br>+// have the match class enum definitions.<br>+unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,<br>+ unsigned Kind) {<br>+ HexagonOperand *Op = static_cast<HexagonOperand *>(&AsmOp);<br>+<br>+ switch (Kind) {<br>+ case MCK_0: {<br>+ int64_t Value;<br>+ return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 0<br>+ ? Match_Success<br>+ : Match_InvalidOperand;<br>+ }<br>+ case MCK_1: {<br>+ int64_t Value;<br>+ return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 1<br>+ ? Match_Success<br>+ : Match_InvalidOperand;<br>+ }<br>+ case MCK__MINUS_1: {<br>+ int64_t Value;<br>+ return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == -1<br>+ ? Match_Success<br>+ : Match_InvalidOperand;<br>+ }<br>+ }<br>+ if (Op->Kind == HexagonOperand::Token && Kind != InvalidMatchClass) {<br>+ StringRef myStringRef = StringRef(Op->Tok.Data, Op->Tok.Length);<br>+ if (matchTokenString(myStringRef.lower()) == (MatchClassKind)Kind)<br>+ return Match_Success;<br>+ if (matchTokenString(myStringRef.upper()) == (MatchClassKind)Kind)<br>+ return Match_Success;<br>+ }<br>+<br>+ DEBUG(dbgs() << "Unmatched Operand:");<br>+ DEBUG(Op->dump());<br>+ DEBUG(dbgs() << "\n");<br>+<br>+ return Match_InvalidOperand;<br>+}<br>+<br>+void HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {<br>+ std::stringstream errStr;<br>+ errStr << "value " << Val << "(0x" << std::hex << Val << std::dec<br>+ << ") out of range: ";<br>+ if (Max >= 0)<br>+ errStr << "0-" << Max;<br>+ else<br>+ errStr << Max << "-" << (-Max - 1);<br>+ Error(IDLoc, errStr.str().c_str());<br>+}<br>+<br>+int HexagonAsmParser::processInstruction(MCInst &Inst,<br>+ OperandVector const &Operands,<br>+ SMLoc IDLoc, bool &MustExtend) {<br>+ MCContext &Context = getParser().getContext();<br>+ const MCRegisterInfo *RI = getContext().getRegisterInfo();<br>+ std::string r = "r";<br>+ std::string v = "v";<br>+ std::string Colon = ":";<br>+<br>+ bool is32bit = false; // used to distinguish between CONST32 and CONST64<br>+ switch (Inst.getOpcode()) {<br>+ default:<br>+ break;<br>+<br>+ case Hexagon::M4_mpyrr_addr:<br>+ case Hexagon::S4_addi_asl_ri:<br>+ case Hexagon::S4_addi_lsr_ri:<br>+ case Hexagon::S4_andi_asl_ri:<br>+ case Hexagon::S4_andi_lsr_ri:<br>+ case Hexagon::S4_ori_asl_ri:<br>+ case Hexagon::S4_ori_lsr_ri:<br>+ case Hexagon::S4_or_andix:<br>+ case Hexagon::S4_subi_asl_ri:<br>+ case Hexagon::S4_subi_lsr_ri: {<br>+ MCOperand &Ry = Inst.getOperand(0);<br>+ MCOperand &src = Inst.getOperand(2);<br>+ if (RI->getEncodingValue(Ry.getReg()) != RI->getEncodingValue(src.getReg()))<br>+ return Match_InvalidOperand;<br>+ break;<br>+ }<br>+<br>+ case Hexagon::C2_cmpgei: {<br>+ MCOperand &MO = Inst.getOperand(2);<br>+ MO.setExpr(MCBinaryExpr::createSub(<br>+ MO.getExpr(), MCConstantExpr::create(1, Context), Context));<br>+ Inst.setOpcode(Hexagon::C2_cmpgti);<br>+ break;<br>+ }<br>+<br>+ case Hexagon::C2_cmpgeui: {<br>+ MCOperand &MO = Inst.getOperand(2);<br>+ int64_t Value;<br>+ bool Success = MO.getExpr()->evaluateAsAbsolute(Value);<br>+ assert(Success && "Assured by matcher");<br>+ if (Value == 0) {<br>+ MCInst TmpInst;<br>+ MCOperand &Pd = Inst.getOperand(0);<br>+ MCOperand &Rt = Inst.getOperand(1);<br>+ TmpInst.setOpcode(Hexagon::C2_cmpeq);<br>+ TmpInst.addOperand(Pd);<br>+ TmpInst.addOperand(Rt);<br>+ TmpInst.addOperand(Rt);<br>+ Inst = TmpInst;<br>+ } else {<br>+ MO.setExpr(MCBinaryExpr::createSub(<br>+ MO.getExpr(), MCConstantExpr::create(1, Context), Context));<br>+ Inst.setOpcode(Hexagon::C2_cmpgtui);<br>+ }<br>+ break;<br>+ }<br>+ case Hexagon::J2_loop1r:<br>+ case Hexagon::J2_loop1i:<br>+ case Hexagon::J2_loop0r:<br>+ case Hexagon::J2_loop0i: {<br>+ MCOperand &MO = Inst.getOperand(0);<br>+ // Loop has different opcodes for extended vs not extended, but we should<br>+ // not use the other opcode as it is a legacy artifact of TD files.<br>+ int64_t Value;<br>+ if (MO.getExpr()->evaluateAsAbsolute(Value)) {<br>+ // if the the operand can fit within a 7:2 field<br>+ if (Value < (1 << 8) && Value >= -(1 << 8)) {<br>+ SMLoc myLoc = Operands[2]->getStartLoc();<br>+ // # is left in startLoc in the case of ##<br>+ // If '##' found then force extension.<br>+ if (*myLoc.getPointer() == '#') {<br>+ MustExtend = true;<br>+ break;<br>+ }<br>+ } else {<br>+ // If immediate and out of 7:2 range.<br>+ MustExtend = true;<br>+ }<br>+ }<br>+ break;<br>+ }<br>+<br>+ // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"<br>+ case Hexagon::A2_tfrp: {<br>+ MCOperand &MO = Inst.getOperand(1);<br>+ unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());<br>+ std::string R1 = r + llvm::utostr_32(RegPairNum + 1);<br>+ StringRef Reg1(R1);<br>+ MO.setReg(MatchRegisterName(Reg1));<br>+ // Add a new operand for the second register in the pair.<br>+ std::string R2 = r + llvm::utostr_32(RegPairNum);<br>+ StringRef Reg2(R2);<br>+ Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));<br>+ Inst.setOpcode(Hexagon::A2_combinew);<br>+ break;<br>+ }<br>+<br>+ case Hexagon::A2_tfrpt:<br>+ case Hexagon::A2_tfrpf: {<br>+ MCOperand &MO = Inst.getOperand(2);<br>+ unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());<br>+ std::string R1 = r + llvm::utostr_32(RegPairNum + 1);<br>+ StringRef Reg1(R1);<br>+ MO.setReg(MatchRegisterName(Reg1));<br>+ // Add a new operand for the second register in the pair.<br>+ std::string R2 = r + llvm::utostr_32(RegPairNum);<br>+ StringRef Reg2(R2);<br>+ Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));<br>+ Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)<br>+ ? Hexagon::C2_ccombinewt<br>+ : Hexagon::C2_ccombinewf);<br>+ break;<br>+ }<br>+ case Hexagon::A2_tfrptnew:<br>+ case Hexagon::A2_tfrpfnew: {<br>+ MCOperand &MO = Inst.getOperand(2);<br>+ unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());<br>+ std::string R1 = r + llvm::utostr_32(RegPairNum + 1);<br>+ StringRef Reg1(R1);<br>+ MO.setReg(MatchRegisterName(Reg1));<br>+ // Add a new operand for the second register in the pair.<br>+ std::string R2 = r + llvm::utostr_32(RegPairNum);<br>+ StringRef Reg2(R2);<br>+ Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));<br>+ Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)<br>+ ? Hexagon::C2_ccombinewnewt<br>+ : Hexagon::C2_ccombinewnewf);<br>+ break;<br>+ }<br>+<br>+ // Translate a "$Rx = CONST32(#imm)" to "$Rx = memw(gp+#LABEL) "<br>+ case Hexagon::CONST32:<br>+ case Hexagon::CONST32_Float_Real:<br>+ case Hexagon::CONST32_Int_Real:<br>+ case Hexagon::FCONST32_nsdata:<br>+ is32bit = true;<br>+ // Translate a "$Rx:y = CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) "<br>+ case Hexagon::CONST64_Float_Real:<br>+ case Hexagon::CONST64_Int_Real:<br>+<br>+ // FIXME: need better way to detect AsmStreamer (upstream removed getKind())<br>+ if (!Parser.getStreamer().hasRawTextSupport()) {<br>+ MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());<br>+ MCOperand &MO_1 = Inst.getOperand(1);<br>+ MCOperand &MO_0 = Inst.getOperand(0);<br>+<br>+ // push section onto section stack<br>+ MES->PushSection();<br>+<br>+ std::string myCharStr;<br>+ MCSectionELF *mySection;<br>+<br>+ // check if this as an immediate or a symbol<br>+ int64_t Value;<br>+ bool Absolute = MO_1.getExpr()->evaluateAsAbsolute(Value);<br>+ if (Absolute) {<br>+ // Create a new section - one for each constant<br>+ // Some or all of the zeros are replaced with the given immediate.<br>+ if (is32bit) {<br>+ std::string myImmStr = utohexstr(static_cast<uint32_t>(Value));<br>+ myCharStr = StringRef(".gnu.linkonce.l4.CONST_00000000")<br>+ .drop_back(myImmStr.size())<br>+ .str() +<br>+ myImmStr;<br>+ } else {<br>+ std::string myImmStr = utohexstr(Value);<br>+ myCharStr = StringRef(".gnu.linkonce.l8.CONST_0000000000000000")<br>+ .drop_back(myImmStr.size())<br>+ .str() +<br>+ myImmStr;<br>+ }<br>+<br>+ mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,<br>+ ELF::SHF_ALLOC | ELF::SHF_WRITE);<br>+ } else if (MO_1.isExpr()) {<br>+ // .lita - for expressions<br>+ myCharStr = ".lita";<br>+ mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,<br>+ ELF::SHF_ALLOC | ELF::SHF_WRITE);<br>+ } else<br>+ llvm_unreachable("unexpected type of machine operand!");<br>+<br>+ MES->SwitchSection(mySection);<br>+ unsigned byteSize = is32bit ? 4 : 8;<br>+ getStreamer().EmitCodeAlignment(byteSize, byteSize);<br>+<br>+ MCSymbol *Sym;<br>+<br>+ // for symbols, get rid of prepended ".gnu.linkonce.lx."<br>+<br>+ // emit symbol if needed<br>+ if (Absolute) {<br>+ Sym = getContext().getOrCreateSymbol(StringRef(myCharStr.c_str() + 16));<br>+ if (Sym->isUndefined()) {<br>+ getStreamer().EmitLabel(Sym);<br>+ getStreamer().EmitSymbolAttribute(Sym, MCSA_Global);<br>+ getStreamer().EmitIntValue(Value, byteSize);<br>+ }<br>+ } else if (MO_1.isExpr()) {<br>+ const char *StringStart = 0;<br>+ const char *StringEnd = 0;<br>+ if (*Operands[4]->getStartLoc().getPointer() == '#') {<br>+ StringStart = Operands[5]->getStartLoc().getPointer();<br>+ StringEnd = Operands[6]->getStartLoc().getPointer();<br>+ } else { // no pound<br>+ StringStart = Operands[4]->getStartLoc().getPointer();<br>+ StringEnd = Operands[5]->getStartLoc().getPointer();<br>+ }<br>+<br>+ unsigned size = StringEnd - StringStart;<br>+ std::string DotConst = ".CONST_";<br>+ Sym = getContext().getOrCreateSymbol(DotConst +<br>+ StringRef(StringStart, size));<br>+<br>+ if (Sym->isUndefined()) {<br>+ // case where symbol is not yet defined: emit symbol<br>+ getStreamer().EmitLabel(Sym);<br>+ getStreamer().EmitSymbolAttribute(Sym, MCSA_Local);<br>+ getStreamer().EmitValue(MO_1.getExpr(), 4);<br>+ }<br>+ } else<br>+ llvm_unreachable("unexpected type of machine operand!");<br>+<br>+ MES->PopSection();<br>+<br>+ if (Sym) {<br>+ MCInst TmpInst;<br>+ if (is32bit) // 32 bit<br>+ TmpInst.setOpcode(Hexagon::L2_loadrigp);<br>+ else // 64 bit<br>+ TmpInst.setOpcode(Hexagon::L2_loadrdgp);<br>+<br>+ TmpInst.addOperand(MO_0);<br>+ TmpInst.addOperand(<br>+ MCOperand::createExpr(MCSymbolRefExpr::create(Sym, getContext())));<br>+ Inst = TmpInst;<br>+ }<br>+ }<br>+ break;<br>+<br>+ // Translate a "$Rdd = #-imm" to "$Rdd = combine(#[-1,0], #-imm)"<br>+ case Hexagon::A2_tfrpi: {<br>+ MCOperand &Rdd = Inst.getOperand(0);<br>+ MCOperand &MO = Inst.getOperand(1);<br>+ int64_t Value;<br>+ int sVal = (MO.getExpr()->evaluateAsAbsolute(Value) && Value < 0) ? -1 : 0;<br>+ MCOperand imm(MCOperand::createExpr(MCConstantExpr::create(sVal, Context)));<br>+ Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, imm, MO);<br>+ break;<br>+ }<br>+<br>+ // Translate a "$Rdd = [#]#imm" to "$Rdd = combine(#, [#]#imm)"<br>+ case Hexagon::TFRI64_V4: {<br>+ MCOperand &Rdd = Inst.getOperand(0);<br>+ MCOperand &MO = Inst.getOperand(1);<br>+ int64_t Value;<br>+ if (MO.getExpr()->evaluateAsAbsolute(Value)) {<br>+ unsigned long long u64 = Value;<br>+ signed int s8 = (u64 >> 32) & 0xFFFFFFFF;<br>+ if (s8 < -128 || s8 > 127)<br>+ OutOfRange(IDLoc, s8, -128);<br>+ MCOperand imm(MCOperand::createExpr(<br>+ MCConstantExpr::create(s8, Context))); // upper 32<br>+ MCOperand imm2(MCOperand::createExpr(<br>+ MCConstantExpr::create(u64 & 0xFFFFFFFF, Context))); // lower 32<br>+ Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);<br>+ } else {<br>+ MCOperand imm(MCOperand::createExpr(<br>+ MCConstantExpr::create(0, Context))); // upper 32<br>+ Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, MO);<br>+ }<br>+ break;<br>+ }<br>+<br>+ // Handle $Rdd = combine(##imm, #imm)"<br>+ case Hexagon::TFRI64_V2_ext: {<br>+ MCOperand &Rdd = Inst.getOperand(0);<br>+ MCOperand &MO1 = Inst.getOperand(1);<br>+ MCOperand &MO2 = Inst.getOperand(2);<br>+ int64_t Value;<br>+ if (MO2.getExpr()->evaluateAsAbsolute(Value)) {<br>+ int s8 = Value;<br>+ if (s8 < -128 || s8 > 127)<br>+ OutOfRange(IDLoc, s8, -128);<br>+ }<br>+ Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2);<br>+ break;<br>+ }<br>+<br>+ // Handle $Rdd = combine(#imm, ##imm)"<br>+ case Hexagon::A4_combineii: {<br>+ MCOperand &Rdd = Inst.getOperand(0);<br>+ MCOperand &MO1 = Inst.getOperand(1);<br>+ int64_t Value;<br>+ if (MO1.getExpr()->evaluateAsAbsolute(Value)) {<br>+ int s8 = Value;<br>+ if (s8 < -128 || s8 > 127)<br>+ OutOfRange(IDLoc, s8, -128);<br>+ }<br>+ MCOperand &MO2 = Inst.getOperand(2);<br>+ Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2);<br>+ break;<br>+ }<br>+<br>+ case Hexagon::S2_tableidxb_goodsyntax: {<br>+ Inst.setOpcode(Hexagon::S2_tableidxb);<br>+ break;<br>+ }<br>+<br>+ case Hexagon::S2_tableidxh_goodsyntax: {<br>+ MCInst TmpInst;<br>+ MCOperand &Rx = Inst.getOperand(0);<br>+ MCOperand &_dst_ = Inst.getOperand(1);<br>+ MCOperand &Rs = Inst.getOperand(2);<br>+ MCOperand &Imm4 = Inst.getOperand(3);<br>+ MCOperand &Imm6 = Inst.getOperand(4);<br>+ Imm6.setExpr(MCBinaryExpr::createSub(<br>+ Imm6.getExpr(), MCConstantExpr::create(1, Context), Context));<br>+ TmpInst.setOpcode(Hexagon::S2_tableidxh);<br>+ TmpInst.addOperand(Rx);<br>+ TmpInst.addOperand(_dst_);<br>+ TmpInst.addOperand(Rs);<br>+ TmpInst.addOperand(Imm4);<br>+ TmpInst.addOperand(Imm6);<br>+ Inst = TmpInst;<br>+ break;<br>+ }<br>+<br>+ case Hexagon::S2_tableidxw_goodsyntax: {<br>+ MCInst TmpInst;<br>+ MCOperand &Rx = Inst.getOperand(0);<br>+ MCOperand &_dst_ = Inst.getOperand(1);<br>+ MCOperand &Rs = Inst.getOperand(2);<br>+ MCOperand &Imm4 = Inst.getOperand(3);<br>+ MCOperand &Imm6 = Inst.getOperand(4);<br>+ Imm6.setExpr(MCBinaryExpr::createSub(<br>+ Imm6.getExpr(), MCConstantExpr::create(2, Context), Context));<br>+ TmpInst.setOpcode(Hexagon::S2_tableidxw);<br>+ TmpInst.addOperand(Rx);<br>+ TmpInst.addOperand(_dst_);<br>+ TmpInst.addOperand(Rs);<br>+ TmpInst.addOperand(Imm4);<br>+ TmpInst.addOperand(Imm6);<br>+ Inst = TmpInst;<br>+ break;<br>+ }<br>+<br>+ case Hexagon::S2_tableidxd_goodsyntax: {<br>+ MCInst TmpInst;<br>+ MCOperand &Rx = Inst.getOperand(0);<br>+ MCOperand &_dst_ = Inst.getOperand(1);<br>+ MCOperand &Rs = Inst.getOperand(2);<br>+ MCOperand &Imm4 = Inst.getOperand(3);<br>+ MCOperand &Imm6 = Inst.getOperand(4);<br>+ Imm6.setExpr(MCBinaryExpr::createSub(<br>+ Imm6.getExpr(), MCConstantExpr::create(3, Context), Context));<br>+ TmpInst.setOpcode(Hexagon::S2_tableidxd);<br>+ TmpInst.addOperand(Rx);<br>+ TmpInst.addOperand(_dst_);<br>+ TmpInst.addOperand(Rs);<br>+ TmpInst.addOperand(Imm4);<br>+ TmpInst.addOperand(Imm6);<br>+ Inst = TmpInst;<br>+ break;<br>+ }<br>+<br>+ case Hexagon::M2_mpyui: {<br>+ Inst.setOpcode(Hexagon::M2_mpyi);<br>+ break;<br>+ }<br>+ case Hexagon::M2_mpysmi: {<br>+ MCInst TmpInst;<br>+ MCOperand &Rd = Inst.getOperand(0);<br>+ MCOperand &Rs = Inst.getOperand(1);<br>+ MCOperand &Imm = Inst.getOperand(2);<br>+ int64_t Value;<br>+ bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);<br>+ assert(Absolute);<br>+ (void)Absolute;<br>+ if (!MustExtend) {<br>+ if (Value < 0 && Value > -256) {<br>+ Imm.setExpr(MCConstantExpr::create(Value * -1, Context));<br>+ TmpInst.setOpcode(Hexagon::M2_mpysin);<br>+ } else if (Value < 256 && Value >= 0)<br>+ TmpInst.setOpcode(Hexagon::M2_mpysip);<br>+ else<br>+ return Match_InvalidOperand;<br>+ } else {<br>+ if (Value >= 0)<br>+ TmpInst.setOpcode(Hexagon::M2_mpysip);<br>+ else<br>+ return Match_InvalidOperand;<br>+ }<br>+ TmpInst.addOperand(Rd);<br>+ TmpInst.addOperand(Rs);<br>+ TmpInst.addOperand(Imm);<br>+ Inst = TmpInst;<br>+ break;<br>+ }<br>+<br>+ case Hexagon::S2_asr_i_r_rnd_goodsyntax: {<br>+ MCOperand &Imm = Inst.getOperand(2);<br>+ MCInst TmpInst;<br>+ int64_t Value;<br>+ bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);<br>+ assert(Absolute);<br>+ (void)Absolute;<br>+ if (Value == 0) { // convert to $Rd = $Rs<br>+ TmpInst.setOpcode(Hexagon::A2_tfr);<br>+ MCOperand &Rd = Inst.getOperand(0);<br>+ MCOperand &Rs = Inst.getOperand(1);<br>+ TmpInst.addOperand(Rd);<br>+ TmpInst.addOperand(Rs);<br>+ } else {<br>+ Imm.setExpr(MCBinaryExpr::createSub(<br>+ Imm.getExpr(), MCConstantExpr::create(1, Context), Context));<br>+ TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);<br>+ MCOperand &Rd = Inst.getOperand(0);<br>+ MCOperand &Rs = Inst.getOperand(1);<br>+ TmpInst.addOperand(Rd);<br>+ TmpInst.addOperand(Rs);<br>+ TmpInst.addOperand(Imm);<br>+ }<br>+ Inst = TmpInst;<br>+ break;<br>+ }<br>+<br>+ case Hexagon::S2_asr_i_p_rnd_goodsyntax: {<br>+ MCOperand &Rdd = Inst.getOperand(0);<br>+ MCOperand &Rss = Inst.getOperand(1);<br>+ MCOperand &Imm = Inst.getOperand(2);<br>+ int64_t Value;<br>+ bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);<br>+ assert(Absolute);<br>+ (void)Absolute;<br>+ if (Value == 0) { // convert to $Rdd = combine ($Rs[0], $Rs[1])<br>+ MCInst TmpInst;<br>+ unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());<br>+ std::string R1 = r + llvm::utostr_32(RegPairNum + 1);<br>+ StringRef Reg1(R1);<br>+ Rss.setReg(MatchRegisterName(Reg1));<br>+ // Add a new operand for the second register in the pair.<br>+ std::string R2 = r + llvm::utostr_32(RegPairNum);<br>+ StringRef Reg2(R2);<br>+ TmpInst.setOpcode(Hexagon::A2_combinew);<br>+ TmpInst.addOperand(Rdd);<br>+ TmpInst.addOperand(Rss);<br>+ TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));<br>+ Inst = TmpInst;<br>+ } else {<br>+ Imm.setExpr(MCBinaryExpr::createSub(<br>+ Imm.getExpr(), MCConstantExpr::create(1, Context), Context));<br>+ Inst.setOpcode(Hexagon::S2_asr_i_p_rnd);<br>+ }<br>+ break;<br>+ }<br>+<br>+ case Hexagon::A4_boundscheck: {<br>+ MCOperand &Rs = Inst.getOperand(1);<br>+ unsigned int RegNum = RI->getEncodingValue(Rs.getReg());<br>+ if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2<br>+ Inst.setOpcode(Hexagon::A4_boundscheck_hi);<br>+ std::string Name =<br>+ r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);<br>+ StringRef RegPair = Name;<br>+ Rs.setReg(MatchRegisterName(RegPair));<br>+ } else { // raw:lo<br>+ Inst.setOpcode(Hexagon::A4_boundscheck_lo);<br>+ std::string Name =<br>+ r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);<br>+ StringRef RegPair = Name;<br>+ Rs.setReg(MatchRegisterName(RegPair));<br>+ }<br>+ break;<br>+ }<br>+<br>+ case Hexagon::A2_addsp: {<br>+ MCOperand &Rs = Inst.getOperand(1);<br>+ unsigned int RegNum = RI->getEncodingValue(Rs.getReg());<br>+ if (RegNum & 1) { // Odd mapped to raw:hi<br>+ Inst.setOpcode(Hexagon::A2_addsph);<br>+ std::string Name =<br>+ r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);<br>+ StringRef RegPair = Name;<br>+ Rs.setReg(MatchRegisterName(RegPair));<br>+ } else { // Even mapped raw:lo<br>+ Inst.setOpcode(Hexagon::A2_addspl);<br>+ std::string Name =<br>+ r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);<br>+ StringRef RegPair = Name;<br>+ Rs.setReg(MatchRegisterName(RegPair));<br>+ }<br>+ break;<br>+ }<br>+<br>+ case Hexagon::M2_vrcmpys_s1: {<br>+ MCOperand &Rt = Inst.getOperand(2);<br>+ unsigned int RegNum = RI->getEncodingValue(Rt.getReg());<br>+ if (RegNum & 1) { // Odd mapped to sat:raw:hi<br>+ Inst.setOpcode(Hexagon::M2_vrcmpys_s1_h);<br>+ std::string Name =<br>+ r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);<br>+ StringRef RegPair = Name;<br>+ Rt.setReg(MatchRegisterName(RegPair));<br>+ } else { // Even mapped sat:raw:lo<br>+ Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l);<br>+ std::string Name =<br>+ r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);<br>+ StringRef RegPair = Name;<br>+ Rt.setReg(MatchRegisterName(RegPair));<br>+ }<br>+ break;<br>+ }<br>+<br>+ case Hexagon::M2_vrcmpys_acc_s1: {<br>+ MCInst TmpInst;<br>+ MCOperand &Rxx = Inst.getOperand(0);<br>+ MCOperand &Rss = Inst.getOperand(2);<br>+ MCOperand &Rt = Inst.getOperand(3);<br>+ unsigned int RegNum = RI->getEncodingValue(Rt.getReg());<br>+ if (RegNum & 1) { // Odd mapped to sat:raw:hi<br>+ TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);<br>+ std::string Name =<br>+ r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);<br>+ StringRef RegPair = Name;<br>+ Rt.setReg(MatchRegisterName(RegPair));<br>+ } else { // Even mapped sat:raw:lo<br>+ TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);<br>+ std::string Name =<br>+ r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);<br>+ StringRef RegPair = Name;<br>+ Rt.setReg(MatchRegisterName(RegPair));<br>+ }<br>+ // Registers are in different positions<br>+ TmpInst.addOperand(Rxx);<br>+ TmpInst.addOperand(Rxx);<br>+ TmpInst.addOperand(Rss);<br>+ TmpInst.addOperand(Rt);<br>+ Inst = TmpInst;<br>+ break;<br>+ }<br>+<br>+ case Hexagon::M2_vrcmpys_s1rp: {<br>+ MCOperand &Rt = Inst.getOperand(2);<br>+ unsigned int RegNum = RI->getEncodingValue(Rt.getReg());<br>+ if (RegNum & 1) { // Odd mapped to rnd:sat:raw:hi<br>+ Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);<br>+ std::string Name =<br>+ r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);<br>+ StringRef RegPair = Name;<br>+ Rt.setReg(MatchRegisterName(RegPair));<br>+ } else { // Even mapped rnd:sat:raw:lo<br>+ Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);<br>+ std::string Name =<br>+ r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum);<br>+ StringRef RegPair = Name;<br>+ Rt.setReg(MatchRegisterName(RegPair));<br>+ }<br>+ break;<br>+ }<br>+<br>+ case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {<br>+ MCOperand &Imm = Inst.getOperand(2);<br>+ int64_t Value;<br>+ bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);<br>+ assert(Absolute);<br>+ (void)Absolute;<br>+ if (Value == 0)<br>+ Inst.setOpcode(Hexagon::S2_vsathub);<br>+ else {<br>+ Imm.setExpr(MCBinaryExpr::createSub(<br>+ Imm.getExpr(), MCConstantExpr::create(1, Context), Context));<br>+ Inst.setOpcode(Hexagon::S5_asrhub_rnd_sat);<br>+ }<br>+ break;<br>+ }<br>+<br>+ case Hexagon::S5_vasrhrnd_goodsyntax: {<br>+ MCOperand &Rdd = Inst.getOperand(0);<br>+ MCOperand &Rss = Inst.getOperand(1);<br>+ MCOperand &Imm = Inst.getOperand(2);<br>+ int64_t Value;<br>+ bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);<br>+ assert(Absolute);<br>+ (void)Absolute;<br>+ if (Value == 0) {<br>+ MCInst TmpInst;<br>+ unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());<br>+ std::string R1 = r + llvm::utostr_32(RegPairNum + 1);<br>+ StringRef Reg1(R1);<br>+ Rss.setReg(MatchRegisterName(Reg1));<br>+ // Add a new operand for the second register in the pair.<br>+ std::string R2 = r + llvm::utostr_32(RegPairNum);<br>+ StringRef Reg2(R2);<br>+ TmpInst.setOpcode(Hexagon::A2_combinew);<br>+ TmpInst.addOperand(Rdd);<br>+ TmpInst.addOperand(Rss);<br>+ TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2)));<br>+ Inst = TmpInst;<br>+ } else {<br>+ Imm.setExpr(MCBinaryExpr::createSub(<br>+ Imm.getExpr(), MCConstantExpr::create(1, Context), Context));<br>+ Inst.setOpcode(Hexagon::S5_vasrhrnd);<br>+ }<br>+ break;<br>+ }<br>+<br>+ case Hexagon::A2_not: {<br>+ MCInst TmpInst;<br>+ MCOperand &Rd = Inst.getOperand(0);<br>+ MCOperand &Rs = Inst.getOperand(1);<br>+ TmpInst.setOpcode(Hexagon::A2_subri);<br>+ TmpInst.addOperand(Rd);<br>+ TmpInst.addOperand(<br>+ MCOperand::createExpr(MCConstantExpr::create(-1, Context)));<br>+ TmpInst.addOperand(Rs);<br>+ Inst = TmpInst;<br>+ break;<br>+ }<br>+ } // switch<br>+<br>+ return Match_Success;<br>+}<br><br>Added: llvm/trunk/lib/Target/Hexagon/AsmParser/LLVMBuild.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/LLVMBuild.txt?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/LLVMBuild.txt?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/AsmParser/LLVMBuild.txt (added)<br>+++ llvm/trunk/lib/Target/Hexagon/AsmParser/LLVMBuild.txt Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,23 @@<br>+;===- ./lib/Target/Hexagon/AsmParser/LLVMBuild.txt --------------*- Conf -*-===;<br>+;<br>+; The LLVM Compiler Infrastructure<br>+;<br>+; This file is distributed under the University of Illinois Open Source<br>+; License. See LICENSE.TXT for details.<br>+;<br>+;===------------------------------------------------------------------------===;<br>+;<br>+; This is an LLVMBuild description file for the components in this subdirectory.<br>+;<br>+; For more information on the LLVMBuild system, please see:<br>+;<br>+; <a href="http://llvm.org/docs/LLVMBuild.html" target="_blank">http://llvm.org/docs/LLVMBuild.html</a><br>+;<br>+;===------------------------------------------------------------------------===;<br>+<br>+[component_0]<br>+type = Library<br>+name = HexagonAsmParser<br>+parent = Hexagon<br>+required_libraries = MC MCParser Support HexagonDesc HexagonInfo<br>+add_to_library_groups = Hexagon<br><br>Added: llvm/trunk/lib/Target/Hexagon/AsmParser/Makefile<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/Makefile?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/Makefile?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/AsmParser/Makefile (added)<br>+++ llvm/trunk/lib/Target/Hexagon/AsmParser/Makefile Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,15 @@<br>+##===- lib/Target/Hexagon/AsmParser/Makefile ------------------*- Makefile -*-===##<br>+#<br>+# The LLVM Compiler Infrastructure<br>+#<br>+# This file is distributed under the University of Illinois Open Source<br>+# License. See LICENSE.TXT for details.<br>+#<br>+##===----------------------------------------------------------------------===##<br>+LEVEL = ../../../..<br>+LIBRARYNAME = LLVMHexagonAsmParser<br>+<br>+# Hack: we need to include 'main' Hexagon target directory to grab private headers<br>+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..<br>+<br>+include $(LEVEL)/Makefile.common<br><br>Modified: llvm/trunk/lib/Target/Hexagon/CMakeLists.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/CMakeLists.txt?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/CMakeLists.txt?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/CMakeLists.txt (original)<br>+++ llvm/trunk/lib/Target/Hexagon/CMakeLists.txt Sun Nov 8 22:07:48 2015<br>@@ -1,5 +1,6 @@<br> set(LLVM_TARGET_DEFINITIONS Hexagon.td)<br><br>+tablegen(LLVM HexagonGenAsmMatcher.inc -gen-asm-matcher)<br> tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)<br> tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)<br> tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)<br>@@ -50,6 +51,7 @@ add_llvm_target(HexagonCodeGen<br> HexagonVLIWPacketizer.cpp<br> )<br><br>+add_subdirectory(AsmParser)<br> add_subdirectory(TargetInfo)<br> add_subdirectory(MCTargetDesc)<br> add_subdirectory(Disassembler)<br><br>Modified: llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp (original)<br>+++ llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp Sun Nov 8 22:07:48 2015<br>@@ -7,42 +7,45 @@<br> //<br> //===----------------------------------------------------------------------===//<br><br>+#define DEBUG_TYPE "hexagon-disassembler"<br>+<br> #include "Hexagon.h"<br> #include "MCTargetDesc/HexagonBaseInfo.h"<br>-#include "MCTargetDesc/HexagonMCInstrInfo.h"<br>+#include "MCTargetDesc/HexagonMCChecker.h"<br> #include "MCTargetDesc/HexagonMCTargetDesc.h"<br>-<br>-#include "llvm/MC/MCContext.h"<br>+#include "MCTargetDesc/HexagonMCInstrInfo.h"<br>+#include "MCTargetDesc/HexagonInstPrinter.h"<br>+#include "llvm/ADT/StringExtras.h"<br> #include "llvm/MC/MCDisassembler.h"<br>+#include "llvm/MC/MCContext.h"<br> #include "llvm/MC/MCExpr.h"<br> #include "llvm/MC/MCFixedLenDisassembler.h"<br> #include "llvm/MC/MCInst.h"<br> #include "llvm/MC/MCInstrDesc.h"<br>+#include "llvm/MC/MCInstrInfo.h"<br> #include "llvm/MC/MCSubtargetInfo.h"<br> #include "llvm/Support/Debug.h"<br>-#include "llvm/Support/Endian.h"<br> #include "llvm/Support/ErrorHandling.h"<br> #include "llvm/Support/LEB128.h"<br>-#include "llvm/Support/TargetRegistry.h"<br>+#include "llvm/Support/MemoryObject.h"<br> #include "llvm/Support/raw_ostream.h"<br>-#include <array><br>+#include "llvm/Support/TargetRegistry.h"<br> #include <vector><br><br> using namespace llvm;<br> using namespace Hexagon;<br><br>-#define DEBUG_TYPE "hexagon-disassembler"<br>-<br>-// Pull DecodeStatus and its enum values into the global namespace.<br>-typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;<br>+typedef MCDisassembler::DecodeStatus DecodeStatus;<br><br> namespace {<br> /// \brief Hexagon disassembler for all Hexagon platforms.<br> class HexagonDisassembler : public MCDisassembler {<br> public:<br>+ std::unique_ptr<MCInstrInfo const> const MCII;<br> std::unique_ptr<MCInst *> CurrentBundle;<br>- HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx)<br>- : MCDisassembler(STI, Ctx), CurrentBundle(new MCInst *) {}<br>+ HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,<br>+ MCInstrInfo const *MCII)<br>+ : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {}<br><br> DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,<br> ArrayRef<uint8_t> Bytes, uint64_t Address,<br>@@ -52,10 +55,16 @@ public:<br> ArrayRef<uint8_t> Bytes, uint64_t Address,<br> raw_ostream &VStream,<br> raw_ostream &CStream) const override;<br>+<br>+ void adjustExtendedInstructions(MCInst &MCI, MCInst const &MCB) const;<br>+ void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const;<br> };<br> }<br><br>-static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>+// Forward declare these because the auto-generated code will reference them.<br>+// Definitions are further down.<br>+<br>+static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br> uint64_t Address,<br> const void *Decoder);<br> static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,<br>@@ -64,23 +73,39 @@ static DecodeStatus DecodeIntRegsLow8Reg<br> static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br> uint64_t Address,<br> const void *Decoder);<br>+static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>+ uint64_t Address,<br>+ const void *Decoder);<br> static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br> uint64_t Address,<br> const void *Decoder);<br>+static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>+ uint64_t Address,<br>+ const void *Decoder);<br> static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br> uint64_t Address,<br> const void *Decoder);<br> static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br> uint64_t Address,<br> const void *Decoder);<br>+static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>+ uint64_t Address,<br>+ const void *Decoder);<br> static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,<br> uint64_t Address,<br>- void const *Decoder);<br>+ const void *Decoder);<br>+<br>+static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn);<br>+static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn,<br>+ void const *Decoder);<br><br> static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,<br> raw_ostream &os);<br>-static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst);<br><br>+static unsigned getRegFromSubinstEncoding(unsigned encoded_reg);<br>+<br>+static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,<br>+ uint64_t Address, const void *Decoder);<br> static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,<br> const void *Decoder);<br> static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,<br>@@ -111,129 +136,15 @@ static DecodeStatus s4_6ImmDecoder(MCIns<br> const void *Decoder);<br> static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,<br> const void *Decoder);<br>-<br>-static const uint16_t IntRegDecoderTable[] = {<br>- Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,<br>- Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,<br>- Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,<br>- Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,<br>- Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,<br>- Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,<br>- Hexagon::R30, Hexagon::R31};<br>-<br>-static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,<br>- Hexagon::P2, Hexagon::P3};<br>-<br>-static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,<br>- const uint16_t Table[], size_t Size) {<br>- if (RegNo < Size) {<br>- Inst.addOperand(MCOperand::createReg(Table[RegNo]));<br>- return MCDisassembler::Success;<br>- } else<br>- return MCDisassembler::Fail;<br>-}<br>-<br>-static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>- uint64_t /*Address*/,<br>- void const *Decoder) {<br>- if (RegNo > 31)<br>- return MCDisassembler::Fail;<br>-<br>- unsigned Register = IntRegDecoderTable[RegNo];<br>- Inst.addOperand(MCOperand::createReg(Register));<br>- return MCDisassembler::Success;<br>-}<br>-<br>-static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>- uint64_t /*Address*/,<br>- const void *Decoder) {<br>- static const uint16_t CtrlRegDecoderTable[] = {<br>- Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,<br>- Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7,<br>- Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,<br>- Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH};<br>-<br>- if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0]))<br>- return MCDisassembler::Fail;<br>-<br>- if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)<br>- return MCDisassembler::Fail;<br>-<br>- unsigned Register = CtrlRegDecoderTable[RegNo];<br>- Inst.addOperand(MCOperand::createReg(Register));<br>- return MCDisassembler::Success;<br>-}<br>-<br>-static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,<br>- uint64_t /*Address*/,<br>- void const *Decoder) {<br>- static const uint16_t CtrlReg64DecoderTable[] = {<br>- Hexagon::C1_0, Hexagon::NoRegister, Hexagon::C3_2,<br>- Hexagon::NoRegister, Hexagon::NoRegister, Hexagon::NoRegister,<br>- Hexagon::C7_6, Hexagon::NoRegister, Hexagon::C9_8,<br>- Hexagon::NoRegister, Hexagon::C11_10, Hexagon::NoRegister,<br>- Hexagon::CS, Hexagon::NoRegister, Hexagon::UPC,<br>- Hexagon::NoRegister};<br>-<br>- if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0]))<br>- return MCDisassembler::Fail;<br>-<br>- if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister)<br>- return MCDisassembler::Fail;<br>-<br>- unsigned Register = CtrlReg64DecoderTable[RegNo];<br>- Inst.addOperand(MCOperand::createReg(Register));<br>- return MCDisassembler::Success;<br>-}<br>-<br>-static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>- uint64_t /*Address*/,<br>- const void *Decoder) {<br>- unsigned Register = 0;<br>- switch (RegNo) {<br>- case 0:<br>- Register = Hexagon::M0;<br>- break;<br>- case 1:<br>- Register = Hexagon::M1;<br>- break;<br>- default:<br>- return MCDisassembler::Fail;<br>- }<br>- Inst.addOperand(MCOperand::createReg(Register));<br>- return MCDisassembler::Success;<br>-}<br>-<br>-static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>- uint64_t /*Address*/,<br>- const void *Decoder) {<br>- static const uint16_t DoubleRegDecoderTable[] = {<br>- Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,<br>- Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,<br>- Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,<br>- Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};<br>-<br>- return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable,<br>- sizeof(DoubleRegDecoderTable)));<br>-}<br>-<br>-static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>- uint64_t /*Address*/,<br>- void const *Decoder) {<br>- if (RegNo > 3)<br>- return MCDisassembler::Fail;<br>-<br>- unsigned Register = PredRegDecoderTable[RegNo];<br>- Inst.addOperand(MCOperand::createReg(Register));<br>- return MCDisassembler::Success;<br>-}<br>+static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,<br>+ const void *Decoder);<br><br> #include "HexagonGenDisassemblerTables.inc"<br><br>-static MCDisassembler *createHexagonDisassembler(Target const &T,<br>- MCSubtargetInfo const &STI,<br>+static MCDisassembler *createHexagonDisassembler(const Target &T,<br>+ const MCSubtargetInfo &STI,<br> MCContext &Ctx) {<br>- return new HexagonDisassembler(STI, Ctx);<br>+ return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());<br> }<br><br> extern "C" void LLVMInitializeHexagonDisassembler() {<br>@@ -251,7 +162,6 @@ DecodeStatus HexagonDisassembler::getIns<br> Size = 0;<br><br> *CurrentBundle = &MI;<br>- MI.clear();<br> MI.setOpcode(Hexagon::BUNDLE);<br> MI.addOperand(MCOperand::createImm(0));<br> while (Result == Success && Complete == false) {<br>@@ -263,7 +173,21 @@ DecodeStatus HexagonDisassembler::getIns<br> Size += HEXAGON_INSTR_SIZE;<br> Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);<br> }<br>- return Result;<br>+ if(Result == MCDisassembler::Fail)<br>+ return Result;<br>+ HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo());<br>+ if(!Checker.check())<br>+ return MCDisassembler::Fail;<br>+ return MCDisassembler::Success;<br>+}<br>+<br>+namespace {<br>+HexagonDisassembler const &disassembler(void const *Decoder) {<br>+ return *static_cast<HexagonDisassembler const *>(Decoder);<br>+}<br>+MCContext &contextFromDecoder(void const *Decoder) {<br>+ return disassembler(Decoder).getContext();<br>+}<br> }<br><br> DecodeStatus HexagonDisassembler::getSingleInstruction(<br>@@ -272,8 +196,7 @@ DecodeStatus HexagonDisassembler::getSin<br> assert(Bytes.size() >= HEXAGON_INSTR_SIZE);<br><br> uint32_t Instruction =<br>- llvm::support::endian::read<uint32_t, llvm::support::little,<br>- llvm::support::unaligned>(Bytes.data());<br>+ (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);<br><br> auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);<br> if ((Instruction & HexagonII::INST_PARSE_MASK) ==<br>@@ -377,8 +300,8 @@ DecodeStatus HexagonDisassembler::getSin<br> MILow->setOpcode(opLow);<br> MCInst *MIHigh = new (getContext()) MCInst;<br> MIHigh->setOpcode(opHigh);<br>- AddSubinstOperands(MILow, opLow, instLow);<br>- AddSubinstOperands(MIHigh, opHigh, instHigh);<br>+ addSubinstOperands(MILow, opLow, instLow);<br>+ addSubinstOperands(MIHigh, opHigh, instHigh);<br> // see ConvertToSubInst() in<br> // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp<br><br>@@ -395,16 +318,189 @@ DecodeStatus HexagonDisassembler::getSin<br> // Calling the auto-generated decoder function.<br> Result =<br> decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI);<br>+<br>+ // If a, "standard" insn isn't found check special cases.<br>+ if (MCDisassembler::Success != Result ||<br>+ MI.getOpcode() == Hexagon::A4_ext) {<br>+ Result = decodeImmext(MI, Instruction, this);<br>+ if (MCDisassembler::Success != Result) {<br>+ Result = decodeSpecial(MI, Instruction);<br>+ }<br>+ } else {<br>+ // If the instruction is a compound instruction, register values will<br>+ // follow the duplex model, so the register values in the MCInst are<br>+ // incorrect. If the instruction is a compound, loop through the<br>+ // operands and change registers appropriately.<br>+ if (llvm::HexagonMCInstrInfo::getType(*MCII, MI) ==<br>+ HexagonII::TypeCOMPOUND) {<br>+ for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) {<br>+ if (i->isReg()) {<br>+ unsigned reg = i->getReg() - Hexagon::R0;<br>+ i->setReg(getRegFromSubinstEncoding(reg));<br>+ }<br>+ }<br>+ }<br>+ }<br> }<br><br>+ if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {<br>+ unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);<br>+ MCOperand &MCO = MI.getOperand(OpIndex);<br>+ assert(MCO.isReg() && "New value consumers must be registers");<br>+ unsigned Register =<br>+ getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());<br>+ if ((Register & 0x6) == 0)<br>+ // HexagonPRM 10.11 Bit 1-2 == 0 is reserved<br>+ return MCDisassembler::Fail;<br>+ unsigned Lookback = (Register & 0x6) >> 1;<br>+ unsigned Offset = 1;<br>+ bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);<br>+ auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);<br>+ auto i = Instructions.end() - 1;<br>+ for (auto n = Instructions.begin() - 1;; --i, ++Offset) {<br>+ if (i == n)<br>+ // Couldn't find producer<br>+ return MCDisassembler::Fail;<br>+ if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst()))<br>+ // Skip scalars when calculating distances for vectors<br>+ ++Lookback;<br>+ if (HexagonMCInstrInfo::isImmext(*i->getInst()))<br>+ ++Lookback;<br>+ if (Offset == Lookback)<br>+ break;<br>+ }<br>+ auto const &Inst = *i->getInst();<br>+ bool SubregBit = (Register & 0x1) != 0;<br>+ if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {<br>+ // If subreg bit is set we're selecting the second produced newvalue<br>+ unsigned Producer =<br>+ HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();<br>+ assert(Producer != Hexagon::NoRegister);<br>+ MCO.setReg(Producer);<br>+ } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {<br>+ unsigned Producer =<br>+ HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();<br>+ if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)<br>+ Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0;<br>+ else if (SubregBit)<br>+ // Subreg bit should not be set for non-doublevector newvalue producers<br>+ return MCDisassembler::Fail;<br>+ assert(Producer != Hexagon::NoRegister);<br>+ MCO.setReg(Producer);<br>+ } else<br>+ return MCDisassembler::Fail;<br>+ }<br>+<br>+ adjustExtendedInstructions(MI, MCB);<br>+ MCInst const *Extender =<br>+ HexagonMCInstrInfo::extenderForIndex(MCB,<br>+ HexagonMCInstrInfo::bundleSize(MCB));<br>+ if(Extender != nullptr) {<br>+ MCInst const & Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) ?<br>+ *MI.getOperand(1).getInst() : MI;<br>+ if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&<br>+ !HexagonMCInstrInfo::isExtended(*MCII, Inst))<br>+ return MCDisassembler::Fail;<br>+ }<br> return Result;<br> }<br>+<br>+void HexagonDisassembler::adjustExtendedInstructions(MCInst &MCI,<br>+ MCInst const &MCB) const {<br>+ if (!HexagonMCInstrInfo::hasExtenderForIndex(<br>+ MCB, HexagonMCInstrInfo::bundleSize(MCB))) {<br>+ unsigned opcode;<br>+ // This code is used by the disassembler to disambiguate between GP<br>+ // relative and absolute addressing instructions since they both have<br>+ // same encoding bits. However, an absolute addressing instruction must<br>+ // follow an immediate extender. Disassembler alwaus select absolute<br>+ // addressing instructions first and uses this code to change them into<br>+ // GP relative instruction in the absence of the corresponding immediate<br>+ // extender.<br>+ switch (MCI.getOpcode()) {<br>+ case Hexagon::S2_storerbabs:<br>+ opcode = Hexagon::S2_storerbgp;<br>+ break;<br>+ case Hexagon::S2_storerhabs:<br>+ opcode = Hexagon::S2_storerhgp;<br>+ break;<br>+ case Hexagon::S2_storerfabs:<br>+ opcode = Hexagon::S2_storerfgp;<br>+ break;<br>+ case Hexagon::S2_storeriabs:<br>+ opcode = Hexagon::S2_storerigp;<br>+ break;<br>+ case Hexagon::S2_storerbnewabs:<br>+ opcode = Hexagon::S2_storerbnewgp;<br>+ break;<br>+ case Hexagon::S2_storerhnewabs:<br>+ opcode = Hexagon::S2_storerhnewgp;<br>+ break;<br>+ case Hexagon::S2_storerinewabs:<br>+ opcode = Hexagon::S2_storerinewgp;<br>+ break;<br>+ case Hexagon::S2_storerdabs:<br>+ opcode = Hexagon::S2_storerdgp;<br>+ break;<br>+ case Hexagon::L4_loadrb_abs:<br>+ opcode = Hexagon::L2_loadrbgp;<br>+ break;<br>+ case Hexagon::L4_loadrub_abs:<br>+ opcode = Hexagon::L2_loadrubgp;<br>+ break;<br>+ case Hexagon::L4_loadrh_abs:<br>+ opcode = Hexagon::L2_loadrhgp;<br>+ break;<br>+ case Hexagon::L4_loadruh_abs:<br>+ opcode = Hexagon::L2_loadruhgp;<br>+ break;<br>+ case Hexagon::L4_loadri_abs:<br>+ opcode = Hexagon::L2_loadrigp;<br>+ break;<br>+ case Hexagon::L4_loadrd_abs:<br>+ opcode = Hexagon::L2_loadrdgp;<br>+ break;<br>+ default:<br>+ opcode = MCI.getOpcode();<br>+ }<br>+ MCI.setOpcode(opcode);<br>+ }<br>+}<br>+<br>+namespace llvm {<br>+extern const MCInstrDesc HexagonInsts[];<br>+}<br>+<br>+static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,<br>+ const uint16_t Table[], size_t Size) {<br>+ if (RegNo < Size) {<br>+ Inst.addOperand(MCOperand::createReg(Table[RegNo]));<br>+ return MCDisassembler::Success;<br>+ } else<br>+ return MCDisassembler::Fail;<br>+}<br>+<br> static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,<br> uint64_t Address,<br> const void *Decoder) {<br> return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);<br> }<br><br>+static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>+ uint64_t Address,<br>+ const void *Decoder) {<br>+ static const uint16_t IntRegDecoderTable[] = {<br>+ Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,<br>+ Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,<br>+ Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,<br>+ Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,<br>+ Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,<br>+ Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,<br>+ Hexagon::R30, Hexagon::R31};<br>+<br>+ return (DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable,<br>+ sizeof(IntRegDecoderTable)));<br>+}<br><br> static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br> uint64_t /*Address*/,<br>@@ -422,6 +518,19 @@ static DecodeStatus DecodeVectorRegsRegi<br> sizeof(VecRegDecoderTable)));<br> }<br><br>+static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>+ uint64_t /*Address*/,<br>+ const void *Decoder) {<br>+ static const uint16_t DoubleRegDecoderTable[] = {<br>+ Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,<br>+ Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,<br>+ Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,<br>+ Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};<br>+<br>+ return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable,<br>+ sizeof(DoubleRegDecoderTable)));<br>+}<br>+<br> static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br> uint64_t /*Address*/,<br> const void *Decoder) {<br>@@ -435,6 +544,16 @@ static DecodeStatus DecodeVecDblRegsRegi<br> sizeof(VecDblRegDecoderTable)));<br> }<br><br>+static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>+ uint64_t /*Address*/,<br>+ const void *Decoder) {<br>+ static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,<br>+ Hexagon::P2, Hexagon::P3};<br>+<br>+ return (DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable,<br>+ sizeof(PredRegDecoderTable)));<br>+}<br>+<br> static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br> uint64_t /*Address*/,<br> const void *Decoder) {<br>@@ -445,111 +564,535 @@ static DecodeStatus DecodeVecPredRegsReg<br> sizeof(VecPredRegDecoderTable)));<br> }<br><br>+static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>+ uint64_t /*Address*/,<br>+ const void *Decoder) {<br>+ static const uint16_t CtrlRegDecoderTable[] = {<br>+ Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,<br>+ Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7,<br>+ Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,<br>+ Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPC<br>+ };<br>+<br>+ if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0]))<br>+ return MCDisassembler::Fail;<br>+<br>+ if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)<br>+ return MCDisassembler::Fail;<br>+<br>+ unsigned Register = CtrlRegDecoderTable[RegNo];<br>+ Inst.addOperand(MCOperand::createReg(Register));<br>+ return MCDisassembler::Success;<br>+}<br>+<br>+static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,<br>+ uint64_t /*Address*/,<br>+ const void *Decoder) {<br>+ static const uint16_t CtrlReg64DecoderTable[] = {<br>+ Hexagon::C1_0, Hexagon::NoRegister,<br>+ Hexagon::C3_2, Hexagon::NoRegister,<br>+ Hexagon::C7_6, Hexagon::NoRegister,<br>+ Hexagon::C9_8, Hexagon::NoRegister,<br>+ Hexagon::C11_10, Hexagon::NoRegister,<br>+ Hexagon::CS, Hexagon::NoRegister,<br>+ Hexagon::UPC, Hexagon::NoRegister<br>+ };<br>+<br>+ if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0]))<br>+ return MCDisassembler::Fail;<br>+<br>+ if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister)<br>+ return MCDisassembler::Fail;<br>+<br>+ unsigned Register = CtrlReg64DecoderTable[RegNo];<br>+ Inst.addOperand(MCOperand::createReg(Register));<br>+ return MCDisassembler::Success;<br>+}<br>+<br>+static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>+ uint64_t /*Address*/,<br>+ const void *Decoder) {<br>+ unsigned Register = 0;<br>+ switch (RegNo) {<br>+ case 0:<br>+ Register = Hexagon::M0;<br>+ break;<br>+ case 1:<br>+ Register = Hexagon::M1;<br>+ break;<br>+ default:<br>+ return MCDisassembler::Fail;<br>+ }<br>+ Inst.addOperand(MCOperand::createReg(Register));<br>+ return MCDisassembler::Success;<br>+}<br>+<br>+namespace {<br>+uint32_t fullValue(MCInstrInfo const &MCII,<br>+ MCInst &MCB,<br>+ MCInst &MI,<br>+ int64_t Value) {<br>+ MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex(<br>+ MCB, HexagonMCInstrInfo::bundleSize(MCB));<br>+ if(!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))<br>+ return Value;<br>+ unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);<br>+ uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;<br>+ int64_t Bits;<br>+ bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits);<br>+ assert(Success);(void)Success;<br>+ uint32_t Upper26 = static_cast<uint32_t>(Bits);<br>+ uint32_t Operand = Upper26 | Lower6;<br>+ return Operand;<br>+}<br>+template <size_t T><br>+void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {<br>+ HexagonDisassembler const &Disassembler = disassembler(Decoder);<br>+ int64_t FullValue = fullValue(*Disassembler.MCII,<br>+ **Disassembler.CurrentBundle,<br>+ MI, SignExtend64<T>(tmp));<br>+ int64_t Extended = SignExtend64<32>(FullValue);<br>+ HexagonMCInstrInfo::addConstant(MI, Extended,<br>+ Disassembler.getContext());<br>+}<br>+}<br>+<br>+static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,<br>+ uint64_t /*Address*/,<br>+ const void *Decoder) {<br>+ HexagonDisassembler const &Disassembler = disassembler(Decoder);<br>+ int64_t FullValue = fullValue(*Disassembler.MCII,<br>+ **Disassembler.CurrentBundle,<br>+ MI, tmp);<br>+ assert(FullValue >= 0 && "Negative in unsigned decoder");<br>+ HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());<br>+ return MCDisassembler::Success;<br>+}<br>+<br> static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<16>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<16>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<12>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<12>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<11>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<11>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<12>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ HexagonMCInstrInfo::addConstant(MI, SignExtend64<12>(tmp), contextFromDecoder(Decoder));<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<13>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<13>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<14>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<14>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<10>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<10>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/,<br> const void *Decoder) {<br>- uint64_t imm = SignExtend64<8>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<8>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<6>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<6>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<4>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<4>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<5>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<5>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<6>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<6>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<7>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<7>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<10>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<10>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br> static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp,<br> uint64_t /*Address*/, const void *Decoder) {<br>- uint64_t imm = SignExtend64<9>(tmp);<br>- MI.addOperand(MCOperand::createImm(imm));<br>+ signedDecoder<19>(MI, tmp, Decoder);<br> return MCDisassembler::Success;<br> }<br><br>+// custom decoder for various jump/call immediates<br>+static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,<br>+ const void *Decoder) {<br>+ HexagonDisassembler const &Disassembler = disassembler(Decoder);<br>+ unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);<br>+ // r13_2 is not extendable, so if there are no extent bits, it's r13_2<br>+ if (Bits == 0)<br>+ Bits = 15;<br>+ uint32_t FullValue = fullValue(*Disassembler.MCII,<br>+ **Disassembler.CurrentBundle,<br>+ MI, SignExtend64(tmp, Bits));<br>+ int64_t Extended = SignExtend64<32>(FullValue) + Address;<br>+ if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true,<br>+ 0, 4))<br>+ HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());<br>+ return MCDisassembler::Success;<br>+}<br>+<br>+// Addressing mode dependent load store opcode map.<br>+// - If an insn is preceded by an extender the address is absolute.<br>+// - memw(##symbol) = r0<br>+// - If an insn is not preceded by an extender the address is GP relative.<br>+// - memw(gp + #symbol) = r0<br>+// Please note that the instructions must be ordered in the descending order<br>+// of their opcode.<br>+// HexagonII::INST_ICLASS_ST<br>+static unsigned int StoreConditionalOpcodeData[][2] = {<br>+ {S4_pstorerdfnew_abs, 0xafc02084},<br>+ {S4_pstorerdtnew_abs, 0xafc02080},<br>+ {S4_pstorerdf_abs, 0xafc00084},<br>+ {S4_pstorerdt_abs, 0xafc00080},<br>+ {S4_pstorerinewfnew_abs, 0xafa03084},<br>+ {S4_pstorerinewtnew_abs, 0xafa03080},<br>+ {S4_pstorerhnewfnew_abs, 0xafa02884},<br>+ {S4_pstorerhnewtnew_abs, 0xafa02880},<br>+ {S4_pstorerbnewfnew_abs, 0xafa02084},<br>+ {S4_pstorerbnewtnew_abs, 0xafa02080},<br>+ {S4_pstorerinewf_abs, 0xafa01084},<br>+ {S4_pstorerinewt_abs, 0xafa01080},<br>+ {S4_pstorerhnewf_abs, 0xafa00884},<br>+ {S4_pstorerhnewt_abs, 0xafa00880},<br>+ {S4_pstorerbnewf_abs, 0xafa00084},<br>+ {S4_pstorerbnewt_abs, 0xafa00080},<br>+ {S4_pstorerifnew_abs, 0xaf802084},<br>+ {S4_pstoreritnew_abs, 0xaf802080},<br>+ {S4_pstorerif_abs, 0xaf800084},<br>+ {S4_pstorerit_abs, 0xaf800080},<br>+ {S4_pstorerhfnew_abs, 0xaf402084},<br>+ {S4_pstorerhtnew_abs, 0xaf402080},<br>+ {S4_pstorerhf_abs, 0xaf400084},<br>+ {S4_pstorerht_abs, 0xaf400080},<br>+ {S4_pstorerbfnew_abs, 0xaf002084},<br>+ {S4_pstorerbtnew_abs, 0xaf002080},<br>+ {S4_pstorerbf_abs, 0xaf000084},<br>+ {S4_pstorerbt_abs, 0xaf000080}};<br>+// HexagonII::INST_ICLASS_LD<br>+<br>+// HexagonII::INST_ICLASS_LD_ST_2<br>+static unsigned int LoadStoreOpcodeData[][2] = {{L4_loadrd_abs, 0x49c00000},<br>+ {L4_loadri_abs, 0x49800000},<br>+ {L4_loadruh_abs, 0x49600000},<br>+ {L4_loadrh_abs, 0x49400000},<br>+ {L4_loadrub_abs, 0x49200000},<br>+ {L4_loadrb_abs, 0x49000000},<br>+ {S2_storerdabs, 0x48c00000},<br>+ {S2_storerinewabs, 0x48a01000},<br>+ {S2_storerhnewabs, 0x48a00800},<br>+ {S2_storerbnewabs, 0x48a00000},<br>+ {S2_storeriabs, 0x48800000},<br>+ {S2_storerfabs, 0x48600000},<br>+ {S2_storerhabs, 0x48400000},<br>+ {S2_storerbabs, 0x48000000}};<br>+static int NumCondS =<br>+ sizeof(StoreConditionalOpcodeData) / sizeof(StoreConditionalOpcodeData[0]);<br>+static int NumLS = sizeof(LoadStoreOpcodeData) / sizeof(LoadStoreOpcodeData[0]);<br>+<br>+static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) {<br>+<br>+ unsigned MachineOpcode = 0;<br>+ unsigned LLVMOpcode = 0;<br>+ int i;<br>+<br>+ if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_ST) {<br>+ for (i = 0; i < NumCondS; ++i) {<br>+ if ((insn & StoreConditionalOpcodeData[i][1]) ==<br>+ StoreConditionalOpcodeData[i][1]) {<br>+ MachineOpcode = StoreConditionalOpcodeData[i][1];<br>+ LLVMOpcode = StoreConditionalOpcodeData[i][0];<br>+ break;<br>+ }<br>+ }<br>+ }<br>+ if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_LD_ST_2) {<br>+ for (i = 0; i < NumLS; ++i) {<br>+ if ((insn & LoadStoreOpcodeData[i][1]) == LoadStoreOpcodeData[i][1]) {<br>+ MachineOpcode = LoadStoreOpcodeData[i][1];<br>+ LLVMOpcode = LoadStoreOpcodeData[i][0];<br>+ break;<br>+ }<br>+ }<br>+ }<br>+<br>+ if (MachineOpcode) {<br>+ unsigned Value = 0;<br>+ unsigned shift = 0;<br>+ MI.setOpcode(LLVMOpcode);<br>+ // Remove the parse bits from the insn.<br>+ insn &= ~HexagonII::INST_PARSE_MASK;<br>+<br>+ switch (LLVMOpcode) {<br>+ default:<br>+ return MCDisassembler::Fail;<br>+ break;<br>+<br>+ case Hexagon::S4_pstorerdf_abs:<br>+ case Hexagon::S4_pstorerdt_abs:<br>+ case Hexagon::S4_pstorerdfnew_abs:<br>+ case Hexagon::S4_pstorerdtnew_abs: {<br>+ // op: Pv<br>+ Value = insn & UINT64_C(3);<br>+ DecodePredRegsRegisterClass(MI, Value, 0, 0);<br>+ // op: u6<br>+ Value = (insn >> 12) & UINT64_C(48);<br>+ Value |= (insn >> 3) & UINT64_C(15);<br>+ MI.addOperand(MCOperand::createImm(Value));<br>+ // op: Rtt<br>+ Value = (insn >> 8) & UINT64_C(31);<br>+ DecodeDoubleRegsRegisterClass(MI, Value, 0, 0);<br>+ break;<br>+ }<br>+<br>+ case Hexagon::S4_pstorerbnewf_abs:<br>+ case Hexagon::S4_pstorerbnewt_abs:<br>+ case Hexagon::S4_pstorerbnewfnew_abs:<br>+ case Hexagon::S4_pstorerbnewtnew_abs:<br>+ case Hexagon::S4_pstorerhnewf_abs:<br>+ case Hexagon::S4_pstorerhnewt_abs:<br>+ case Hexagon::S4_pstorerhnewfnew_abs:<br>+ case Hexagon::S4_pstorerhnewtnew_abs:<br>+ case Hexagon::S4_pstorerinewf_abs:<br>+ case Hexagon::S4_pstorerinewt_abs:<br>+ case Hexagon::S4_pstorerinewfnew_abs:<br>+ case Hexagon::S4_pstorerinewtnew_abs: {<br>+ // op: Pv<br>+ Value = insn & UINT64_C(3);<br>+ DecodePredRegsRegisterClass(MI, Value, 0, 0);<br>+ // op: u6<br>+ Value = (insn >> 12) & UINT64_C(48);<br>+ Value |= (insn >> 3) & UINT64_C(15);<br>+ MI.addOperand(MCOperand::createImm(Value));<br>+ // op: Nt<br>+ Value = (insn >> 8) & UINT64_C(7);<br>+ DecodeIntRegsRegisterClass(MI, Value, 0, 0);<br>+ break;<br>+ }<br>+<br>+ case Hexagon::S4_pstorerbf_abs:<br>+ case Hexagon::S4_pstorerbt_abs:<br>+ case Hexagon::S4_pstorerbfnew_abs:<br>+ case Hexagon::S4_pstorerbtnew_abs:<br>+ case Hexagon::S4_pstorerhf_abs:<br>+ case Hexagon::S4_pstorerht_abs:<br>+ case Hexagon::S4_pstorerhfnew_abs:<br>+ case Hexagon::S4_pstorerhtnew_abs:<br>+ case Hexagon::S4_pstorerif_abs:<br>+ case Hexagon::S4_pstorerit_abs:<br>+ case Hexagon::S4_pstorerifnew_abs:<br>+ case Hexagon::S4_pstoreritnew_abs: {<br>+ // op: Pv<br>+ Value = insn & UINT64_C(3);<br>+ DecodePredRegsRegisterClass(MI, Value, 0, 0);<br>+ // op: u6<br>+ Value = (insn >> 12) & UINT64_C(48);<br>+ Value |= (insn >> 3) & UINT64_C(15);<br>+ MI.addOperand(MCOperand::createImm(Value));<br>+ // op: Rt<br>+ Value = (insn >> 8) & UINT64_C(31);<br>+ DecodeIntRegsRegisterClass(MI, Value, 0, 0);<br>+ break;<br>+ }<br>+<br>+ case Hexagon::L4_ploadrdf_abs:<br>+ case Hexagon::L4_ploadrdt_abs:<br>+ case Hexagon::L4_ploadrdfnew_abs:<br>+ case Hexagon::L4_ploadrdtnew_abs: {<br>+ // op: Rdd<br>+ Value = insn & UINT64_C(31);<br>+ DecodeDoubleRegsRegisterClass(MI, Value, 0, 0);<br>+ // op: Pt<br>+ Value = ((insn >> 9) & UINT64_C(3));<br>+ DecodePredRegsRegisterClass(MI, Value, 0, 0);<br>+ // op: u6<br>+ Value = ((insn >> 15) & UINT64_C(62));<br>+ Value |= ((insn >> 8) & UINT64_C(1));<br>+ MI.addOperand(MCOperand::createImm(Value));<br>+ break;<br>+ }<br>+<br>+ case Hexagon::L4_ploadrbf_abs:<br>+ case Hexagon::L4_ploadrbt_abs:<br>+ case Hexagon::L4_ploadrbfnew_abs:<br>+ case Hexagon::L4_ploadrbtnew_abs:<br>+ case Hexagon::L4_ploadrhf_abs:<br>+ case Hexagon::L4_ploadrht_abs:<br>+ case Hexagon::L4_ploadrhfnew_abs:<br>+ case Hexagon::L4_ploadrhtnew_abs:<br>+ case Hexagon::L4_ploadrubf_abs:<br>+ case Hexagon::L4_ploadrubt_abs:<br>+ case Hexagon::L4_ploadrubfnew_abs:<br>+ case Hexagon::L4_ploadrubtnew_abs:<br>+ case Hexagon::L4_ploadruhf_abs:<br>+ case Hexagon::L4_ploadruht_abs:<br>+ case Hexagon::L4_ploadruhfnew_abs:<br>+ case Hexagon::L4_ploadruhtnew_abs:<br>+ case Hexagon::L4_ploadrif_abs:<br>+ case Hexagon::L4_ploadrit_abs:<br>+ case Hexagon::L4_ploadrifnew_abs:<br>+ case Hexagon::L4_ploadritnew_abs:<br>+ // op: Rd<br>+ Value = insn & UINT64_C(31);<br>+ DecodeIntRegsRegisterClass(MI, Value, 0, 0);<br>+ // op: Pt<br>+ Value = (insn >> 9) & UINT64_C(3);<br>+ DecodePredRegsRegisterClass(MI, Value, 0, 0);<br>+ // op: u6<br>+ Value = (insn >> 15) & UINT64_C(62);<br>+ Value |= (insn >> 8) & UINT64_C(1);<br>+ MI.addOperand(MCOperand::createImm(Value));<br>+ break;<br>+<br>+ // op: g16_2<br>+ case (Hexagon::L4_loadri_abs):<br>+ ++shift;<br>+ // op: g16_1<br>+ case Hexagon::L4_loadrh_abs:<br>+ case Hexagon::L4_loadruh_abs:<br>+ ++shift;<br>+ // op: g16_0<br>+ case Hexagon::L4_loadrb_abs:<br>+ case Hexagon::L4_loadrub_abs: {<br>+ // op: Rd<br>+ Value |= insn & UINT64_C(31);<br>+ DecodeIntRegsRegisterClass(MI, Value, 0, 0);<br>+ Value = (insn >> 11) & UINT64_C(49152);<br>+ Value |= (insn >> 7) & UINT64_C(15872);<br>+ Value |= (insn >> 5) & UINT64_C(511);<br>+ MI.addOperand(MCOperand::createImm(Value << shift));<br>+ break;<br>+ }<br>+<br>+ case Hexagon::L4_loadrd_abs: {<br>+ Value = insn & UINT64_C(31);<br>+ DecodeDoubleRegsRegisterClass(MI, Value, 0, 0);<br>+ Value = (insn >> 11) & UINT64_C(49152);<br>+ Value |= (insn >> 7) & UINT64_C(15872);<br>+ Value |= (insn >> 5) & UINT64_C(511);<br>+ MI.addOperand(MCOperand::createImm(Value << 3));<br>+ break;<br>+ }<br>+<br>+ case Hexagon::S2_storerdabs: {<br>+ // op: g16_3<br>+ Value = (insn >> 11) & UINT64_C(49152);<br>+ Value |= (insn >> 7) & UINT64_C(15872);<br>+ Value |= (insn >> 5) & UINT64_C(256);<br>+ Value |= insn & UINT64_C(255);<br>+ MI.addOperand(MCOperand::createImm(Value << 3));<br>+ // op: Rtt<br>+ Value = (insn >> 8) & UINT64_C(31);<br>+ DecodeDoubleRegsRegisterClass(MI, Value, 0, 0);<br>+ break;<br>+ }<br>+<br>+ // op: g16_2<br>+ case Hexagon::S2_storerinewabs:<br>+ ++shift;<br>+ // op: g16_1<br>+ case Hexagon::S2_storerhnewabs:<br>+ ++shift;<br>+ // op: g16_0<br>+ case Hexagon::S2_storerbnewabs: {<br>+ Value = (insn >> 11) & UINT64_C(49152);<br>+ Value |= (insn >> 7) & UINT64_C(15872);<br>+ Value |= (insn >> 5) & UINT64_C(256);<br>+ Value |= insn & UINT64_C(255);<br>+ MI.addOperand(MCOperand::createImm(Value << shift));<br>+ // op: Nt<br>+ Value = (insn >> 8) & UINT64_C(7);<br>+ DecodeIntRegsRegisterClass(MI, Value, 0, 0);<br>+ break;<br>+ }<br>+<br>+ // op: g16_2<br>+ case Hexagon::S2_storeriabs:<br>+ ++shift;<br>+ // op: g16_1<br>+ case Hexagon::S2_storerhabs:<br>+ case Hexagon::S2_storerfabs:<br>+ ++shift;<br>+ // op: g16_0<br>+ case Hexagon::S2_storerbabs: {<br>+ Value = (insn >> 11) & UINT64_C(49152);<br>+ Value |= (insn >> 7) & UINT64_C(15872);<br>+ Value |= (insn >> 5) & UINT64_C(256);<br>+ Value |= insn & UINT64_C(255);<br>+ MI.addOperand(MCOperand::createImm(Value << shift));<br>+ // op: Rt<br>+ Value = (insn >> 8) & UINT64_C(31);<br>+ DecodeIntRegsRegisterClass(MI, Value, 0, 0);<br>+ break;<br>+ }<br>+ }<br>+ return MCDisassembler::Success;<br>+ }<br>+ return MCDisassembler::Fail;<br>+}<br>+<br>+static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn,<br>+ void const *Decoder) {<br>+<br>+ // Instruction Class for a constant a extender: bits 31:28 = 0x0000<br>+ if ((~insn & 0xf0000000) == 0xf0000000) {<br>+ unsigned Value;<br>+ // 27:16 High 12 bits of 26-bit extender.<br>+ Value = (insn & 0x0fff0000) << 4;<br>+ // 13:0 Low 14 bits of 26-bit extender.<br>+ Value |= ((insn & 0x3fff) << 6);<br>+ MI.setOpcode(Hexagon::A4_ext);<br>+ HexagonMCInstrInfo::addConstant(MI, Value, contextFromDecoder(Decoder));<br>+ return MCDisassembler::Success;<br>+ }<br>+ return MCDisassembler::Fail;<br>+}<br>+<br> // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td<br> enum subInstBinaryValues {<br> V4_SA1_addi_BITS = 0x0000,<br>@@ -807,6 +1350,8 @@ static unsigned getRegFromSubinstEncodin<br> return Hexagon::R0 + encoded_reg;<br> else if (encoded_reg < 16)<br> return Hexagon::R0 + encoded_reg + 8;<br>+<br>+ // patently false value<br> return Hexagon::NoRegister;<br> }<br><br>@@ -815,10 +1360,13 @@ static unsigned getDRegFromSubinstEncodi<br> return Hexagon::D0 + encoded_dreg;<br> else if (encoded_dreg < 8)<br> return Hexagon::D0 + encoded_dreg + 4;<br>+<br>+ // patently false value<br> return Hexagon::NoRegister;<br> }<br><br>-static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) {<br>+void HexagonDisassembler::addSubinstOperands(MCInst *MI, unsigned opcode,<br>+ unsigned inst) const {<br> int64_t operand;<br> MCOperand Op;<br> switch (opcode) {<br>@@ -838,8 +1386,7 @@ static void AddSubinstOperands(MCInst *M<br> case Hexagon::V4_SS2_allocframe:<br> // u 8-4{5_3}<br> operand = ((inst & 0x1f0) >> 4) << 3;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SL1_loadri_io:<br> // Rd 3-0, Rs 7-4, u 11-8{4_2}<br>@@ -850,8 +1397,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = (inst & 0xf00) >> 6;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SL1_loadrub_io:<br> // Rd 3-0, Rs 7-4, u 11-8<br>@@ -862,8 +1408,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = (inst & 0xf00) >> 8;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SL2_loadrb_io:<br> // Rd 3-0, Rs 7-4, u 10-8<br>@@ -874,8 +1419,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = (inst & 0x700) >> 8;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SL2_loadrh_io:<br> case Hexagon::V4_SL2_loadruh_io:<br>@@ -887,8 +1431,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = ((inst & 0x700) >> 8) << 1;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SL2_loadrd_sp:<br> // Rdd 2-0, u 7-3{5_3}<br>@@ -896,8 +1439,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = ((inst & 0x0f8) >> 3) << 3;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SL2_loadri_sp:<br> // Rd 3-0, u 8-4{5_2}<br>@@ -905,8 +1447,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = ((inst & 0x1f0) >> 4) << 2;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SA1_addi:<br> // Rx 3-0 (x2), s7 10-4<br>@@ -915,8 +1456,7 @@ static void AddSubinstOperands(MCInst *M<br> MI->addOperand(Op);<br> MI->addOperand(Op);<br> operand = SignExtend64<7>((inst & 0x7f0) >> 4);<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SA1_addrx:<br> // Rx 3-0 (x2), Rs 7-4<br>@@ -949,8 +1489,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = ((inst & 0x3f0) >> 4) << 2;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SA1_seti:<br> // Rd 3-0, u 9-4<br>@@ -958,8 +1497,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = (inst & 0x3f0) >> 4;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SA1_clrf:<br> case Hexagon::V4_SA1_clrfnew:<br>@@ -977,8 +1515,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = inst & 0x3;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SA1_combine0i:<br> case Hexagon::V4_SA1_combine1i:<br>@@ -989,8 +1526,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = (inst & 0x060) >> 5;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SA1_combinerz:<br> case Hexagon::V4_SA1_combinezr:<br>@@ -1008,8 +1544,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = (inst & 0xf00) >> 8;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> operand = getRegFromSubinstEncoding(inst & 0xf);<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br>@@ -1020,8 +1555,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = ((inst & 0xf00) >> 8) << 2;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> operand = getRegFromSubinstEncoding(inst & 0xf);<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br>@@ -1033,8 +1567,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = inst & 0xf;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SS2_storewi0:<br> case Hexagon::V4_SS2_storewi1:<br>@@ -1043,14 +1576,12 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = (inst & 0xf) << 2;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> break;<br> case Hexagon::V4_SS2_stored_sp:<br> // s 8-3{6_3}, Rtt 2-0<br> operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3);<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> operand = getDRegFromSubinstEncoding(inst & 0x7);<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br>@@ -1061,8 +1592,7 @@ static void AddSubinstOperands(MCInst *M<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br> operand = ((inst & 0x700) >> 8) << 1;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> operand = getRegFromSubinstEncoding(inst & 0xf);<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br>@@ -1070,8 +1600,7 @@ static void AddSubinstOperands(MCInst *M<br> case Hexagon::V4_SS2_storew_sp:<br> // u 8-4{5_2}, Rd 3-0<br> operand = ((inst & 0x1f0) >> 4) << 2;<br>- Op = MCOperand::createImm(operand);<br>- MI->addOperand(Op);<br>+ HexagonMCInstrInfo::addConstant(*MI, operand, getContext());<br> operand = getRegFromSubinstEncoding(inst & 0xf);<br> Op = MCOperand::createReg(operand);<br> MI->addOperand(Op);<br><br>Modified: llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt (original)<br>+++ llvm/trunk/lib/Target/Hexagon/Disassembler/LLVMBuild.txt Sun Nov 8 22:07:48 2015<br>@@ -19,5 +19,5 @@<br> type = Library<br> name = HexagonDisassembler<br> parent = Hexagon<br>-required_libraries = HexagonDesc HexagonInfo MCDisassembler Support<br>+required_libraries = HexagonDesc HexagonInfo MC MCDisassembler Support<br> add_to_library_groups = Hexagon<br><br>Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)<br>+++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Sun Nov 8 22:07:48 2015<br>@@ -30,6 +30,9 @@ def ArchV60: SubtargetFeature<"v60", "He<br> // Hexagon ISA Extensions<br> def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps",<br> "true", "Hexagon HVX instructions">;<br>+def ExtensionHVXDbl: SubtargetFeature<"hvxDbl", "UseHVXDblOps",<br>+ "true", "Hexagon HVX Double instructions">;<br>+<br> //===----------------------------------------------------------------------===//<br> // Hexagon Instruction Predicate Definitions.<br> //===----------------------------------------------------------------------===//<br>@@ -212,7 +215,13 @@ def : Proc<"hexagonv5", HexagonModelV4,<br> // Declare the target which we are implementing<br> //===----------------------------------------------------------------------===//<br><br>+def HexagonAsmParserVariant : AsmParserVariant {<br>+ int Variant = 0;<br>+ string TokenizingCharacters = "#()=:.<>!+*";<br>+}<br>+<br> def Hexagon : Target {<br> // Pull in Instruction Info:<br> let InstructionSet = HexagonInstrInfo;<br>+ let AssemblyParserVariants = [HexagonAsmParserVariant];<br> }<br><br>Modified: llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp (original)<br>+++ llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp Sun Nov 8 22:07:48 2015<br>@@ -73,11 +73,14 @@ void llvm::HexagonLowerToMC(MachineInstr<br> APFloat Val = MO.getFPImm()->getValueAPF();<br> // FP immediates are used only when setting GPRs, so they may be dealt<br> // with like regular immediates from this point on.<br>- MCO = MCOperand::createImm(*Val.bitcastToAPInt().getRawData());<br>+ MCO = MCOperand::createExpr(<br>+ MCConstantExpr::create(*Val.bitcastToAPInt().getRawData(),<br>+ AP.OutContext));<br> break;<br> }<br> case MachineOperand::MO_Immediate:<br>- MCO = MCOperand::createImm(MO.getImm());<br>+ MCO = MCOperand::createExpr(<br>+ MCConstantExpr::create(MO.getImm(), AP.OutContext));<br> break;<br> case MachineOperand::MO_MachineBasicBlock:<br> MCO = MCOperand::createExpr<br><br>Modified: llvm/trunk/lib/Target/Hexagon/HexagonOperands.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOperands.td?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOperands.td?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/HexagonOperands.td (original)<br>+++ llvm/trunk/lib/Target/Hexagon/HexagonOperands.td Sun Nov 8 22:07:48 2015<br>@@ -1,4 +1,4 @@<br>-//===- HexagonOperands.td - Hexagon immediate processing -*- tablegen -*-===//<br>+//===- HexagonImmediates.td - Hexagon immediate processing -*- tablegen -*-===//<br> //<br> // The LLVM Compiler Infrastructure<br> //<br>@@ -7,57 +7,100 @@<br> //<br> //===----------------------------------------------------------------------===//<br><br>+def s32ImmOperand : AsmOperandClass { let Name = "s32Imm"; }<br>+def s8ImmOperand : AsmOperandClass { let Name = "s8Imm"; }<br>+def s8Imm64Operand : AsmOperandClass { let Name = "s8Imm64"; }<br>+def s6ImmOperand : AsmOperandClass { let Name = "s6Imm"; }<br>+def s4ImmOperand : AsmOperandClass { let Name = "s4Imm"; }<br> def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; }<br> def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; }<br> def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; }<br> def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; }<br> def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; }<br> def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; }<br>-<br>+def u64ImmOperand : AsmOperandClass { let Name = "u64Imm"; }<br>+def u32ImmOperand : AsmOperandClass { let Name = "u32Imm"; }<br>+def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; }<br>+def u16ImmOperand : AsmOperandClass { let Name = "u16Imm"; }<br>+def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; }<br>+def u16_1ImmOperand : AsmOperandClass { let Name = "u16_1Imm"; }<br>+def u16_2ImmOperand : AsmOperandClass { let Name = "u16_2Imm"; }<br>+def u16_3ImmOperand : AsmOperandClass { let Name = "u16_3Imm"; }<br>+def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; }<br>+def u10ImmOperand : AsmOperandClass { let Name = "u10Imm"; }<br>+def u9ImmOperand : AsmOperandClass { let Name = "u9Imm"; }<br>+def u8ImmOperand : AsmOperandClass { let Name = "u8Imm"; }<br>+def u7ImmOperand : AsmOperandClass { let Name = "u7Imm"; }<br>+def u6ImmOperand : AsmOperandClass { let Name = "u6Imm"; }<br>+def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; }<br>+def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; }<br>+def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; }<br>+def u6_3ImmOperand : AsmOperandClass { let Name = "u6_3Imm"; }<br>+def u5ImmOperand : AsmOperandClass { let Name = "u5Imm"; }<br>+def u4ImmOperand : AsmOperandClass { let Name = "u4Imm"; }<br>+def u3ImmOperand : AsmOperandClass { let Name = "u3Imm"; }<br>+def u2ImmOperand : AsmOperandClass { let Name = "u2Imm"; }<br>+def u1ImmOperand : AsmOperandClass { let Name = "u1Imm"; }<br>+def n8ImmOperand : AsmOperandClass { let Name = "n8Imm"; }<br> // Immediate operands.<br><br>-let PrintMethod = "printImmOperand" in {<br>- def s32Imm : Operand<i32>;<br>- def s8Imm : Operand<i32>;<br>- def s8Imm64 : Operand<i64>;<br>- def s6Imm : Operand<i32>;<br>+let OperandType = "OPERAND_IMMEDIATE",<br>+ DecoderMethod = "unsignedImmDecoder" in {<br>+ def s32Imm : Operand<i32> { let ParserMatchClass = s32ImmOperand;<br>+ let DecoderMethod = "s32ImmDecoder"; }<br>+ def s8Imm : Operand<i32> { let ParserMatchClass = s8ImmOperand;<br>+ let DecoderMethod = "s8ImmDecoder"; }<br>+ def s8Imm64 : Operand<i64> { let ParserMatchClass = s8Imm64Operand;<br>+ let DecoderMethod = "s8ImmDecoder"; }<br>+ def s6Imm : Operand<i32> { let ParserMatchClass = s6ImmOperand;<br>+ let DecoderMethod = "s6_0ImmDecoder"; }<br> def s6_3Imm : Operand<i32>;<br>- def s4Imm : Operand<i32>;<br>- def s4_0Imm : Operand<i32> { let DecoderMethod = "s4_0ImmDecoder"; }<br>- def s4_1Imm : Operand<i32> { let DecoderMethod = "s4_1ImmDecoder"; }<br>- def s4_2Imm : Operand<i32> { let DecoderMethod = "s4_2ImmDecoder"; }<br>- def s4_3Imm : Operand<i32> { let DecoderMethod = "s4_3ImmDecoder"; }<br>- def u64Imm : Operand<i64>;<br>- def u32Imm : Operand<i32>;<br>- def u26_6Imm : Operand<i32>;<br>- def u16Imm : Operand<i32>;<br>- def u16_0Imm : Operand<i32>;<br>- def u16_1Imm : Operand<i32>;<br>- def u16_2Imm : Operand<i32>;<br>- def u16_3Imm : Operand<i32>;<br>- def u11_3Imm : Operand<i32>;<br>- def u10Imm : Operand<i32>;<br>- def u9Imm : Operand<i32>;<br>- def u8Imm : Operand<i32>;<br>- def u7Imm : Operand<i32>;<br>- def u6Imm : Operand<i32>;<br>- def u6_0Imm : Operand<i32>;<br>- def u6_1Imm : Operand<i32>;<br>- def u6_2Imm : Operand<i32>;<br>- def u6_3Imm : Operand<i32>;<br>- def u5Imm : Operand<i32>;<br>+ def s4Imm : Operand<i32> { let ParserMatchClass = s4ImmOperand;<br>+ let DecoderMethod = "s4_0ImmDecoder"; }<br>+ def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand;<br>+ let DecoderMethod = "s4_0ImmDecoder"; }<br>+ def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand;<br>+ let DecoderMethod = "s4_1ImmDecoder"; }<br>+ def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand;<br>+ let DecoderMethod = "s4_2ImmDecoder"; }<br>+ def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand;<br>+ let DecoderMethod = "s4_3ImmDecoder"; }<br>+ def u64Imm : Operand<i64> { let ParserMatchClass = u64ImmOperand; }<br>+ def u32Imm : Operand<i32> { let ParserMatchClass = u32ImmOperand; }<br>+ def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; }<br>+ def u16Imm : Operand<i32> { let ParserMatchClass = u16ImmOperand; }<br>+ def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; }<br>+ def u16_1Imm : Operand<i32> { let ParserMatchClass = u16_1ImmOperand; }<br>+ def u16_2Imm : Operand<i32> { let ParserMatchClass = u16_2ImmOperand; }<br>+ def u16_3Imm : Operand<i32> { let ParserMatchClass = u16_3ImmOperand; }<br>+ def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; }<br>+ def u10Imm : Operand<i32> { let ParserMatchClass = u10ImmOperand; }<br>+ def u9Imm : Operand<i32> { let ParserMatchClass = u9ImmOperand; }<br>+ def u8Imm : Operand<i32> { let ParserMatchClass = u8ImmOperand; }<br>+ def u7Imm : Operand<i32> { let ParserMatchClass = u7ImmOperand; }<br>+ def u6Imm : Operand<i32> { let ParserMatchClass = u6ImmOperand; }<br>+ def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; }<br>+ def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; }<br>+ def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; }<br>+ def u6_3Imm : Operand<i32> { let ParserMatchClass = u6_3ImmOperand; }<br>+ def u5Imm : Operand<i32> { let ParserMatchClass = u5ImmOperand; }<br>+ def u5_0Imm : Operand<i32>;<br>+ def u5_1Imm : Operand<i32>;<br> def u5_2Imm : Operand<i32>;<br> def u5_3Imm : Operand<i32>;<br>- def u4Imm : Operand<i32>;<br>+ def u4Imm : Operand<i32> { let ParserMatchClass = u4ImmOperand; }<br> def u4_0Imm : Operand<i32>;<br>+ def u4_1Imm : Operand<i32>;<br> def u4_2Imm : Operand<i32>;<br>- def u3Imm : Operand<i32>;<br>+ def u4_3Imm : Operand<i32>;<br>+ def u3Imm : Operand<i32> { let ParserMatchClass = u3ImmOperand; }<br> def u3_0Imm : Operand<i32>;<br> def u3_1Imm : Operand<i32>;<br>- def u2Imm : Operand<i32>;<br>- def u1Imm : Operand<i32>;<br>- def n8Imm : Operand<i32>;<br>- def m6Imm : Operand<i32>;<br>+ def u3_2Imm : Operand<i32>;<br>+ def u3_3Imm : Operand<i32>;<br>+ def u2Imm : Operand<i32> { let ParserMatchClass = u2ImmOperand; }<br>+ def u1Imm : Operand<i32> { let ParserMatchClass = u1ImmOperand; }<br>+ def n8Imm : Operand<i32> { let ParserMatchClass = n8ImmOperand; }<br> }<br><br> let OperandType = "OPERAND_IMMEDIATE" in {<br>@@ -73,9 +116,6 @@ let OperandType = "OPERAND_IMMEDIATE" in<br> let DecoderMethod = "s3_6ImmDecoder";}<br> }<br><br>-let PrintMethod = "printNOneImmOperand" in<br>-def nOneImm : Operand<i32>;<br>-<br> //<br> // Immediate predicates<br> //<br>@@ -169,7 +209,6 @@ def s4_3ImmPred : PatLeaf<(i32 imm), [{<br> return isShiftedInt<4,3>(v);<br> }]>;<br><br>-<br> def u64ImmPred : PatLeaf<(i64 imm), [{<br> // Adding "N ||" to suppress gcc unused warning.<br> return (N || true);<br>@@ -225,6 +264,11 @@ def u11_3ImmPred : PatLeaf<(i32 imm), [{<br> return isShiftedUInt<11,3>(v);<br> }]>;<br><br>+def u10ImmPred : PatLeaf<(i32 imm), [{<br>+ int64_t v = (int64_t)N->getSExtValue();<br>+ return isUInt<10>(v);<br>+}]>;<br>+<br> def u9ImmPred : PatLeaf<(i32 imm), [{<br> int64_t v = (int64_t)N->getSExtValue();<br> return isUInt<9>(v);<br>@@ -296,6 +340,11 @@ def u1ImmPred : PatLeaf<(i1 imm), [{<br> return isUInt<1>(v);<br> }]>;<br><br>+def u1ImmPred32 : PatLeaf<(i32 imm), [{<br>+ int64_t v = (int64_t)N->getSExtValue();<br>+ return isUInt<1>(v);<br>+}]>;<br>+<br> def m5BImmPred : PatLeaf<(i32 imm), [{<br> // m5BImmPred predicate - True if the (char) number is in range -1 .. -31<br> // and will fit in a 5 bit field when made positive, for use in memops.<br>@@ -408,29 +457,65 @@ def SetClr3ImmPred : PatLeaf<(i32 imm),<br><br><br> // Extendable immediate operands.<br>+def f32ExtOperand : AsmOperandClass { let Name = "f32Ext"; }<br>+def s16ExtOperand : AsmOperandClass { let Name = "s16Ext"; }<br>+def s12ExtOperand : AsmOperandClass { let Name = "s12Ext"; }<br>+def s10ExtOperand : AsmOperandClass { let Name = "s10Ext"; }<br>+def s9ExtOperand : AsmOperandClass { let Name = "s9Ext"; }<br>+def s8ExtOperand : AsmOperandClass { let Name = "s8Ext"; }<br>+def s7ExtOperand : AsmOperandClass { let Name = "s7Ext"; }<br>+def s6ExtOperand : AsmOperandClass { let Name = "s6Ext"; }<br>+def s11_0ExtOperand : AsmOperandClass { let Name = "s11_0Ext"; }<br>+def s11_1ExtOperand : AsmOperandClass { let Name = "s11_1Ext"; }<br>+def s11_2ExtOperand : AsmOperandClass { let Name = "s11_2Ext"; }<br>+def s11_3ExtOperand : AsmOperandClass { let Name = "s11_3Ext"; }<br>+def u6ExtOperand : AsmOperandClass { let Name = "u6Ext"; }<br>+def u7ExtOperand : AsmOperandClass { let Name = "u7Ext"; }<br>+def u8ExtOperand : AsmOperandClass { let Name = "u8Ext"; }<br>+def u9ExtOperand : AsmOperandClass { let Name = "u9Ext"; }<br>+def u10ExtOperand : AsmOperandClass { let Name = "u10Ext"; }<br>+def u6_0ExtOperand : AsmOperandClass { let Name = "u6_0Ext"; }<br>+def u6_1ExtOperand : AsmOperandClass { let Name = "u6_1Ext"; }<br>+def u6_2ExtOperand : AsmOperandClass { let Name = "u6_2Ext"; }<br>+def u6_3ExtOperand : AsmOperandClass { let Name = "u6_3Ext"; }<br>+def u32MustExtOperand : AsmOperandClass { let Name = "u32MustExt"; }<br>+<br><br>-let PrintMethod = "printExtOperand" in {<br>- def f32Ext : Operand<f32>;<br>- def s16Ext : Operand<i32> { let DecoderMethod = "s16ImmDecoder"; }<br>- def s12Ext : Operand<i32> { let DecoderMethod = "s12ImmDecoder"; }<br>- def s11_0Ext : Operand<i32> { let DecoderMethod = "s11_0ImmDecoder"; }<br>- def s11_1Ext : Operand<i32> { let DecoderMethod = "s11_1ImmDecoder"; }<br>- def s11_2Ext : Operand<i32> { let DecoderMethod = "s11_2ImmDecoder"; }<br>- def s11_3Ext : Operand<i32> { let DecoderMethod = "s11_3ImmDecoder"; }<br>- def s10Ext : Operand<i32> { let DecoderMethod = "s10ImmDecoder"; }<br>- def s9Ext : Operand<i32> { let DecoderMethod = "s90ImmDecoder"; }<br>- def s8Ext : Operand<i32> { let DecoderMethod = "s8ImmDecoder"; }<br>- def s7Ext : Operand<i32>;<br>- def s6Ext : Operand<i32> { let DecoderMethod = "s6_0ImmDecoder"; }<br>- def u6Ext : Operand<i32>;<br>- def u7Ext : Operand<i32>;<br>- def u8Ext : Operand<i32>;<br>- def u9Ext : Operand<i32>;<br>- def u10Ext : Operand<i32>;<br>- def u6_0Ext : Operand<i32>;<br>- def u6_1Ext : Operand<i32>;<br>- def u6_2Ext : Operand<i32>;<br>- def u6_3Ext : Operand<i32>;<br>+<br>+let OperandType = "OPERAND_IMMEDIATE", PrintMethod = "printExtOperand",<br>+ DecoderMethod = "unsignedImmDecoder" in {<br>+ def f32Ext : Operand<f32> { let ParserMatchClass = f32ExtOperand; }<br>+ def s16Ext : Operand<i32> { let ParserMatchClass = s16ExtOperand;<br>+ let DecoderMethod = "s16ImmDecoder"; }<br>+ def s12Ext : Operand<i32> { let ParserMatchClass = s12ExtOperand;<br>+ let DecoderMethod = "s12ImmDecoder"; }<br>+ def s11_0Ext : Operand<i32> { let ParserMatchClass = s11_0ExtOperand;<br>+ let DecoderMethod = "s11_0ImmDecoder"; }<br>+ def s11_1Ext : Operand<i32> { let ParserMatchClass = s11_1ExtOperand;<br>+ let DecoderMethod = "s11_1ImmDecoder"; }<br>+ def s11_2Ext : Operand<i32> { let ParserMatchClass = s11_2ExtOperand;<br>+ let DecoderMethod = "s11_2ImmDecoder"; }<br>+ def s11_3Ext : Operand<i32> { let ParserMatchClass = s11_3ExtOperand;<br>+ let DecoderMethod = "s11_3ImmDecoder"; }<br>+ def s10Ext : Operand<i32> { let ParserMatchClass = s10ExtOperand;<br>+ let DecoderMethod = "s10ImmDecoder"; }<br>+ def s9Ext : Operand<i32> { let ParserMatchClass = s9ExtOperand;<br>+ let DecoderMethod = "s90ImmDecoder"; }<br>+ def s8Ext : Operand<i32> { let ParserMatchClass = s8ExtOperand;<br>+ let DecoderMethod = "s8ImmDecoder"; }<br>+ def s7Ext : Operand<i32> { let ParserMatchClass = s7ExtOperand; }<br>+ def s6Ext : Operand<i32> { let ParserMatchClass = s6ExtOperand;<br>+ let DecoderMethod = "s6_0ImmDecoder"; }<br>+ def u6Ext : Operand<i32> { let ParserMatchClass = u6ExtOperand; }<br>+ def u7Ext : Operand<i32> { let ParserMatchClass = u7ExtOperand; }<br>+ def u8Ext : Operand<i32> { let ParserMatchClass = u8ExtOperand; }<br>+ def u9Ext : Operand<i32> { let ParserMatchClass = u9ExtOperand; }<br>+ def u10Ext : Operand<i32> { let ParserMatchClass = u10ExtOperand; }<br>+ def u6_0Ext : Operand<i32> { let ParserMatchClass = u6_0ExtOperand; }<br>+ def u6_1Ext : Operand<i32> { let ParserMatchClass = u6_1ExtOperand; }<br>+ def u6_2Ext : Operand<i32> { let ParserMatchClass = u6_2ExtOperand; }<br>+ def u6_3Ext : Operand<i32> { let ParserMatchClass = u6_3ExtOperand; }<br>+ def u32MustExt : Operand<i32> { let ParserMatchClass = u32MustExtOperand; }<br> }<br><br><br>@@ -492,21 +577,21 @@ let PrintMethod = "printGlobalOperand" i<br> let PrintMethod = "printJumpTable" in<br> def jumptablebase : Operand<i32>;<br><br>-def brtarget : Operand<OtherVT>;<br>+def brtarget : Operand<OtherVT> {<br>+ let DecoderMethod = "brtargetDecoder";<br>+ let PrintMethod = "printBrtarget";<br>+}<br> def brtargetExt : Operand<OtherVT> {<br>- let PrintMethod = "printExtBrtarget";<br>+ let DecoderMethod = "brtargetDecoder";<br>+ let PrintMethod = "printBrtarget";<br>+}<br>+def calltarget : Operand<i32> {<br>+ let DecoderMethod = "brtargetDecoder";<br>+ let PrintMethod = "printBrtarget";<br> }<br>-def calltarget : Operand<i32>;<br><br> def bblabel : Operand<i32>;<br>-def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;<br>-<br>-def symbolHi32 : Operand<i32> {<br>- let PrintMethod = "printSymbolHi";<br>-}<br>-def symbolLo32 : Operand<i32> {<br>- let PrintMethod = "printSymbolLo";<br>-}<br>+def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf, [], "BasicBlockSDNode">;<br><br> // Return true if for a 32 to 64-bit sign-extended load.<br> def is_sext_i32 : PatLeaf<(i64 DoubleRegs:$src1), [{<br><br>Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td (original)<br>+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td Sun Nov 8 22:07:48 2015<br>@@ -137,20 +137,21 @@ let Namespace = "Hexagon" in {<br> def LC1 : Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>;<br> def P3_0 : Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>,<br> DwarfRegNum<[71]>;<br>- def C6 : Rc<6, "c6", [], [M0]>, DwarfRegNum<[72]>;<br>- def C7 : Rc<7, "c7", [], [M1]>, DwarfRegNum<[73]>;<br>+ def C5 : Rc<5, "c5", ["c5"]>, DwarfRegNum<[72]>; // future use<br>+ def C6 : Rc<6, "c6", [], [M0]>, DwarfRegNum<[73]>;<br>+ def C7 : Rc<7, "c7", [], [M1]>, DwarfRegNum<[74]>;<br><br>- def USR : Rc<8, "usr", ["c8"]>, DwarfRegNum<[74]> {<br>+ def USR : Rc<8, "usr", ["c8"]>, DwarfRegNum<[75]> {<br> let SubRegIndices = [subreg_overflow];<br> let SubRegs = [USR_OVF];<br> }<br>- def PC : Rc<9, "pc">, DwarfRegNum<[75]>;<br>- def UGP : Rc<10, "ugp", ["c10"]>, DwarfRegNum<[76]>;<br>- def GP : Rc<11, "gp">, DwarfRegNum<[77]>;<br>- def CS0 : Rc<12, "cs0", ["c12"]>, DwarfRegNum<[78]>;<br>- def CS1 : Rc<13, "cs1", ["c13"]>, DwarfRegNum<[79]>;<br>- def UPCL : Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[80]>;<br>- def UPCH : Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[81]>;<br>+ def PC : Rc<9, "pc">, DwarfRegNum<[76]>;<br>+ def UGP : Rc<10, "ugp", ["c10"]>, DwarfRegNum<[77]>;<br>+ def GP : Rc<11, "gp">, DwarfRegNum<[78]>;<br>+ def CS0 : Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>;<br>+ def CS1 : Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>;<br>+ def UPCL : Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>;<br>+ def UPCH : Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>;<br> }<br><br> // Control registers pairs.<br><br>Modified: llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt (original)<br>+++ llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt Sun Nov 8 22:07:48 2015<br>@@ -16,7 +16,7 @@<br> ;===------------------------------------------------------------------------===;<br><br> [common]<br>-subdirectories = Disassembler MCTargetDesc TargetInfo<br>+subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo<br><br> [component_0]<br> type = TargetGroup<br><br>Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt (original)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt Sun Nov 8 22:07:48 2015<br>@@ -3,10 +3,12 @@ add_llvm_library(LLVMHexagonDesc<br> HexagonELFObjectWriter.cpp<br> HexagonInstPrinter.cpp<br> HexagonMCAsmInfo.cpp<br>+ HexagonMCChecker.cpp<br> HexagonMCCodeEmitter.cpp<br> HexagonMCCompound.cpp<br> HexagonMCDuplexInfo.cpp<br> HexagonMCELFStreamer.cpp<br>+ HexagonMCExpr.cpp<br> HexagonMCInstrInfo.cpp<br> HexagonMCShuffler.cpp<br> HexagonMCTargetDesc.cpp<br><br>Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h (original)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h Sun Nov 8 22:07:48 2015<br>@@ -44,6 +44,25 @@ namespace HexagonII {<br> TypeMEMOP = 9,<br> TypeNV = 10,<br> TypeDUPLEX = 11,<br>+ TypeCOMPOUND = 12,<br>+ TypeCVI_FIRST = 13,<br>+ TypeCVI_VA = TypeCVI_FIRST,<br>+ TypeCVI_VA_DV = 14,<br>+ TypeCVI_VX = 15,<br>+ TypeCVI_VX_DV = 16,<br>+ TypeCVI_VP = 17,<br>+ TypeCVI_VP_VS = 18,<br>+ TypeCVI_VS = 19,<br>+ TypeCVI_VINLANESAT= 20,<br>+ TypeCVI_VM_LD = 21,<br>+ TypeCVI_VM_TMP_LD = 22,<br>+ TypeCVI_VM_CUR_LD = 23,<br>+ TypeCVI_VM_VP_LDU = 24,<br>+ TypeCVI_VM_ST = 25,<br>+ TypeCVI_VM_NEW_ST = 26,<br>+ TypeCVI_VM_STU = 27,<br>+ TypeCVI_HIST = 28,<br>+ TypeCVI_LAST = TypeCVI_HIST,<br> TypePREFIX = 30, // Such as extenders.<br> TypeENDLOOP = 31 // Such as end of a HW loop.<br> };<br>@@ -164,7 +183,15 @@ namespace HexagonII {<br><br> // Floating-point instructions.<br> FPPos = 48,<br>- FPMask = 0x1<br>+ FPMask = 0x1,<br>+<br>+ // New-Value producer-2 instructions.<br>+ hasNewValuePos2 = 50,<br>+ hasNewValueMask2 = 0x1,<br>+<br>+ // Which operand consumes or produces a new value.<br>+ NewValueOpPos2 = 51,<br>+ NewValueOpMask2 = 0x7<br> };<br><br> // *** The code above must match HexagonInstrFormat*.td *** //<br>@@ -219,6 +246,26 @@ namespace HexagonII {<br> INST_PARSE_EXTENDER = 0x00000000<br> };<br><br>+ enum InstIClassBits {<br>+ INST_ICLASS_MASK = 0xf0000000,<br>+ INST_ICLASS_EXTENDER = 0x00000000,<br>+ INST_ICLASS_J_1 = 0x10000000,<br>+ INST_ICLASS_J_2 = 0x20000000,<br>+ INST_ICLASS_LD_ST_1 = 0x30000000,<br>+ INST_ICLASS_LD_ST_2 = 0x40000000,<br>+ INST_ICLASS_J_3 = 0x50000000,<br>+ INST_ICLASS_CR = 0x60000000,<br>+ INST_ICLASS_ALU32_1 = 0x70000000,<br>+ INST_ICLASS_XTYPE_1 = 0x80000000,<br>+ INST_ICLASS_LD = 0x90000000,<br>+ INST_ICLASS_ST = 0xa0000000,<br>+ INST_ICLASS_ALU32_2 = 0xb0000000,<br>+ INST_ICLASS_XTYPE_2 = 0xc0000000,<br>+ INST_ICLASS_XTYPE_3 = 0xd0000000,<br>+ INST_ICLASS_XTYPE_4 = 0xe0000000,<br>+ INST_ICLASS_ALU32_3 = 0xf0000000<br>+ };<br>+<br> } // End namespace HexagonII.<br><br> } // End namespace llvm.<br><br>Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp (original)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp Sun Nov 8 22:07:48 2015<br>@@ -12,13 +12,13 @@<br> //===----------------------------------------------------------------------===//<br><br> #include "HexagonAsmPrinter.h"<br>-#include "Hexagon.h"<br> #include "HexagonInstPrinter.h"<br>+#include "MCTargetDesc/HexagonBaseInfo.h"<br> #include "MCTargetDesc/HexagonMCInstrInfo.h"<br>-#include "llvm/ADT/StringExtras.h"<br> #include "llvm/MC/MCAsmInfo.h"<br> #include "llvm/MC/MCExpr.h"<br> #include "llvm/MC/MCInst.h"<br>+#include "llvm/Support/Debug.h"<br> #include "llvm/Support/raw_ostream.h"<br><br> using namespace llvm;<br>@@ -28,63 +28,33 @@ using namespace llvm;<br> #define GET_INSTRUCTION_NAME<br> #include "HexagonGenAsmWriter.inc"<br><br>-// Return the minimum value that a constant extendable operand can have<br>-// without being extended.<br>-static int getMinValue(uint64_t TSFlags) {<br>- unsigned isSigned =<br>- (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;<br>- unsigned bits =<br>- (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;<br>-<br>- if (isSigned)<br>- return -1U << (bits - 1);<br>-<br>- return 0;<br>-}<br>-<br>-// Return the maximum value that a constant extendable operand can have<br>-// without being extended.<br>-static int getMaxValue(uint64_t TSFlags) {<br>- unsigned isSigned =<br>- (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;<br>- unsigned bits =<br>- (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;<br>-<br>- if (isSigned)<br>- return ~(-1U << (bits - 1));<br>-<br>- return ~(-1U << bits);<br>-}<br>-<br>-// Return true if the instruction must be extended.<br>-static bool isExtended(uint64_t TSFlags) {<br>- return (TSFlags >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;<br>-}<br>-<br>-// Currently just used in an assert statement<br>-static bool isExtendable(uint64_t TSFlags) LLVM_ATTRIBUTE_UNUSED;<br>-// Return true if the instruction may be extended based on the operand value.<br>-static bool isExtendable(uint64_t TSFlags) {<br>- return (TSFlags >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;<br>+HexagonInstPrinter::HexagonInstPrinter(MCAsmInfo const &MAI,<br>+ MCInstrInfo const &MII,<br>+ MCRegisterInfo const &MRI)<br>+ : MCInstPrinter(MAI, MII, MRI), MII(MII), HasExtender(false) {<br> }<br><br> StringRef HexagonInstPrinter::getOpcodeName(unsigned Opcode) const {<br> return MII.getName(Opcode);<br> }<br><br>-void HexagonInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {<br>- OS << getRegisterName(RegNo);<br>+void HexagonInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {<br>+ O << getRegName(RegNo);<br>+}<br>+<br>+StringRef HexagonInstPrinter::getRegName(unsigned RegNo) const {<br>+ return getRegisterName(RegNo);<br> }<br><br> void HexagonInstPrinter::setExtender(MCInst const &MCI) {<br> HasExtender = HexagonMCInstrInfo::isImmext(MCI);<br> }<br><br>-void HexagonInstPrinter::printInst(MCInst const *MI, raw_ostream &OS,<br>- StringRef Annot,<br>- MCSubtargetInfo const &STI) {<br>+void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,<br>+ StringRef Annot, const MCSubtargetInfo &STI) {<br> assert(HexagonMCInstrInfo::isBundle(*MI));<br> assert(HexagonMCInstrInfo::bundleSize(*MI) <= HEXAGON_PACKET_SIZE);<br>+ assert(HexagonMCInstrInfo::bundleSize(*MI) > 0);<br> HasExtender = false;<br> for (auto const &I : HexagonMCInstrInfo::bundleInstructions(*MI)) {<br> MCInst const &MCI = *I.getInst();<br>@@ -116,173 +86,148 @@ void HexagonInstPrinter::printInst(MCIns<br> }<br> }<br><br>-void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,<br>+void HexagonInstPrinter::printOperand(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const {<br>- const MCOperand& MO = MI->getOperand(OpNo);<br>-<br>+ if (HexagonMCInstrInfo::getExtendableOp(MII, *MI) == OpNo &&<br>+ (HasExtender || HexagonMCInstrInfo::isConstExtended(MII, *MI)))<br>+ O << "#";<br>+ MCOperand const &MO = MI->getOperand(OpNo);<br> if (MO.isReg()) {<br>- printRegName(O, MO.getReg());<br>- } else if(MO.isExpr()) {<br>- MO.getExpr()->print(O, &MAI);<br>- } else if(MO.isImm()) {<br>- printImmOperand(MI, OpNo, O);<br>+ O << getRegisterName(MO.getReg());<br>+ } else if (MO.isExpr()) {<br>+ int64_t Value;<br>+ if (MO.getExpr()->evaluateAsAbsolute(Value))<br>+ O << formatImm(Value);<br>+ else<br>+ O << *MO.getExpr();<br> } else {<br> llvm_unreachable("Unknown operand");<br> }<br> }<br><br>-void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo,<br>+void HexagonInstPrinter::printExtOperand(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const {<br>- const MCOperand& MO = MI->getOperand(OpNo);<br>-<br>- if(MO.isExpr()) {<br>- MO.getExpr()->print(O, &MAI);<br>- } else if(MO.isImm()) {<br>- O << MI->getOperand(OpNo).getImm();<br>- } else {<br>- llvm_unreachable("Unknown operand");<br>- }<br>-}<br>-<br>-void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,<br>- raw_ostream &O) const {<br>- const MCOperand &MO = MI->getOperand(OpNo);<br>- const MCInstrDesc &MII = getMII().get(MI->getOpcode());<br>-<br>- assert((isExtendable(MII.TSFlags) || isExtended(MII.TSFlags)) &&<br>- "Expecting an extendable operand");<br>-<br>- if (MO.isExpr() || isExtended(MII.TSFlags)) {<br>- O << "#";<br>- } else if (MO.isImm()) {<br>- int ImmValue = MO.getImm();<br>- if (ImmValue < getMinValue(MII.TSFlags) ||<br>- ImmValue > getMaxValue(MII.TSFlags))<br>- O << "#";<br>- }<br> printOperand(MI, OpNo, O);<br> }<br><br>-void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI,<br>- unsigned OpNo, raw_ostream &O) const {<br>+void HexagonInstPrinter::printUnsignedImmOperand(MCInst const *MI,<br>+ unsigned OpNo,<br>+ raw_ostream &O) const {<br> O << MI->getOperand(OpNo).getImm();<br> }<br><br>-void HexagonInstPrinter::printNegImmOperand(const MCInst *MI, unsigned OpNo,<br>+void HexagonInstPrinter::printNegImmOperand(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const {<br> O << -MI->getOperand(OpNo).getImm();<br> }<br><br>-void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,<br>+void HexagonInstPrinter::printNOneImmOperand(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const {<br> O << -1;<br> }<br><br> void HexagonInstPrinter::prints3_6ImmOperand(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const {<br>- int64_t Imm = MI->getOperand(OpNo).getImm();<br>+ int64_t Imm;<br>+ bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);<br>+ Imm = SignExtend64<9>(Imm);<br>+ assert(Success); (void)Success;<br> assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO.");<br> O << formatImm(Imm/64);<br> }<br><br> void HexagonInstPrinter::prints3_7ImmOperand(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const {<br>- int64_t Imm = MI->getOperand(OpNo).getImm();<br>+ int64_t Imm;<br>+ bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);<br>+ Imm = SignExtend64<10>(Imm);<br>+ assert(Success); (void)Success;<br> assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO.");<br> O << formatImm(Imm/128);<br> }<br><br> void HexagonInstPrinter::prints4_6ImmOperand(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const {<br>- int64_t Imm = MI->getOperand(OpNo).getImm();<br>+ int64_t Imm;<br>+ bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);<br>+ Imm = SignExtend64<10>(Imm);<br>+ assert(Success); (void)Success;<br> assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO.");<br> O << formatImm(Imm/64);<br> }<br><br> void HexagonInstPrinter::prints4_7ImmOperand(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const {<br>- int64_t Imm = MI->getOperand(OpNo).getImm();<br>+ int64_t Imm;<br>+ bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);<br>+ Imm = SignExtend64<11>(Imm);<br>+ assert(Success); (void)Success;<br> assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO.");<br> O << formatImm(Imm/128);<br> }<br><br>-void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,<br>- raw_ostream &O) const {<br>- const MCOperand& MO0 = MI->getOperand(OpNo);<br>- const MCOperand& MO1 = MI->getOperand(OpNo + 1);<br>-<br>- printRegName(O, MO0.getReg());<br>- O << " + #" << MO1.getImm();<br>-}<br>-<br>-void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,<br>- raw_ostream &O) const {<br>- const MCOperand& MO0 = MI->getOperand(OpNo);<br>- const MCOperand& MO1 = MI->getOperand(OpNo + 1);<br>-<br>- printRegName(O, MO0.getReg());<br>- O << ", #" << MO1.getImm();<br>-}<br>-<br>-void HexagonInstPrinter::printGlobalOperand(const MCInst *MI, unsigned OpNo,<br>+void HexagonInstPrinter::printGlobalOperand(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const {<br>- assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");<br>-<br> printOperand(MI, OpNo, O);<br> }<br><br>-void HexagonInstPrinter::printJumpTable(const MCInst *MI, unsigned OpNo,<br>+void HexagonInstPrinter::printJumpTable(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const {<br> assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");<br><br> printOperand(MI, OpNo, O);<br> }<br><br>-void HexagonInstPrinter::printConstantPool(const MCInst *MI, unsigned OpNo,<br>+void HexagonInstPrinter::printConstantPool(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const {<br> assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");<br><br> printOperand(MI, OpNo, O);<br> }<br><br>-void HexagonInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,<br>+void HexagonInstPrinter::printBranchOperand(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const {<br> // Branches can take an immediate operand. This is used by the branch<br> // selection pass to print $+8, an eight byte displacement from the PC.<br> llvm_unreachable("Unknown branch operand.");<br> }<br><br>-void HexagonInstPrinter::printCallOperand(const MCInst *MI, unsigned OpNo,<br>- raw_ostream &O) const {<br>-}<br>+void HexagonInstPrinter::printCallOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const {}<br><br>-void HexagonInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,<br>- raw_ostream &O) const {<br>-}<br>+void HexagonInstPrinter::printAbsAddrOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const {}<br><br>-void HexagonInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,<br>- raw_ostream &O) const {<br>-}<br>+void HexagonInstPrinter::printPredicateOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const {}<br><br>-void HexagonInstPrinter::printSymbol(const MCInst *MI, unsigned OpNo,<br>+void HexagonInstPrinter::printSymbol(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O, bool hi) const {<br>- assert(MI->getOperand(OpNo).isImm() && "Unknown symbol operand");<br>+ MCOperand const &MO = MI->getOperand(OpNo);<br><br>- O << '#' << (hi ? "HI" : "LO") << "(#";<br>- printOperand(MI, OpNo, O);<br>+ O << '#' << (hi ? "HI" : "LO") << '(';<br>+ if (MO.isImm()) {<br>+ O << '#';<br>+ printOperand(MI, OpNo, O);<br>+ } else {<br>+ printOperand(MI, OpNo, O);<br>+ assert("Unknown symbol operand");<br>+ }<br> O << ')';<br> }<br><br>-void HexagonInstPrinter::printExtBrtarget(const MCInst *MI, unsigned OpNo,<br>- raw_ostream &O) const {<br>- const MCOperand &MO = MI->getOperand(OpNo);<br>- const MCInstrDesc &MII = getMII().get(MI->getOpcode());<br>-<br>- assert((isExtendable(MII.TSFlags) || isExtended(MII.TSFlags)) &&<br>- "Expecting an extendable operand");<br>-<br>- if (MO.isExpr() || isExtended(MII.TSFlags)) {<br>- O << "##";<br>+void HexagonInstPrinter::printBrtarget(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const {<br>+ MCOperand const &MO = MI->getOperand(OpNo);<br>+ assert (MO.isExpr());<br>+ MCExpr const &Expr = *MO.getExpr();<br>+ int64_t Value;<br>+ if (Expr.evaluateAsAbsolute(Value))<br>+ O << format("0x%" PRIx64, Value);<br>+ else {<br>+ if (HasExtender || HexagonMCInstrInfo::isConstExtended(MII, *MI))<br>+ if (HexagonMCInstrInfo::getExtendableOp(MII, *MI) == OpNo)<br>+ O << "##";<br>+ O << Expr;<br> }<br>- printOperand(MI, OpNo, O);<br> }<br><br>Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h (original)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h Sun Nov 8 22:07:48 2015<br>@@ -7,7 +7,6 @@<br> //<br> //===----------------------------------------------------------------------===//<br> //<br>-// This class prints an Hexagon MCInst to a .s file.<br> //<br> //===----------------------------------------------------------------------===//<br><br>@@ -15,7 +14,6 @@<br> #define LLVM_LIB_TARGET_HEXAGON_INSTPRINTER_HEXAGONINSTPRINTER_H<br><br> #include "llvm/MC/MCInstPrinter.h"<br>-#include "llvm/MC/MCInstrInfo.h"<br><br> namespace llvm {<br> /// Prints bundles as a newline separated list of individual instructions<br>@@ -25,76 +23,69 @@ namespace llvm {<br> /// r0 = add(r1, r2)<br> /// r0 = #0 \v jump 0x0<br> /// :endloop0 :endloop1<br>- class HexagonInstPrinter : public MCInstPrinter {<br>- public:<br>- explicit HexagonInstPrinter(MCAsmInfo const &MAI,<br>- MCInstrInfo const &MII,<br>- MCRegisterInfo const &MRI)<br>- : MCInstPrinter(MAI, MII, MRI), MII(MII) {}<br>-<br>- void printInst(MCInst const *MI, raw_ostream &O, StringRef Annot,<br>- const MCSubtargetInfo &STI) override;<br>- virtual StringRef getOpcodeName(unsigned Opcode) const;<br>- void printInstruction(const MCInst *MI, raw_ostream &O);<br>- void printRegName(raw_ostream &OS, unsigned RegNo) const override;<br>- static const char *getRegisterName(unsigned RegNo);<br>-<br>- void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>- void printImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>- void printExtOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>- void printUnsignedImmOperand(const MCInst *MI, unsigned OpNo,<br>- raw_ostream &O) const;<br>- void printNegImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>- const;<br>- void printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>- const;<br>- void prints3_6ImmOperand(MCInst const *MI, unsigned OpNo,<br>- raw_ostream &O) const;<br>- void prints3_7ImmOperand(MCInst const *MI, unsigned OpNo,<br>- raw_ostream &O) const;<br>- void prints4_6ImmOperand(MCInst const *MI, unsigned OpNo,<br>- raw_ostream &O) const;<br>- void prints4_7ImmOperand(MCInst const *MI, unsigned OpNo,<br>+class HexagonInstPrinter : public MCInstPrinter {<br>+public:<br>+ explicit HexagonInstPrinter(MCAsmInfo const &MAI, MCInstrInfo const &MII,<br>+ MCRegisterInfo const &MRI);<br>+ void printInst(MCInst const *MI, raw_ostream &O, StringRef Annot,<br>+ const MCSubtargetInfo &STI) override;<br>+ virtual StringRef getOpcodeName(unsigned Opcode) const;<br>+ void printInstruction(MCInst const *MI, raw_ostream &O);<br>+<br>+ StringRef getRegName(unsigned RegNo) const;<br>+ static char const *getRegisterName(unsigned RegNo);<br>+ void printRegName(raw_ostream &O, unsigned RegNo) const override;<br>+<br>+ void printOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;<br>+ void printExtOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;<br>+ void printUnsignedImmOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const;<br>+ void printNegImmOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const;<br>+ void printNOneImmOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const;<br>+ void prints3_6ImmOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const;<br>+ void prints3_7ImmOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const;<br>+ void prints4_6ImmOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const;<br>+ void prints4_7ImmOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const;<br>+ void printBranchOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const;<br>+ void printCallOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;<br>+ void printAbsAddrOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const;<br>+ void printPredicateOperand(MCInst const *MI, unsigned OpNo,<br> raw_ostream &O) const;<br>- void printMEMriOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>- const;<br>- void printFrameIndexOperand(const MCInst *MI, unsigned OpNo,<br>- raw_ostream &O) const;<br>- void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>- const;<br>- void printCallOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>- const;<br>- void printAbsAddrOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>- const;<br>- void printPredicateOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>- const;<br>- void printGlobalOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>- const;<br>- void printJumpTable(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>- void printExtBrtarget(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>-<br>- void printConstantPool(const MCInst *MI, unsigned OpNo,<br>- raw_ostream &O) const;<br>-<br>- void printSymbolHi(const MCInst *MI, unsigned OpNo, raw_ostream &O) const<br>- { printSymbol(MI, OpNo, O, true); }<br>- void printSymbolLo(const MCInst *MI, unsigned OpNo, raw_ostream &O) const<br>- { printSymbol(MI, OpNo, O, false); }<br>-<br>- const MCInstrInfo &getMII() const {<br>- return MII;<br>- }<br>-<br>- protected:<br>- void printSymbol(const MCInst *MI, unsigned OpNo, raw_ostream &O, bool hi)<br>- const;<br>-<br>- private:<br>- const MCInstrInfo &MII;<br>-<br>- bool HasExtender;<br>- void setExtender(MCInst const &MCI);<br>- };<br>+ void printGlobalOperand(MCInst const *MI, unsigned OpNo,<br>+ raw_ostream &O) const;<br>+ void printJumpTable(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;<br>+ void printBrtarget(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;<br>+<br>+ void printConstantPool(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;<br>+<br>+ void printSymbolHi(MCInst const *MI, unsigned OpNo, raw_ostream &O) const {<br>+ printSymbol(MI, OpNo, O, true);<br>+ }<br>+ void printSymbolLo(MCInst const *MI, unsigned OpNo, raw_ostream &O) const {<br>+ printSymbol(MI, OpNo, O, false);<br>+ }<br>+<br>+ MCAsmInfo const &getMAI() const { return MAI; }<br>+ MCInstrInfo const &getMII() const { return MII; }<br>+<br>+protected:<br>+ void printSymbol(MCInst const *MI, unsigned OpNo, raw_ostream &O,<br>+ bool hi) const;<br>+<br>+private:<br>+ MCInstrInfo const &MII;<br>+<br>+ bool HasExtender;<br>+ void setExtender(MCInst const &MCI);<br>+};<br><br> } // end namespace llvm<br><br><br>Added: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp (added)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,580 @@<br>+//===----- HexagonMCChecker.cpp - Instruction bundle checking -------------===//<br>+//<br>+// The LLVM Compiler Infrastructure<br>+//<br>+// This file is distributed under the University of Illinois Open Source<br>+// License. See LICENSE.TXT for details.<br>+//<br>+//===----------------------------------------------------------------------===//<br>+//<br>+// This implements the checking of insns inside a bundle according to the<br>+// packet constraint rules of the Hexagon ISA.<br>+//<br>+//===----------------------------------------------------------------------===//<br>+<br>+#include "HexagonMCChecker.h"<br>+<br>+#include "HexagonBaseInfo.h"<br>+<br>+#include "llvm/ADT/SmallVector.h"<br>+#include "llvm/MC/MCInstrDesc.h"<br>+#include "llvm/MC/MCInstrInfo.h"<br>+#include "llvm/Support/CommandLine.h"<br>+#include "llvm/Support/Debug.h"<br>+#include "llvm/Support/raw_ostream.h"<br>+<br>+using namespace llvm;<br>+<br>+static cl::opt<bool> RelaxNVChecks("relax-nv-checks", cl::init(false),<br>+ cl::ZeroOrMore, cl::Hidden, cl::desc("Relax checks of new-value validity"));<br>+<br>+const HexagonMCChecker::PredSense<br>+ HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);<br>+<br>+void HexagonMCChecker::init() {<br>+ // Initialize read-only registers set.<br>+ ReadOnly.insert(Hexagon::PC);<br>+<br>+ // Figure out the loop-registers definitions.<br>+ if (HexagonMCInstrInfo::isInnerLoop(MCB)) {<br>+ Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?<br>+ Defs[Hexagon::LC0].insert(Unconditional);<br>+ }<br>+ if (HexagonMCInstrInfo::isOuterLoop(MCB)) {<br>+ Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?<br>+ Defs[Hexagon::LC1].insert(Unconditional);<br>+ }<br>+<br>+ if (HexagonMCInstrInfo::isBundle(MCB))<br>+ // Unfurl a bundle.<br>+ for (auto const&I : HexagonMCInstrInfo::bundleInstructions(MCB)) {<br>+ init(*I.getInst());<br>+ }<br>+ else<br>+ init(MCB);<br>+}<br>+<br>+void HexagonMCChecker::init(MCInst const& MCI) {<br>+ const MCInstrDesc& MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);<br>+ unsigned PredReg = Hexagon::NoRegister;<br>+ bool isTrue = false;<br>+<br>+ // Get used registers.<br>+ for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)<br>+ if (MCI.getOperand(i).isReg()) {<br>+ unsigned R = MCI.getOperand(i).getReg();<br>+<br>+ if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) {<br>+ // Note an used predicate register.<br>+ PredReg = R;<br>+ isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);<br>+<br>+ // Note use of new predicate register.<br>+ if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))<br>+ NewPreds.insert(PredReg);<br>+ }<br>+ else<br>+ // Note register use. Super-registers are not tracked directly,<br>+ // but their components.<br>+ for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());<br>+ SRI.isValid();<br>+ ++SRI)<br>+ if (!MCSubRegIterator(*SRI, &RI).isValid())<br>+ // Skip super-registers used indirectly.<br>+ Uses.insert(*SRI);<br>+ }<br>+<br>+ // Get implicit register definitions.<br>+ const uint16_t* ImpDefs = MCID.getImplicitDefs();<br>+ for (unsigned i = 0; i < MCID.getNumImplicitDefs(); ++i) {<br>+ unsigned R = ImpDefs[i];<br>+<br>+ if (Hexagon::R31 != R && MCID.isCall())<br>+ // Any register other than the LR and the PC are actually volatile ones<br>+ // as defined by the ABI, not modified implicitly by the call insn.<br>+ continue;<br>+ if (Hexagon::PC == R)<br>+ // Branches are the only insns that can change the PC,<br>+ // otherwise a read-only register.<br>+ continue;<br>+<br>+ if (Hexagon::USR_OVF == R)<br>+ // Many insns change the USR implicitly, but only one or another flag.<br>+ // The instruction table models the USR.OVF flag, which can be implicitly<br>+ // modified more than once, but cannot be modified in the same packet<br>+ // with an instruction that modifies is explicitly. Deal with such situ-<br>+ // ations individually.<br>+ SoftDefs.insert(R);<br>+ else if (isPredicateRegister(R) && HexagonMCInstrInfo::isPredicateLate(MCII, MCI))<br>+ // Include implicit late predicates.<br>+ LatePreds.insert(R);<br>+ else<br>+ Defs[R].insert(PredSense(PredReg, isTrue));<br>+ }<br>+<br>+ // Figure out explicit register definitions.<br>+ for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {<br>+ unsigned R = MCI.getOperand(i).getReg(),<br>+ S = Hexagon::NoRegister;<br>+<br>+ // Note register definitions, direct ones as well as indirect side-effects.<br>+ // Super-registers are not tracked directly, but their components.<br>+ for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());<br>+ SRI.isValid();<br>+ ++SRI) {<br>+ if (MCSubRegIterator(*SRI, &RI).isValid())<br>+ // Skip super-registers defined indirectly.<br>+ continue;<br>+<br>+ if (R == *SRI) {<br>+ if (S == R)<br>+ // Avoid scoring the defined register multiple times.<br>+ continue;<br>+ else<br>+ // Note that the defined register has already been scored.<br>+ S = R;<br>+ }<br>+<br>+ if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI)<br>+ // P3:0 is a special case, since multiple predicate register definitions<br>+ // in a packet is allowed as the equivalent of their logical "and".<br>+ // Only an explicit definition of P3:0 is noted as such; if a<br>+ // side-effect, then note as a soft definition.<br>+ SoftDefs.insert(*SRI);<br>+ else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) && isPredicateRegister(*SRI))<br>+ // Some insns produce predicates too late to be used in the same packet.<br>+ LatePreds.insert(*SRI);<br>+ else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_CUR_LD)<br>+ // Current loads should be used in the same packet.<br>+ // TODO: relies on the impossibility of a current and a temporary loads<br>+ // in the same packet.<br>+ CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue));<br>+ else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_TMP_LD)<br>+ // Temporary loads should be used in the same packet, but don't commit<br>+ // results, so it should be disregarded if another insn changes the same<br>+ // register.<br>+ // TODO: relies on the impossibility of a current and a temporary loads<br>+ // in the same packet.<br>+ TmpDefs.insert(*SRI);<br>+ else if (i <= 1 && llvm::HexagonMCInstrInfo::hasNewValue2(MCII, MCI) )<br>+ // vshuff(Vx, Vy, Rx) <- Vx(0) and Vy(1) are both source and<br>+ // destination registers with this instruction. same for vdeal(Vx,Vy,Rx)<br>+ Uses.insert(*SRI);<br>+ else<br>+ Defs[*SRI].insert(PredSense(PredReg, isTrue));<br>+ }<br>+ }<br>+<br>+ // Figure out register definitions that produce new values.<br>+ if (HexagonMCInstrInfo::hasNewValue(MCII, MCI)) {<br>+ unsigned R = HexagonMCInstrInfo::getNewValueOperand(MCII, MCI).getReg();<br>+<br>+ if (HexagonMCInstrInfo::isCompound(MCII, MCI))<br>+ compoundRegisterMap(R); // Compound insns have a limited register range.<br>+<br>+ for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());<br>+ SRI.isValid();<br>+ ++SRI)<br>+ if (!MCSubRegIterator(*SRI, &RI).isValid())<br>+ // No super-registers defined indirectly.<br>+ NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI),<br>+ HexagonMCInstrInfo::isFloat(MCII, MCI)));<br>+<br>+ // For fairly unique 2-dot-new producers, example:<br>+ // vdeal(V1, V9, R0) V1.new and V9.new can be used by consumers.<br>+ if (HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) {<br>+ unsigned R2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, MCI).getReg();<br>+<br>+ for(MCRegAliasIterator SRI(R2, &RI, !MCSubRegIterator(R2, &RI).isValid());<br>+ SRI.isValid();<br>+ ++SRI)<br>+ if (!MCSubRegIterator(*SRI, &RI).isValid())<br>+ NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI),<br>+ HexagonMCInstrInfo::isFloat(MCII, MCI)));<br>+ }<br>+ }<br>+<br>+ // Figure out definitions of new predicate registers.<br>+ if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))<br>+ for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)<br>+ if (MCI.getOperand(i).isReg()) {<br>+ unsigned P = MCI.getOperand(i).getReg();<br>+<br>+ if (isPredicateRegister(P))<br>+ NewPreds.insert(P);<br>+ }<br>+<br>+ // Figure out uses of new values.<br>+ if (HexagonMCInstrInfo::isNewValue(MCII, MCI)) {<br>+ unsigned N = HexagonMCInstrInfo::getNewValueOperand(MCII, MCI).getReg();<br>+<br>+ if (!MCSubRegIterator(N, &RI).isValid()) {<br>+ // Super-registers cannot use new values.<br>+ if (MCID.isBranch())<br>+ NewUses[N] = NewSense::Jmp(llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV);<br>+ else<br>+ NewUses[N] = NewSense::Use(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI));<br>+ }<br>+ }<br>+}<br>+<br>+HexagonMCChecker::HexagonMCChecker(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &mcb, MCInst &mcbdx,<br>+ MCRegisterInfo const &ri)<br>+ : MCB(mcb), MCBDX(mcbdx), RI(ri), MCII(MCII), STI(STI),<br>+ bLoadErrInfo(false) {<br>+ init();<br>+}<br>+<br>+bool HexagonMCChecker::check() {<br>+ bool chkB = checkBranches();<br>+ bool chkP = checkPredicates();<br>+ bool chkNV = checkNewValues();<br>+ bool chkR = checkRegisters();<br>+ bool chkS = checkSolo();<br>+ bool chkSh = checkShuffle();<br>+ bool chkSl = checkSlots();<br>+ bool chk = chkB && chkP && chkNV && chkR && chkS && chkSh && chkSl;<br>+<br>+ return chk;<br>+}<br>+<br>+bool HexagonMCChecker::checkSlots()<br>+<br>+{<br>+ unsigned slotsUsed = 0;<br>+ for (auto HMI: HexagonMCInstrInfo::bundleInstructions(MCBDX)) {<br>+ MCInst const& MCI = *HMI.getInst();<br>+ if (HexagonMCInstrInfo::isImmext(MCI))<br>+ continue;<br>+ if (HexagonMCInstrInfo::isDuplex(MCII, MCI))<br>+ slotsUsed += 2;<br>+ else<br>+ ++slotsUsed;<br>+ }<br>+<br>+ if (slotsUsed > HEXAGON_PACKET_SIZE) {<br>+ HexagonMCErrInfo errInfo;<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_NOSLOTS);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ return true;<br>+}<br>+<br>+// Check legal use of branches.<br>+bool HexagonMCChecker::checkBranches() {<br>+ HexagonMCErrInfo errInfo;<br>+ if (HexagonMCInstrInfo::isBundle(MCB)) {<br>+ bool hasConditional = false;<br>+ unsigned Branches = 0, Returns = 0, NewIndirectBranches = 0,<br>+ NewValueBranches = 0, Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE,<br>+ Unconditional = HEXAGON_PRESHUFFLE_PACKET_SIZE;<br>+<br>+ for (unsigned i = HexagonMCInstrInfo::bundleInstructionsOffset;<br>+ i < MCB.size(); ++i) {<br>+ MCInst const &MCI = *MCB.begin()[i].getInst();<br>+<br>+ if (HexagonMCInstrInfo::isImmext(MCI))<br>+ continue;<br>+ if (HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch() ||<br>+ HexagonMCInstrInfo::getDesc(MCII, MCI).isCall()) {<br>+ ++Branches;<br>+ if (HexagonMCInstrInfo::getDesc(MCII, MCI).isIndirectBranch() &&<br>+ HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))<br>+ ++NewIndirectBranches;<br>+ if (HexagonMCInstrInfo::isNewValue(MCII, MCI))<br>+ ++NewValueBranches;<br>+<br>+ if (HexagonMCInstrInfo::isPredicated(MCII, MCI) ||<br>+ HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) {<br>+ hasConditional = true;<br>+ Conditional = i; // Record the position of the conditional branch.<br>+ } else {<br>+ Unconditional = i; // Record the position of the unconditional branch.<br>+ }<br>+ }<br>+ if (HexagonMCInstrInfo::getDesc(MCII, MCI).isReturn() &&<br>+ HexagonMCInstrInfo::getDesc(MCII, MCI).mayLoad())<br>+ ++Returns;<br>+ }<br>+<br>+ if (Branches) // FIXME: should "Defs.count(Hexagon::PC)" be here too?<br>+ if (HexagonMCInstrInfo::isInnerLoop(MCB) ||<br>+ HexagonMCInstrInfo::isOuterLoop(MCB)) {<br>+ // Error out if there's any branch in a loop-end packet.<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_ENDLOOP, Hexagon::PC);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ if (Branches > 1)<br>+ if (!hasConditional || Conditional > Unconditional) {<br>+ // Error out if more than one unconditional branch or<br>+ // the conditional branch appears after the unconditional one.<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_BRANCHES);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ }<br>+<br>+ return true;<br>+}<br>+<br>+// Check legal use of predicate registers.<br>+bool HexagonMCChecker::checkPredicates() {<br>+ HexagonMCErrInfo errInfo;<br>+ // Check for proper use of new predicate registers.<br>+ for (const auto& I : NewPreds) {<br>+ unsigned P = I;<br>+<br>+ if (!Defs.count(P) || LatePreds.count(P)) {<br>+ // Error out if the new predicate register is not defined,<br>+ // or defined "late"<br>+ // (e.g., "{ if (p3.new)... ; p3 = sp1loop0(#r7:2, Rs) }").<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_NEWP, P);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ }<br>+<br>+ // Check for proper use of auto-anded of predicate registers.<br>+ for (const auto& I : LatePreds) {<br>+ unsigned P = I;<br>+<br>+ if (LatePreds.count(P) > 1 || Defs.count(P)) {<br>+ // Error out if predicate register defined "late" multiple times or<br>+ // defined late and regularly defined<br>+ // (e.g., "{ p3 = sp1loop0(...); p3 = cmp.eq(...) }".<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, P);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ }<br>+<br>+ return true;<br>+}<br>+<br>+// Check legal use of new values.<br>+bool HexagonMCChecker::checkNewValues() {<br>+ HexagonMCErrInfo errInfo;<br>+ memset(&errInfo, 0, sizeof(errInfo));<br>+ for (auto& I : NewUses) {<br>+ unsigned R = I.first;<br>+ NewSense &US = I.second;<br>+<br>+ if (!hasValidNewValueDef(US, NewDefs[R])) {<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_NEWV, R);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ }<br>+<br>+ return true;<br>+}<br>+<br>+// Check for legal register uses and definitions.<br>+bool HexagonMCChecker::checkRegisters() {<br>+ HexagonMCErrInfo errInfo;<br>+ // Check for proper register definitions.<br>+ for (const auto& I : Defs) {<br>+ unsigned R = I.first;<br>+<br>+ if (ReadOnly.count(R)) {<br>+ // Error out for definitions of read-only registers.<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_READONLY, R);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ if (isLoopRegister(R) && Defs.count(R) > 1 &&<br>+ (HexagonMCInstrInfo::isInnerLoop(MCB) ||<br>+ HexagonMCInstrInfo::isOuterLoop(MCB))) {<br>+ // Error out for definitions of loop registers at the end of a loop.<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_LOOP, R);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ if (SoftDefs.count(R)) {<br>+ // Error out for explicit changes to registers also weakly defined<br>+ // (e.g., "{ usr = r0; r0 = sfadd(...) }").<br>+ unsigned UsrR = Hexagon::USR; // Silence warning about mixed types in ?:.<br>+ unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, BadR);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ if (!isPredicateRegister(R) && Defs[R].size() > 1) {<br>+ // Check for multiple register definitions.<br>+ PredSet &PM = Defs[R];<br>+<br>+ // Check for multiple unconditional register definitions.<br>+ if (PM.count(Unconditional)) {<br>+ // Error out on an unconditional change when there are any other<br>+ // changes, conditional or not.<br>+ unsigned UsrR = Hexagon::USR;<br>+ unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, BadR);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ // Check for multiple conditional register definitions.<br>+ for (const auto& J : PM) {<br>+ PredSense P = J;<br>+<br>+ // Check for multiple uses of the same condition.<br>+ if (PM.count(P) > 1) {<br>+ // Error out on conditional changes based on the same predicate<br>+ // (e.g., "{ if (!p0) r0 =...; if (!p0) r0 =... }").<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, R);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ // Check for the use of the complementary condition.<br>+ P.second = !P.second;<br>+ if (PM.count(P) && PM.size() > 2) {<br>+ // Error out on conditional changes based on the same predicate<br>+ // multiple times<br>+ // (e.g., "{ if (p0) r0 =...; if (!p0) r0 =... }; if (!p0) r0 =... }").<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, R);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ }<br>+ }<br>+ }<br>+<br>+ // Check for use of current definitions.<br>+ for (const auto& I : CurDefs) {<br>+ unsigned R = I;<br>+<br>+ if (!Uses.count(R)) {<br>+ // Warn on an unused current definition.<br>+ errInfo.setWarning(HexagonMCErrInfo::CHECK_WARN_CURRENT, R);<br>+ addErrInfo(errInfo);<br>+ return true;<br>+ }<br>+ }<br>+<br>+ // Check for use of temporary definitions.<br>+ for (const auto& I : TmpDefs) {<br>+ unsigned R = I;<br>+<br>+ if (!Uses.count(R)) {<br>+ // special case for vhist<br>+ bool vHistFound = false;<br>+ for (auto const&HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {<br>+ if(llvm::HexagonMCInstrInfo::getType(MCII, *HMI.getInst()) == HexagonII::TypeCVI_HIST) {<br>+ vHistFound = true; // vhist() implicitly uses ALL REGxx.tmp<br>+ break;<br>+ }<br>+ }<br>+ // Warn on an unused temporary definition.<br>+ if (vHistFound == false) {<br>+ errInfo.setWarning(HexagonMCErrInfo::CHECK_WARN_TEMPORARY, R);<br>+ addErrInfo(errInfo);<br>+ return true;<br>+ }<br>+ }<br>+ }<br>+<br>+ return true;<br>+}<br>+<br>+// Check for legal use of solo insns.<br>+bool HexagonMCChecker::checkSolo() {<br>+ HexagonMCErrInfo errInfo;<br>+ if (HexagonMCInstrInfo::isBundle(MCB) &&<br>+ HexagonMCInstrInfo::bundleSize(MCB) > 1) {<br>+ for (auto const&I : HexagonMCInstrInfo::bundleInstructions(MCB)) {<br>+ if (llvm::HexagonMCInstrInfo::isSolo(MCII, *I.getInst())) {<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SOLO);<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ }<br>+ }<br>+<br>+ return true;<br>+}<br>+<br>+bool HexagonMCChecker::checkShuffle() {<br>+ HexagonMCErrInfo errInfo;<br>+ // Branch info is lost when duplexing. The unduplexed insns must be<br>+ // checked and only branch errors matter for this case.<br>+ HexagonMCShuffler MCS(MCII, STI, MCB);<br>+ if (!MCS.check()) {<br>+ if (MCS.getError() == HexagonShuffler::SHUFFLE_ERROR_BRANCHES) {<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SHUFFLE);<br>+ errInfo.setShuffleError(MCS.getError());<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ }<br>+ HexagonMCShuffler MCSDX(MCII, STI, MCBDX);<br>+ if (!MCSDX.check()) {<br>+ errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SHUFFLE);<br>+ errInfo.setShuffleError(MCSDX.getError());<br>+ addErrInfo(errInfo);<br>+ return false;<br>+ }<br>+ return true;<br>+}<br>+<br>+void HexagonMCChecker::compoundRegisterMap(unsigned& Register) {<br>+ switch (Register) {<br>+ default:<br>+ break;<br>+ case Hexagon::R15:<br>+ Register = Hexagon::R23;<br>+ break;<br>+ case Hexagon::R14:<br>+ Register = Hexagon::R22;<br>+ break;<br>+ case Hexagon::R13:<br>+ Register = Hexagon::R21;<br>+ break;<br>+ case Hexagon::R12:<br>+ Register = Hexagon::R20;<br>+ break;<br>+ case Hexagon::R11:<br>+ Register = Hexagon::R19;<br>+ break;<br>+ case Hexagon::R10:<br>+ Register = Hexagon::R18;<br>+ break;<br>+ case Hexagon::R9:<br>+ Register = Hexagon::R17;<br>+ break;<br>+ case Hexagon::R8:<br>+ Register = Hexagon::R16;<br>+ break;<br>+ }<br>+}<br>+<br>+bool HexagonMCChecker::hasValidNewValueDef(const NewSense &Use,<br>+ const NewSenseList &Defs) const {<br>+ bool Strict = !RelaxNVChecks;<br>+<br>+ for (unsigned i = 0, n = Defs.size(); i < n; ++i) {<br>+ const NewSense &Def = Defs[i];<br>+ // NVJ cannot use a new FP value [7.6.1]<br>+ if (Use.IsNVJ && (Def.IsFloat || Def.PredReg != 0))<br>+ continue;<br>+ // If the definition was not predicated, then it does not matter if<br>+ // the use is.<br>+ if (Def.PredReg == 0)<br>+ return true;<br>+ // With the strict checks, both the definition and the use must be<br>+ // predicated on the same register and condition.<br>+ if (Strict) {<br>+ if (Def.PredReg == Use.PredReg && Def.Cond == Use.Cond)<br>+ return true;<br>+ } else {<br>+ // With the relaxed checks, if the definition was predicated, the only<br>+ // detectable violation is if the use is predicated on the opposing<br>+ // condition, otherwise, it's ok.<br>+ if (Def.PredReg != Use.PredReg || Def.Cond == Use.Cond)<br>+ return true;<br>+ }<br>+ }<br>+ return false;<br>+}<br>+<br><br>Added: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h (added)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,218 @@<br>+//===----- HexagonMCChecker.h - Instruction bundle checking ---------------===//<br>+//<br>+// The LLVM Compiler Infrastructure<br>+//<br>+// This file is distributed under the University of Illinois Open Source<br>+// License. See LICENSE.TXT for details.<br>+//<br>+//===----------------------------------------------------------------------===//<br>+//<br>+// This implements the checking of insns inside a bundle according to the<br>+// packet constraint rules of the Hexagon ISA.<br>+//<br>+//===----------------------------------------------------------------------===//<br>+<br>+#ifndef HEXAGONMCCHECKER_H<br>+#define HEXAGONMCCHECKER_H<br>+<br>+#include <map><br>+#include <set><br>+#include <queue><br>+#include "MCTargetDesc/HexagonMCShuffler.h"<br>+<br>+using namespace llvm;<br>+<br>+namespace llvm {<br>+class MCOperandInfo;<br>+<br>+typedef struct {<br>+ unsigned Error, Warning, ShuffleError;<br>+ unsigned Register;<br>+} ErrInfo_T;<br>+<br>+class HexagonMCErrInfo {<br>+public:<br>+ enum {<br>+ CHECK_SUCCESS = 0,<br>+ // Errors.<br>+ CHECK_ERROR_BRANCHES = 0x00001,<br>+ CHECK_ERROR_NEWP = 0x00002,<br>+ CHECK_ERROR_NEWV = 0x00004,<br>+ CHECK_ERROR_REGISTERS = 0x00008,<br>+ CHECK_ERROR_READONLY = 0x00010,<br>+ CHECK_ERROR_LOOP = 0x00020,<br>+ CHECK_ERROR_ENDLOOP = 0x00040,<br>+ CHECK_ERROR_SOLO = 0x00080,<br>+ CHECK_ERROR_SHUFFLE = 0x00100,<br>+ CHECK_ERROR_NOSLOTS = 0x00200,<br>+ CHECK_ERROR_UNKNOWN = 0x00400,<br>+ // Warnings.<br>+ CHECK_WARN_CURRENT = 0x10000,<br>+ CHECK_WARN_TEMPORARY = 0x20000<br>+ };<br>+ ErrInfo_T s;<br>+<br>+ void reset() {<br>+ s.Error = CHECK_SUCCESS;<br>+ s.Warning = CHECK_SUCCESS;<br>+ s.ShuffleError = HexagonShuffler::SHUFFLE_SUCCESS;<br>+ s.Register = Hexagon::NoRegister;<br>+ };<br>+ HexagonMCErrInfo() {<br>+ reset();<br>+ };<br>+<br>+ void setError(unsigned e, unsigned r = Hexagon::NoRegister)<br>+ { s.Error = e; s.Register = r; };<br>+ void setWarning(unsigned w, unsigned r = Hexagon::NoRegister)<br>+ { s.Warning = w; s.Register = r; };<br>+ void setShuffleError(unsigned e) { s.ShuffleError = e; };<br>+};<br>+<br>+/// Check for a valid bundle.<br>+class HexagonMCChecker {<br>+ /// Insn bundle.<br>+ MCInst& MCB;<br>+ MCInst& MCBDX;<br>+ const MCRegisterInfo& RI;<br>+ MCInstrInfo const &MCII;<br>+ MCSubtargetInfo const &STI;<br>+ bool bLoadErrInfo;<br>+<br>+ /// Set of definitions: register #, if predicated, if predicated true.<br>+ typedef std::pair<unsigned, bool> PredSense;<br>+ static const PredSense Unconditional;<br>+ typedef std::multiset<PredSense> PredSet;<br>+ typedef std::multiset<PredSense>::iterator PredSetIterator;<br>+<br>+ typedef llvm::DenseMap<unsigned, PredSet>::iterator DefsIterator;<br>+ llvm::DenseMap<unsigned, PredSet> Defs;<br>+<br>+ /// Information about how a new-value register is defined or used:<br>+ /// PredReg = predicate register, 0 if use/def not predicated,<br>+ /// Cond = true/false for if(PredReg)/if(!PredReg) respectively,<br>+ /// IsFloat = true if definition produces a floating point value<br>+ /// (not valid for uses),<br>+ /// IsNVJ = true if the use is a new-value branch (not valid for<br>+ /// definitions).<br>+ struct NewSense {<br>+ unsigned PredReg;<br>+ bool IsFloat, IsNVJ, Cond;<br>+ // The special-case "constructors":<br>+ static NewSense Jmp(bool isNVJ) {<br>+ NewSense NS = { /*PredReg=*/ 0, /*IsFloat=*/ false, /*IsNVJ=*/ isNVJ,<br>+ /*Cond=*/ false };<br>+ return NS;<br>+ }<br>+ static NewSense Use(unsigned PR, bool True) {<br>+ NewSense NS = { /*PredReg=*/ PR, /*IsFloat=*/ false, /*IsNVJ=*/ false,<br>+ /*Cond=*/ True };<br>+ return NS;<br>+ }<br>+ static NewSense Def(unsigned PR, bool True, bool Float) {<br>+ NewSense NS = { /*PredReg=*/ PR, /*IsFloat=*/ Float, /*IsNVJ=*/ false,<br>+ /*Cond=*/ True };<br>+ return NS;<br>+ }<br>+ };<br>+ /// Set of definitions that produce new register:<br>+ typedef llvm::SmallVector<NewSense,2> NewSenseList;<br>+ typedef llvm::DenseMap<unsigned, NewSenseList>::iterator NewDefsIterator;<br>+ llvm::DenseMap<unsigned, NewSenseList> NewDefs;<br>+<br>+ /// Set of weak definitions whose clashes should be enforced selectively.<br>+ typedef std::set<unsigned>::iterator SoftDefsIterator;<br>+ std::set<unsigned> SoftDefs;<br>+<br>+ /// Set of current definitions committed to the register file.<br>+ typedef std::set<unsigned>::iterator CurDefsIterator;<br>+ std::set<unsigned> CurDefs;<br>+<br>+ /// Set of temporary definitions not committed to the register file.<br>+ typedef std::set<unsigned>::iterator TmpDefsIterator;<br>+ std::set<unsigned> TmpDefs;<br>+<br>+ /// Set of new predicates used.<br>+ typedef std::set<unsigned>::iterator NewPredsIterator;<br>+ std::set<unsigned> NewPreds;<br>+<br>+ /// Set of predicates defined late.<br>+ typedef std::multiset<unsigned>::iterator LatePredsIterator;<br>+ std::multiset<unsigned> LatePreds;<br>+<br>+ /// Set of uses.<br>+ typedef std::set<unsigned>::iterator UsesIterator;<br>+ std::set<unsigned> Uses;<br>+<br>+ /// Set of new values used: new register, if new-value jump.<br>+ typedef llvm::DenseMap<unsigned, NewSense>::iterator NewUsesIterator;<br>+ llvm::DenseMap<unsigned, NewSense> NewUses;<br>+<br>+ /// Pre-defined set of read-only registers.<br>+ typedef std::set<unsigned>::iterator ReadOnlyIterator;<br>+ std::set<unsigned> ReadOnly;<br>+<br>+ std::queue<ErrInfo_T> ErrInfoQ;<br>+ HexagonMCErrInfo CrntErrInfo;<br>+<br>+ void getErrInfo() {<br>+ if (bLoadErrInfo == true) {<br>+ if (ErrInfoQ.empty()) {<br>+ CrntErrInfo.reset();<br>+ } else {<br>+ CrntErrInfo.s = ErrInfoQ.front();<br>+ ErrInfoQ.pop();<br>+ }<br>+ }<br>+ bLoadErrInfo = false;<br>+ }<br>+<br>+ void init();<br>+ void init(MCInst const&);<br>+<br>+ // Checks performed.<br>+ bool checkBranches();<br>+ bool checkPredicates();<br>+ bool checkNewValues();<br>+ bool checkRegisters();<br>+ bool checkSolo();<br>+ bool checkShuffle();<br>+ bool checkSlots();<br>+<br>+ static void compoundRegisterMap(unsigned&);<br>+<br>+ bool isPredicateRegister(unsigned R) const {<br>+ return (Hexagon::P0 == R || Hexagon::P1 == R ||<br>+ Hexagon::P2 == R || Hexagon::P3 == R);<br>+ };<br>+ bool isLoopRegister(unsigned R) const {<br>+ return (Hexagon::SA0 == R || Hexagon::LC0 == R ||<br>+ Hexagon::SA1 == R || Hexagon::LC1 == R);<br>+ };<br>+<br>+ bool hasValidNewValueDef(const NewSense &Use,<br>+ const NewSenseList &Defs) const;<br>+<br>+ public:<br>+ explicit HexagonMCChecker(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst& mcb, MCInst &mcbdx,<br>+ const MCRegisterInfo& ri);<br>+<br>+ bool check();<br>+<br>+ /// add a new error/warning<br>+ void addErrInfo(HexagonMCErrInfo &err) { ErrInfoQ.push(err.s); };<br>+<br>+ /// Return the error code for the last operation in the insn bundle.<br>+ unsigned getError() { getErrInfo(); return CrntErrInfo.s.Error; };<br>+ unsigned getWarning() { getErrInfo(); return CrntErrInfo.s.Warning; };<br>+ unsigned getShuffleError() { getErrInfo(); return CrntErrInfo.s.ShuffleError; };<br>+ unsigned getErrRegister() { getErrInfo(); return CrntErrInfo.s.Register; };<br>+ bool getNextErrInfo() {<br>+ bLoadErrInfo = true;<br>+ return (ErrInfoQ.empty()) ? false : (getErrInfo(), true);<br>+ }<br>+};<br>+<br>+}<br>+<br>+#endif // HEXAGONMCCHECKER_H<br><br>Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp (original)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp Sun Nov 8 22:07:48 2015<br>@@ -195,15 +195,13 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> // Special case this one from Group L2.<br> // Rd = memw(r29+#u5:2)<br> if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {<br>- if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &&<br>- MCI.getOperand(2).isImm() &&<br>- isShiftedUInt<5, 2>(MCI.getOperand(2).getImm())) {<br>+ if (HexagonMCInstrInfo::isIntReg(SrcReg) &&<br>+ Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {<br> return HexagonII::HSIG_L2;<br> }<br> // Rd = memw(Rs+#u4:2)<br> if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&<br>- (MCI.getOperand(2).isImm() &&<br>- isShiftedUInt<4, 2>(MCI.getOperand(2).getImm()))) {<br>+ inRange<4, 2>(MCI, 2)) {<br> return HexagonII::HSIG_L1;<br> }<br> }<br>@@ -214,7 +212,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> SrcReg = MCI.getOperand(1).getReg();<br> if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&<br> HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&<br>- MCI.getOperand(2).isImm() && isUInt<4>(MCI.getOperand(2).getImm())) {<br>+ inRange<4>(MCI, 2)) {<br> return HexagonII::HSIG_L1;<br> }<br> break;<br>@@ -235,8 +233,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> SrcReg = MCI.getOperand(1).getReg();<br> if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&<br> HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&<br>- MCI.getOperand(2).isImm() &&<br>- isShiftedUInt<3, 1>(MCI.getOperand(2).getImm())) {<br>+ inRange<3, 1>(MCI, 2)) {<br> return HexagonII::HSIG_L2;<br> }<br> break;<br>@@ -246,7 +243,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> SrcReg = MCI.getOperand(1).getReg();<br> if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&<br> HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&<br>- MCI.getOperand(2).isImm() && isUInt<3>(MCI.getOperand(2).getImm())) {<br>+ inRange<3>(MCI, 2)) {<br> return HexagonII::HSIG_L2;<br> }<br> break;<br>@@ -256,8 +253,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> SrcReg = MCI.getOperand(1).getReg();<br> if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) &&<br> HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &&<br>- MCI.getOperand(2).isImm() &&<br>- isShiftedUInt<5, 3>(MCI.getOperand(2).getImm())) {<br>+ inRange<5, 3>(MCI, 2)) {<br> return HexagonII::HSIG_L2;<br> }<br> break;<br>@@ -326,15 +322,13 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> Src2Reg = MCI.getOperand(2).getReg();<br> if (HexagonMCInstrInfo::isIntReg(Src1Reg) &&<br> HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&<br>- Hexagon::R29 == Src1Reg && MCI.getOperand(1).isImm() &&<br>- isShiftedUInt<5, 2>(MCI.getOperand(1).getImm())) {<br>+ Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) {<br> return HexagonII::HSIG_S2;<br> }<br> // memw(Rs+#u4:2) = Rt<br> if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&<br> HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&<br>- MCI.getOperand(1).isImm() &&<br>- isShiftedUInt<4, 2>(MCI.getOperand(1).getImm())) {<br>+ inRange<4, 2>(MCI, 1)) {<br> return HexagonII::HSIG_S1;<br> }<br> break;<br>@@ -344,7 +338,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> Src2Reg = MCI.getOperand(2).getReg();<br> if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&<br> HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&<br>- MCI.getOperand(1).isImm() && isUInt<4>(MCI.getOperand(1).getImm())) {<br>+ inRange<4>(MCI, 1)) {<br> return HexagonII::HSIG_S1;<br> }<br> break;<br>@@ -363,8 +357,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> Src2Reg = MCI.getOperand(2).getReg();<br> if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&<br> HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&<br>- MCI.getOperand(1).isImm() &&<br>- isShiftedUInt<3, 1>(MCI.getOperand(1).getImm())) {<br>+ inRange<3, 1>(MCI, 1)) {<br> return HexagonII::HSIG_S2;<br> }<br> break;<br>@@ -374,8 +367,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> Src2Reg = MCI.getOperand(2).getReg();<br> if (HexagonMCInstrInfo::isDblRegForSubInst(Src2Reg) &&<br> HexagonMCInstrInfo::isIntReg(Src1Reg) && Hexagon::R29 == Src1Reg &&<br>- MCI.getOperand(1).isImm() &&<br>- isShiftedInt<6, 3>(MCI.getOperand(1).getImm())) {<br>+ inSRange<6, 3>(MCI, 1)) {<br> return HexagonII::HSIG_S2;<br> }<br> break;<br>@@ -383,9 +375,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> // memw(Rs+#u4:2) = #U1<br> Src1Reg = MCI.getOperand(0).getReg();<br> if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&<br>- MCI.getOperand(1).isImm() &&<br>- isShiftedUInt<4, 2>(MCI.getOperand(1).getImm()) &&<br>- MCI.getOperand(2).isImm() && isUInt<1>(MCI.getOperand(2).getImm())) {<br>+ inRange<4, 2>(MCI, 1) && inRange<1>(MCI, 2)) {<br> return HexagonII::HSIG_S2;<br> }<br> break;<br>@@ -393,16 +383,13 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> // memb(Rs+#u4) = #U1<br> Src1Reg = MCI.getOperand(0).getReg();<br> if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&<br>- MCI.getOperand(1).isImm() && isUInt<4>(MCI.getOperand(1).getImm()) &&<br>- MCI.getOperand(2).isImm() && isUInt<1>(MCI.getOperand(2).getImm())) {<br>+ inRange<4>(MCI, 1) && inRange<1>(MCI, 2)) {<br> return HexagonII::HSIG_S2;<br> }<br> break;<br> case Hexagon::S2_allocframe:<br>- if (MCI.getOperand(0).isImm() &&<br>- isShiftedUInt<5, 3>(MCI.getOperand(0).getImm())) {<br>+ if (inRange<5, 3>(MCI, 0))<br> return HexagonII::HSIG_S2;<br>- }<br> break;<br> //<br> // Group A:<br>@@ -428,8 +415,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {<br> // Rd = add(r29,#u6:2)<br> if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &&<br>- MCI.getOperand(2).isImm() &&<br>- isShiftedUInt<6, 2>(MCI.getOperand(2).getImm())) {<br>+ inRange<6, 2>(MCI, 2)) {<br> return HexagonII::HSIG_A;<br> }<br> // Rx = add(Rx,#s7)<br>@@ -439,8 +425,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> // Rd = add(Rs,#1)<br> // Rd = add(Rs,#-1)<br> if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&<br>- MCI.getOperand(2).isImm() && ((MCI.getOperand(2).getImm() == 1) ||<br>- (MCI.getOperand(2).getImm() == -1))) {<br>+ (minConstant(MCI, 2) == 1 || minConstant(MCI, 2) == -1)) {<br> return HexagonII::HSIG_A;<br> }<br> }<br>@@ -460,8 +445,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> SrcReg = MCI.getOperand(1).getReg();<br> if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&<br> HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&<br>- MCI.getOperand(2).isImm() && ((MCI.getOperand(2).getImm() == 1) ||<br>- (MCI.getOperand(2).getImm() == 255))) {<br>+ (minConstant(MCI, 2) == 1 || minConstant(MCI, 2) == 255)) {<br> return HexagonII::HSIG_A;<br> }<br> break;<br>@@ -491,8 +475,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> DstReg = MCI.getOperand(0).getReg(); // Rd<br> PredReg = MCI.getOperand(1).getReg(); // P0<br> if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&<br>- Hexagon::P0 == PredReg && MCI.getOperand(2).isImm() &&<br>- MCI.getOperand(2).getImm() == 0) {<br>+ Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) {<br> return HexagonII::HSIG_A;<br> }<br> break;<br>@@ -502,7 +485,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> SrcReg = MCI.getOperand(1).getReg();<br> if (Hexagon::P0 == DstReg &&<br> HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&<br>- MCI.getOperand(2).isImm() && isUInt<2>(MCI.getOperand(2).getImm())) {<br>+ inRange<2>(MCI, 2)) {<br> return HexagonII::HSIG_A;<br> }<br> break;<br>@@ -511,10 +494,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> // Rdd = combine(#u2,#U2)<br> DstReg = MCI.getOperand(0).getReg();<br> if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) &&<br>- // TODO: Handle Globals/Symbols<br>- (MCI.getOperand(1).isImm() && isUInt<2>(MCI.getOperand(1).getImm())) &&<br>- ((MCI.getOperand(2).isImm() &&<br>- isUInt<2>(MCI.getOperand(2).getImm())))) {<br>+ inRange<2>(MCI, 1) && inRange<2>(MCI, 2)) {<br> return HexagonII::HSIG_A;<br> }<br> break;<br>@@ -524,7 +504,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> SrcReg = MCI.getOperand(1).getReg();<br> if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) &&<br> HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&<br>- (MCI.getOperand(2).isImm() && MCI.getOperand(2).getImm() == 0)) {<br>+ minConstant(MCI, 2) == 0) {<br> return HexagonII::HSIG_A;<br> }<br> break;<br>@@ -534,7 +514,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> SrcReg = MCI.getOperand(2).getReg();<br> if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) &&<br> HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&<br>- (MCI.getOperand(1).isImm() && MCI.getOperand(1).getImm() == 0)) {<br>+ minConstant(MCI, 1) == 0) {<br> return HexagonII::HSIG_A;<br> }<br> break;<br>@@ -556,19 +536,17 @@ unsigned HexagonMCInstrInfo::getDuplexCa<br> }<br><br> bool HexagonMCInstrInfo::subInstWouldBeExtended(MCInst const &potentialDuplex) {<br>-<br> unsigned DstReg, SrcReg;<br>-<br> switch (potentialDuplex.getOpcode()) {<br> case Hexagon::A2_addi:<br> // testing for case of: Rx = add(Rx,#s7)<br> DstReg = potentialDuplex.getOperand(0).getReg();<br> SrcReg = potentialDuplex.getOperand(1).getReg();<br> if (DstReg == SrcReg && HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {<br>- if (potentialDuplex.getOperand(2).isExpr())<br>+ int64_t Value;<br>+ if (!potentialDuplex.getOperand(2).getExpr()->evaluateAsAbsolute(Value))<br> return true;<br>- if (potentialDuplex.getOperand(2).isImm() &&<br>- !(isShiftedInt<7, 0>(potentialDuplex.getOperand(2).getImm())))<br>+ if (!isShiftedInt<7, 0>(Value))<br> return true;<br> }<br> break;<br>@@ -576,15 +554,14 @@ bool HexagonMCInstrInfo::subInstWouldBeE<br> DstReg = potentialDuplex.getOperand(0).getReg();<br><br> if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {<br>- if (potentialDuplex.getOperand(1).isExpr())<br>+ int64_t Value;<br>+ if (!potentialDuplex.getOperand(1).getExpr()->evaluateAsAbsolute(Value))<br> return true;<br> // Check for case of Rd = #-1.<br>- if (potentialDuplex.getOperand(1).isImm() &&<br>- (potentialDuplex.getOperand(1).getImm() == -1))<br>+ if (Value == -1)<br> return false;<br> // Check for case of Rd = #u6.<br>- if (potentialDuplex.getOperand(1).isImm() &&<br>- !isShiftedUInt<6, 0>(potentialDuplex.getOperand(1).getImm()))<br>+ if (!isShiftedUInt<6, 0>(Value))<br> return true;<br> }<br> break;<br>@@ -712,19 +689,23 @@ inline static void addOps(MCInst &subIns<br><br> MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {<br> MCInst Result;<br>+ bool Absolute;<br>+ int64_t Value;<br> switch (Inst.getOpcode()) {<br> default:<br> // dbgs() << "opcode: "<< Inst->getOpcode() << "\n";<br> llvm_unreachable("Unimplemented subinstruction \n");<br> break;<br> case Hexagon::A2_addi:<br>- if (Inst.getOperand(2).isImm() && Inst.getOperand(2).getImm() == 1) {<br>+ Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);<br>+ assert(Absolute);(void)Absolute;<br>+ if (Value == 1) {<br> Result.setOpcode(Hexagon::V4_SA1_inc);<br> addOps(Result, Inst, 0);<br> addOps(Result, Inst, 1);<br> break;<br> } // 1,2 SUBInst $Rd = add($Rs, #1)<br>- else if (Inst.getOperand(2).isImm() && Inst.getOperand(2).getImm() == -1) {<br>+ else if (Value == -1) {<br> Result.setOpcode(Hexagon::V4_SA1_dec);<br> addOps(Result, Inst, 0);<br> addOps(Result, Inst, 1);<br>@@ -754,7 +735,7 @@ MCInst HexagonMCInstrInfo::deriveSubInst<br> addOps(Result, Inst, 0);<br> break; // 1 SUBInst allocframe(#$u5_3)<br> case Hexagon::A2_andir:<br>- if (Inst.getOperand(2).getImm() == 255) {<br>+ if (minConstant(Inst, 2) == 255) {<br> Result.setOpcode(Hexagon::V4_SA1_zxtb);<br> addOps(Result, Inst, 0);<br> addOps(Result, Inst, 1);<br>@@ -772,26 +753,27 @@ MCInst HexagonMCInstrInfo::deriveSubInst<br> break; // 2,3 SUBInst p0 = cmp.eq($Rs, #$u2)<br> case Hexagon::A4_combineii:<br> case Hexagon::A2_combineii:<br>- if (Inst.getOperand(1).getImm() == 1) {<br>+ Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);<br>+ assert(Absolute);(void)Absolute;<br>+ if (Value == 1) {<br> Result.setOpcode(Hexagon::V4_SA1_combine1i);<br> addOps(Result, Inst, 0);<br> addOps(Result, Inst, 2);<br> break; // 1,3 SUBInst $Rdd = combine(#1, #$u2)<br> }<br>-<br>- if (Inst.getOperand(1).getImm() == 3) {<br>+ if (Value == 3) {<br> Result.setOpcode(Hexagon::V4_SA1_combine3i);<br> addOps(Result, Inst, 0);<br> addOps(Result, Inst, 2);<br> break; // 1,3 SUBInst $Rdd = combine(#3, #$u2)<br> }<br>- if (Inst.getOperand(1).getImm() == 0) {<br>+ if (Value == 0) {<br> Result.setOpcode(Hexagon::V4_SA1_combine0i);<br> addOps(Result, Inst, 0);<br> addOps(Result, Inst, 2);<br> break; // 1,3 SUBInst $Rdd = combine(#0, #$u2)<br> }<br>- if (Inst.getOperand(1).getImm() == 2) {<br>+ if (Value == 2) {<br> Result.setOpcode(Hexagon::V4_SA1_combine2i);<br> addOps(Result, Inst, 0);<br> addOps(Result, Inst, 2);<br>@@ -894,12 +876,14 @@ MCInst HexagonMCInstrInfo::deriveSubInst<br> break; // 1,2,3 SUBInst $Rd = memw($Rs + #$u4_2)<br> }<br> case Hexagon::S4_storeirb_io:<br>- if (Inst.getOperand(2).getImm() == 0) {<br>+ Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);<br>+ assert(Absolute);(void)Absolute;<br>+ if (Value == 0) {<br> Result.setOpcode(Hexagon::V4_SS2_storebi0);<br> addOps(Result, Inst, 0);<br> addOps(Result, Inst, 1);<br> break; // 1,2 SUBInst memb($Rs + #$u4_0)=#0<br>- } else if (Inst.getOperand(2).getImm() == 1) {<br>+ } else if (Value == 1) {<br> Result.setOpcode(Hexagon::V4_SS2_storebi1);<br> addOps(Result, Inst, 0);<br> addOps(Result, Inst, 1);<br>@@ -923,12 +907,14 @@ MCInst HexagonMCInstrInfo::deriveSubInst<br> addOps(Result, Inst, 2);<br> break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt<br> case Hexagon::S4_storeiri_io:<br>- if (Inst.getOperand(2).getImm() == 0) {<br>+ Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);<br>+ assert(Absolute);(void)Absolute;<br>+ if (Value == 0) {<br> Result.setOpcode(Hexagon::V4_SS2_storewi0);<br> addOps(Result, Inst, 0);<br> addOps(Result, Inst, 1);<br> break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#0<br>- } else if (Inst.getOperand(2).getImm() == 1) {<br>+ } else if (Value == 1) {<br> Result.setOpcode(Hexagon::V4_SS2_storewi1);<br> addOps(Result, Inst, 0);<br> addOps(Result, Inst, 1);<br>@@ -983,7 +969,8 @@ MCInst HexagonMCInstrInfo::deriveSubInst<br> addOps(Result, Inst, 0);<br> break; // 2 SUBInst if (p0) $Rd = #0<br> case Hexagon::A2_tfrsi:<br>- if (Inst.getOperand(1).isImm() && Inst.getOperand(1).getImm() == -1) {<br>+ Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);<br>+ if (Absolute && Value == -1) {<br> Result.setOpcode(Hexagon::V4_SA1_setin1);<br> addOps(Result, Inst, 0);<br> break; // 2 1 SUBInst $Rd = #-1<br>@@ -1044,6 +1031,8 @@ HexagonMCInstrInfo::getDuplexPossibiltie<br> << "\n");<br> bisReversable = false;<br> }<br>+ if (HexagonMCInstrInfo::isMemReorderDisabled(MCB)) // }:mem_noshuf<br>+ bisReversable = false;<br><br> // Try in order.<br> if (isOrderedDuplexPair(<br><br>Added: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp (added)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,49 @@<br>+//===-- HexagonMCExpr.cpp - Hexagon specific MC expression classes<br>+//----------===//<br>+//<br>+// The LLVM Compiler Infrastructure<br>+//<br>+// This file is distributed under the University of Illinois Open Source<br>+// License. See LICENSE.TXT for details.<br>+//<br>+//===----------------------------------------------------------------------===//<br>+<br>+#include "HexagonMCExpr.h"<br>+#include "llvm/MC/MCContext.h"<br>+#include "llvm/MC/MCValue.h"<br>+#include "llvm/Support/raw_ostream.h"<br>+<br>+using namespace llvm;<br>+<br>+#define DEBUG_TYPE "hexagon-mcexpr"<br>+<br>+HexagonNoExtendOperand *HexagonNoExtendOperand::Create(MCExpr const *Expr,<br>+ MCContext &Ctx) {<br>+ return new (Ctx) HexagonNoExtendOperand(Expr);<br>+}<br>+<br>+bool HexagonNoExtendOperand::evaluateAsRelocatableImpl(<br>+ MCValue &Res, MCAsmLayout const *Layout, MCFixup const *Fixup) const {<br>+ return Expr->evaluateAsRelocatable(Res, Layout, Fixup);<br>+}<br>+<br>+void HexagonNoExtendOperand::visitUsedExpr(MCStreamer &Streamer) const {}<br>+<br>+MCFragment *llvm::HexagonNoExtendOperand::findAssociatedFragment() const {<br>+ return Expr->findAssociatedFragment();<br>+}<br>+<br>+void HexagonNoExtendOperand::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {}<br>+<br>+MCExpr const *HexagonNoExtendOperand::getExpr() const { return Expr; }<br>+<br>+bool HexagonNoExtendOperand::classof(MCExpr const *E) {<br>+ return E->getKind() == MCExpr::Target;<br>+}<br>+<br>+HexagonNoExtendOperand::HexagonNoExtendOperand(MCExpr const *Expr)<br>+ : Expr(Expr) {}<br>+<br>+void HexagonNoExtendOperand::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {<br>+ Expr->print(OS, MAI);<br>+}<br><br>Added: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h (added)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,35 @@<br>+//==- HexagonMCExpr.h - Hexagon specific MC expression classes --*- C++ -*-===//<br>+//<br>+// The LLVM Compiler Infrastructure<br>+//<br>+// This file is distributed under the University of Illinois Open Source<br>+// License. See LICENSE.TXT for details.<br>+//<br>+//===----------------------------------------------------------------------===//<br>+<br>+#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMCEXPR_H<br>+#define LLVM_LIB_TARGET_HEXAGON_HEXAGONMCEXPR_H<br>+<br>+#include "llvm/MC/MCExpr.h"<br>+<br>+namespace llvm {<br>+class MCInst;<br>+class HexagonNoExtendOperand : public MCTargetExpr {<br>+public:<br>+ static HexagonNoExtendOperand *Create(MCExpr const *Expr, MCContext &Ctx);<br>+ void printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const override;<br>+ bool evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout,<br>+ const MCFixup *Fixup) const override;<br>+ void visitUsedExpr(MCStreamer &Streamer) const override;<br>+ MCFragment *findAssociatedFragment() const override;<br>+ void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override;<br>+ static bool classof(MCExpr const *E);<br>+ MCExpr const *getExpr() const;<br>+<br>+private:<br>+ HexagonNoExtendOperand(MCExpr const *Expr);<br>+ MCExpr const *Expr;<br>+};<br>+} // end namespace llvm<br>+<br>+#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMCEXPR_H<br><br>Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp (original)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp Sun Nov 8 22:07:48 2015<br>@@ -15,12 +15,32 @@<br><br> #include "Hexagon.h"<br> #include "HexagonBaseInfo.h"<br>+#include "HexagonMCChecker.h"<br><br> #include "llvm/MC/MCContext.h"<br>+#include "llvm/MC/MCExpr.h"<br> #include "llvm/MC/MCInstrInfo.h"<br> #include "llvm/MC/MCSubtargetInfo.h"<br><br> namespace llvm {<br>+void HexagonMCInstrInfo::addConstant(MCInst &MI, uint64_t Value,<br>+ MCContext &Context) {<br>+ MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(Value, Context)));<br>+}<br>+<br>+void HexagonMCInstrInfo::addConstExtender(MCInstrInfo const &MCII, MCInst &MCB,<br>+ MCInst const &MCI) {<br>+ assert(HexagonMCInstrInfo::isBundle(MCB));<br>+ MCOperand const &exOp =<br>+ MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));<br>+<br>+ // Create the extender.<br>+ MCInst *XMCI =<br>+ new MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));<br>+<br>+ MCB.addOperand(MCOperand::createInst(XMCI));<br>+}<br>+<br> iterator_range<MCInst::const_iterator><br> HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {<br> assert(isBundle(MCI));<br>@@ -35,6 +55,38 @@ size_t HexagonMCInstrInfo::bundleSize(MC<br> return (1);<br> }<br><br>+bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII,<br>+ MCSubtargetInfo const &STI,<br>+ MCContext &Context, MCInst &MCB,<br>+ HexagonMCChecker *Check) {<br>+ // Examine the packet and convert pairs of instructions to compound<br>+ // instructions when possible.<br>+ if (!HexagonDisableCompound)<br>+ HexagonMCInstrInfo::tryCompound(MCII, Context, MCB);<br>+ // Check the bundle for errors.<br>+ bool CheckOk = Check ? Check->check() : true;<br>+ if (!CheckOk)<br>+ return false;<br>+ HexagonMCShuffle(MCII, STI, MCB);<br>+ // Examine the packet and convert pairs of instructions to duplex<br>+ // instructions when possible.<br>+ MCInst InstBundlePreDuplex = MCInst(MCB);<br>+ if (!HexagonDisableDuplex) {<br>+ SmallVector<DuplexCandidate, 8> possibleDuplexes;<br>+ possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(MCII, MCB);<br>+ HexagonMCShuffle(MCII, STI, Context, MCB, possibleDuplexes);<br>+ }<br>+ // Examines packet and pad the packet, if needed, when an<br>+ // end-loop is in the bundle.<br>+ HexagonMCInstrInfo::padEndloop(MCB);<br>+ // If compounding and duplexing didn't reduce the size below<br>+ // 4 or less we have a packet that is too big.<br>+ if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE)<br>+ return false;<br>+ HexagonMCShuffle(MCII, STI, MCB);<br>+ return true;<br>+}<br>+<br> void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII, MCInst &MCI) {<br> assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||<br> HexagonMCInstrInfo::isExtended(MCII, MCI));<br>@@ -64,6 +116,27 @@ MCInst *HexagonMCInstrInfo::deriveDuplex<br> return duplexInst;<br> }<br><br>+MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII,<br>+ MCInst const &Inst,<br>+ MCOperand const &MO) {<br>+ assert(HexagonMCInstrInfo::isExtendable(MCII, Inst) ||<br>+ HexagonMCInstrInfo::isExtended(MCII, Inst));<br>+<br>+ MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst);<br>+ MCInst XMI;<br>+ XMI.setOpcode((Desc.isBranch() || Desc.isCall() ||<br>+ HexagonMCInstrInfo::getType(MCII, Inst) == HexagonII::TypeCR)<br>+ ? Hexagon::A4_ext_b<br>+ : Hexagon::A4_ext);<br>+ if (MO.isImm())<br>+ XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));<br>+ else if (MO.isExpr())<br>+ XMI.addOperand(MCOperand::createExpr(MO.getExpr()));<br>+ else<br>+ llvm_unreachable("invalid extendable operand");<br>+ return XMI;<br>+}<br>+<br> MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,<br> size_t Index) {<br> assert(Index <= bundleSize(MCB));<br>@@ -76,6 +149,12 @@ MCInst const *HexagonMCInstrInfo::extend<br> return nullptr;<br> }<br><br>+void HexagonMCInstrInfo::extendIfNeeded(MCInstrInfo const &MCII, MCInst &MCB,<br>+ MCInst const &MCI, bool MustExtend) {<br>+ if (isConstExtended(MCII, MCI) || MustExtend)<br>+ addConstExtender(MCII, MCB, MCI);<br>+}<br>+<br> HexagonII::MemAccessSize<br> HexagonMCInstrInfo::getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI) {<br> const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;<br>@@ -186,6 +265,25 @@ MCOperand const &HexagonMCInstrInfo::get<br> return (MCO);<br> }<br><br>+/// Return the new value or the newly produced value.<br>+unsigned short HexagonMCInstrInfo::getNewValueOp2(MCInstrInfo const &MCII,<br>+ MCInst const &MCI) {<br>+ const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;<br>+ return ((F >> HexagonII::NewValueOpPos2) & HexagonII::NewValueOpMask2);<br>+}<br>+<br>+MCOperand const &<br>+HexagonMCInstrInfo::getNewValueOperand2(MCInstrInfo const &MCII,<br>+ MCInst const &MCI) {<br>+ unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);<br>+ MCOperand const &MCO = MCI.getOperand(O);<br>+<br>+ assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||<br>+ HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&<br>+ MCO.isReg());<br>+ return (MCO);<br>+}<br>+<br> int HexagonMCInstrInfo::getSubTarget(MCInstrInfo const &MCII,<br> MCInst const &MCI) {<br> const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;<br>@@ -242,6 +340,13 @@ bool HexagonMCInstrInfo::hasNewValue(MCI<br> return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);<br> }<br><br>+/// Return whether the insn produces a second value.<br>+bool HexagonMCInstrInfo::hasNewValue2(MCInstrInfo const &MCII,<br>+ MCInst const &MCI) {<br>+ const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;<br>+ return ((F >> HexagonII::hasNewValuePos2) & HexagonII::hasNewValueMask2);<br>+}<br>+<br> MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {<br> assert(isBundle(MCB));<br> assert(Index < HEXAGON_PACKET_SIZE);<br>@@ -261,6 +366,11 @@ bool HexagonMCInstrInfo::isCanon(MCInstr<br> HexagonMCInstrInfo::getType(MCII, MCI) != HexagonII::TypeENDLOOP);<br> }<br><br>+bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,<br>+ MCInst const &MCI) {<br>+ return (getType(MCII, MCI) == HexagonII::TypeCOMPOUND);<br>+}<br>+<br> bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {<br> return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||<br> (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));<br>@@ -282,14 +392,21 @@ bool HexagonMCInstrInfo::isConstExtended<br> MCInst const &MCI) {<br> if (HexagonMCInstrInfo::isExtended(MCII, MCI))<br> return true;<br>-<br>- if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))<br>+ // Branch insns are handled as necessary by relaxation.<br>+ if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||<br>+ (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCOMPOUND &&<br>+ HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||<br>+ (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV &&<br>+ HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()))<br>+ return false;<br>+ // Otherwise loop instructions and other CR insts are handled by relaxation<br>+ else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&<br>+ (MCI.getOpcode() != Hexagon::C4_addipc))<br>+ return false;<br>+ else if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))<br> return false;<br><br>- short ExtOpNum = HexagonMCInstrInfo::getCExtOpNum(MCII, MCI);<br>- int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);<br>- int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);<br>- MCOperand const &MO = MCI.getOperand(ExtOpNum);<br>+ MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI);<br><br> // We could be using an instruction with an extendable immediate and shoehorn<br> // a global address into it. If it is a global address it will be constant<br>@@ -297,15 +414,13 @@ bool HexagonMCInstrInfo::isConstExtended<br> // We currently only handle isGlobal() because it is the only kind of<br> // object we are going to end up with here for now.<br> // In the future we probably should add isSymbol(), etc.<br>- if (MO.isExpr())<br>+ assert(!MO.isImm());<br>+ int64_t Value;<br>+ if (!MO.getExpr()->evaluateAsAbsolute(Value))<br> return true;<br>-<br>- // If the extendable operand is not 'Immediate' type, the instruction should<br>- // have 'isExtended' flag set.<br>- assert(MO.isImm() && "Extendable operand must be Immediate type");<br>-<br>- int ImmValue = MO.getImm();<br>- return (ImmValue < MinValue || ImmValue > MaxValue);<br>+ int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);<br>+ int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);<br>+ return (MinValue > Value || Value > MaxValue);<br> }<br><br> bool HexagonMCInstrInfo::isExtendable(MCInstrInfo const &MCII,<br>@@ -374,6 +489,19 @@ bool HexagonMCInstrInfo::isPredicated(MC<br> return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);<br> }<br><br>+bool HexagonMCInstrInfo::isPredicateLate(MCInstrInfo const &MCII,<br>+ MCInst const &MCI) {<br>+ const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;<br>+ return (F >> HexagonII::PredicateLatePos & HexagonII::PredicateLateMask);<br>+}<br>+<br>+/// Return whether the insn is newly predicated.<br>+bool HexagonMCInstrInfo::isPredicatedNew(MCInstrInfo const &MCII,<br>+ MCInst const &MCI) {<br>+ const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;<br>+ return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);<br>+}<br>+<br> bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,<br> MCInst const &MCI) {<br> const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;<br>@@ -394,6 +522,18 @@ bool HexagonMCInstrInfo::isSolo(MCInstrI<br> return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);<br> }<br><br>+bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) {<br>+ assert(isBundle(MCI));<br>+ auto Flags = MCI.getOperand(0).getImm();<br>+ return (Flags & memReorderDisabledMask) != 0;<br>+}<br>+<br>+bool HexagonMCInstrInfo::isMemStoreReorderEnabled(MCInst const &MCI) {<br>+ assert(isBundle(MCI));<br>+ auto Flags = MCI.getOperand(0).getImm();<br>+ return (Flags & memStoreReorderEnabledMask) != 0;<br>+}<br>+<br> bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {<br> const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;<br> return ((F >> HexagonII::SoloAXPos) & HexagonII::SoloAXMask);<br>@@ -405,6 +545,27 @@ bool HexagonMCInstrInfo::isSoloAin1(MCIn<br> return ((F >> HexagonII::SoloAin1Pos) & HexagonII::SoloAin1Mask);<br> }<br><br>+bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {<br>+ if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&<br>+ (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))<br>+ return true;<br>+ return false;<br>+}<br>+<br>+int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {<br>+ auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())<br>+ << 8;<br>+ if (MCI.size() <= Index)<br>+ return Sentinal;<br>+ MCOperand const &MCO = MCI.getOperand(Index);<br>+ if (!MCO.isExpr())<br>+ return Sentinal;<br>+ int64_t Value;<br>+ if (!MCO.getExpr()->evaluateAsAbsolute(Value))<br>+ return Sentinal;<br>+ return Value;<br>+}<br>+<br> void HexagonMCInstrInfo::padEndloop(MCInst &MCB) {<br> MCInst Nop;<br> Nop.setOpcode(Hexagon::A2_nop);<br>@@ -456,6 +617,20 @@ void HexagonMCInstrInfo::setInnerLoop(MC<br> Operand.setImm(Operand.getImm() | innerLoopMask);<br> }<br><br>+void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) {<br>+ assert(isBundle(MCI));<br>+ MCOperand &Operand = MCI.getOperand(0);<br>+ Operand.setImm(Operand.getImm() | memReorderDisabledMask);<br>+ assert(isMemReorderDisabled(MCI));<br>+}<br>+<br>+void HexagonMCInstrInfo::setMemStoreReorderEnabled(MCInst &MCI) {<br>+ assert(isBundle(MCI));<br>+ MCOperand &Operand = MCI.getOperand(0);<br>+ Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask);<br>+ assert(isMemStoreReorderEnabled(MCI));<br>+}<br>+<br> void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {<br> assert(isBundle(MCI));<br> MCOperand &Operand = MCI.getOperand(0);<br><br>Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h (original)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h Sun Nov 8 22:07:48 2015<br>@@ -14,9 +14,11 @@<br> #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H<br> #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H<br><br>+#include "HexagonMCExpr.h"<br> #include "llvm/MC/MCInst.h"<br><br> namespace llvm {<br>+class HexagonMCChecker;<br> class MCContext;<br> class MCInstrDesc;<br> class MCInstrInfo;<br>@@ -39,20 +41,44 @@ int64_t const innerLoopMask = 1 << inner<br> size_t const outerLoopOffset = 1;<br> int64_t const outerLoopMask = 1 << outerLoopOffset;<br><br>+// do not reorder memory load/stores by default load/stores are re-ordered<br>+// and by default loads can be re-ordered<br>+size_t const memReorderDisabledOffset = 2;<br>+int64_t const memReorderDisabledMask = 1 << memReorderDisabledOffset;<br>+<br>+// allow re-ordering of memory stores by default stores cannot be re-ordered<br>+size_t const memStoreReorderEnabledOffset = 3;<br>+int64_t const memStoreReorderEnabledMask = 1 << memStoreReorderEnabledOffset;<br>+<br> size_t const bundleInstructionsOffset = 1;<br><br>+void addConstant(MCInst &MI, uint64_t Value, MCContext &Context);<br>+void addConstExtender(MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI);<br>+<br> // Returns a iterator range of instructions in this bundle<br> iterator_range<MCInst::const_iterator> bundleInstructions(MCInst const &MCI);<br><br> // Returns the number of instructions in the bundle<br> size_t bundleSize(MCInst const &MCI);<br><br>+// Put the packet in to canonical form, compound, duplex, pad, and shuffle<br>+bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,<br>+ MCContext &Context, MCInst &MCB,<br>+ HexagonMCChecker *Checker);<br>+<br> // Clamp off upper 26 bits of extendable operand for emission<br> void clampExtended(MCInstrInfo const &MCII, MCInst &MCI);<br><br>+// Return the extender for instruction at Index or nullptr if none<br>+MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);<br>+void extendIfNeeded(MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI,<br>+ bool MustExtend);<br>+<br> // Create a duplex instruction given the two subinsts<br> MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0,<br> MCInst const &inst1);<br>+MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,<br>+ MCOperand const &MO);<br><br> // Convert this instruction in to a duplex subinst<br> MCInst deriveSubInst(MCInst const &Inst);<br>@@ -108,6 +134,9 @@ unsigned short getNewValueOp(MCInstrInfo<br><br> // Return the operand that consumes or produces a new value.<br> MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI);<br>+unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI);<br>+MCOperand const &getNewValueOperand2(MCInstrInfo const &MCII,<br>+ MCInst const &MCI);<br><br> int getSubTarget(MCInstrInfo const &MCII, MCInst const &MCI);<br><br>@@ -125,6 +154,7 @@ bool hasImmExt(MCInst const &MCI);<br><br> // Return whether the instruction is a legal new-value producer.<br> bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI);<br>+bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI);<br><br> // Return the instruction at Index<br> MCInst const &instruction(MCInst const &MCB, size_t Index);<br>@@ -134,10 +164,24 @@ bool isBundle(MCInst const &MCI);<br><br> // Return whether the insn is an actual insn.<br> bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);<br>+bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI);<br><br> // Return the duplex iclass given the two duplex classes<br> unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb);<br><br>+int64_t minConstant(MCInst const &MCI, size_t Index);<br>+template <unsigned N, unsigned S><br>+bool inRange(MCInst const &MCI, size_t Index) {<br>+ return isShiftedUInt<N, S>(minConstant(MCI, Index));<br>+}<br>+template <unsigned N, unsigned S><br>+bool inSRange(MCInst const &MCI, size_t Index) {<br>+ return isShiftedInt<N, S>(minConstant(MCI, Index));<br>+}<br>+template <unsigned N> bool inRange(MCInst const &MCI, size_t Index) {<br>+ return isUInt<N>(minConstant(MCI, Index));<br>+}<br>+<br> // Return whether the instruction needs to be constant extended.<br> bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI);<br><br>@@ -173,6 +217,8 @@ bool isIntReg(unsigned Reg);<br><br> // Is this register suitable for use in a duplex subinst<br> bool isIntRegForSubInst(unsigned Reg);<br>+bool isMemReorderDisabled(MCInst const &MCI);<br>+bool isMemStoreReorderEnabled(MCInst const &MCI);<br><br> // Return whether the insn is a new-value consumer.<br> bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);<br>@@ -191,6 +237,8 @@ bool isOuterLoop(MCInst const &MCI);<br><br> // Return whether this instruction is predicated<br> bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);<br>+bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI);<br>+bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI);<br><br> // Return whether the predicate sense is true<br> bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI);<br>@@ -209,6 +257,7 @@ bool isSoloAX(MCInstrInfo const &MCII, M<br><br> /// Return whether the insn can be packaged only with an A-type insn in slot #1.<br> bool isSoloAin1(MCInstrInfo const &MCII, MCInst const &MCI);<br>+bool isVector(MCInstrInfo const &MCII, MCInst const &MCI);<br><br> // Pad the bundle with nops to satisfy endloop requirements<br> void padEndloop(MCInst &MCI);<br>@@ -220,6 +269,8 @@ void replaceDuplex(MCContext &Context, M<br><br> // Marks a bundle as endloop0<br> void setInnerLoop(MCInst &MCI);<br>+void setMemReorderDisabled(MCInst &MCI);<br>+void setMemStoreReorderEnabled(MCInst &MCI);<br><br> // Marks a bundle as endloop1<br> void setOuterLoop(MCInst &MCI);<br><br>Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (original)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Sun Nov 8 22:07:48 2015<br>@@ -40,6 +40,14 @@ using namespace llvm;<br> #define GET_REGINFO_MC_DESC<br> #include "HexagonGenRegisterInfo.inc"<br><br>+cl::opt<bool> llvm::HexagonDisableCompound<br>+ ("mno-compound",<br>+ cl::desc("Disable looking for compound instructions for Hexagon"));<br>+<br>+cl::opt<bool> llvm::HexagonDisableDuplex<br>+ ("mno-pairing",<br>+ cl::desc("Disable looking for duplex instructions for Hexagon"));<br>+<br> MCInstrInfo *llvm::createHexagonMCInstrInfo() {<br> MCInstrInfo *X = new MCInstrInfo();<br> InitHexagonMCInstrInfo(X);<br>@@ -54,7 +62,10 @@ static MCRegisterInfo *createHexagonMCRe<br><br> static MCSubtargetInfo *<br> createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {<br>- return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);<br>+ StringRef CPUName = CPU;<br>+ if (CPU.empty())<br>+ CPUName = "hexagonv5";<br>+ return createHexagonMCSubtargetInfoImpl(TT, CPUName, FS);<br> }<br><br> namespace {<br><br>Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h (original)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h Sun Nov 8 22:07:48 2015<br>@@ -16,6 +16,8 @@<br><br> #include <cstdint><br><br>+#include "llvm/Support/CommandLine.h"<br>+<br> namespace llvm {<br> struct InstrItinerary;<br> struct InstrStage;<br>@@ -33,7 +35,8 @@ class raw_ostream;<br> class raw_pwrite_stream;<br><br> extern Target TheHexagonTarget;<br>-<br>+extern cl::opt<bool> HexagonDisableCompound;<br>+extern cl::opt<bool> HexagonDisableDuplex;<br> extern const InstrStage HexagonStages[];<br><br> MCInstrInfo *createHexagonMCInstrInfo();<br><br>Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h (original)<br>+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h Sun Nov 8 22:07:48 2015<br>@@ -108,6 +108,8 @@ public:<br> SHUFFLE_ERROR_BRANCHES, ///< No free slots for branch insns.<br> SHUFFLE_ERROR_NOSLOTS, ///< No free slots for other insns.<br> SHUFFLE_ERROR_SLOTS, ///< Over-subscribed slots.<br>+ SHUFFLE_ERROR_ERRATA2, ///< Errata violation (v60).<br>+ SHUFFLE_ERROR_STORE_LOAD_CONFLICT, ///< store/load conflict<br> SHUFFLE_ERROR_UNKNOWN ///< Unknown error.<br> };<br><br><br>Modified: llvm/trunk/test/CodeGen/Hexagon/absaddr-store.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/absaddr-store.ll?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/absaddr-store.ll?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Hexagon/absaddr-store.ll (original)<br>+++ llvm/trunk/test/CodeGen/Hexagon/absaddr-store.ll Sun Nov 8 22:07:48 2015<br>@@ -1,5 +1,6 @@<br> ; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s<br> ; Check that we generate load instructions with absolute addressing mode.<br>+; XFAIL: *<br><br> @a0 = external global i32<br> @a1 = external global i32<br><br>Modified: llvm/trunk/test/CodeGen/Hexagon/absimm.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/absimm.ll?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/absimm.ll?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Hexagon/absimm.ll (original)<br>+++ llvm/trunk/test/CodeGen/Hexagon/absimm.ll Sun Nov 8 22:07:48 2015<br>@@ -1,6 +1,7 @@<br> ; RUN: llc -march=hexagon < %s | FileCheck %s<br> ; Check that we generate absolute addressing mode instructions<br> ; with immediate value.<br>+; XFAIL: *<br><br> define i32 @f1(i32 %i) nounwind {<br> ; CHECK: memw(##786432){{ *}}={{ *}}r{{[0-9]+}}<br><br>Modified: llvm/trunk/test/CodeGen/Hexagon/always-ext.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/always-ext.ll?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/always-ext.ll?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Hexagon/always-ext.ll (original)<br>+++ llvm/trunk/test/CodeGen/Hexagon/always-ext.ll Sun Nov 8 22:07:48 2015<br>@@ -1,4 +1,5 @@<br> ; RUN: llc -march=hexagon < %s | FileCheck %s<br>+; XFAIL: *<br><br> ; Check that we don't generate an invalid packet with too many instructions<br> ; due to a store that has a must-extend operand.<br><br>Modified: llvm/trunk/test/CodeGen/Hexagon/compound.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/compound.ll?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/compound.ll?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Hexagon/compound.ll (original)<br>+++ llvm/trunk/test/CodeGen/Hexagon/compound.ll Sun Nov 8 22:07:48 2015<br>@@ -1,4 +1,5 @@<br> ; RUN: llc -march=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+; XFAIL: *<br><br> ; CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r0,#-1); if (!p0.new) jump:nt<br><br><br>Modified: llvm/trunk/test/CodeGen/Hexagon/static.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/static.ll?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/static.ll?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Hexagon/static.ll (original)<br>+++ llvm/trunk/test/CodeGen/Hexagon/static.ll Sun Nov 8 22:07:48 2015<br>@@ -1,4 +1,5 @@<br> ; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s<br>+; XFAIL: *<br><br> @num = external global i32<br> @acc = external global i32<br><br>Modified: llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll (original)<br>+++ llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll Sun Nov 8 22:07:48 2015<br>@@ -1,4 +1,5 @@<br> ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s<br>+; XFAIL: *<br><br> ; CHECK: r{{[0-9]+}} = ##i129_l+16<br> ; CHECK: r{{[0-9]+}} = ##i129_s+16<br><br>Added: llvm/trunk/test/MC/Disassembler/Hexagon/invalid_packet.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/invalid_packet.txt?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/invalid_packet.txt?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Disassembler/Hexagon/invalid_packet.txt (added)<br>+++ llvm/trunk/test/MC/Disassembler/Hexagon/invalid_packet.txt Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,4 @@<br>+# RUN: llvm-mc -triple=hexagon -disassemble < %s 2>&1 | FileCheck %s<br>+<br>+#CHECK: warning: invalid instruction encoding<br>+0x00 0x40 0x20 0x6c 0x00 0xc0 0x00 0x7f<br>\ No newline at end of file<br><br>Modified: llvm/trunk/test/MC/Disassembler/Hexagon/j.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/j.txt?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/j.txt?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Disassembler/Hexagon/j.txt (original)<br>+++ llvm/trunk/test/MC/Disassembler/Hexagon/j.txt Sun Nov 8 22:07:48 2015<br>@@ -11,149 +11,149 @@<br><br> # Compare and jump<br> 0x00 0xc0 0x89 0x11<br>-# CHECK: p0 = cmp.eq(r9,#-1); if (p0.new) jump:nt<br>+# CHECK: p0 = cmp.eq(r17,#-1); if (p0.new) jump:nt<br> 0x00 0xc1 0x89 0x11<br>-# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9,#-1); if (p0.new) jump:nt<br>+# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (p0.new) jump:nt<br> 0x00 0xc3 0x89 0x11<br>-# CHECK: p0 = tstbit(r9, #0); if (p0.new) jump:nt<br>+# CHECK: p0 = tstbit(r17, #0); if (p0.new) jump:nt<br> 0x00 0xe0 0x89 0x11<br>-# CHECK: p0 = cmp.eq(r9,#-1); if (p0.new) jump:t<br>+# CHECK: p0 = cmp.eq(r17,#-1); if (p0.new) jump:t<br> 0x00 0xe1 0x89 0x11<br>-# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9,#-1); if (p0.new) jump:t<br>+# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (p0.new) jump:t<br> 0x00 0xe3 0x89 0x11<br>-# CHECK: p0 = tstbit(r9, #0); if (p0.new) jump:t<br>+# CHECK: p0 = tstbit(r17, #0); if (p0.new) jump:t<br> 0x00 0xc0 0xc9 0x11<br>-# CHECK: p0 = cmp.eq(r9,#-1); if (!p0.new) jump:nt<br>+# CHECK: p0 = cmp.eq(r17,#-1); if (!p0.new) jump:nt<br> 0x00 0xc1 0xc9 0x11<br>-# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9,#-1); if (!p0.new) jump:nt<br>+# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (!p0.new) jump:nt<br> 0x00 0xc3 0xc9 0x11<br>-# CHECK: p0 = tstbit(r9, #0); if (!p0.new) jump:nt<br>+# CHECK: p0 = tstbit(r17, #0); if (!p0.new) jump:nt<br> 0x00 0xe0 0xc9 0x11<br>-# CHECK: p0 = cmp.eq(r9,#-1); if (!p0.new) jump:t<br>+# CHECK: p0 = cmp.eq(r17,#-1); if (!p0.new) jump:t<br> 0x00 0xe1 0xc9 0x11<br>-# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9,#-1); if (!p0.new) jump:t<br>+# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (!p0.new) jump:t<br> 0x00 0xe3 0xc9 0x11<br>-# CHECK: p0 = tstbit(r9, #0); if (!p0.new) jump:t<br>+# CHECK: p0 = tstbit(r17, #0); if (!p0.new) jump:t<br> 0x00 0xd5 0x09 0x10<br>-# CHECK: p0 = cmp.eq(r9, #21); if (p0.new) jump:nt<br>+# CHECK: p0 = cmp.eq(r17, #21); if (p0.new) jump:nt<br> 0x00 0xf5 0x09 0x10<br>-# CHECK: p0 = cmp.eq(r9, #21); if (p0.new) jump:t<br>+# CHECK: p0 = cmp.eq(r17, #21); if (p0.new) jump:t<br> 0x00 0xd5 0x49 0x10<br>-# CHECK: p0 = cmp.eq(r9, #21); if (!p0.new) jump:nt<br>+# CHECK: p0 = cmp.eq(r17, #21); if (!p0.new) jump:nt<br> 0x00 0xf5 0x49 0x10<br>-# CHECK: p0 = cmp.eq(r9, #21); if (!p0.new) jump:t<br>+# CHECK: p0 = cmp.eq(r17, #21); if (!p0.new) jump:t<br> 0x00 0xd5 0x89 0x10<br>-# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, #21); if (p0.new) jump:nt<br>+# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (p0.new) jump:nt<br> 0x00 0xf5 0x89 0x10<br>-# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, #21); if (p0.new) jump:t<br>+# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (p0.new) jump:t<br> 0x00 0xd5 0xc9 0x10<br>-# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, #21); if (!p0.new) jump:nt<br>+# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (!p0.new) jump:nt<br> 0x00 0xf5 0xc9 0x10<br>-# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, #21); if (!p0.new) jump:t<br>+# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (!p0.new) jump:t<br> 0x00 0xd5 0x09 0x11<br>-# CHECK: p0 = cmp.gtu(r9, #21); if (p0.new) jump:nt<br>+# CHECK: p0 = cmp.gtu(r17, #21); if (p0.new) jump:nt<br> 0x00 0xf5 0x09 0x11<br>-# CHECK: p0 = cmp.gtu(r9, #21); if (p0.new) jump:t<br>+# CHECK: p0 = cmp.gtu(r17, #21); if (p0.new) jump:t<br> 0x00 0xd5 0x49 0x11<br>-# CHECK: p0 = cmp.gtu(r9, #21); if (!p0.new) jump:nt<br>+# CHECK: p0 = cmp.gtu(r17, #21); if (!p0.new) jump:nt<br> 0x00 0xf5 0x49 0x11<br>-# CHECK: p0 = cmp.gtu(r9, #21); if (!p0.new) jump:t<br>+# CHECK: p0 = cmp.gtu(r17, #21); if (!p0.new) jump:t<br> 0x00 0xc0 0x89 0x13<br>-# CHECK: p1 = cmp.eq(r9,#-1); if (p1.new) jump:nt<br>+# CHECK: p1 = cmp.eq(r17,#-1); if (p1.new) jump:nt<br> 0x00 0xc1 0x89 0x13<br>-# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9,#-1); if (p1.new) jump:nt<br>+# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (p1.new) jump:nt<br> 0x00 0xc3 0x89 0x13<br>-# CHECK: p1 = tstbit(r9, #0); if (p1.new) jump:nt<br>+# CHECK: p1 = tstbit(r17, #0); if (p1.new) jump:nt<br> 0x00 0xe0 0x89 0x13<br>-# CHECK: p1 = cmp.eq(r9,#-1); if (p1.new) jump:t<br>+# CHECK: p1 = cmp.eq(r17,#-1); if (p1.new) jump:t<br> 0x00 0xe1 0x89 0x13<br>-# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9,#-1); if (p1.new) jump:t<br>+# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (p1.new) jump:t<br> 0x00 0xe3 0x89 0x13<br>-# CHECK: p1 = tstbit(r9, #0); if (p1.new) jump:t<br>+# CHECK: p1 = tstbit(r17, #0); if (p1.new) jump:t<br> 0x00 0xc0 0xc9 0x13<br>-# CHECK: p1 = cmp.eq(r9,#-1); if (!p1.new) jump:nt<br>+# CHECK: p1 = cmp.eq(r17,#-1); if (!p1.new) jump:nt<br> 0x00 0xc1 0xc9 0x13<br>-# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9,#-1); if (!p1.new) jump:nt<br>+# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (!p1.new) jump:nt<br> 0x00 0xc3 0xc9 0x13<br>-# CHECK: p1 = tstbit(r9, #0); if (!p1.new) jump:nt<br>+# CHECK: p1 = tstbit(r17, #0); if (!p1.new) jump:nt<br> 0x00 0xe0 0xc9 0x13<br>-# CHECK: p1 = cmp.eq(r9,#-1); if (!p1.new) jump:t<br>+# CHECK: p1 = cmp.eq(r17,#-1); if (!p1.new) jump:t<br> 0x00 0xe1 0xc9 0x13<br>-# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9,#-1); if (!p1.new) jump:t<br>+# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (!p1.new) jump:t<br> 0x00 0xe3 0xc9 0x13<br>-# CHECK: p1 = tstbit(r9, #0); if (!p1.new) jump:t<br>+# CHECK: p1 = tstbit(r17, #0); if (!p1.new) jump:t<br> 0x00 0xd5 0x09 0x12<br>-# CHECK: p1 = cmp.eq(r9, #21); if (p1.new) jump:nt<br>+# CHECK: p1 = cmp.eq(r17, #21); if (p1.new) jump:nt<br> 0x00 0xf5 0x09 0x12<br>-# CHECK: p1 = cmp.eq(r9, #21); if (p1.new) jump:t<br>+# CHECK: p1 = cmp.eq(r17, #21); if (p1.new) jump:t<br> 0x00 0xd5 0x49 0x12<br>-# CHECK: p1 = cmp.eq(r9, #21); if (!p1.new) jump:nt<br>+# CHECK: p1 = cmp.eq(r17, #21); if (!p1.new) jump:nt<br> 0x00 0xf5 0x49 0x12<br>-# CHECK: p1 = cmp.eq(r9, #21); if (!p1.new) jump:t<br>+# CHECK: p1 = cmp.eq(r17, #21); if (!p1.new) jump:t<br> 0x00 0xd5 0x89 0x12<br>-# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, #21); if (p1.new) jump:nt<br>+# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (p1.new) jump:nt<br> 0x00 0xf5 0x89 0x12<br>-# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, #21); if (p1.new) jump:t<br>+# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (p1.new) jump:t<br> 0x00 0xd5 0xc9 0x12<br>-# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, #21); if (!p1.new) jump:nt<br>+# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (!p1.new) jump:nt<br> 0x00 0xf5 0xc9 0x12<br>-# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, #21); if (!p1.new) jump:t<br>+# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (!p1.new) jump:t<br> 0x00 0xd5 0x09 0x13<br>-# CHECK: p1 = cmp.gtu(r9, #21); if (p1.new) jump:nt<br>+# CHECK: p1 = cmp.gtu(r17, #21); if (p1.new) jump:nt<br> 0x00 0xf5 0x09 0x13<br>-# CHECK: p1 = cmp.gtu(r9, #21); if (p1.new) jump:t<br>+# CHECK: p1 = cmp.gtu(r17, #21); if (p1.new) jump:t<br> 0x00 0xd5 0x49 0x13<br>-# CHECK: p1 = cmp.gtu(r9, #21); if (!p1.new) jump:nt<br>+# CHECK: p1 = cmp.gtu(r17, #21); if (!p1.new) jump:nt<br> 0x00 0xf5 0x49 0x13<br>-# CHECK: p1 = cmp.gtu(r9, #21); if (!p1.new) jump:t<br>+# CHECK: p1 = cmp.gtu(r17, #21); if (!p1.new) jump:t<br> 0x00 0xcd 0x09 0x14<br>-# CHECK: p0 = cmp.eq(r9, r13); if (p0.new) jump:nt<br>+# CHECK: p0 = cmp.eq(r17, r21); if (p0.new) jump:nt<br> 0x00 0xdd 0x09 0x14<br>-# CHECK: p1 = cmp.eq(r9, r13); if (p1.new) jump:nt<br>+# CHECK: p1 = cmp.eq(r17, r21); if (p1.new) jump:nt<br> 0x00 0xed 0x09 0x14<br>-# CHECK: p0 = cmp.eq(r9, r13); if (p0.new) jump:t<br>+# CHECK: p0 = cmp.eq(r17, r21); if (p0.new) jump:t<br> 0x00 0xfd 0x09 0x14<br>-# CHECK: p1 = cmp.eq(r9, r13); if (p1.new) jump:t<br>+# CHECK: p1 = cmp.eq(r17, r21); if (p1.new) jump:t<br> 0x00 0xcd 0x49 0x14<br>-# CHECK: p0 = cmp.eq(r9, r13); if (!p0.new) jump:nt<br>+# CHECK: p0 = cmp.eq(r17, r21); if (!p0.new) jump:nt<br> 0x00 0xdd 0x49 0x14<br>-# CHECK: p1 = cmp.eq(r9, r13); if (!p1.new) jump:nt<br>+# CHECK: p1 = cmp.eq(r17, r21); if (!p1.new) jump:nt<br> 0x00 0xed 0x49 0x14<br>-# CHECK: p0 = cmp.eq(r9, r13); if (!p0.new) jump:t<br>+# CHECK: p0 = cmp.eq(r17, r21); if (!p0.new) jump:t<br> 0x00 0xfd 0x49 0x14<br>-# CHECK: p1 = cmp.eq(r9, r13); if (!p1.new) jump:t<br>+# CHECK: p1 = cmp.eq(r17, r21); if (!p1.new) jump:t<br> 0x00 0xcd 0x89 0x14<br>-# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, r13); if (p0.new) jump:nt<br>+# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (p0.new) jump:nt<br> 0x00 0xdd 0x89 0x14<br>-# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, r13); if (p1.new) jump:nt<br>+# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (p1.new) jump:nt<br> 0x00 0xed 0x89 0x14<br>-# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, r13); if (p0.new) jump:t<br>+# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (p0.new) jump:t<br> 0x00 0xfd 0x89 0x14<br>-# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, r13); if (p1.new) jump:t<br>+# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (p1.new) jump:t<br> 0x00 0xcd 0xc9 0x14<br>-# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, r13); if (!p0.new) jump:nt<br>+# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (!p0.new) jump:nt<br> 0x00 0xdd 0xc9 0x14<br>-# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, r13); if (!p1.new) jump:nt<br>+# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (!p1.new) jump:nt<br> 0x00 0xed 0xc9 0x14<br>-# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, r13); if (!p0.new) jump:t<br>+# CHECK: p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (!p0.new) jump:t<br> 0x00 0xfd 0xc9 0x14<br>-# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r9, r13); if (!p1.new) jump:t<br>+# CHECK: p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (!p1.new) jump:t<br> 0x00 0xcd 0x09 0x15<br>-# CHECK: p0 = cmp.gtu(r9, r13); if (p0.new) jump:nt<br>+# CHECK: p0 = cmp.gtu(r17, r21); if (p0.new) jump:nt<br> 0x00 0xdd 0x09 0x15<br>-# CHECK: p1 = cmp.gtu(r9, r13); if (p1.new) jump:nt<br>+# CHECK: p1 = cmp.gtu(r17, r21); if (p1.new) jump:nt<br> 0x00 0xed 0x09 0x15<br>-# CHECK: p0 = cmp.gtu(r9, r13); if (p0.new) jump:t<br>+# CHECK: p0 = cmp.gtu(r17, r21); if (p0.new) jump:t<br> 0x00 0xfd 0x09 0x15<br>-# CHECK: p1 = cmp.gtu(r9, r13); if (p1.new) jump:t<br>+# CHECK: p1 = cmp.gtu(r17, r21); if (p1.new) jump:t<br> 0x00 0xcd 0x49 0x15<br>-# CHECK: p0 = cmp.gtu(r9, r13); if (!p0.new) jump:nt<br>+# CHECK: p0 = cmp.gtu(r17, r21); if (!p0.new) jump:nt<br> 0x00 0xdd 0x49 0x15<br>-# CHECK: p1 = cmp.gtu(r9, r13); if (!p1.new) jump:nt<br>+# CHECK: p1 = cmp.gtu(r17, r21); if (!p1.new) jump:nt<br> 0x00 0xed 0x49 0x15<br>-# CHECK: p0 = cmp.gtu(r9, r13); if (!p0.new) jump:t<br>+# CHECK: p0 = cmp.gtu(r17, r21); if (!p0.new) jump:t<br> 0x00 0xfd 0x49 0x15<br>-# CHECK: p1 = cmp.gtu(r9, r13); if (!p1.new) jump:t<br>+# CHECK: p1 = cmp.gtu(r17, r21); if (!p1.new) jump:t<br><br> # Jump to address<br> 0x22 0xc0 0x00 0x58<br>@@ -197,6 +197,6 @@<br><br> # Transfer and jump<br> 0x00 0xd5 0x09 0x16<br>-# CHECK: r9 = #21 ; jump<br>+# CHECK: r17 = #21 ; jump<br> 0x00 0xc9 0x0d 0x17<br>-# CHECK: r9 = r13 ; jump<br>+# CHECK: r17 = r21 ; jump<br><br>Modified: llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt (original)<br>+++ llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt Sun Nov 8 22:07:48 2015<br>@@ -1,15 +1,22 @@<br> # RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s<br> # Hexagon Programmer's Reference Manual 11.5 LD<br>+# XFAIL: *<br><br> # Load doubleword<br> 0x90 0xff 0xd5 0x3a<br> # CHECK: r17:16 = memd(r21 + r31<<#3)<br>-0x10 0xc5 0xc0 0x49<br>-# CHECK: r17:16 = memd(##320)<br>+0xb0 0xc2 0xc0 0x49<br>+# CHECK: r17:16 = memd(#168)<br>+0x02 0x40 0x00 0x00 0x10 0xc5 0xc0 0x49<br>+# CHECK: r17:16 = memd(##168)<br>+0xd0 0xc0 0xd5 0x91<br>+# CHECK: r17:16 = memd(r21 + #48)<br> 0xb0 0xe0 0xd5 0x99<br> # CHECK: r17:16 = memd(r21 ++ #40:circ(m1))<br> 0x10 0xe2 0xd5 0x99<br> # CHECK: r17:16 = memd(r21 ++ I:circ(m1))<br>+0x00 0x40 0x00 0x00 0x70 0xd7 0xd5 0x9b<br>+# CHECK: r17:16 = memd(r21 = ##31)<br> 0xb0 0xc0 0xd5 0x9b<br> # CHECK: r17:16 = memd(r21++#40)<br> 0x10 0xe0 0xd5 0x9d<br>@@ -53,6 +60,8 @@<br> 0x91 0xff 0x15 0x3a<br> # CHECK: r17 = memb(r21 + r31<<#3)<br> 0xb1 0xc2 0x00 0x49<br>+# CHECK: r17 = memb(#21)<br>+0x00 0x40 0x00 0x00 0xb1 0xc2 0x00 0x49<br> # CHECK: r17 = memb(##21)<br> 0xf1 0xc3 0x15 0x91<br> # CHECK: r17 = memb(r21 + #31)<br>@@ -60,6 +69,8 @@<br> # CHECK: r17 = memb(r21 ++ #5:circ(m1))<br> 0x11 0xe2 0x15 0x99<br> # CHECK: r17 = memb(r21 ++ I:circ(m1))<br>+0x00 0x40 0x00 0x00 0x71 0xd7 0x15 0x9b<br>+# CHECK: r17 = memb(r21 = ##31)<br> 0xb1 0xc0 0x15 0x9b<br> # CHECK: r17 = memb(r21++#5)<br> 0x11 0xe0 0x15 0x9d<br>@@ -99,17 +110,37 @@<br> # CHECK: p3 = r5<br> # CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5)<br><br>+# Load byte into shifted vector<br>+0xf0 0xc3 0x95 0x90<br>+# CHECK: r17:16 = memb_fifo(r21 + #31)<br>+0xb0 0xe0 0x95 0x98<br>+# CHECK: r17:16 = memb_fifo(r21 ++ #5:circ(m1))<br>+0x10 0xe2 0x95 0x98<br>+# CHECK: r17:16 = memb_fifo(r21 ++ I:circ(m1))<br>+<br>+# Load half into shifted vector<br>+0xf0 0xc3 0x55 0x90<br>+# CHECK: r17:16 = memh_fifo(r21 + #62)<br>+0xb0 0xe0 0x55 0x98<br>+# CHECK: r17:16 = memh_fifo(r21 ++ #10:circ(m1))<br>+0x10 0xe2 0x55 0x98<br>+# CHECK: r17:16 = memh_fifo(r21 ++ I:circ(m1))<br>+<br> # Load halfword<br> 0x91 0xff 0x55 0x3a<br> # CHECK: r17 = memh(r21 + r31<<#3)<br>-0x51 0xc5 0x40 0x49<br>-# CHECK: r17 = memh(##84)<br>+0xb1 0xc2 0x40 0x49<br>+# CHECK: r17 = memh(#42)<br>+0x00 0x40 0x00 0x00 0x51 0xc5 0x40 0x49<br>+# CHECK: r17 = memh(##42)<br> 0xf1 0xc3 0x55 0x91<br> # CHECK: r17 = memh(r21 + #62)<br> 0xb1 0xe0 0x55 0x99<br> # CHECK: r17 = memh(r21 ++ #10:circ(m1))<br> 0x11 0xe2 0x55 0x99<br> # CHECK: r17 = memh(r21 ++ I:circ(m1))<br>+0x00 0x40 0x00 0x00 0x71 0xd7 0x55 0x9b<br>+# CHECK: r17 = memh(r21 = ##31)<br> 0xb1 0xc0 0x55 0x9b<br> # CHECK: r17 = memh(r21++#10)<br> 0x11 0xe0 0x55 0x9d<br>@@ -138,11 +169,23 @@<br> 0x03 0x40 0x45 0x85 0xb1 0xfe 0x55 0x9b<br> # CHECK: p3 = r5<br> # CHECK-NEXT: if (!p3.new) r17 = memh(r21++#10)<br>+0xf1 0xdb 0x55 0x41<br>+# CHECK: if (p3) r17 = memh(r21 + #62)<br>+0xf1 0xdb 0x55 0x45<br>+# CHECK: if (!p3) r17 = memh(r21 + #62)<br>+0x03 0x40 0x45 0x85 0xf1 0xdb 0x55 0x43<br>+# CHECK: p3 = r5<br>+# CHECK-NEXT: if (p3.new) r17 = memh(r21 + #62)<br>+0x03 0x40 0x45 0x85 0xf1 0xdb 0x55 0x47<br>+# CHECK: p3 = r5<br>+# CHECK-NEXT: if (!p3.new) r17 = memh(r21 + #62)<br><br> # Load unsigned byte<br> 0x91 0xff 0x35 0x3a<br> # CHECK: r17 = memub(r21 + r31<<#3)<br> 0xb1 0xc2 0x20 0x49<br>+# CHECK: r17 = memub(#21)<br>+0x00 0x40 0x00 0x00 0xb1 0xc2 0x20 0x49<br> # CHECK: r17 = memub(##21)<br> 0xf1 0xc3 0x35 0x91<br> # CHECK: r17 = memub(r21 + #31)<br>@@ -150,6 +193,8 @@<br> # CHECK: r17 = memub(r21 ++ #5:circ(m1))<br> 0x11 0xe2 0x35 0x99<br> # CHECK: r17 = memub(r21 ++ I:circ(m1))<br>+0x00 0x40 0x00 0x00 0x71 0xd7 0x35 0x9b<br>+# CHECK: r17 = memub(r21 = ##31)<br> 0xb1 0xc0 0x35 0x9b<br> # CHECK: r17 = memub(r21++#5)<br> 0x11 0xe0 0x35 0x9d<br>@@ -192,14 +237,18 @@<br> # Load unsigned halfword<br> 0x91 0xff 0x75 0x3a<br> # CHECK: r17 = memuh(r21 + r31<<#3)<br>-0x51 0xc5 0x60 0x49<br>-# CHECK: r17 = memuh(##84)<br>+0xb1 0xc2 0x60 0x49<br>+# CHECK: r17 = memuh(#42)<br>+0x00 0x40 0x00 0x00 0x51 0xc5 0x60 0x49<br>+# CHECK: r17 = memuh(##42)<br> 0xb1 0xc2 0x75 0x91<br> # CHECK: r17 = memuh(r21 + #42)<br> 0xb1 0xe0 0x75 0x99<br> # CHECK: r17 = memuh(r21 ++ #10:circ(m1))<br> 0x11 0xe2 0x75 0x99<br> # CHECK: r17 = memuh(r21 ++ I:circ(m1))<br>+0x00 0x40 0x00 0x00 0x71 0xd7 0x75 0x9b<br>+# CHECK: r17 = memuh(r21 = ##31)<br> 0xb1 0xc0 0x75 0x9b<br> # CHECK: r17 = memuh(r21++#10)<br> 0x11 0xe0 0x75 0x9d<br>@@ -242,14 +291,18 @@<br> # Load word<br> 0x91 0xff 0x95 0x3a<br> # CHECK: r17 = memw(r21 + r31<<#3)<br>-0x91 0xc2 0x80 0x49<br>-# CHECK: r17 = memw(##80)<br>+0xb1 0xc2 0x80 0x49<br>+# CHECK: r17 = memw(#84)<br>+0x01 0x40 0x00 0x00 0x91 0xc2 0x80 0x49<br>+# CHECK: r17 = memw(##84)<br> 0xb1 0xc2 0x95 0x91<br> # CHECK: r17 = memw(r21 + #84)<br> 0xb1 0xe0 0x95 0x99<br> # CHECK: r17 = memw(r21 ++ #20:circ(m1))<br> 0x11 0xe2 0x95 0x99<br> # CHECK: r17 = memw(r21 ++ I:circ(m1))<br>+0x00 0x40 0x00 0x00 0x71 0xd7 0x95 0x9b<br>+# CHECK: r17 = memw(r21 = ##31)<br> 0xb1 0xc0 0x95 0x9b<br> # CHECK: r17 = memw(r21++#20)<br> 0x11 0xe0 0x95 0x9d<br>@@ -338,14 +391,36 @@<br> # CHECK: r17:16 = memubh(r21 ++ #20:circ(m1))<br> 0x10 0xe2 0xb5 0x98<br> # CHECK: r17:16 = memubh(r21 ++ I:circ(m1))<br>+0x00 0x40 0x00 0x00 0x71 0xd7 0x35 0x9a<br>+# CHECK: r17 = membh(r21 = ##31)<br> 0xb1 0xc0 0x35 0x9a<br> # CHECK: r17 = membh(r21++#10)<br>+0x00 0x40 0x00 0x00 0x71 0xd7 0x75 0x9a<br>+# CHECK: r17 = memubh(r21 = ##31)<br> 0xb1 0xc0 0x75 0x9a<br> # CHECK: r17 = memubh(r21++#10)<br>+0x00 0x40 0x00 0x00 0x70 0xd7 0xb5 0x9a<br>+# CHECK: r17:16 = memubh(r21 = ##31)<br> 0xb0 0xc0 0xb5 0x9a<br> # CHECK: r17:16 = memubh(r21++#20)<br>+0x00 0x40 0x00 0x00 0x70 0xd7 0xf5 0x9a<br>+# CHECK: r17:16 = membh(r21 = ##31)<br> 0xb0 0xc0 0xf5 0x9a<br> # CHECK: r17:16 = membh(r21++#20)<br>+0x00 0x40 0x00 0x00 0xf1 0xf7 0x35 0x9c<br>+# CHECK: r17 = membh(r21<<#3 + ##31)<br>+0x11 0xe0 0x35 0x9c<br>+# CHECK: r17 = membh(r21++m1)<br>+0x00 0x40 0x00 0x00 0xf1 0xf7 0x75 0x9c<br>+# CHECK: r17 = memubh(r21<<#3 + ##31)<br>+0x11 0xe0 0x75 0x9c<br>+# CHECK: r17 = memubh(r21++m1)<br>+0x00 0x40 0x00 0x00 0xf0 0xf7 0xf5 0x9c<br>+# CHECK: r17:16 = membh(r21<<#3 + ##31)<br>+0x10 0xe0 0xf5 0x9c<br>+# CHECK: r17:16 = membh(r21++m1)<br>+0x00 0x40 0x00 0x00 0xf0 0xf7 0xb5 0x9c<br>+# CHECK: r17:16 = memubh(r21<<#3 + ##31)<br> 0x11 0xe0 0x35 0x9c<br> # CHECK: r17 = membh(r21++m1)<br> 0x11 0xe0 0x75 0x9c<br><br>Modified: llvm/trunk/test/MC/Disassembler/Hexagon/lit.local.cfg<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/lit.local.cfg?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/lit.local.cfg?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Disassembler/Hexagon/lit.local.cfg (original)<br>+++ llvm/trunk/test/MC/Disassembler/Hexagon/lit.local.cfg Sun Nov 8 22:07:48 2015<br>@@ -1,3 +1,3 @@<br>-if not 'Hexagon' in config.root.targets:<br>- config.unsupported = True<br>-<br>+if not 'Hexagon' in config.root.targets:<br>+ config.unsupported = True<br>+<br><br>Modified: llvm/trunk/test/MC/Disassembler/Hexagon/nv_j.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/nv_j.txt?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/nv_j.txt?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Disassembler/Hexagon/nv_j.txt (original)<br>+++ llvm/trunk/test/MC/Disassembler/Hexagon/nv_j.txt Sun Nov 8 22:07:48 2015<br>@@ -4,133 +4,133 @@<br> # Jump to address conditioned on new register value<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x20<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (cmp.eq(r2.new, r21)) jump:nt<br>+# CHECK-NEXT: if (cmp.eq(r17.new, r21)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x20<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (cmp.eq(r2.new, r21)) jump:t<br>+# CHECK-NEXT: if (cmp.eq(r17.new, r21)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x20<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!cmp.eq(r2.new, r21)) jump:nt<br>+# CHECK-NEXT: if (!cmp.eq(r17.new, r21)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x20<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!cmp.eq(r2.new, r21)) jump:t<br>+# CHECK-NEXT: if (!cmp.eq(r17.new, r21)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x20<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r2.new, r21)) jump:nt<br>+# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, r21)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x20<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r2.new, r21)) jump:t<br>+# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, r21)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x20<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r2.new, r21)) jump:nt<br>+# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, r21)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x20<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r2.new, r21)) jump:t<br>+# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, r21)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x21<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (cmp.gtu(r2.new, r21)) jump:nt<br>+# CHECK-NEXT: if (cmp.gtu(r17.new, r21)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x21<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (cmp.gtu(r2.new, r21)) jump:t<br>+# CHECK-NEXT: if (cmp.gtu(r17.new, r21)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x21<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!cmp.gtu(r2.new, r21)) jump:nt<br>+# CHECK-NEXT: if (!cmp.gtu(r17.new, r21)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x21<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!cmp.gtu(r2.new, r21)) jump:t<br>+# CHECK-NEXT: if (!cmp.gtu(r17.new, r21)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x21<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r2.new)) jump:nt<br>+# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r17.new)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x21<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r2.new)) jump:t<br>+# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r17.new)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x21<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r2.new)) jump:nt<br>+# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r17.new)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x21<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r2.new)) jump:t<br>+# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r17.new)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x22<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (cmp.gtu(r21, r2.new)) jump:nt<br>+# CHECK-NEXT: if (cmp.gtu(r21, r17.new)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x22<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (cmp.gtu(r21, r2.new)) jump:t<br>+# CHECK-NEXT: if (cmp.gtu(r21, r17.new)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x22<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!cmp.gtu(r21, r2.new)) jump:nt<br>+# CHECK-NEXT: if (!cmp.gtu(r21, r17.new)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x22<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!cmp.gtu(r21, r2.new)) jump:t<br>+# CHECK-NEXT: if (!cmp.gtu(r21, r17.new)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x24<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (cmp.eq(r2.new, #21)) jump:nt<br>+# CHECK-NEXT: if (cmp.eq(r17.new, #21)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x24<br> # CHECK: r17 = r17<br>-# CHECK-NETX: if (cmp.eq(r2.new, #21)) jump:t<br>+# CHECK-NETX: if (cmp.eq(r17.new, #21)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x24<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!cmp.eq(r2.new, #21)) jump:nt<br>+# CHECK-NEXT: if (!cmp.eq(r17.new, #21)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x24<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!cmp.eq(r2.new, #21)) jump:t<br>+# CHECK-NEXT: if (!cmp.eq(r17.new, #21)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x24<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r2.new, #21)) jump:nt<br>+# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #21)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x24<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r2.new, #21)) jump:t<br>+# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #21)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x24<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r2.new, #21)) jump:nt<br>+# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #21)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x24<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r2.new, #21)) jump:t<br>+# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #21)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x25<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (cmp.gtu(r2.new, #21)) jump:nt<br>+# CHECK-NEXT: if (cmp.gtu(r17.new, #21)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x25<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (cmp.gtu(r2.new, #21)) jump:t<br>+# CHECK-NEXT: if (cmp.gtu(r17.new, #21)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x25<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!cmp.gtu(r2.new, #21)) jump:nt<br>+# CHECK-NEXT: if (!cmp.gtu(r17.new, #21)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x25<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!cmp.gtu(r2.new, #21)) jump:t<br>+# CHECK-NEXT: if (!cmp.gtu(r17.new, #21)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xc0 0x82 0x25<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (tstbit(r2.new, #0)) jump:nt<br>+# CHECK-NEXT: if (tstbit(r17.new, #0)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xe0 0x82 0x25<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (tstbit(r2.new, #0)) jump:t<br>+# CHECK-NEXT: if (tstbit(r17.new, #0)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xc0 0xc2 0x25<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!tstbit(r2.new, #0)) jump:nt<br>+# CHECK-NEXT: if (!tstbit(r17.new, #0)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xe0 0xc2 0x25<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!tstbit(r2.new, #0)) jump:t<br>+# CHECK-NEXT: if (!tstbit(r17.new, #0)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xc0 0x02 0x26<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (cmp.eq(r2.new, #-1)) jump:nt<br>+# CHECK-NEXT: if (cmp.eq(r17.new, #-1)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xe0 0x02 0x26<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (cmp.eq(r2.new, #-1)) jump:t<br>+# CHECK-NEXT: if (cmp.eq(r17.new, #-1)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xc0 0x42 0x26<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!cmp.eq(r2.new, #-1)) jump:nt<br>+# CHECK-NEXT: if (!cmp.eq(r17.new, #-1)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xe0 0x42 0x26<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!cmp.eq(r2.new, #-1)) jump:t<br>+# CHECK-NEXT: if (!cmp.eq(r17.new, #-1)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xc0 0x82 0x26<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r2.new, #-1)) jump:nt<br>+# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #-1)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xe0 0x82 0x26<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r2.new, #-1)) jump:t<br>+# CHECK-NEXT: if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #-1)) jump:t<br> 0x11 0x40 0x71 0x70 0x92 0xc0 0xc2 0x26<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r2.new, #-1)) jump:nt<br>+# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #-1)) jump:nt<br> 0x11 0x40 0x71 0x70 0x92 0xe0 0xc2 0x26<br> # CHECK: r17 = r17<br>-# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r2.new, #-1)) jump:t<br>+# CHECK-NEXT: if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #-1)) jump:t<br><br>Modified: llvm/trunk/test/MC/Disassembler/Hexagon/nv_st.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/nv_st.txt?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/nv_st.txt?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Disassembler/Hexagon/nv_st.txt (original)<br>+++ llvm/trunk/test/MC/Disassembler/Hexagon/nv_st.txt Sun Nov 8 22:07:48 2015<br>@@ -4,200 +4,209 @@<br> # Store new-value byte<br> 0x1f 0x40 0x7f 0x70 0x82 0xf5 0xb1 0x3b<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memb(r17 + r21<<#3) = r2.new<br>+# CHECK-NEXT: memb(r17 + r21<<#3) = r31.new<br>+0x1f 0x40 0x7f 0x70 0x11 0xc2 0xa0 0x48<br>+# CHECK: r31 = r31<br>+# CHECK-NEXT: memb(#17) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x15 0xc2 0xb1 0xa1<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memb(r17+#21) = r2.new<br>+# CHECK-NEXT: memb(r17+#21) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x02 0xe2 0xb1 0xa9<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memb(r17 ++ I:circ(m1)) = r2.new<br>+# CHECK-NEXT: memb(r17 ++ I:circ(m1)) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x28 0xe2 0xb1 0xa9<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memb(r17 ++ #5:circ(m1)) = r2.new<br>+# CHECK-NEXT: memb(r17 ++ #5:circ(m1)) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x28 0xc2 0xb1 0xab<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memb(r17++#5) = r2.new<br>+# CHECK-NEXT: memb(r17++#5) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x00 0xe2 0xb1 0xad<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memb(r17++m1) = r2.new<br>+# CHECK-NEXT: memb(r17++m1) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x00 0xe2 0xb1 0xaf<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memb(r17 ++ m1:brev) = r2.new<br>+# CHECK-NEXT: memb(r17 ++ m1:brev) = r31.new<br><br> # Store new-value byte conditionally<br> 0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (p3) memb(r17+r21<<#3) = r2.new<br>+# CHECK-NEXT: if (p3) memb(r17+r21<<#3) = r31.new<br> 0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x35<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (!p3) memb(r17+r21<<#3) = r2.new<br>+# CHECK-NEXT: if (!p3) memb(r17+r21<<#3) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x36<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (p3.new) memb(r17+r21<<#3) = r2.new<br>+# CHECK-NEXT: if (p3.new) memb(r17+r21<<#3) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x37<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (!p3.new) memb(r17+r21<<#3) = r2.new<br>+# CHECK-NEXT: if (!p3.new) memb(r17+r21<<#3) = r31.new<br> 0x1f 0x40 0x7f 0x70 0xab 0xc2 0xb1 0x40<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (p3) memb(r17+#21) = r2.new<br>+# CHECK-NEXT: if (p3) memb(r17+#21) = r31.new<br> 0x1f 0x40 0x7f 0x70 0xab 0xc2 0xb1 0x44<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (!p3) memb(r17+#21) = r2.new<br>+# CHECK-NEXT: if (!p3) memb(r17+#21) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xc2 0xb1 0x42<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (p3.new) memb(r17+#21) = r2.new<br>+# CHECK-NEXT: if (p3.new) memb(r17+#21) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xc2 0xb1 0x46<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (!p3.new) memb(r17+#21) = r2.new<br>+# CHECK-NEXT: if (!p3.new) memb(r17+#21) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x2b 0xe2 0xb1 0xab<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (p3) memb(r17++#5) = r2.new<br>+# CHECK-NEXT: if (p3) memb(r17++#5) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x2f 0xe2 0xb1 0xab<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (!p3) memb(r17++#5) = r2.new<br>+# CHECK-NEXT: if (!p3) memb(r17++#5) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xe2 0xb1 0xab<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (p3.new) memb(r17++#5) = r2.new<br>+# CHECK-NEXT: if (p3.new) memb(r17++#5) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xaf 0xe2 0xb1 0xab<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (!p3.new) memb(r17++#5) = r2.new<br>+# CHECK-NEXT: if (!p3.new) memb(r17++#5) = r31.new<br><br> # Store new-value halfword<br> 0x1f 0x40 0x7f 0x70 0x8a 0xf5 0xb1 0x3b<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memh(r17 + r21<<#3) = r2.new<br>+# CHECK-NEXT: memh(r17 + r21<<#3) = r31.new<br>+0x1f 0x40 0x7f 0x70 0x15 0xca 0xa0 0x48<br>+# CHECK: r31 = r31<br>+# CHECK-NEXT: memh(#42) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x15 0xca 0xb1 0xa1<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memh(r17+#42) = r2.new<br>+# CHECK-NEXT: memh(r17+#42) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x02 0xea 0xb1 0xa9<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memh(r17 ++ I:circ(m1)) = r2.new<br>+# CHECK-NEXT: memh(r17 ++ I:circ(m1)) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x28 0xea 0xb1 0xa9<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memh(r17 ++ #10:circ(m1)) = r2.new<br>+# CHECK-NEXT: memh(r17 ++ #10:circ(m1)) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x28 0xca 0xb1 0xab<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memh(r17++#10) = r2.new<br>+# CHECK-NEXT: memh(r17++#10) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x00 0xea 0xb1 0xad<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memh(r17++m1) = r2.new<br>+# CHECK-NEXT: memh(r17++m1) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x00 0xea 0xb1 0xaf<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memh(r17 ++ m1:brev) = r2.new<br>+# CHECK-NEXT: memh(r17 ++ m1:brev) = r31.new<br><br> # Store new-value halfword conditionally<br> 0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (p3) memh(r17+r21<<#3) = r2.new<br>+# CHECK-NEXT: if (p3) memh(r17+r21<<#3) = r31.new<br> 0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x35<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (!p3) memh(r17+r21<<#3) = r2.new<br>+# CHECK-NEXT: if (!p3) memh(r17+r21<<#3) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x36<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (p3.new) memh(r17+r21<<#3) = r2.new<br>+# CHECK-NEXT: if (p3.new) memh(r17+r21<<#3) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x37<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (!p3.new) memh(r17+r21<<#3) = r2.new<br>+# CHECK-NEXT: if (!p3.new) memh(r17+r21<<#3) = r31.new<br> 0x1f 0x40 0x7f 0x70 0xab 0xca 0xb1 0x40<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (p3) memh(r17+#42) = r2.new<br>+# CHECK-NEXT: if (p3) memh(r17+#42) = r31.new<br> 0x1f 0x40 0x7f 0x70 0xab 0xca 0xb1 0x44<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (!p3) memh(r17+#42) = r2.new<br>+# CHECK-NEXT: if (!p3) memh(r17+#42) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xca 0xb1 0x42<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (p3.new) memh(r17+#42) = r2.new<br>+# CHECK-NEXT: if (p3.new) memh(r17+#42) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xca 0xb1 0x46<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (!p3.new) memh(r17+#42) = r2.new<br>+# CHECK-NEXT: if (!p3.new) memh(r17+#42) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x2b 0xea 0xb1 0xab<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (p3) memh(r17++#10) = r2.new<br>+# CHECK-NEXT: if (p3) memh(r17++#10) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x2f 0xea 0xb1 0xab<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (!p3) memh(r17++#10) = r2.new<br>+# CHECK-NEXT: if (!p3) memh(r17++#10) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xea 0xb1 0xab<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (p3.new) memh(r17++#10) = r2.new<br>+# CHECK-NEXT: if (p3.new) memh(r17++#10) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xaf 0xea 0xb1 0xab<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (!p3.new) memh(r17++#10) = r2.new<br>+# CHECK-NEXT: if (!p3.new) memh(r17++#10) = r31.new<br><br> # Store new-value word<br> 0x1f 0x40 0x7f 0x70 0x92 0xf5 0xb1 0x3b<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memw(r17 + r21<<#3) = r2.new<br>-0x1f 0x40 0x7f 0x70 0x15 0xd2 0xb1 0xa1<br>+# CHECK-NEXT: memw(r17 + r21<<#3) = r31.new<br>+0x1f 0x40 0x7f 0x70 0x15 0xd2 0xa0 0x48<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memw(r17+#84) = r2.new<br>-0x1f 0x40 0x7f 0x70 0x28 0xf2 0xb1 0xa9<br>+# CHECK-NEXT: memw(#84) = r31.new<br>+0x1f 0x40 0x7f 0x70 0x15 0xd2 0xb1 0xa1<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memw(r17 ++ #20:circ(m1)) = r2.new<br>+# CHECK-NEXT: memw(r17+#84) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x02 0xf2 0xb1 0xa9<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memw(r17 ++ I:circ(m1)) = r2.new<br>+# CHECK-NEXT: memw(r17 ++ I:circ(m1)) = r31.new<br>+0x1f 0x40 0x7f 0x70 0x28 0xf2 0xb1 0xa9<br>+# CHECK: r31 = r31<br>+# CHECK-NEXT: memw(r17 ++ #20:circ(m1)) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x28 0xd2 0xb1 0xab<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memw(r17++#20) = r2.new<br>+# CHECK-NEXT: memw(r17++#20) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x00 0xf2 0xb1 0xad<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memw(r17++m1) = r2.new<br>+# CHECK-NEXT: memw(r17++m1) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x00 0xf2 0xb1 0xaf<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: memw(r17 ++ m1:brev) = r2.new<br>+# CHECK-NEXT: memw(r17 ++ m1:brev) = r31.new<br><br> # Store new-value word conditionally<br> 0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (p3) memw(r17+r21<<#3) = r2.new<br>+# CHECK-NEXT: if (p3) memw(r17+r21<<#3) = r31.new<br> 0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x35<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (!p3) memw(r17+r21<<#3) = r2.new<br>+# CHECK-NEXT: if (!p3) memw(r17+r21<<#3) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x36<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (p3.new) memw(r17+r21<<#3) = r2.new<br>+# CHECK-NEXT: if (p3.new) memw(r17+r21<<#3) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x37<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (!p3.new) memw(r17+r21<<#3) = r2.new<br>+# CHECK-NEXT: if (!p3.new) memw(r17+r21<<#3) = r31.new<br> 0x1f 0x40 0x7f 0x70 0xab 0xd2 0xb1 0x40<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (p3) memw(r17+#84) = r2.new<br>+# CHECK-NEXT: if (p3) memw(r17+#84) = r31.new<br> 0x1f 0x40 0x7f 0x70 0xab 0xd2 0xb1 0x44<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (!p3) memw(r17+#84) = r2.new<br>+# CHECK-NEXT: if (!p3) memw(r17+#84) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xd2 0xb1 0x42<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (p3.new) memw(r17+#84) = r2.new<br>+# CHECK-NEXT: if (p3.new) memw(r17+#84) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xd2 0xb1 0x46<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (!p3.new) memw(r17+#84) = r2.new<br>+# CHECK-NEXT: if (!p3.new) memw(r17+#84) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x2b 0xf2 0xb1 0xab<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (p3) memw(r17++#20) = r2.new<br>+# CHECK-NEXT: if (p3) memw(r17++#20) = r31.new<br> 0x1f 0x40 0x7f 0x70 0x2f 0xf2 0xb1 0xab<br> # CHECK: r31 = r31<br>-# CHECK-NEXT: if (!p3) memw(r17++#20) = r2.new<br>+# CHECK-NEXT: if (!p3) memw(r17++#20) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xf2 0xb1 0xab<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (p3.new) memw(r17++#20) = r2.new<br>+# CHECK-NEXT: if (p3.new) memw(r17++#20) = r31.new<br> 0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xaf 0xf2 0xb1 0xab<br> # CHECK: p3 = r5<br> # CHECK-NEXT: r31 = r31<br>-# CHECK-NEXT: if (!p3.new) memw(r17++#20) = r2.new<br>+# CHECK-NEXT: if (!p3.new) memw(r17++#20) = r31.new<br><br>Modified: llvm/trunk/test/MC/Disassembler/Hexagon/st.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/st.txt?rev=252443&r1=252442&r2=252443&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/st.txt?rev=252443&r1=252442&r2=252443&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Disassembler/Hexagon/st.txt (original)<br>+++ llvm/trunk/test/MC/Disassembler/Hexagon/st.txt Sun Nov 8 22:07:48 2015<br>@@ -1,11 +1,14 @@<br> # RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s<br> # Hexagon Programmer's Reference Manual 11.8 ST<br>+# XFAIL: *<br><br> # Store doubleword<br> 0x9e 0xf5 0xd1 0x3b<br> # CHECK: memd(r17 + r21<<#3) = r31:30<br> 0x28 0xd4 0xc0 0x48<br>-# CHECK: memd(##320) = r21:20<br>+# CHECK: memd(#320) = r21:20<br>+0x02 0x40 0x00 0x00 0x28 0xd4 0xc0 0x48<br>+# CHECK: memd(##168) = r21:20<br> 0x15 0xd4 0xd1 0xa1<br> # CHECK: memd(r17+#168) = r21:20<br> 0x02 0xf4 0xd1 0xa9<br>@@ -14,6 +17,8 @@<br> # CHECK: memd(r17 ++ #40:circ(m1)) = r21:20<br> 0x28 0xd4 0xd1 0xab<br> # CHECK: memd(r17++#40) = r21:20<br>+0x00 0x40 0x00 0x00 0xd5 0xfe 0xd1 0xad<br>+# CHECK: memd(r17<<#3 + ##21) = r31:30<br> 0x00 0xf4 0xd1 0xad<br> # CHECK: memd(r17++m1) = r21:20<br> 0x00 0xf4 0xd1 0xaf<br>@@ -50,6 +55,16 @@<br> 0x03 0x40 0x45 0x85 0xaf 0xf4 0xd1 0xab<br> # CHECK: p3 = r5<br> # CHECK-NEXT: if (!p3.new) memd(r17++#40) = r21:20<br>+0x02 0x40 0x00 0x00 0xc3 0xd4 0xc2 0xaf<br>+# CHECK: if (p3) memd(##168) = r21:20<br>+0x02 0x40 0x00 0x00 0xc7 0xd4 0xc2 0xaf<br>+# CHECK: if (!p3) memd(##168) = r21:20<br>+0x03 0x40 0x45 0x85 0x02 0x40 0x00 0x00 0xc3 0xf4 0xc2 0xaf<br>+# CHECK: p3 = r5<br>+# CHECK-NEXT: if (p3.new) memd(##168) = r21:20<br>+0x03 0x40 0x45 0x85 0x02 0x40 0x00 0x00 0xc7 0xf4 0xc2 0xaf<br>+# CHECK: p3 = r5<br>+# CHECK-NEXT: if (!p3.new) memd(##168) = r21:20<br><br> # Store byte<br> 0x9f 0xf5 0x11 0x3b<br>@@ -57,6 +72,8 @@<br> 0x9f 0xca 0x11 0x3c<br> # CHECK: memb(r17+#21)=#31<br> 0x15 0xd5 0x00 0x48<br>+# CHECK: memb(#21) = r21<br>+0x00 0x40 0x00 0x00 0x15 0xd5 0x00 0x48<br> # CHECK: memb(##21) = r21<br> 0x15 0xd5 0x11 0xa1<br> # CHECK: memb(r17+#21) = r21<br>@@ -66,6 +83,8 @@<br> # CHECK: memb(r17 ++ #5:circ(m1)) = r21<br> 0x28 0xd5 0x11 0xab<br> # CHECK: memb(r17++#5) = r21<br>+0x00 0x40 0x00 0x00 0xd5 0xff 0x11 0xad<br>+# CHECK: memb(r17<<#3 + ##21) = r31<br> 0x00 0xf5 0x11 0xad<br> # CHECK: memb(r17++m1) = r21<br> 0x00 0xf5 0x11 0xaf<br>@@ -112,6 +131,16 @@<br> 0x03 0x40 0x45 0x85 0xaf 0xf5 0x11 0xab<br> # CHECK: p3 = r5<br> # CHECK-NEXT: if (!p3.new) memb(r17++#5) = r21<br>+0x00 0x40 0x00 0x00 0xab 0xd5 0x01 0xaf<br>+# CHECK: if (p3) memb(##21) = r21<br>+0x00 0x40 0x00 0x00 0xaf 0xd5 0x01 0xaf<br>+# CHECK: if (!p3) memb(##21) = r21<br>+0x03 0x40 0x45 0x85 0x00 0x40 0x00 0x00 0xab 0xf5 0x01 0xaf<br>+# CHECK: p3 = r5<br>+# CHECK-NEXT: if (p3.new) memb(##21) = r21<br>+0x03 0x40 0x45 0x85 0x00 0x40 0x00 0x00 0xaf 0xf5 0x01 0xaf<br>+# CHECK: p3 = r5<br>+# CHECK-NEXT: if (!p3.new) memb(##21) = r21<br><br> # Store halfword<br> 0x9f 0xf5 0x51 0x3b<br>@@ -120,10 +149,14 @@<br> # CHECK: memh(r17 + r21<<#3) = r31.h<br> 0x95 0xcf 0x31 0x3c<br> # CHECK: memh(r17+#62)=#21<br>+0x00 0x40 0x00 0x00 0x2a 0xd5 0x40 0x48<br>+# CHECK: memh(##42) = r21<br>+0x00 0x40 0x00 0x00 0x2a 0xd5 0x60 0x48<br>+# CHECK: memh(##42) = r21.h<br> 0x2a 0xd5 0x40 0x48<br>-# CHECK: memh(##84) = r21<br>+# CHECK: memh(#84) = r21<br> 0x2a 0xd5 0x60 0x48<br>-# CHECK: memh(##84) = r21.h<br>+# CHECK: memh(#84) = r21.h<br> 0x15 0xdf 0x51 0xa1<br> # CHECK: memh(r17+#42) = r31<br> 0x15 0xdf 0x71 0xa1<br>@@ -138,8 +171,12 @@<br> # CHECK: memh(r17 ++ #10:circ(m1)) = r21.h<br> 0x28 0xd5 0x51 0xab<br> # CHECK: memh(r17++#10) = r21<br>+0x00 0x40 0x00 0x00 0xd5 0xff 0x51 0xad<br>+# CHECK: memh(r17<<#3 + ##21) = r31<br> 0x28 0xd5 0x71 0xab<br> # CHECK: memh(r17++#10) = r21.h<br>+0x00 0x40 0x00 0x00 0xd5 0xff 0x71 0xad<br>+# CHECK: memh(r17<<#3 + ##21) = r31.h<br> 0x00 0xf5 0x51 0xad<br> # CHECK: memh(r17++m1) = r21<br> 0x00 0xf5 0x71 0xad<br>@@ -220,22 +257,48 @@<br> 0x03 0x40 0x45 0x85 0xaf 0xf5 0x71 0xab<br> # CHECK: p3 = r5<br> # CHECK-NEXT: if (!p3.new) memh(r17++#10) = r21.h<br>+0x00 0x40 0x00 0x00 0xd3 0xd5 0x42 0xaf<br>+# CHECK: if (p3) memh(##42) = r21<br>+0x00 0x40 0x00 0x00 0xd3 0xd5 0x62 0xaf<br>+# CHECK: if (p3) memh(##42) = r21.h<br>+0x00 0x40 0x00 0x00 0xd7 0xd5 0x42 0xaf<br>+# CHECK: if (!p3) memh(##42) = r21<br>+0x00 0x40 0x00 0x00 0xd7 0xd5 0x62 0xaf<br>+# CHECK: if (!p3) memh(##42) = r21.h<br>+0x03 0x40 0x45 0x85 0x00 0x40 0x00 0x00 0xd3 0xf5 0x42 0xaf<br>+# CHECK: p3 = r5<br>+# CHECK-NEXT: if (p3.new) memh(##42) = r21<br>+0x03 0x40 0x45 0x85 0x00 0x40 0x00 0x00 0xd3 0xf5 0x62 0xaf<br>+# CHECK: p3 = r5<br>+# CHECK-NEXT: if (p3.new) memh(##42) = r21.h<br>+0x03 0x40 0x45 0x85 0x00 0x40 0x00 0x00 0xd7 0xf5 0x42 0xaf<br>+# CHECK: p3 = r5<br>+# CHECK-NEXT: if (!p3.new) memh(##42) = r21<br>+0x03 0x40 0x45 0x85 0x00 0x40 0x00 0x00 0xd7 0xf5 0x62 0xaf<br>+# CHECK: p3 = r5<br>+# CHECK-NEXT: if (!p3.new) memh(##42) = r21.h<br><br> # Store word<br> 0x9f 0xf5 0x91 0x3b<br> # CHECK: memw(r17 + r21<<#3) = r31<br> 0x9f 0xca 0x51 0x3c<br>+# CHECK: memw(r17{{ *}}+{{ *}}#84)=#31<br>+0x15 0xdf 0x80 0x48<br>+# CHECK: memw(#84) = r31<br>+0x01 0x40 0x00 0x00 0x14 0xd5 0x80 0x48<br>+# CHECK: memw(##84) = r21<br>+0x9f 0xca 0x51 0x3c<br> # CHECK: memw(r17+#84)=#31<br> 0x15 0xdf 0x91 0xa1<br> # CHECK: memw(r17+#84) = r31<br>-0x14 0xd5 0x80 0x48<br>-# CHECK: memw(##80) = r21<br> 0x02 0xf5 0x91 0xa9<br> # CHECK: memw(r17 ++ I:circ(m1)) = r21<br> 0x28 0xf5 0x91 0xa9<br> # CHECK: memw(r17 ++ #20:circ(m1)) = r21<br> 0x28 0xd5 0x91 0xab<br> # CHECK: memw(r17++#20) = r21<br>+0x00 0x40 0x00 0x00 0xd5 0xff 0x91 0xad<br>+# CHECK: memw(r17<<#3 + ##21) = r31<br> 0x00 0xf5 0x91 0xad<br> # CHECK: memw(r17++m1) = r21<br> 0x00 0xf5 0x91 0xaf<br>@@ -282,7 +345,17 @@<br> 0x03 0x40 0x45 0x85 0xab 0xf5 0x91 0xab<br> # CHECK: p3 = r5<br> # CHECK-NEXT: if (p3.new) memw(r17++#20) = r21<br>+0x01 0x40 0x00 0x00 0xa3 0xd5 0x81 0xaf<br>+# CHECK: if (p3) memw(##84) = r21<br>+0x01 0x40 0x00 0x00 0xa7 0xd5 0x81 0xaf<br>+# CHECK: if (!p3) memw(##84) = r21<br>+0x03 0x40 0x45 0x85 0x01 0x40 0x00 0x00 0xa3 0xf5 0x81 0xaf<br>+# CHECK: p3 = r5<br>+# CHECK-NEXT: if (p3.new) memw(##84) = r21<br>+0x03 0x40 0x45 0x85 0x01 0x40 0x00 0x00 0xa7 0xf5 0x81 0xaf<br>+# CHECK: p3 = r5<br>+# CHECK-NEXT: if (!p3.new) memw(##84) = r21<br><br> # Allocate stack frame<br> 0x1f 0xc0 0x9d 0xa0<br>-# CHECK: allocframe(#248)<br>\ No newline at end of file<br>+# CHECK: allocframe(#248)<br><br>Added: llvm/trunk/test/MC/Disassembler/Hexagon/too_many_instructions.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/too_many_instructions.txt?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/too_many_instructions.txt?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Disassembler/Hexagon/too_many_instructions.txt (added)<br>+++ llvm/trunk/test/MC/Disassembler/Hexagon/too_many_instructions.txt Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,4 @@<br>+# RUN: llvm-mc -triple=hexagon -disassemble < %s 2>&1 | FileCheck %s<br>+<br>+#CHECK: warning: invalid instruction encoding<br>+0x00 0x40 0x00 0x7f 0x00 0x40 0x00 0x7f 0x00 0x40 0x00 0x7f 0x00 0x40 0x00 0x7f 0x00 0xc0 0x00 0x7f<br>\ No newline at end of file<br><br>Added: llvm/trunk/test/MC/Disassembler/Hexagon/too_many_loop_ends.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/too_many_loop_ends.txt?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/too_many_loop_ends.txt?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Disassembler/Hexagon/too_many_loop_ends.txt (added)<br>+++ llvm/trunk/test/MC/Disassembler/Hexagon/too_many_loop_ends.txt Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,4 @@<br>+# RUN: llvm-mc -triple=hexagon -disassemble < %s 2>&1 | FileCheck %s<br>+<br>+#CHECK: warning: invalid instruction encoding<br>+0x00 0x80 0x00 0x7f 0x00 0x80 0x00 0x7f 0x00 0x80 0x00 0x7f 0x00 0xc0 0x00 0x7f<br>\ No newline at end of file<br><br>Added: llvm/trunk/test/MC/Disassembler/Hexagon/unextendable.txt<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/unextendable.txt?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/unextendable.txt?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Disassembler/Hexagon/unextendable.txt (added)<br>+++ llvm/trunk/test/MC/Disassembler/Hexagon/unextendable.txt Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,9 @@<br>+# RUN: llvm-mc -triple=hexagon -disassemble < %s 2>&1 | FileCheck %s<br>+<br>+#Invalid immediate extend duplex load/load<br>+#CHECK: warning: invalid instruction encoding<br>+0xfe 0x40 0x00 0x00 0x11 0x00 0x00 0x00<br>+<br>+#Invalid immediate extend barrier<br>+#CHECK: warning: invalid instruction encoding<br>+0xfe 0x40 0x00 0x00 0x00 0xc0 0x00 0xa8<br>\ No newline at end of file<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/alu32_alu.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/alu32_alu.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/alu32_alu.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/alu32_alu.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/alu32_alu.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,84 @@<br>+# RUN: llvm-mc -triple hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.1.1 ALU32/ALU<br>+<br>+# Add<br>+# CHECK: f1 c3 15 b0<br>+r17 = add(r21, #31)<br>+# CHECK: 11 df 15 f3<br>+r17 = add(r21, r31)<br>+# CHECK: 11 df 55 f6<br>+r17 = add(r21, r31):sat<br>+<br>+# And<br>+# CHECK: f1 c3 15 76<br>+r17 = and(r21, #31)<br>+# CHECK: f1 c3 95 76<br>+r17 = or(r21, #31)<br>+# CHECK: 11 df 15 f1<br>+r17 = and(r21, r31)<br>+# CHECK: 11 df 35 f1<br>+r17 = or(r21, r31)<br>+# CHECK: 11 df 75 f1<br>+r17 = xor(r21, r31)<br>+# CHECK: 11 d5 9f f1<br>+r17 = and(r21, ~r31)<br>+# CHECK: 11 d5 bf f1<br>+r17 = or(r21, ~r31)<br>+<br>+# Nop<br>+# CHECK: 00 c0 00 7f<br>+nop<br>+<br>+# Subtract<br>+# CHECK: b1 c2 5f 76<br>+r17 = sub(#21, r31)<br>+# CHECK: 11 df 35 f3<br>+r17 = sub(r31, r21)<br>+# CHECK: 11 df d5 f6<br>+r17 = sub(r31, r21):sat<br>+<br>+# Sign extend<br>+# CHECK: 11 c0 bf 70<br>+r17 = sxtb(r31)<br>+<br>+# Transfer immediate<br>+# CHECK: 15 c0 31 72<br>+r17.h = #21<br>+# CHECK: 15 c0 31 71<br>+r17.l = #21<br>+# CHECK: f1 ff 5f 78<br>+r17 = #32767<br>+# CHECK: f1 ff df 78<br>+r17 = #-1<br>+<br>+# Transfer register<br>+# CHECK: 11 c0 75 70<br>+r17 = r21<br>+<br>+# Vector add halfwords<br>+# CHECK: 11 df 15 f6<br>+r17 = vaddh(r21, r31)<br>+# CHECK: 11 df 35 f6<br>+r17 = vaddh(r21, r31):sat<br>+# CHECK: 11 df 75 f6<br>+r17 = vadduh(r21, r31):sat<br>+<br>+# Vector average halfwords<br>+# CHECK: 11 df 15 f7<br>+r17 = vavgh(r21, r31)<br>+# CHECK: 11 df 35 f7<br>+r17 = vavgh(r21, r31):rnd<br>+# CHECK: 11 df 75 f7<br>+r17 = vnavgh(r31, r21)<br>+<br>+# Vector subtract halfwords<br>+# CHECK: 11 df 95 f6<br>+r17 = vsubh(r31, r21)<br>+# CHECK: 11 df b5 f6<br>+r17 = vsubh(r31, r21):sat<br>+# CHECK: 11 df f5 f6<br>+r17 = vsubuh(r31, r21):sat<br>+<br>+# Zero extend<br>+# CHECK: 11 c0 d5 70<br>+r17 = zxth(r21)<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/alu32_perm.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/alu32_perm.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/alu32_perm.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/alu32_perm.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/alu32_perm.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,40 @@<br>+# RUN: llvm-mc -triple hexagon -filetype=obj %s -o - | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM<br>+<br>+# Combine words in to doublewords<br>+# CHECK: 11 df 95 f3<br>+r17 = combine(r31.h, r21.h)<br>+# CHECK: 11 df b5 f3<br>+r17 = combine(r31.h, r21.l)<br>+# CHECK: 11 df d5 f3<br>+r17 = combine(r31.l, r21.h)<br>+# CHECK: 11 df f5 f3<br>+r17 = combine(r31.l, r21.l)<br>+# CHECK: b0 e2 0f 7c<br>+r17:16 = combine(#21, #31)<br>+# CHECK: b0 e2 3f 73<br>+r17:16 = combine(#21, r31)<br>+# CHECK: f0 e3 15 73<br>+r17:16 = combine(r21, #31)<br>+# CHECK: 10 df 15 f5<br>+r17:16 = combine(r21, r31)<br>+<br>+# Mux<br>+# CHECK: f1 c3 75 73<br>+r17 = mux(p3, r21, #31)<br>+# CHECK: b1 c2 ff 73<br>+r17 = mux(p3, #21, r31)<br>+# CHECK: b1 e2 8f 7b<br>+r17 = mux(p3, #21, #31)<br>+# CHECK: 71 df 15 f4<br>+r17 = mux(p3, r21, r31)<br>+<br>+# Shift word by 16<br>+# CHECK: 11 c0 15 70<br>+r17 = aslh(r21)<br>+# CHECK: 11 c0 35 70<br>+r17 = asrh(r21)<br>+<br>+# Pack high and low halfwords<br>+# CHECK: 10 df 95 f5<br>+r17:16 = packhl(r21, r31)<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/alu32_pred.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/alu32_pred.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/alu32_pred.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/alu32_pred.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/alu32_pred.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,222 @@<br>+# RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.1.3 ALU32/PRED<br>+<br>+# Conditional add<br>+# CHECK: f1 c3 75 74<br>+if (p3) r17 = add(r21, #31)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 e3 75 74<br>+{ p3 = r5<br>+ if (p3.new) r17 = add(r21, #31) }<br>+# CHECK: f1 c3 f5 74<br>+if (!p3) r17 = add(r21, #31)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 e3 f5 74<br>+{ p3 = r5<br>+ if (!p3.new) r17 = add(r21, #31) }<br>+# CHECK: 71 df 15 fb<br>+if (p3) r17 = add(r21, r31)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 71 ff 15 fb<br>+{ p3 = r5<br>+ if (p3.new) r17 = add(r21, r31) }<br>+# CHECK: f1 df 15 fb<br>+if (!p3) r17 = add(r21, r31)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 15 fb<br>+{ p3 = r5<br>+ if (!p3.new) r17 = add(r21, r31) }<br>+<br>+# Conditional shift halfword<br>+# CHECK: 11 e3 15 70<br>+if (p3) r17 = aslh(r21)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 11 e7 15 70<br>+{ p3 = r5<br>+ if (p3.new) r17 = aslh(r21) }<br>+# CHECK: 11 eb 15 70<br>+if (!p3) r17 = aslh(r21)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 11 ef 15 70<br>+{ p3 = r5<br>+ if (!p3.new) r17 = aslh(r21) }<br>+# CHECK: 11 e3 35 70<br>+if (p3) r17 = asrh(r21)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 11 e7 35 70<br>+{ p3 = r5<br>+ if (p3.new) r17 = asrh(r21) }<br>+# CHECK: 11 eb 35 70<br>+if (!p3) r17 = asrh(r21)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 11 ef 35 70<br>+{ p3 = r5<br>+ if (!p3.new) r17 = asrh(r21) }<br>+<br>+# Conditional combine<br>+# CHECK: 70 df 15 fd<br>+if (p3) r17:16 = combine(r21, r31)<br>+# CHECK: f0 df 15 fd<br>+if (!p3) r17:16 = combine(r21, r31)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 70 ff 15 fd<br>+{ p3 = r5<br>+ if (p3.new) r17:16 = combine(r21, r31) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f0 ff 15 fd<br>+{ p3 = r5<br>+ if (!p3.new) r17:16 = combine(r21, r31) }<br>+<br>+# Conditional logical operations<br>+# CHECK: 71 df 15 f9<br>+if (p3) r17 = and(r21, r31)<br>+# CHECK: f1 df 15 f9<br>+if (!p3) r17 = and(r21, r31)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 71 ff 15 f9<br>+{ p3 = r5<br>+ if (p3.new) r17 = and(r21, r31) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 15 f9<br>+{ p3 = r5<br>+ if (!p3.new) r17 = and(r21, r31) }<br>+# CHECK: 71 df 35 f9<br>+if (p3) r17 = or(r21, r31)<br>+# CHECK: f1 df 35 f9<br>+if (!p3) r17 = or(r21, r31)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 71 ff 35 f9<br>+{ p3 = r5<br>+ if (p3.new) r17 = or(r21, r31) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 35 f9<br>+{ p3 = r5<br>+ if (!p3.new) r17 = or(r21, r31) }<br>+# CHECK: 71 df 75 f9<br>+if (p3) r17 = xor(r21, r31)<br>+# CHECK: f1 df 75 f9<br>+if (!p3) r17 = xor(r21, r31)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 71 ff 75 f9<br>+{ p3 = r5<br>+ if (p3.new) r17 = xor(r21, r31) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 75 f9<br>+{ p3 = r5<br>+ if (!p3.new) r17 = xor(r21, r31) }<br>+<br>+# Conditional subtract<br>+# CHECK: 71 df 35 fb<br>+if (p3) r17 = sub(r31, r21)<br>+# CHECK: f1 df 35 fb<br>+if (!p3) r17 = sub(r31, r21)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 71 ff 35 fb<br>+{ p3 = r5<br>+ if (p3.new) r17 = sub(r31, r21) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 35 fb<br>+{ p3 = r5<br>+ if (!p3.new) r17 = sub(r31, r21) }<br>+<br>+# Conditional sign extend<br>+# CHECK: 11 e3 b5 70<br>+if (p3) r17 = sxtb(r21)<br>+# CHECK: 11 eb b5 70<br>+if (!p3) r17 = sxtb(r21)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 11 e7 b5 70<br>+{ p3 = r5<br>+ if (p3.new) r17 = sxtb(r21) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 11 ef b5 70<br>+{ p3 = r5<br>+ if (!p3.new) r17 = sxtb(r21) }<br>+# CHECK: 11 e3 f5 70<br>+if (p3) r17 = sxth(r21)<br>+# CHECK: 11 eb f5 70<br>+if (!p3) r17 = sxth(r21)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 11 e7 f5 70<br>+{ p3 = r5<br>+ if (p3.new) r17 = sxth(r21) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 11 ef f5 70<br>+{ p3 = r5<br>+ if (!p3.new) r17 = sxth(r21) }<br>+<br>+# Conditional transfer<br>+# CHECK: b1 c2 60 7e<br>+if (p3) r17 = #21<br>+# CHECK: b1 c2 e0 7e<br>+if (!p3) r17 = #21<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 e2 60 7e<br>+{ p3 = r5<br>+ if (p3.new) r17 = #21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 e2 e0 7e<br>+{ p3 = r5<br>+ if (!p3.new) r17 = #21 }<br>+<br>+# Conditional zero extend<br>+# CHECK: 11 e3 95 70<br>+if (p3) r17 = zxtb(r21)<br>+# CHECK: 11 eb 95 70<br>+if (!p3) r17 = zxtb(r21)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 11 e7 95 70<br>+{ p3 = r5<br>+ if (p3.new) r17 = zxtb(r21) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 11 ef 95 70<br>+{ p3 = r5<br>+ if (!p3.new) r17 = zxtb(r21) }<br>+# CHECK: 11 e3 d5 70<br>+if (p3) r17 = zxth(r21)<br>+# CHECK: 11 eb d5 70<br>+if (!p3) r17 = zxth(r21)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 11 e7 d5 70<br>+{ p3 = r5<br>+ if (p3.new) r17 = zxth(r21) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 11 ef d5 70<br>+{ p3 = r5<br>+ if (!p3.new) r17 = zxth(r21) }<br>+<br>+# Compare<br>+# CHECK: e3 c3 15 75<br>+p3 = cmp.eq(r21, #31)<br>+# CHECK: f3 c3 15 75<br>+p3 = !cmp.eq(r21, #31)<br>+# CHECK: e3 c3 55 75<br>+p3 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, #31)<br>+# CHECK: f3 c3 55 75<br>+p3 = !<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, #31)<br>+# CHECK: e3 c3 95 75<br>+p3 = cmp.gtu(r21, #31)<br>+# CHECK: f3 c3 95 75<br>+p3 = !cmp.gtu(r21, #31)<br>+# CHECK: 03 df 15 f2<br>+p3 = cmp.eq(r21, r31)<br>+# CHECK: 13 df 15 f2<br>+p3 = !cmp.eq(r21, r31)<br>+# CHECK: 03 df 55 f2<br>+p3 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r31)<br>+# CHECK: 13 df 55 f2<br>+p3 = !<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r31)<br>+# CHECK: 03 df 75 f2<br>+p3 = cmp.gtu(r21, r31)<br>+# CHECK: 13 df 75 f2<br>+p3 = !cmp.gtu(r21, r31)<br>+<br>+# Compare to general register<br>+# CHECK: f1 e3 55 73<br>+r17 = cmp.eq(r21, #31)<br>+# CHECK: f1 e3 75 73<br>+r17 = !cmp.eq(r21, #31)<br>+# CHECK: 11 df 55 f3<br>+r17 = cmp.eq(r21, r31)<br>+# CHECK: 11 df 75 f3<br>+r17 = !cmp.eq(r21, r31)<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/cr.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/cr.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/cr.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/cr.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/cr.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,78 @@<br>+# RUN: llvm-mc --triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.2 CR<br>+<br>+# Corner detection acceleration<br>+# CHECK: 93 e1 12 6b<br>+p3 = !fastcorner9(p2, p1)<br>+# CHECK: 91 e3 02 6b<br>+p1 = fastcorner9(p2, p3)<br>+<br>+# Logical reductions on predicates<br>+# CHECK: 01 c0 82 6b<br>+p1 = any8(p2)<br>+# CHECK: 01 c0 a2 6b<br>+p1 = all8(p2)<br>+<br>+# Looping instructions<br>+# CHECK: 00 c0 15 60<br>+loop0(0, r21)<br>+# CHECK: 00 c0 35 60<br>+loop1(0, r21)<br>+# CHECK: 60 c0 00 69<br>+loop0(0, #12)<br>+# CHECK: 60 c0 20 69<br>+loop1(0, #12)<br>+<br>+# Add to PC<br>+# CHECK: 91 ca 49 6a<br>+r17 = add(pc, #21)<br>+<br>+# Pipelined loop instructions<br>+# CHECK: 00 c0 b5 60<br>+p3 = sp1loop0(0, r21)<br>+# CHECK: 00 c0 d5 60<br>+p3 = sp2loop0(0, r21)<br>+# CHECK: 00 c0 f5 60<br>+p3 = sp3loop0(0, r21)<br>+# CHECK: a1 c0 a0 69<br>+p3 = sp1loop0(0, #21)<br>+# CHECK: a1 c0 c0 69<br>+p3 = sp2loop0(0, #21)<br>+# CHECK: a1 c0 e0 69<br>+p3 = sp3loop0(0, #21)<br>+<br>+# Logical operations on predicates<br>+# CHECK: 01 c3 02 6b<br>+p1 = and(p3, p2)<br>+# CHECK: c1 c3 12 6b<br>+p1 = and(p2, and(p3, p3))<br>+# CHECK: 01 c3 22 6b<br>+p1 = or(p3, p2)<br>+# CHECK: c1 c3 32 6b<br>+p1 = and(p2, or(p3, p3))<br>+# CHECK: 01 c3 42 6b<br>+p1 = xor(p2, p3)<br>+# CHECK: c1 c3 52 6b<br>+p1 = or(p2, and(p3, p3))<br>+# CHECK: 01 c2 63 6b<br>+p1 = and(p2, !p3)<br>+# CHECK: c1 c3 72 6b<br>+p1 = or(p2, or(p3, p3))<br>+# CHECK: c1 c3 92 6b<br>+p1 = and(p2, and(p3, !p3))<br>+# CHECK: c1 c3 b2 6b<br>+p1 = and(p2, or(p3, !p3))<br>+# CHECK: 01 c0 c2 6b<br>+p1 = not(p2)<br>+# CHECK: c1 c3 d2 6b<br>+p1 = or(p2, and(p3, !p3))<br>+# CHECK: 01 c2 e3 6b<br>+p1 = or(p2, !p3)<br>+# CHECK: c1 c3 f2 6b<br>+p1 = or(p2, or(p3, !p3))<br>+<br>+# User control register transfer<br>+# CHECK: 0d c0 35 62<br>+cs1 = r21<br>+# CHECK: 11 c0 0d 6a<br>+r17 = cs1<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/j.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/j.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/j.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/j.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/j.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,207 @@<br>+# RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.4 J<br>+# XFAIL: *<br>+<br>+# Call subroutine<br>+# CHECK: 00 c0 00 5a<br>+call 0<br>+# CHECK: 00 c3 00 5d<br>+if (p3) call 0<br>+# CHECK: 00 c3 20 5d<br>+if (!p3) call 0<br>+<br>+# Compare and jump<br>+# CHECK: 00 c0 89 11<br>+{ p0 = cmp.eq(r17,#-1); if (p0.new) jump:nt 0 }<br>+# CHECK: 00 c1 89 11<br>+{ p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (p0.new) jump:nt 0 }<br>+# CHECK: 00 c3 89 11<br>+{ p0 = tstbit(r17, #0); if (p0.new) jump:nt 0 }<br>+# CHECK: 00 e0 89 11<br>+{ p0 = cmp.eq(r17,#-1); if (p0.new) jump:t 0 }<br>+# CHECK: 00 e1 89 11<br>+{ p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (p0.new) jump:t 0 }<br>+# CHECK: 00 e3 89 11<br>+{ p0 = tstbit(r17, #0); if (p0.new) jump:t 0 }<br>+# CHECK: 00 c0 c9 11<br>+{ p0 = cmp.eq(r17,#-1); if (!p0.new) jump:nt 0 }<br>+# CHECK: 00 c1 c9 11<br>+{ p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (!p0.new) jump:nt 0 }<br>+# CHECK: 00 c3 c9 11<br>+{ p0 = tstbit(r17, #0); if (!p0.new) jump:nt 0 }<br>+# CHECK: 00 e0 c9 11<br>+{ p0 = cmp.eq(r17,#-1); if (!p0.new) jump:t 0 }<br>+# CHECK: 00 e1 c9 11<br>+{ p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (!p0.new) jump:t 0 }<br>+# CHECK: 00 e3 c9 11<br>+{ p0 = tstbit(r17, #0); if (!p0.new) jump:t 0 }<br>+# CHECK: 00 d5 09 10<br>+{ p0 = cmp.eq(r17, #21); if (p0.new) jump:nt 0 }<br>+# CHECK: 00 f5 09 10<br>+{ p0 = cmp.eq(r17, #21); if (p0.new) jump:t 0 }<br>+# CHECK: 00 d5 49 10<br>+{ p0 = cmp.eq(r17, #21); if (!p0.new) jump:nt 0 }<br>+# CHECK: 00 f5 49 10<br>+{ p0 = cmp.eq(r17, #21); if (!p0.new) jump:t 0 }<br>+# CHECK: 00 d5 89 10<br>+{ p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (p0.new) jump:nt 0 }<br>+# CHECK: 00 f5 89 10<br>+{ p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (p0.new) jump:t 0 }<br>+# CHECK: 00 d5 c9 10<br>+{ p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (!p0.new) jump:nt 0 }<br>+# CHECK: 00 f5 c9 10<br>+{ p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (!p0.new) jump:t 0 }<br>+# CHECK: 00 d5 09 11<br>+{ p0 = cmp.gtu(r17, #21); if (p0.new) jump:nt 0 }<br>+# CHECK: 00 f5 09 11<br>+{ p0 = cmp.gtu(r17, #21); if (p0.new) jump:t 0 }<br>+# CHECK: 00 d5 49 11<br>+{ p0 = cmp.gtu(r17, #21); if (!p0.new) jump:nt 0 }<br>+# CHECK: 00 f5 49 11<br>+{ p0 = cmp.gtu(r17, #21); if (!p0.new) jump:t 0 }<br>+# CHECK: 00 c0 89 13<br>+{ p1 = cmp.eq(r17,#-1); if (p1.new) jump:nt 0 }<br>+# CHECK: 00 c1 89 13<br>+{ p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (p1.new) jump:nt 0 }<br>+# CHECK: 00 c3 89 13<br>+{ p1 = tstbit(r17, #0); if (p1.new) jump:nt 0 }<br>+# CHECK: 00 e0 89 13<br>+{ p1 = cmp.eq(r17,#-1); if (p1.new) jump:t 0 }<br>+# CHECK: 00 e1 89 13<br>+{ p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (p1.new) jump:t 0 }<br>+# CHECK: 00 e3 89 13<br>+{ p1 = tstbit(r17, #0); if (p1.new) jump:t 0 }<br>+# CHECK: 00 c0 c9 13<br>+{ p1 = cmp.eq(r17,#-1); if (!p1.new) jump:nt 0 }<br>+# CHECK: 00 c1 c9 13<br>+{ p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (!p1.new) jump:nt 0 }<br>+# CHECK: 00 c3 c9 13<br>+{ p1 = tstbit(r17, #0); if (!p1.new) jump:nt 0 }<br>+# CHECK: 00 e0 c9 13<br>+{ p1 = cmp.eq(r17,#-1); if (!p1.new) jump:t 0 }<br>+# CHECK: 00 e1 c9 13<br>+{ p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17,#-1); if (!p1.new) jump:t 0 }<br>+# CHECK: 00 e3 c9 13<br>+{ p1 = tstbit(r17, #0); if (!p1.new) jump:t 0 }<br>+# CHECK: 00 d5 09 12<br>+{ p1 = cmp.eq(r17, #21); if (p1.new) jump:nt 0 }<br>+# CHECK: 00 f5 09 12<br>+{ p1 = cmp.eq(r17, #21); if (p1.new) jump:t 0 }<br>+# CHECK: 00 d5 49 12<br>+{ p1 = cmp.eq(r17, #21); if (!p1.new) jump:nt 0 }<br>+# CHECK: 00 f5 49 12<br>+{ p1 = cmp.eq(r17, #21); if (!p1.new) jump:t 0 }<br>+# CHECK: 00 d5 89 12<br>+{ p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (p1.new) jump:nt 0 }<br>+# CHECK: 00 f5 89 12<br>+{ p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (p1.new) jump:t 0 }<br>+# CHECK: 00 d5 c9 12<br>+{ p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (!p1.new) jump:nt 0 }<br>+# CHECK: 00 f5 c9 12<br>+{ p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, #21); if (!p1.new) jump:t 0 }<br>+# CHECK: 00 d5 09 13<br>+{ p1 = cmp.gtu(r17, #21); if (p1.new) jump:nt 0 }<br>+# CHECK: 00 f5 09 13<br>+{ p1 = cmp.gtu(r17, #21); if (p1.new) jump:t 0 }<br>+# CHECK: 00 d5 49 13<br>+{ p1 = cmp.gtu(r17, #21); if (!p1.new) jump:nt 0 }<br>+# CHECK: 00 f5 49 13<br>+{ p1 = cmp.gtu(r17, #21); if (!p1.new) jump:t 0 }<br>+# CHECK: 00 cd 09 14<br>+{ p0 = cmp.eq(r17, r21); if (p0.new) jump:nt 0 }<br>+# CHECK: 00 dd 09 14<br>+{ p1 = cmp.eq(r17, r21); if (p1.new) jump:nt 0 }<br>+# CHECK: 00 ed 09 14<br>+{ p0 = cmp.eq(r17, r21); if (p0.new) jump:t 0 }<br>+# CHECK: 00 fd 09 14<br>+{ p1 = cmp.eq(r17, r21); if (p1.new) jump:t 0 }<br>+# CHECK: 00 cd 49 14<br>+{ p0 = cmp.eq(r17, r21); if (!p0.new) jump:nt 0 }<br>+# CHECK: 00 dd 49 14<br>+{ p1 = cmp.eq(r17, r21); if (!p1.new) jump:nt 0 }<br>+# CHECK: 00 ed 49 14<br>+{ p0 = cmp.eq(r17, r21); if (!p0.new) jump:t 0 }<br>+# CHECK: 00 fd 49 14<br>+{ p1 = cmp.eq(r17, r21); if (!p1.new) jump:t 0 }<br>+# CHECK: 00 cd 89 14<br>+{ p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (p0.new) jump:nt 0 }<br>+# CHECK: 00 dd 89 14<br>+{ p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (p1.new) jump:nt 0 }<br>+# CHECK: 00 ed 89 14<br>+{ p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (p0.new) jump:t 0 }<br>+# CHECK: 00 fd 89 14<br>+{ p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (p1.new) jump:t 0 }<br>+# CHECK: 00 cd c9 14<br>+{ p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (!p0.new) jump:nt 0 }<br>+# CHECK: 00 dd c9 14<br>+{ p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (!p1.new) jump:nt 0 }<br>+# CHECK: 00 ed c9 14<br>+{ p0 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (!p0.new) jump:t 0 }<br>+# CHECK: 00 fd c9 14<br>+{ p1 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17, r21); if (!p1.new) jump:t 0 }<br>+# CHECK: 00 cd 09 15<br>+{ p0 = cmp.gtu(r17, r21); if (p0.new) jump:nt 0 }<br>+# CHECK: 00 dd 09 15<br>+{ p1 = cmp.gtu(r17, r21); if (p1.new) jump:nt 0 }<br>+# CHECK: 00 ed 09 15<br>+{ p0 = cmp.gtu(r17, r21); if (p0.new) jump:t 0 }<br>+# CHECK: 00 fd 09 15<br>+{ p1 = cmp.gtu(r17, r21); if (p1.new) jump:t 0 }<br>+# CHECK: 00 cd 49 15<br>+{ p0 = cmp.gtu(r17, r21); if (!p0.new) jump:nt 0 }<br>+# CHECK: 00 dd 49 15<br>+{ p1 = cmp.gtu(r17, r21); if (!p1.new) jump:nt 0 }<br>+# CHECK: 00 ed 49 15<br>+{ p0 = cmp.gtu(r17, r21); if (!p0.new) jump:t 0 }<br>+# CHECK: 00 fd 49 15<br>+{ p1 = cmp.gtu(r17, r21); if (!p1.new) jump:t 0 }<br>+<br>+# Jump to address<br>+# CHECK: 00 c0 00 58<br>+jump 0<br>+# CHECK: 00 c3 00 5c<br>+if (p3) jump 0<br>+# CHECK: 00 c3 20 5c<br>+if (!p3) jump 0<br>+<br>+# Jump to address conditioned on new predicate<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 cb 00 5c<br>+{ p3 = r5<br>+ if (p3.new) jump:nt 0 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 db 00 5c<br>+{ p3 = r5<br>+ if (p3.new) jump:t 0 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 cb 20 5c<br>+{ p3 = r5<br>+ if (!p3.new) jump:nt 0 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 db 20 5c<br>+{ p3 = r5<br>+ if (!p3.new) jump:t 0 }<br>+<br>+# Jump to address conditioned on register value<br>+# CHECK: 00 c0 11 61<br>+if (r17!=#0) jump:nt 0<br>+# CHECK: 00 d0 11 61<br>+if (r17!=#0) jump:t 0<br>+# CHECK: 00 c0 51 61<br>+if (r17>=#0) jump:nt 0<br>+# CHECK: 00 d0 51 61<br>+if (r17>=#0) jump:t 0<br>+# CHECK: 00 c0 91 61<br>+if (r17==#0) jump:nt 0<br>+# CHECK: 00 d0 91 61<br>+if (r17==#0) jump:t 0<br>+# CHECK: 00 c0 d1 61<br>+if (r17<=#0) jump:nt 0<br>+# CHECK: 00 d0 d1 61<br>+if (r17<=#0) jump:t 0<br>+<br>+# Transfer and jump<br>+# CHECK: 00 d5 09 16<br>+{ r17 = #21 ; jump 0}<br>+# CHECK: 00 c9 0d 17<br>+{ r17 = r21 ; jump 0 }<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/jr.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/jr.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/jr.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/jr.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/jr.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,38 @@<br>+# RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.3 JR<br>+<br>+# Call subroutine from register<br>+# CHECK: 00 c0 b5 50<br>+callr r21<br>+# CHECK: 00 c1 15 51<br>+if (p1) callr r21<br>+# CHECK: 00 c3 35 51<br>+if (!p3) callr r21<br>+<br>+# Hint an indirect jump address<br>+# CHECK: 00 c0 b5 52<br>+hintjr(r21)<br>+<br>+# Jump to address from register<br>+# CHECK: 00 c0 95 52<br>+jumpr r21<br>+# CHECK: 00 c1 55 53<br>+if (p1) jumpr r21<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 cb 55 53<br>+{ p3 = r5<br>+ if (p3.new) jumpr:nt r21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 db 55 53<br>+{ p3 = r5<br>+ if (p3.new) jumpr:t r21 }<br>+# CHECK: 00 c3 75 53<br>+if (!p3) jumpr r21<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 cb 75 53<br>+{ p3 = r5<br>+ if (!p3.new) jumpr:nt r21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 db 75 53<br>+{ p3 = r5<br>+ if (!p3.new) jumpr:t r21 }<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/ld.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/ld.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/ld.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/ld.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/ld.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,499 @@<br>+# RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.5 LD<br>+# XFAIL: *<br>+<br>+# Load doubleword<br>+# CHECK: 90 ff d5 3a<br>+r17:16 = memd(r21 + r31<<#3)<br>+# CHECK: b0 c2 c0 49<br>+r17:16 = memd(#168)<br>+# CHECK: 02 40 00 00<br>+# CHECK-NEXT: 10 c5 c0 49<br>+r17:16 = memd(##168)<br>+# CHECK: d0 c0 d5 91<br>+r17:16 = memd(r21 + #48)<br>+# CHECK: b0 e0 d5 99<br>+r17:16 = memd(r21 ++ #40:circ(m1))<br>+# CHECK: 10 e2 d5 99<br>+r17:16 = memd(r21 ++ I:circ(m1))<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 70 d7 d5 9b<br>+r17:16 = memd(r21 = ##31)<br>+# CHECK: b0 c0 d5 9b<br>+r17:16 = memd(r21++#40)<br>+# CHECK: 10 e0 d5 9d<br>+r17:16 = memd(r21++m1)<br>+# CHECK: 10 e0 d5 9f<br>+r17:16 = memd(r21 ++ m1:brev)<br>+<br>+# Load doubleword conditionally<br>+# CHECK: f0 ff d5 30<br>+if (p3) r17:16 = memd(r21+r31<<#3)<br>+# CHECK: f0 ff d5 31<br>+if (!p3) r17:16 = memd(r21+r31<<#3)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f0 ff d5 32<br>+{ p3 = r5<br>+ if (p3.new) r17:16 = memd(r21+r31<<#3) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f0 ff d5 33<br>+{ p3 = r5<br>+ if (!p3.new) r17:16 = memd(r21+r31<<#3) }<br>+# CHECK: 70 d8 d5 41<br>+if (p3) r17:16 = memd(r21 + #24)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 70 d8 d5 43<br>+{ p3 = r5<br>+ if (p3.new) r17:16 = memd(r21 + #24) }<br>+# CHECK: 70 d8 d5 45<br>+if (!p3) r17:16 = memd(r21 + #24)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 70 d8 d5 47<br>+{ p3 = r5<br>+ if (!p3.new) r17:16 = memd(r21 + #24) }<br>+# CHECK: b0 e6 d5 9b<br>+if (p3) r17:16 = memd(r21++#40)<br>+# CHECK: b0 ee d5 9b<br>+if (!p3) r17:16 = memd(r21++#40)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b0 f6 d5 9b<br>+{ p3 = r5<br>+ if (p3.new) r17:16 = memd(r21++#40) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b0 fe d5 9b<br>+{ p3 = r5<br>+ if (!p3.new) r17:16 = memd(r21++#40) }<br>+<br>+# Load byte<br>+# CHECK: 91 ff 15 3a<br>+r17 = memb(r21 + r31<<#3)<br>+# CHECK: b1 c2 00 49<br>+r17 = memb(#21)<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: b1 c2 00 49<br>+r17 = memb(##21)<br>+# CHECK: f1 c3 15 91<br>+r17 = memb(r21 + #31)<br>+# CHECK: b1 e0 15 99<br>+r17 = memb(r21 ++ #5:circ(m1))<br>+# CHECK: 11 e2 15 99<br>+r17 = memb(r21 ++ I:circ(m1))<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 71 d7 15 9b<br>+r17 = memb(r21 = ##31)<br>+# CHECK: b1 c0 15 9b<br>+r17 = memb(r21++#5)<br>+# CHECK: 11 e0 15 9d<br>+r17 = memb(r21++m1)<br>+# CHECK: 11 e0 15 9f<br>+r17 = memb(r21 ++ m1:brev)<br>+<br>+# Load byte conditionally<br>+# CHECK: f1 ff 15 30<br>+if (p3) r17 = memb(r21+r31<<#3)<br>+# CHECK: f1 ff 15 31<br>+if (!p3) r17 = memb(r21+r31<<#3)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 15 32<br>+{ p3 = r5<br>+ if (p3.new) r17 = memb(r21+r31<<#3) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 15 33<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memb(r21+r31<<#3) }<br>+# CHECK: 91 dd 15 41<br>+if (p3) r17 = memb(r21 + #44)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 91 dd 15 43<br>+{ p3 = r5<br>+ if (p3.new) r17 = memb(r21 + #44) }<br>+# CHECK: 91 dd 15 45<br>+if (!p3) r17 = memb(r21 + #44)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 91 dd 15 47<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memb(r21 + #44) }<br>+# CHECK: b1 e6 15 9b<br>+if (p3) r17 = memb(r21++#5)<br>+# CHECK: b1 ee 15 9b<br>+if (!p3) r17 = memb(r21++#5)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 f6 15 9b<br>+{ p3 = r5<br>+ if (p3.new) r17 = memb(r21++#5) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 fe 15 9b<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memb(r21++#5) }<br>+<br>+# Load byte into shifted vector<br>+# CHECK: f0 c3 95 90<br>+r17:16 = memb_fifo(r21 + #31)<br>+# CHECK: b0 e0 95 98<br>+r17:16 = memb_fifo(r21 ++ #5:circ(m1))<br>+# CHECK: 10 e2 95 98<br>+r17:16 = memb_fifo(r21 ++ I:circ(m1))<br>+<br>+# Load half into shifted vector<br>+# CHECK: f0 c3 55 90<br>+r17:16 = memh_fifo(r21 + #62)<br>+# CHECK: b0 e0 55 98<br>+r17:16 = memh_fifo(r21 ++ #10:circ(m1))<br>+# CHECK: 10 e2 55 98<br>+r17:16 = memh_fifo(r21 ++ I:circ(m1))<br>+<br>+# Load halfword<br>+# CHECK: 91 ff 55 3a<br>+r17 = memh(r21 + r31<<#3)<br>+# CHECK: b1 c2 40 49<br>+r17 = memh(#42)<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 51 c5 40 49<br>+r17 = memh(##42)<br>+# CHECK: f1 c3 55 91<br>+r17 = memh(r21 + #62)<br>+# CHECK: b1 e0 55 99<br>+r17 = memh(r21 ++ #10:circ(m1))<br>+# CHECK: 11 e2 55 99<br>+r17 = memh(r21 ++ I:circ(m1))<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 71 d7 55 9b<br>+r17 = memh(r21 = ##31)<br>+# CHECK: b1 c0 55 9b<br>+r17 = memh(r21++#10)<br>+# CHECK: 11 e0 55 9d<br>+r17 = memh(r21++m1)<br>+# CHECK: 11 e0 55 9f<br>+r17 = memh(r21 ++ m1:brev)<br>+<br>+# Load halfword conditionally<br>+# CHECK: f1 ff 55 30<br>+if (p3) r17 = memh(r21+r31<<#3)<br>+# CHECK: f1 ff 55 31<br>+if (!p3) r17 = memh(r21+r31<<#3)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 55 32<br>+{ p3 = r5<br>+ if (p3.new) r17 = memh(r21+r31<<#3) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 55 33<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memh(r21+r31<<#3) }<br>+# CHECK: b1 e6 55 9b<br>+if (p3) r17 = memh(r21++#10)<br>+# CHECK: b1 ee 55 9b<br>+if (!p3) r17 = memh(r21++#10)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 f6 55 9b<br>+{ p3 = r5<br>+ if (p3.new) r17 = memh(r21++#10) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 fe 55 9b<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memh(r21++#10) }<br>+# CHECK: f1 db 55 41<br>+if (p3) r17 = memh(r21 + #62)<br>+# CHECK: f1 db 55 45<br>+if (!p3) r17 = memh(r21 + #62)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 db 55 43<br>+{ p3 = r5<br>+ if (p3.new) r17 = memh(r21 + #62) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 db 55 47<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memh(r21 + #62) }<br>+<br>+# Load unsigned byte<br>+# CHECK: 91 ff 35 3a<br>+r17 = memub(r21 + r31<<#3)<br>+# CHECK: b1 c2 20 49<br>+r17 = memub(#21)<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: b1 c2 20 49<br>+r17 = memub(##21)<br>+# CHECK: f1 c3 35 91<br>+r17 = memub(r21 + #31)<br>+# CHECK: b1 e0 35 99<br>+r17 = memub(r21 ++ #5:circ(m1))<br>+# CHECK: 11 e2 35 99<br>+r17 = memub(r21 ++ I:circ(m1))<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 71 d7 35 9b<br>+r17 = memub(r21 = ##31)<br>+# CHECK: b1 c0 35 9b<br>+r17 = memub(r21++#5)<br>+# CHECK: 11 e0 35 9d<br>+r17 = memub(r21++m1)<br>+# CHECK: 11 e0 35 9f<br>+r17 = memub(r21 ++ m1:brev)<br>+<br>+# Load unsigned byte conditionally<br>+# CHECK: f1 ff 35 30<br>+if (p3) r17 = memub(r21+r31<<#3)<br>+# CHECK: f1 ff 35 31<br>+if (!p3) r17 = memub(r21+r31<<#3)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 35 32<br>+{ p3 = r5<br>+ if (p3.new) r17 = memub(r21+r31<<#3) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 35 33<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memub(r21+r31<<#3) }<br>+# CHECK: f1 db 35 41<br>+if (p3) r17 = memub(r21 + #31)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 db 35 43<br>+{ p3 = r5<br>+ if (p3.new) r17 = memub(r21 + #31) }<br>+# CHECK: f1 db 35 45<br>+if (!p3) r17 = memub(r21 + #31)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 db 35 47<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memub(r21 + #31) }<br>+# CHECK: b1 e6 35 9b<br>+if (p3) r17 = memub(r21++#5)<br>+# CHECK: b1 ee 35 9b<br>+if (!p3) r17 = memub(r21++#5)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 f6 35 9b<br>+{ p3 = r5<br>+ if (p3.new) r17 = memub(r21++#5) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 fe 35 9b<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memub(r21++#5) }<br>+<br>+# Load unsigned halfword<br>+# CHECK: 91 ff 75 3a<br>+r17 = memuh(r21 + r31<<#3)<br>+# CHECK: b1 c2 60 49<br>+r17 = memuh(#42)<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 51 c5 60 49<br>+r17 = memuh(##42)<br>+# CHECK: b1 c2 75 91<br>+r17 = memuh(r21 + #42)<br>+# CHECK: b1 e0 75 99<br>+r17 = memuh(r21 ++ #10:circ(m1))<br>+# CHECK: 11 e2 75 99<br>+r17 = memuh(r21 ++ I:circ(m1))<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 71 d7 75 9b<br>+r17 = memuh(r21 = ##31)<br>+# CHECK: b1 c0 75 9b<br>+r17 = memuh(r21++#10)<br>+# CHECK: 11 e0 75 9d<br>+r17 = memuh(r21++m1)<br>+# CHECK: 11 e0 75 9f<br>+r17 = memuh(r21 ++ m1:brev)<br>+<br>+# Load unsigned halfword conditionally<br>+# CHECK: f1 ff 75 30<br>+if (p3) r17 = memuh(r21+r31<<#3)<br>+# CHECK: f1 ff 75 31<br>+if (!p3) r17 = memuh(r21+r31<<#3)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 75 32<br>+{ p3 = r5<br>+ if (p3.new) r17 = memuh(r21+r31<<#3) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 75 33<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memuh(r21+r31<<#3) }<br>+# CHECK: b1 da 75 41<br>+if (p3) r17 = memuh(r21 + #42)<br>+# CHECK: b1 da 75 45<br>+if (!p3) r17 = memuh(r21 + #42)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 da 75 43<br>+{ p3 = r5<br>+ if (p3.new) r17 = memuh(r21 + #42) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 da 75 47<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memuh(r21 + #42) }<br>+# CHECK: b1 e6 75 9b<br>+if (p3) r17 = memuh(r21++#10)<br>+# CHECK: b1 ee 75 9b<br>+if (!p3) r17 = memuh(r21++#10)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 f6 75 9b<br>+{ p3 = r5<br>+ if (p3.new) r17 = memuh(r21++#10) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 fe 75 9b<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memuh(r21++#10) }<br>+<br>+# Load word<br>+# CHECK: 91 ff 95 3a<br>+r17 = memw(r21 + r31<<#3)<br>+# CHECK: b1 c2 80 49<br>+r17 = memw(#84)<br>+# CHECK: 01 40 00 00<br>+# CHECK-NEXT: 91 c2 80 49<br>+r17 = memw(##84)<br>+# CHECK: b1 c2 95 91<br>+r17 = memw(r21 + #84)<br>+# CHECK: b1 e0 95 99<br>+r17 = memw(r21 ++ #20:circ(m1))<br>+# CHECK: 11 e2 95 99<br>+r17 = memw(r21 ++ I:circ(m1))<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 71 d7 95 9b<br>+r17 = memw(r21 = ##31)<br>+# CHECK: b1 c0 95 9b<br>+r17 = memw(r21++#20)<br>+# CHECK: 11 e0 95 9d<br>+r17 = memw(r21++m1)<br>+# CHECK: 11 e0 95 9f<br>+r17 = memw(r21 ++ m1:brev)<br>+<br>+# Load word conditionally<br>+# CHECK: f1 ff 95 30<br>+if (p3) r17 = memw(r21+r31<<#3)<br>+# CHECK: f1 ff 95 31<br>+if (!p3) r17 = memw(r21+r31<<#3)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 95 32<br>+{ p3 = r5<br>+ if (p3.new) r17 = memw(r21+r31<<#3) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f1 ff 95 33<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memw(r21+r31<<#3) }<br>+# CHECK: b1 da 95 41<br>+if (p3) r17 = memw(r21 + #84)<br>+# CHECK: b1 da 95 45<br>+if (!p3) r17 = memw(r21 + #84)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 da 95 43<br>+{ p3 = r5<br>+ if (p3.new) r17 = memw(r21 + #84) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 da 95 47<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memw(r21 + #84) }<br>+# CHECK: b1 e6 95 9b<br>+if (p3) r17 = memw(r21++#20)<br>+# CHECK: b1 ee 95 9b<br>+if (!p3) r17 = memw(r21++#20)<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 f6 95 9b<br>+{ p3 = r5<br>+ if (p3.new) r17 = memw(r21++#20) }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: b1 fe 95 9b<br>+{ p3 = r5<br>+ if (!p3.new) r17 = memw(r21++#20) }<br>+<br>+# Deallocate stack frame<br>+# CHECK: 1e c0 1e 90<br>+deallocframe<br>+<br>+# Deallocate stack frame and return<br>+# CHECK: 1e c0 1e 96<br>+dealloc_return<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1e cb 1e 96<br>+{ p3 = r5<br>+ if (p3.new) dealloc_return:nt }<br>+# CHECK: 1e d3 1e 96<br>+if (p3) dealloc_return<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1e db 1e 96<br>+{ p3 = r5<br>+ if (p3.new) dealloc_return:t }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1e eb 1e 96<br>+{ p3 = r5<br>+ if (!p3.new) dealloc_return:nt }<br>+# CHECK: 1e f3 1e 96<br>+if (!p3) dealloc_return<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1e fb 1e 96<br>+{ p3 = r5<br>+ if (!p3.new) dealloc_return:t }<br>+<br>+# Load and unpack bytes to halfwords<br>+# CHECK: f1 c3 35 90<br>+r17 = membh(r21 + #62)<br>+# CHECK: f1 c3 75 90<br>+r17 = memubh(r21 + #62)<br>+# CHECK: f0 c3 b5 90<br>+r17:16 = memubh(r21 + #124)<br>+# CHECK: f0 c3 f5 90<br>+r17:16 = membh(r21 + #124)<br>+# CHECK: b1 e0 35 98<br>+r17 = membh(r21 ++ #10:circ(m1))<br>+# CHECK: 11 e2 35 98<br>+r17 = membh(r21 ++ I:circ(m1))<br>+# CHECK: b1 e0 75 98<br>+r17 = memubh(r21 ++ #10:circ(m1))<br>+# CHECK: 11 e2 75 98<br>+r17 = memubh(r21 ++ I:circ(m1))<br>+# CHECK: b0 e0 f5 98<br>+r17:16 = membh(r21 ++ #20:circ(m1))<br>+# CHECK: 10 e2 f5 98<br>+r17:16 = membh(r21 ++ I:circ(m1))<br>+# CHECK: b0 e0 b5 98<br>+r17:16 = memubh(r21 ++ #20:circ(m1))<br>+# CHECK: 10 e2 b5 98<br>+r17:16 = memubh(r21 ++ I:circ(m1))<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 71 d7 35 9a<br>+r17 = membh(r21 = ##31)<br>+# CHECK: b1 c0 35 9a<br>+r17 = membh(r21++#10)<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 71 d7 75 9a<br>+r17 = memubh(r21 = ##31)<br>+# CHECK: b1 c0 75 9a<br>+r17 = memubh(r21++#10)<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 70 d7 b5 9a<br>+r17:16 = memubh(r21 = ##31)<br>+# CHECK: b0 c0 b5 9a<br>+r17:16 = memubh(r21++#20)<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 70 d7 f5 9a<br>+r17:16 = membh(r21 = ##31)<br>+# CHECK: b0 c0 f5 9a<br>+r17:16 = membh(r21++#20)<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: f1 f7 35 9c<br>+r17 = membh(r21<<#3 + ##31)<br>+# CHECK: 11 e0 35 9c<br>+r17 = membh(r21++m1)<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: f1 f7 75 9c<br>+r17 = memubh(r21<<#3 + ##31)<br>+# CHECK: 11 e0 75 9c<br>+r17 = memubh(r21++m1)<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: f0 f7 f5 9c<br>+r17:16 = membh(r21<<#3 + ##31)<br>+# CHECK: 10 e0 f5 9c<br>+r17:16 = membh(r21++m1)<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: f0 f7 b5 9c<br>+r17:16 = memubh(r21<<#3 + ##31)<br>+# CHECK: 11 e0 35 9c<br>+r17 = membh(r21++m1)<br>+# CHECK: 11 e0 75 9c<br>+r17 = memubh(r21++m1)<br>+# CHECK: 10 e0 f5 9c<br>+r17:16 = membh(r21++m1)<br>+# CHECK: 10 e0 b5 9c<br>+r17:16 = memubh(r21++m1)<br>+# CHECK: 11 e0 35 9e<br>+r17 = membh(r21 ++ m1:brev)<br>+# CHECK: 11 e0 75 9e<br>+r17 = memubh(r21 ++ m1:brev)<br>+# CHECK: 10 e0 b5 9e<br>+r17:16 = memubh(r21 ++ m1:brev)<br>+# CHECK: 10 e0 f5 9e<br>+r17:16 = membh(r21 ++ m1:brev)<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/memop.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/memop.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/memop.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/memop.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/memop.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,56 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.6 MEMOP<br>+<br>+# Operation on memory byte<br>+# CHECK: 95 d9 11 3e<br>+memb(r17+#51) += r21<br>+# CHECK: b5 d9 11 3e<br>+memb(r17+#51) -= r21<br>+# CHECK: d5 d9 11 3e<br>+memb(r17+#51) &= r21<br>+# CHECK: f5 d9 11 3e<br>+memb(r17+#51) |= r21<br>+# CHECK: 95 d9 11 3f<br>+memb(r17+#51) += #21<br>+# CHECK: b5 d9 11 3f<br>+memb(r17+#51) -= #21<br>+# CHECK: d5 d9 11 3f<br>+memb(r17+#51) = clrbit(#21)<br>+# CHECK: f5 d9 11 3f<br>+memb(r17+#51) = setbit(#21)<br>+<br>+# Operation on memory halfword<br>+# CHECK: 95 d9 31 3e<br>+memh(r17+#102) += r21<br>+# CHECK: b5 d9 31 3e<br>+memh(r17+#102) -= r21<br>+# CHECK: d5 d9 31 3e<br>+memh(r17+#102) &= r21<br>+# CHECK: f5 d9 31 3e<br>+memh(r17+#102) |= r21<br>+# CHECK: 95 d9 31 3f<br>+memh(r17+#102) += #21<br>+# CHECK: b5 d9 31 3f<br>+memh(r17+#102) -= #21<br>+# CHECK: d5 d9 31 3f<br>+memh(r17+#102) = clrbit(#21)<br>+# CHECK: f5 d9 31 3f<br>+memh(r17+#102) = setbit(#21)<br>+<br>+# Operation on memory word<br>+# CHECK: 95 d9 51 3e<br>+memw(r17+#204) += r21<br>+# CHECK: b5 d9 51 3e<br>+memw(r17+#204) -= r21<br>+# CHECK: d5 d9 51 3e<br>+memw(r17+#204) &= r21<br>+# CHECK: f5 d9 51 3e<br>+memw(r17+#204) |= r21<br>+# CHECK: 95 d9 51 3f<br>+memw(r17+#204) += #21<br>+# CHECK: b5 d9 51 3f<br>+memw(r17+#204) -= #21<br>+# CHECK: d5 d9 51 3f<br>+memw(r17+#204) = clrbit(#21)<br>+# CHECK: f5 d9 51 3f<br>+memw(r17+#204) = setbit(#21)<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/nv_j.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/nv_j.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/nv_j.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/nv_j.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/nv_j.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,180 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.7.1 NV/J<br>+<br>+# Jump to address conditioned on new register value<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 02 20<br>+{ r17 = r17<br>+ if (cmp.eq(r17.new, r21)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 02 20<br>+{ r17 = r17<br>+ if (cmp.eq(r17.new, r21)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 42 20<br>+{ r17 = r17<br>+ if (!cmp.eq(r17.new, r21)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 42 20<br>+{ r17 = r17<br>+ if (!cmp.eq(r17.new, r21)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 82 20<br>+{ r17 = r17<br>+ if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, r21)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 82 20<br>+{ r17 = r17<br>+ if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, r21)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 c2 20<br>+{ r17 = r17<br>+ if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, r21)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 c2 20<br>+{ r17 = r17<br>+ if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, r21)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 02 21<br>+{ r17 = r17<br>+ if (cmp.gtu(r17.new, r21)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 02 21<br>+{ r17 = r17<br>+ if (cmp.gtu(r17.new, r21)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 42 21<br>+{ r17 = r17<br>+ if (!cmp.gtu(r17.new, r21)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 42 21<br>+{ r17 = r17<br>+ if (!cmp.gtu(r17.new, r21)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 82 21<br>+{ r17 = r17<br>+ if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r17.new)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 82 21<br>+{ r17 = r17<br>+ if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r17.new)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 c2 21<br>+{ r17 = r17<br>+ if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r17.new)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 c2 21<br>+{ r17 = r17<br>+ if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21, r17.new)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 02 22<br>+{ r17 = r17<br>+ if (cmp.gtu(r21, r17.new)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 02 22<br>+{ r17 = r17<br>+ if (cmp.gtu(r21, r17.new)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 42 22<br>+{ r17 = r17<br>+ if (!cmp.gtu(r21, r17.new)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 42 22<br>+{ r17 = r17<br>+ if (!cmp.gtu(r21, r17.new)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 02 24<br>+{ r17 = r17<br>+ if (cmp.eq(r17.new, #21)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 02 24<br>+{ r17 = r17<br>+ if (cmp.eq(r17.new, #21)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 42 24<br>+{ r17 = r17<br>+ if (!cmp.eq(r17.new, #21)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 42 24<br>+{ r17 = r17<br>+ if (!cmp.eq(r17.new, #21)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 82 24<br>+{ r17 = r17<br>+ if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #21)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 82 24<br>+{ r17 = r17<br>+ if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #21)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 c2 24<br>+{ r17 = r17<br>+ if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #21)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 c2 24<br>+{ r17 = r17<br>+ if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #21)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 02 25<br>+{ r17 = r17<br>+ if (cmp.gtu(r17.new, #21)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 02 25<br>+{ r17 = r17<br>+ if (cmp.gtu(r17.new, #21)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 d5 42 25<br>+{ r17 = r17<br>+ if (!cmp.gtu(r17.new, #21)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 f5 42 25<br>+{ r17 = r17<br>+ if (!cmp.gtu(r17.new, #21)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 c0 82 25<br>+{ r17 = r17<br>+ if (tstbit(r17.new, #0)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 e0 82 25<br>+{ r17 = r17<br>+ if (tstbit(r17.new, #0)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 c0 c2 25<br>+{ r17 = r17<br>+ if (!tstbit(r17.new, #0)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 e0 c2 25<br>+{ r17 = r17<br>+ if (!tstbit(r17.new, #0)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 c0 02 26<br>+{ r17 = r17<br>+ if (cmp.eq(r17.new, #-1)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 e0 02 26<br>+{ r17 = r17<br>+ if (cmp.eq(r17.new, #-1)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 c0 42 26<br>+{ r17 = r17<br>+ if (!cmp.eq(r17.new, #-1)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 e0 42 26<br>+{ r17 = r17<br>+ if (!cmp.eq(r17.new, #-1)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 c0 82 26<br>+{ r17 = r17<br>+ if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #-1)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 e0 82 26<br>+{ r17 = r17<br>+ if (<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #-1)) jump:t 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 c0 c2 26<br>+{ r17 = r17<br>+ if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #-1)) jump:nt 0x0 }<br>+# CHECK: 11 40 71 70<br>+# CHECK-NEXT: 00 e0 c2 26<br>+{ r17 = r17<br>+ if (!<a href="http://cmp.gt" target="_blank">cmp.gt</a>(r17.new, #-1)) jump:t 0x0 }<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/nv_st.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/nv_st.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/nv_st.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/nv_st.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/nv_st.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,290 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.7.2 NV/ST<br>+<br>+# Store new-value byte<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 82 f5 b1 3b<br>+{ r31 = r31<br>+ memb(r17 + r21<<#3) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 11 c2 a0 48<br>+{ r31 = r31<br>+ memb(#17) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 15 c2 b1 a1<br>+{ r31 = r31<br>+ memb(r17+#21) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 02 e2 b1 a9<br>+{ r31 = r31<br>+ memb(r17 ++ I:circ(m1)) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 28 e2 b1 a9<br>+{ r31 = r31<br>+ memb(r17 ++ #5:circ(m1)) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 28 c2 b1 ab<br>+{ r31 = r31<br>+ memb(r17++#5) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 00 e2 b1 ad<br>+{ r31 = r31<br>+ memb(r17++m1) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 00 e2 b1 af<br>+{ r31 = r31<br>+ memb(r17 ++ m1:brev) = r31.new }<br>+<br>+# Store new-value byte conditionally<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: e2 f5 b1 34<br>+{ r31 = r31<br>+ if (p3) memb(r17+r21<<#3) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: e2 f5 b1 35<br>+{ r31 = r31<br>+ if (!p3) memb(r17+r21<<#3) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: e2 f5 b1 36<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (p3.new) memb(r17+r21<<#3) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: e2 f5 b1 37<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (!p3.new) memb(r17+r21<<#3) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: ab c2 b1 40<br>+{ r31 = r31<br>+ if (p3) memb(r17+#21) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: ab c2 b1 44<br>+{ r31 = r31<br>+ if (!p3) memb(r17+#21) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: ab c2 b1 42<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (p3.new) memb(r17+#21) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: ab c2 b1 46<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (!p3.new) memb(r17+#21) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 2b e2 b1 ab<br>+{ r31 = r31<br>+ if (p3) memb(r17++#5) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 2f e2 b1 ab<br>+{ r31 = r31<br>+ if (!p3) memb(r17++#5) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: ab e2 b1 ab<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (p3.new) memb(r17++#5) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: af e2 b1 ab<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (!p3.new) memb(r17++#5) = r31.new }<br>+<br>+# Store new-value halfword<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 8a f5 b1 3b<br>+{ r31 = r31<br>+ memh(r17 + r21<<#3) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 15 ca a0 48<br>+{ r31 = r31<br>+ memh(#42) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 15 ca b1 a1<br>+{ r31 = r31<br>+ memh(r17+#42) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 02 ea b1 a9<br>+{ r31 = r31<br>+ memh(r17 ++ I:circ(m1)) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 28 ea b1 a9<br>+{ r31 = r31<br>+ memh(r17 ++ #10:circ(m1)) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 28 ca b1 ab<br>+{ r31 = r31<br>+ memh(r17++#10) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 00 ea b1 ad<br>+{ r31 = r31<br>+ memh(r17++m1) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 00 ea b1 af<br>+{ r31 = r31<br>+ memh(r17 ++ m1:brev) = r31.new }<br>+<br>+# Store new-value halfword conditionally<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: ea f5 b1 34<br>+{ r31 = r31<br>+ if (p3) memh(r17+r21<<#3) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: ea f5 b1 35<br>+{ r31 = r31<br>+ if (!p3) memh(r17+r21<<#3) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: ea f5 b1 36<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (p3.new) memh(r17+r21<<#3) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: ea f5 b1 37<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (!p3.new) memh(r17+r21<<#3) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: ab ca b1 40<br>+{ r31 = r31<br>+ if (p3) memh(r17+#42) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: ab ca b1 44<br>+{ r31 = r31<br>+ if (!p3) memh(r17+#42) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: ab ca b1 42<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (p3.new) memh(r17+#42) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: ab ca b1 46<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (!p3.new) memh(r17+#42) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 2b ea b1 ab<br>+{ r31 = r31<br>+ if (p3) memh(r17++#10) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 2f ea b1 ab<br>+{ r31 = r31<br>+ if (!p3) memh(r17++#10) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: ab ea b1 ab<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (p3.new) memh(r17++#10) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: af ea b1 ab<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (!p3.new) memh(r17++#10) = r31.new }<br>+<br>+# Store new-value word<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 92 f5 b1 3b<br>+{ r31 = r31<br>+ memw(r17 + r21<<#3) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 15 d2 a0 48<br>+{ r31 = r31<br>+ memw(#84) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 15 d2 b1 a1<br>+{ r31 = r31<br>+ memw(r17+#84) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 02 f2 b1 a9<br>+{ r31 = r31<br>+ memw(r17 ++ I:circ(m1)) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 28 f2 b1 a9<br>+{ r31 = r31<br>+ memw(r17 ++ #20:circ(m1)) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 28 d2 b1 ab<br>+{ r31 = r31<br>+ memw(r17++#20) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 00 f2 b1 ad<br>+{ r31 = r31<br>+ memw(r17++m1) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 00 f2 b1 af<br>+{ r31 = r31<br>+ memw(r17 ++ m1:brev) = r31.new }<br>+<br>+# Store new-value word conditionally<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: f2 f5 b1 34<br>+{ r31 = r31<br>+ if (p3) memw(r17+r21<<#3) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: f2 f5 b1 35<br>+{ r31 = r31<br>+ if (!p3) memw(r17+r21<<#3) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: f2 f5 b1 36<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (p3.new) memw(r17+r21<<#3) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: f2 f5 b1 37<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (!p3.new) memw(r17+r21<<#3) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: ab d2 b1 40<br>+{ r31 = r31<br>+ if (p3) memw(r17+#84) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: ab d2 b1 44<br>+{ r31 = r31<br>+ if (!p3) memw(r17+#84) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: ab d2 b1 42<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (p3.new) memw(r17+#84) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: ab d2 b1 46<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (!p3.new) memw(r17+#84) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 2b f2 b1 ab<br>+{ r31 = r31<br>+ if (p3) memw(r17++#20) = r31.new }<br>+# CHECK: 1f 40 7f 70<br>+# CHECK-NEXT: 2f f2 b1 ab<br>+{ r31 = r31<br>+ if (!p3) memw(r17++#20) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: ab f2 b1 ab<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (p3.new) memw(r17++#20) = r31.new }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 1f 40 7f 70<br>+# CHECK-NEXT: af f2 b1 ab<br>+{ p3 = r5<br>+ r31 = r31<br>+ if (!p3.new) memw(r17++#20) = r31.new }<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/st.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/st.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/st.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/st.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/st.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,435 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.8 ST<br>+# XFAIL: *<br>+<br>+# Store doubleword<br>+# CHECK: 9e f5 d1 3b<br>+memd(r17 + r21<<#3) = r31:30<br>+# CHECK: 28 d4 c0 48<br>+memd(#320) = r21:20<br>+# CHECK: 02 40 00 00<br>+# CHECK-NEXT: 28 d4 c0 48<br>+memd(##168) = r21:20<br>+memd(r17+#168) = r21:20<br>+# CHECK: 02 f4 d1 a9<br>+memd(r17 ++ I:circ(m1)) = r21:20<br>+# CHECK: 28 f4 d1 a9<br>+memd(r17 ++ #40:circ(m1)) = r21:20<br>+# CHECK: 28 d4 d1 ab<br>+memd(r17++#40) = r21:20<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: d5 fe d1 ad<br>+memd(r17<<#3 + ##21) = r31:30<br>+memd(r17++m1) = r21:20<br>+# CHECK: 00 f4 d1 af<br>+memd(r17 ++ m1:brev) = r21:20<br>+<br>+# Store doubleword conditionally<br>+# CHECK: fe f5 d1 34<br>+if (p3) memd(r17+r21<<#3) = r31:30<br>+# CHECK: fe f5 d1 35<br>+if (!p3) memd(r17+r21<<#3) = r31:30<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: fe f5 d1 36<br>+{ p3 = r5<br>+ if (p3.new) memd(r17+r21<<#3) = r31:30 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: fe f5 d1 37<br>+{ p3 = r5<br>+ if (!p3.new) memd(r17+r21<<#3) = r31:30 }<br>+# CHECK: ab de d1 40<br>+if (p3) memd(r17+#168) = r31:30<br>+# CHECK: ab de d1 44<br>+if (!p3) memd(r17+#168) = r31:30<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ab de d1 42<br>+{ p3 = r5<br>+ if (p3.new) memd(r17+#168) = r31:30 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ab de d1 46<br>+{ p3 = r5<br>+ if (!p3.new) memd(r17+#168) = r31:30 }<br>+# CHECK: 2b f4 d1 ab<br>+if (p3) memd(r17++#40) = r21:20<br>+# CHECK: 2f f4 d1 ab<br>+if (!p3) memd(r17++#40) = r21:20<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ab f4 d1 ab<br>+{ p3 = r5<br>+ if (p3.new) memd(r17++#40) = r21:20 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: af f4 d1 ab<br>+{ p3 = r5<br>+ if (!p3.new) memd(r17++#40) = r21:20 }<br>+# CHECK: 02 40 00 00<br>+# CHECK-NEXT: c3 d4 c2 af<br>+if (p3) memd(##168) = r21:20<br>+# CHECK: 02 40 00 00<br>+# CHECK-NEXT: c7 d4 c2 af<br>+if (!p3) memd(##168) = r21:20<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 02 40 00 00<br>+# CHECK-NEXT: c3 f4 c2 af<br>+{ p3 = r5<br>+ if (p3.new) memd(##168) = r21:20 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 02 40 00 00<br>+# CHECK-NEXT: c7 f4 c2 af<br>+{ p3 = r5<br>+ if (!p3.new) memd(##168) = r21:20 }<br>+<br>+# Store byte<br>+# CHECK: 9f f5 11 3b<br>+memb(r17 + r21<<#3) = r31<br>+# CHECK: 9f ca 11 3c<br>+memb(r17+#21)=#31<br>+# CHECK: 15 d5 00 48<br>+memb(#21) = r21<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 15 d5 00 48<br>+memb(##21) = r21<br>+# CHECK: 15 d5 11 a1<br>+memb(r17+#21) = r21<br>+# CHECK: 02 f5 11 a9<br>+memb(r17 ++ I:circ(m1)) = r21<br>+# CHECK: 28 f5 11 a9<br>+memb(r17 ++ #5:circ(m1)) = r21<br>+# CHECK: 28 d5 11 ab<br>+memb(r17++#5) = r21<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: d5 ff 11 ad<br>+memb(r17<<#3 + ##21) = r31<br>+# CHECK: 00 f5 11 ad<br>+memb(r17++m1) = r21<br>+# CHECK: 00 f5 11 af<br>+memb(r17 ++ m1:brev) = r21<br>+<br>+# Store byte conditionally<br>+# CHECK: ff f5 11 34<br>+if (p3) memb(r17+r21<<#3) = r31<br>+# CHECK: ff f5 11 35<br>+if (!p3) memb(r17+r21<<#3) = r31<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ff f5 11 36<br>+{ p3 = r5<br>+ if (p3.new) memb(r17+r21<<#3) = r31 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ff f5 11 37<br>+{ p3 = r5<br>+ if (!p3.new) memb(r17+r21<<#3) = r31 }<br>+# CHECK: ff ca 11 38<br>+if (p3) memb(r17+#21)=#31<br>+# CHECK: ff ca 91 38<br>+if (!p3) memb(r17+#21)=#31<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ff ca 11 39<br>+{ p3 = r5<br>+ if (p3.new) memb(r17+#21)=#31 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ff ca 91 39<br>+{ p3 = r5<br>+ if (!p3.new) memb(r17+#21)=#31 }<br>+# CHECK: ab df 11 40<br>+if (p3) memb(r17+#21) = r31<br>+# CHECK: ab df 11 44<br>+if (!p3) memb(r17+#21) = r31<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ab df 11 42<br>+{ p3 = r5<br>+ if (p3.new) memb(r17+#21) = r31 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ab df 11 46<br>+{ p3 = r5<br>+ if (!p3.new) memb(r17+#21) = r31 }<br>+# CHECK: 2b f5 11 ab<br>+if (p3) memb(r17++#5) = r21<br>+# CHECK: 2f f5 11 ab<br>+if (!p3) memb(r17++#5) = r21<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ab f5 11 ab<br>+{ p3 = r5<br>+ if (p3.new) memb(r17++#5) = r21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: af f5 11 ab<br>+{ p3 = r5<br>+ if (!p3.new) memb(r17++#5) = r21 }<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: ab d5 01 af<br>+if (p3) memb(##21) = r21<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: af d5 01 af<br>+if (!p3) memb(##21) = r21<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 40 00 00<br>+# CHECK-NEXT: ab f5 01 af<br>+{ p3 = r5<br>+ if (p3.new) memb(##21) = r21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 40 00 00<br>+# CHECK-NEXT: af f5 01 af<br>+{ p3 = r5<br>+ if (!p3.new) memb(##21) = r21 }<br>+<br>+# Store halfword<br>+# CHECK: 9f f5 51 3b<br>+memh(r17 + r21<<#3) = r31<br>+# CHECK: 9f f5 71 3b<br>+memh(r17 + r21<<#3) = r31.h<br>+# CHECK: 95 cf 31 3c<br>+memh(r17+#62)=#21<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 2a d5 40 48<br>+memh(##42) = r21<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: 2a d5 60 48<br>+memh(##42) = r21.h<br>+# CHECK: 2a d5 40 48<br>+memh(#84) = r21<br>+# CHECK: 2a d5 60 48<br>+memh(#84) = r21.h<br>+# CHECK: 15 df 51 a1<br>+memh(r17+#42) = r31<br>+# CHECK: 15 df 71 a1<br>+memh(r17+#42) = r31.h<br>+# CHECK: 02 f5 51 a9<br>+memh(r17 ++ I:circ(m1)) = r21<br>+# CHECK: 28 f5 51 a9<br>+memh(r17 ++ #10:circ(m1)) = r21<br>+# CHECK: 02 f5 71 a9<br>+memh(r17 ++ I:circ(m1)) = r21.h<br>+# CHECK: 28 f5 71 a9<br>+memh(r17 ++ #10:circ(m1)) = r21.h<br>+# CHECK: 28 d5 51 ab<br>+memh(r17++#10) = r21<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: d5 ff 51 ad<br>+memh(r17<<#3 + ##21) = r31<br>+# CHECK: 28 d5 71 ab<br>+memh(r17++#10) = r21.h<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: d5 ff 71 ad<br>+memh(r17<<#3 + ##21) = r31.h<br>+# CHECK: 00 f5 51 ad<br>+memh(r17++m1) = r21<br>+# CHECK: 00 f5 71 ad<br>+memh(r17++m1) = r21.h<br>+# CHECK: 00 f5 51 af<br>+memh(r17 ++ m1:brev) = r21<br>+# CHECK: 00 f5 71 af<br>+memh(r17 ++ m1:brev) = r21.h<br>+<br>+# Store halfword conditionally<br>+# CHECK: ff f5 51 34<br>+if (p3) memh(r17+r21<<#3) = r31<br>+# CHECK: ff f5 71 34<br>+if (p3) memh(r17+r21<<#3) = r31.h<br>+# CHECK: ff f5 51 35<br>+if (!p3) memh(r17+r21<<#3) = r31<br>+# CHECK: ff f5 71 35<br>+if (!p3) memh(r17+r21<<#3) = r31.h<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ff f5 51 36<br>+{ p3 = r5<br>+ if (p3.new) memh(r17+r21<<#3) = r31 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ff f5 71 36<br>+{ p3 = r5<br>+ if (p3.new) memh(r17+r21<<#3) = r31.h }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ff f5 51 37<br>+{ p3 = r5<br>+ if (!p3.new) memh(r17+r21<<#3) = r31 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ff f5 71 37<br>+{ p3 = r5<br>+ if (!p3.new) memh(r17+r21<<#3) = r31.h }<br>+# CHECK: f5 cf 31 38<br>+if (p3) memh(r17+#62)=#21<br>+# CHECK: f5 cf b1 38<br>+if (!p3) memh(r17+#62)=#21<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f5 cf 31 39<br>+{ p3 = r5<br>+ if (p3.new) memh(r17+#62)=#21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: f5 cf b1 39<br>+{ p3 = r5<br>+ if (!p3.new) memh(r17+#62)=#21 }<br>+# CHECK: fb d5 51 40<br>+if (p3) memh(r17+#62) = r21<br>+# CHECK: fb d5 71 40<br>+if (p3) memh(r17+#62) = r21.h<br>+# CHECK: fb d5 51 44<br>+if (!p3) memh(r17+#62) = r21<br>+# CHECK: fb d5 71 44<br>+if (!p3) memh(r17+#62) = r21.h<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: fb d5 51 42<br>+{ p3 = r5<br>+ if (p3.new) memh(r17+#62) = r21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: fb d5 71 42<br>+{ p3 = r5<br>+ if (p3.new) memh(r17+#62) = r21.h }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: fb d5 51 46<br>+{ p3 = r5<br>+ if (!p3.new) memh(r17+#62) = r21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: fb d5 71 46<br>+{ p3 = r5<br>+ if (!p3.new) memh(r17+#62) = r21.h }<br>+# CHECK: 2b f5 51 ab<br>+if (p3) memh(r17++#10) = r21<br>+# CHECK: 2f f5 51 ab<br>+if (!p3) memh(r17++#10) = r21<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ab f5 51 ab<br>+{ p3 = r5<br>+ if (p3.new) memh(r17++#10) = r21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: af f5 51 ab<br>+{ p3 = r5<br>+ if (!p3.new) memh(r17++#10) = r21 }<br>+# CHECK: 2b f5 71 ab<br>+if (p3) memh(r17++#10) = r21.h<br>+# CHECK: 2f f5 71 ab<br>+if (!p3) memh(r17++#10) = r21.h<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ab f5 71 ab<br>+{ p3 = r5<br>+ if (p3.new) memh(r17++#10) = r21.h }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: af f5 71 ab<br>+{ p3 = r5<br>+ if (!p3.new) memh(r17++#10) = r21.h }<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: d3 d5 42 af<br>+if (p3) memh(##42) = r21<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: d3 d5 62 af<br>+if (p3) memh(##42) = r21.h<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: d7 d5 42 af<br>+if (!p3) memh(##42) = r21<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: d7 d5 62 af<br>+if (!p3) memh(##42) = r21.h<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 40 00 00<br>+# CHECK-NEXT: d3 f5 42 af<br>+{ p3 = r5<br>+ if (p3.new) memh(##42) = r21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 40 00 00<br>+# CHECK-NEXT: d3 f5 62 af<br>+{ p3 = r5<br>+ if (p3.new) memh(##42) = r21.h }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 40 00 00<br>+# CHECK-NEXT: d7 f5 42 af<br>+{ p3 = r5<br>+ if (!p3.new) memh(##42) = r21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 00 40 00 00<br>+# CHECK-NEXT: d7 f5 62 af<br>+{ p3 = r5<br>+ if (!p3.new) memh(##42) = r21.h }<br>+<br>+# Store word<br>+# CHECK: 9f f5 91 3b<br>+memw(r17 + r21<<#3) = r31<br>+# CHECK: 9f ca 51 3c<br>+memw(r17+#84)=#31<br>+# CHECK: 15 df 80 48<br>+memw(#84) = r31<br>+# CHECK: 01 40 00 00<br>+# CHECK-NEXT: 14 d5 80 48<br>+memw(##84) = r21<br>+# CHECK: 9f ca 51 3c<br>+memw(r17+#84)=#31<br>+# CHECK: 15 df 91 a1<br>+memw(r17+#84) = r31<br>+# CHECK: 02 f5 91 a9<br>+memw(r17 ++ I:circ(m1)) = r21<br>+# CHECK: 28 f5 91 a9<br>+memw(r17 ++ #20:circ(m1)) = r21<br>+# CHECK: 28 d5 91 ab<br>+memw(r17++#20) = r21<br>+# CHECK: 00 40 00 00<br>+# CHECK-NEXT: d5 ff 91 ad<br>+memw(r17<<#3 + ##21) = r31<br>+# CHECK: 00 f5 91 ad<br>+memw(r17++m1) = r21<br>+# CHECK: 00 f5 91 af<br>+memw(r17 ++ m1:brev) = r21<br>+<br>+# Store word conditionally<br>+# CHECK: ff f5 91 34<br>+if (p3) memw(r17+r21<<#3) = r31<br>+# CHECK: ff f5 91 35<br>+if (!p3) memw(r17+r21<<#3) = r31<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ff f5 91 36<br>+{ p3 = r5<br>+ if (p3.new) memw(r17+r21<<#3) = r31 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ff f5 91 37<br>+{ p3 = r5<br>+ if (!p3.new) memw(r17+r21<<#3) = r31 }<br>+# CHECK: ff ca 51 38<br>+if (p3) memw(r17+#84)=#31<br>+# CHECK: ff ca d1 38<br>+if (!p3) memw(r17+#84)=#31<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ff ca 51 39<br>+{ p3 = r5<br>+ if (p3.new) memw(r17+#84)=#31 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ff ca d1 39<br>+{ p3 = r5<br>+ if (!p3.new) memw(r17+#84)=#31 }<br>+# CHECK: ab df 91 40<br>+if (p3) memw(r17+#84) = r31<br>+# CHECK: ab df 91 44<br>+if (!p3) memw(r17+#84) = r31<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ab df 91 42<br>+{ p3 = r5<br>+ if (p3.new) memw(r17+#84) = r31 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ab df 91 46<br>+{ p3 = r5<br>+ if (!p3.new) memw(r17+#84) = r31 }<br>+# CHECK: 2b f5 91 ab<br>+if (p3) memw(r17++#20) = r21<br>+# CHECK: 2f f5 91 ab<br>+if (!p3) memw(r17++#20) = r21<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: af f5 91 ab<br>+{ p3 = r5<br>+ if (!p3.new) memw(r17++#20) = r21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: ab f5 91 ab<br>+{ p3 = r5<br>+ if (p3.new) memw(r17++#20) = r21 }<br>+# CHECK: 01 40 00 00<br>+# CHECK-NEXT: a3 d5 81 af<br>+if (p3) memw(##84) = r21<br>+# CHECK: 01 40 00 00<br>+# CHECK-NEXT: a7 d5 81 af<br>+if (!p3) memw(##84) = r21<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 01 40 00 00<br>+# CHECK-NEXT: a3 f5 81 af<br>+{ p3 = r5<br>+ if (p3.new) memw(##84) = r21 }<br>+# CHECK: 03 40 45 85<br>+# CHECK-NEXT: 01 40 00 00<br>+# CHECK-NEXT: a7 f5 81 af<br>+{ p3 = r5<br>+ if (!p3.new) memw(##84) = r21 }<br>+<br>+# Allocate stack frame<br>+# CHECK: 1f c0 9d a0<br>+allocframe(#248)<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/system_user.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/system_user.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/system_user.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/system_user.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/system_user.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,26 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.9.1 SYSTEM/USER<br>+<br>+# Load locked<br>+# CHECK: 11 c0 15 92<br>+r17 = memw_locked(r21)<br>+# CHECK: 10 d0 15 92<br>+r17:16 = memd_locked(r21)<br>+<br>+# Store conditional<br>+# CHECK: 03 d5 b1 a0<br>+memw_locked(r17, p3) = r21<br>+# CHECK: 03 d4 f1 a0<br>+memd_locked(r17, p3) = r21:20<br>+<br>+# Memory barrier<br>+# CHECK: 00 c0 00 a8<br>+barrier<br>+<br>+# Data cache prefetch<br>+# CHECK: 15 c0 11 94<br>+dcfetch(r17 + #168)<br>+<br>+# Send value to ETM trace<br>+# CHECK: 00 c0 51 62<br>+trace(r17)<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/xtype_alu.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_alu.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_alu.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/xtype_alu.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/xtype_alu.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,395 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.10.1 XTYPE/ALU<br>+<br>+# Absolute value doubleword<br>+# CHECK: d0 c0 94 80<br>+r17:16 = abs(r21:20)<br>+# CHECK: 91 c0 95 8c<br>+r17 = abs(r21)<br>+# CHECK: b1 c0 95 8c<br>+r17 = abs(r21):sat<br>+<br>+# Add and accumulate<br>+# CHECK: ff d1 35 db<br>+r17 = add(r21, add(r31, #23))<br>+# CHECK: ff d1 b5 db<br>+r17 = add(r21, sub(#23, r31))<br>+# CHECK: f1 c2 15 e2<br>+r17 += add(r21, #23)<br>+# CHECK: f1 c2 95 e2<br>+r17 -= add(r21, #23)<br>+# CHECK: 31 df 15 ef<br>+r17 += add(r21, r31)<br>+# CHECK: 31 df 95 ef<br>+r17 -= add(r21, r31)<br>+<br>+# Add doublewords<br>+# CHECK: f0 de 14 d3<br>+r17:16 = add(r21:20, r31:30)<br>+# CHECK: b0 de 74 d3<br>+r17:16 = add(r21:20, r31:30):sat<br>+# CHECK: d0 de 74 d3<br>+r17:16 = add(r21:20, r31:30):raw:lo<br>+# CHECK: f0 de 74 d3<br>+r17:16 = add(r21:20, r31:30):raw:hi<br>+<br>+# Add halfword<br>+# CHECK: 11 d5 1f d5<br>+r17 = add(r21.l, r31.l)<br>+# CHECK: 51 d5 1f d5<br>+r17 = add(r21.l, r31.h)<br>+# CHECK: 91 d5 1f d5<br>+r17 = add(r21.l, r31.l):sat<br>+# CHECK: d1 d5 1f d5<br>+r17 = add(r21.l, r31.h):sat<br>+# CHECK: 11 d5 5f d5<br>+r17 = add(r21.l, r31.l):<<16<br>+# CHECK: 31 d5 5f d5<br>+r17 = add(r21.l, r31.h):<<16<br>+# CHECK: 51 d5 5f d5<br>+r17 = add(r21.h, r31.l):<<16<br>+# CHECK: 71 d5 5f d5<br>+r17 = add(r21.h, r31.h):<<16<br>+# CHECK: 91 d5 5f d5<br>+r17 = add(r21.l, r31.l):sat:<<16<br>+# CHECK: b1 d5 5f d5<br>+r17 = add(r21.l, r31.h):sat:<<16<br>+# CHECK: d1 d5 5f d5<br>+r17 = add(r21.h, r31.l):sat:<<16<br>+# CHECK: f1 d5 5f d5<br>+r17 = add(r21.h, r31.h):sat:<<16<br>+<br>+# Add or subtract doublewords with carry<br>+# CHECK: 70 de d4 c2<br>+r17:16 = add(r21:20, r31:30, p3):carry<br>+# CHECK: 70 de f4 c2<br>+r17:16 = sub(r21:20, r31:30, p3):carry<br>+<br>+# Logical doublewords<br>+# CHECK: 90 c0 94 80<br>+r17:16 = not(r21:20)<br>+# CHECK: 10 de f4 d3<br>+r17:16 = and(r21:20, r31:30)<br>+# CHECK: 30 d4 fe d3<br>+r17:16 = and(r21:20, ~r31:30)<br>+# CHECK: 50 de f4 d3<br>+r17:16 = or(r21:20, r31:30)<br>+# CHECK: 70 d4 fe d3<br>+r17:16 = or(r21:20, ~r31:30)<br>+# CHECK: 90 de f4 d3<br>+r17:16 = xor(r21:20, r31:30)<br>+<br>+# Logical-logical doublewords<br>+# CHECK: 10 de 94 ca<br>+r17:16 ^= xor(r21:20, r31:30)<br>+<br>+# Logical-logical words<br>+# CHECK: f1 c3 15 da<br>+r17 |= and(r21, #31)<br>+# CHECK: f5 c3 51 da<br>+r17 = or(r21, and(r17, #31))<br>+# CHECK: f1 c3 95 da<br>+r17 |= or(r21, #31)<br>+# CHECK: 11 df 35 ef<br>+r17 |= and(r21, ~r31)<br>+# CHECK: 31 df 35 ef<br>+r17 &= and(r21, ~r31)<br>+# CHECK: 51 df 35 ef<br>+r17 ^= and(r21, ~r31)<br>+# CHECK: 11 df 55 ef<br>+r17 &= and(r21, r31)<br>+# CHECK: 31 df 55 ef<br>+r17 &= or(r21, r31)<br>+# CHECK: 51 df 55 ef<br>+r17 &= xor(r21, r31)<br>+# CHECK: 71 df 55 ef<br>+r17 |= and(r21, r31)<br>+# CHECK: 71 df 95 ef<br>+r17 ^= xor(r21, r31)<br>+# CHECK: 11 df d5 ef<br>+r17 |= or(r21, r31)<br>+# CHECK: 31 df d5 ef<br>+r17 |= xor(r21, r31)<br>+# CHECK: 51 df d5 ef<br>+r17 ^= and(r21, r31)<br>+# CHECK: 71 df d5 ef<br>+r17 ^= or(r21, r31)<br>+<br>+# Maximum words<br>+# CHECK: 11 df d5 d5<br>+r17 = max(r21, r31)<br>+# CHECK: 91 df d5 d5<br>+r17 = maxu(r21, r31)<br>+<br>+# Maximum doublewords<br>+# CHECK: 90 de d4 d3<br>+r17:16 = max(r21:20, r31:30)<br>+# CHECK: b0 de d4 d3<br>+r17:16 = maxu(r21:20, r31:30)<br>+<br>+# Minimum words<br>+# CHECK: 11 d5 bf d5<br>+r17 = min(r21, r31)<br>+# CHECK: 91 d5 bf d5<br>+r17 = minu(r21, r31)<br>+<br>+# Minimum doublewords<br>+# CHECK: d0 d4 be d3<br>+r17:16 = min(r21:20, r31:30)<br>+# CHECK: f0 d4 be d3<br>+r17:16 = minu(r21:20, r31:30)<br>+<br>+# Module wrap<br>+# CHECK: f1 df f5 d3<br>+r17 = modwrap(r21, r31)<br>+<br>+# Negate<br>+# CHECK: b0 c0 94 80<br>+r17:16 = neg(r21:20)<br>+# CHECK: d1 c0 95 8c<br>+r17 = neg(r21):sat<br>+<br>+# Round<br>+# CHECK: 31 c0 d4 88<br>+r17 = round(r21:20):sat<br>+# CHECK: 11 df f5 8c<br>+r17 = cround(r21, #31)<br>+# CHECK: 91 df f5 8c<br>+r17 = round(r21, #31)<br>+# CHECK: d1 df f5 8c<br>+r17 = round(r21, #31):sat<br>+# CHECK: 11 df d5 c6<br>+r17 = cround(r21, r31)<br>+# CHECK: 91 df d5 c6<br>+r17 = round(r21, r31)<br>+# CHECK: d1 df d5 c6<br>+r17 = round(r21, r31):sat<br>+<br>+# Subtract doublewords<br>+# CHECK: f0 d4 3e d3<br>+r17:16 = sub(r21:20, r31:30)<br>+<br>+# Subtract and accumulate words<br>+# CHECK: 71 d5 1f ef<br>+r17 += sub(r21, r31)<br>+<br>+# Subtract halfword<br>+# CHECK: 11 d5 3f d5<br>+r17 = sub(r21.l, r31.l)<br>+# CHECK: 51 d5 3f d5<br>+r17 = sub(r21.l, r31.h)<br>+# CHECK: 91 d5 3f d5<br>+r17 = sub(r21.l, r31.l):sat<br>+# CHECK: d1 d5 3f d5<br>+r17 = sub(r21.l, r31.h):sat<br>+# CHECK: 11 d5 7f d5<br>+r17 = sub(r21.l, r31.l):<<16<br>+# CHECK: 31 d5 7f d5<br>+r17 = sub(r21.l, r31.h):<<16<br>+# CHECK: 51 d5 7f d5<br>+r17 = sub(r21.h, r31.l):<<16<br>+# CHECK: 71 d5 7f d5<br>+r17 = sub(r21.h, r31.h):<<16<br>+# CHECK: 91 d5 7f d5<br>+r17 = sub(r21.l, r31.l):sat:<<16<br>+# CHECK: b1 d5 7f d5<br>+r17 = sub(r21.l, r31.h):sat:<<16<br>+# CHECK: d1 d5 7f d5<br>+r17 = sub(r21.h, r31.l):sat:<<16<br>+# CHECK: f1 d5 7f d5<br>+r17 = sub(r21.h, r31.h):sat:<<16<br>+<br>+# Sign extend word to doubleword<br>+# CHECK: 10 c0 55 84<br>+r17:16 = sxtw(r21)<br>+<br>+# Vector absolute value halfwords<br>+# CHECK: 90 c0 54 80<br>+r17:16 = vabsh(r21:20)<br>+# CHECK: b0 c0 54 80<br>+r17:16 = vabsh(r21:20):sat<br>+<br>+# Vector absolute value words<br>+# CHECK: d0 c0 54 80<br>+r17:16 = vabsw(r21:20)<br>+# CHECK: f0 c0 54 80<br>+r17:16 = vabsw(r21:20):sat<br>+<br>+# Vector absolute difference halfwords<br>+# CHECK: 10 d4 7e e8<br>+r17:16 = vabsdiffh(r21:20, r31:30)<br>+<br>+# Vector absolute difference words<br>+# CHECK: 10 d4 3e e8<br>+r17:16 = vabsdiffw(r21:20, r31:30)<br>+<br>+# Vector add halfwords<br>+# CHECK: 50 de 14 d3<br>+r17:16 = vaddh(r21:20, r31:30)<br>+# CHECK: 70 de 14 d3<br>+r17:16 = vaddh(r21:20, r31:30):sat<br>+# CHECK: 90 de 14 d3<br>+r17:16 = vadduh(r21:20, r31:30):sat<br>+<br>+# Vector add halfwords with saturate and pack to unsigned bytes<br>+# CHECK: 31 de 54 c1<br>+r17 = vaddhub(r21:20, r31:30):sat<br>+<br>+# Vector reduce add unsigned bytes<br>+# CHECK: 30 de 54 e8<br>+r17:16 = vraddub(r21:20, r31:30)<br>+# CHECK: 30 de 54 ea<br>+r17:16 += vraddub(r21:20, r31:30)<br>+<br>+# Vector reduce add halfwords<br>+# CHECK: 31 de 14 e9<br>+r17 = vradduh(r21:20, r31:30)<br>+# CHECK: f1 de 34 e9<br>+r17 = vraddh(r21:20, r31:30)<br>+<br>+# Vector add bytes<br>+# CHECK: 10 de 14 d3<br>+r17:16 = vaddub(r21:20, r31:30)<br>+# CHECK: 30 de 14 d3<br>+r17:16 = vaddub(r21:20, r31:30):sat<br>+<br>+# Vector add words<br>+# CHECK: b0 de 14 d3<br>+r17:16 = vaddw(r21:20, r31:30)<br>+# CHECK: d0 de 14 d3<br>+r17:16 = vaddw(r21:20, r31:30):sat<br>+<br>+# Vector average halfwords<br>+# CHECK: 50 de 54 d3<br>+r17:16 = vavgh(r21:20, r31:30)<br>+# CHECK: 70 de 54 d3<br>+r17:16 = vavgh(r21:20, r31:30):rnd<br>+# CHECK: 90 de 54 d3<br>+r17:16 = vavgh(r21:20, r31:30):crnd<br>+# CHECK: b0 de 54 d3<br>+r17:16 = vavguh(r21:20, r31:30)<br>+# CHECK: d0 de 54 d3<br>+r17:16 = vavguh(r21:20, r31:30):rnd<br>+# CHECK: 10 d4 9e d3<br>+r17:16 = vnavgh(r21:20, r31:30)<br>+# CHECK: 30 d4 9e d3<br>+r17:16 = vnavgh(r21:20, r31:30):rnd:sat<br>+# CHECK: 50 d4 9e d3<br>+r17:16 = vnavgh(r21:20, r31:30):crnd:sat<br>+<br>+# Vector average unsigned bytes<br>+# CHECK: 10 de 54 d3<br>+r17:16 = vavgub(r21:20, r31:30)<br>+# CHECK: 30 de 54 d3<br>+r17:16 = vavgub(r21:20, r31:30):rnd<br>+<br>+# Vector average words<br>+# CHECK: 10 de 74 d3<br>+r17:16 = vavgw(r21:20, r31:30)<br>+# CHECK: 30 de 74 d3<br>+r17:16 = vavgw(r21:20, r31:30):rnd<br>+# CHECK: 50 de 74 d3<br>+r17:16 = vavgw(r21:20, r31:30):crnd<br>+# CHECK: 70 de 74 d3<br>+r17:16 = vavguw(r21:20, r31:30)<br>+# CHECK: 90 de 74 d3<br>+r17:16 = vavguw(r21:20, r31:30):rnd<br>+# CHECK: 70 d4 9e d3<br>+r17:16 = vnavgw(r21:20, r31:30)<br>+# CHECK: 90 d4 9e d3<br>+r17:16 = vnavgw(r21:20, r31:30):rnd:sat<br>+# CHECK: d0 d4 9e d3<br>+r17:16 = vnavgw(r21:20, r31:30):crnd:sat<br>+<br>+# Vector conditional negate<br>+# CHECK: 50 df d4 c3<br>+r17:16 = vcnegh(r21:20, r31)<br>+<br>+# CHECK: f0 ff 34 cb<br>+r17:16 += vrcnegh(r21:20, r31)<br>+<br>+# Vector maximum bytes<br>+# CHECK: 10 d4 de d3<br>+r17:16 = vmaxub(r21:20, r31:30)<br>+# CHECK: d0 d4 de d3<br>+r17:16 = vmaxb(r21:20, r31:30)<br>+<br>+# Vector maximum halfwords<br>+# CHECK: 30 d4 de d3<br>+r17:16 = vmaxh(r21:20, r31:30)<br>+# CHECK: 50 d4 de d3<br>+r17:16 = vmaxuh(r21:20, r31:30)<br>+<br>+# Vector reduce maximum halfwords<br>+# CHECK: 3f d0 34 cb<br>+r17:16 = vrmaxh(r21:20, r31)<br>+# CHECK: 3f f0 34 cb<br>+r17:16 = vrmaxuh(r21:20, r31)<br>+<br>+# Vector reduce maximum words<br>+# CHECK: 5f d0 34 cb<br>+r17:16 = vrmaxw(r21:20, r31)<br>+# CHECK: 5f f0 34 cb<br>+r17:16 = vrmaxuw(r21:20, r31)<br>+<br>+# Vector maximum words<br>+# CHECK: b0 d4 be d3<br>+r17:16 = vmaxuw(r21:20, r31:30)<br>+# CHECK: 70 d4 de d3<br>+r17:16 = vmaxw(r21:20, r31:30)<br>+<br>+# Vector minimum bytes<br>+# CHECK: 10 d4 be d3<br>+r17:16 = vminub(r21:20, r31:30)<br>+# CHECK: f0 d4 de d3<br>+r17:16 = vminb(r21:20, r31:30)<br>+<br>+# Vector minimum halfwords<br>+# CHECK: 30 d4 be d3<br>+r17:16 = vminh(r21:20, r31:30)<br>+# CHECK: 50 d4 be d3<br>+r17:16 = vminuh(r21:20, r31:30)<br>+<br>+# Vector reduce minimum halfwords<br>+# CHECK: bf d0 34 cb<br>+r17:16 = vrminh(r21:20, r31)<br>+# CHECK: bf f0 34 cb<br>+r17:16 = vrminuh(r21:20, r31)<br>+<br>+# Vector reduce minimum words<br>+# CHECK: df d0 34 cb<br>+r17:16 = vrminw(r21:20, r31)<br>+# CHECK: df f0 34 cb<br>+r17:16 = vrminuw(r21:20, r31)<br>+<br>+# Vector minimum words<br>+# CHECK: 70 d4 be d3<br>+r17:16 = vminw(r21:20, r31:30)<br>+# CHECK: 90 d4 be d3<br>+r17:16 = vminuw(r21:20, r31:30)<br>+<br>+# Vector sum of absolute differences unsigned bytes<br>+# CHECK: 50 de 54 e8<br>+r17:16 = vrsadub(r21:20, r31:30)<br>+# CHECK: 50 de 54 ea<br>+r17:16 += vrsadub(r21:20, r31:30)<br>+<br>+# Vector subtract halfwords<br>+# CHECK: 50 d4 3e d3<br>+r17:16 = vsubh(r21:20, r31:30)<br>+# CHECK: 70 d4 3e d3<br>+r17:16 = vsubh(r21:20, r31:30):sat<br>+# CHECK: 90 d4 3e d3<br>+r17:16 = vsubuh(r21:20, r31:30):sat<br>+<br>+# Vector subtract bytes<br>+# CHECK: 10 d4 3e d3<br>+r17:16 = vsubub(r21:20, r31:30)<br>+# CHECK: 30 d4 3e d3<br>+r17:16 = vsubub(r21:20, r31:30):sat<br>+<br>+# Vector subtract words<br>+# CHECK: b0 d4 3e d3<br>+r17:16 = vsubw(r21:20, r31:30)<br>+# CHECK: d0 d4 3e d3<br>+r17:16 = vsubw(r21:20, r31:30):sat<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/xtype_bit.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_bit.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_bit.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/xtype_bit.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/xtype_bit.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,118 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.10.2 XTYPE/BIT<br>+<br>+# Count leading<br>+# CHECK: 11 c0 54 88<br>+r17 = clb(r21:20)<br>+# CHECK: 51 c0 54 88<br>+r17 = cl0(r21:20)<br>+# CHECK: 91 c0 54 88<br>+r17 = cl1(r21:20)<br>+# CHECK: 11 c0 74 88<br>+r17 = normamt(r21:20)<br>+# CHECK: 51 d7 74 88<br>+r17 = add(clb(r21:20), #23)<br>+# CHECK: 11 d7 35 8c<br>+r17 = add(clb(r21), #23)<br>+# CHECK: 91 c0 15 8c<br>+r17 = clb(r21)<br>+# CHECK: b1 c0 15 8c<br>+r17 = cl0(r21)<br>+# CHECK: d1 c0 15 8c<br>+r17 = cl1(r21)<br>+# CHECK: f1 c0 15 8c<br>+r17 = normamt(r21)<br>+<br>+# Count population<br>+# CHECK: 71 c0 74 88<br>+r17 = popcount(r21:20)<br>+<br>+# Count trailing<br>+# CHECK: 51 c0 f4 88<br>+r17 = ct0(r21:20)<br>+# CHECK: 91 c0 f4 88<br>+r17 = ct1(r21:20)<br>+# CHECK: 91 c0 55 8c<br>+r17 = ct0(r21)<br>+# CHECK: b1 c0 55 8c<br>+r17 = ct1(r21)<br>+<br>+# Extract bitfield<br>+# CHECK: f0 df 54 81<br>+r17:16 = extractu(r21:20, #31, #23)<br>+# CHECK: f0 df 54 8a<br>+r17:16 = extract(r21:20, #31, #23)<br>+# CHECK: f1 df 55 8d<br>+r17 = extractu(r21, #31, #23)<br>+# CHECK: f1 df d5 8d<br>+r17 = extract(r21, #31, #23)<br>+# CHECK: 10 de 14 c1<br>+r17:16 = extractu(r21:20, r31:30)<br>+# CHECK: 90 de d4 c1<br>+r17:16 = extract(r21:20, r31:30)<br>+# CHECK: 11 de 15 c9<br>+r17 = extractu(r21, r31:30)<br>+# CHECK: 51 de 15 c9<br>+r17 = extract(r21, r31:30)<br>+<br>+# Insert bitfield<br>+# CHECK: f0 df 54 83<br>+r17:16 = insert(r21:20, #31, #23)<br>+# CHECK: f1 df 55 8f<br>+r17 = insert(r21, #31, #23)<br>+# CHECK: 11 de 15 c8<br>+r17 = insert(r21, r31:30)<br>+# CHECK: 10 de 14 ca<br>+r17:16 = insert(r21:20, r31:30)<br>+<br>+# Interleave/deinterleave<br>+# CHECK: 90 c0 d4 80<br>+r17:16 = deinterleave(r21:20)<br>+# CHECK: b0 c0 d4 80<br>+r17:16 = interleave(r21:20)<br>+<br>+# Linear feedback-shift iteration<br>+# CHECK: d0 de 94 c1<br>+r17:16 = lfs(r21:20, r31:30)<br>+<br>+# Masked parity<br>+# CHECK: 11 de 14 d0<br>+r17 = parity(r21:20, r31:30)<br>+# CHECK: 11 df f5 d5<br>+r17 = parity(r21, r31)<br>+<br>+# Bit reverse<br>+# CHECK: d0 c0 d4 80<br>+r17:16 = brev(r21:20)<br>+# CHECK: d1 c0 55 8c<br>+r17 = brev(r21)<br>+<br>+# Set/clear/toggle bit<br>+# CHECK: 11 df d5 8c<br>+r17 = setbit(r21, #31)<br>+# CHECK: 31 df d5 8c<br>+r17 = clrbit(r21, #31)<br>+# CHECK: 51 df d5 8c<br>+r17 = togglebit(r21, #31)<br>+# CHECK: 11 df 95 c6<br>+r17 = setbit(r21, r31)<br>+# CHECK: 51 df 95 c6<br>+r17 = clrbit(r21, r31)<br>+# CHECK: 91 df 95 c6<br>+r17 = togglebit(r21, r31)<br>+<br>+# Split bitfield<br>+# CHECK: 90 df d5 88<br>+r17:16 = bitsplit(r21, #31)<br>+# CHECK: 10 df 35 d4<br>+r17:16 = bitsplit(r21, r31)<br>+<br>+# Table index<br>+# CHECK: f1 cd 15 87<br>+r17 = tableidxb(r21, #7, #13):raw<br>+# CHECK: f1 cd 55 87<br>+r17 = tableidxh(r21, #7, #13):raw<br>+# CHECK: f1 cd 95 87<br>+r17 = tableidxw(r21, #7, #13):raw<br>+# CHECK: f1 cd d5 87<br>+r17 = tableidxd(r21, #7, #13):raw<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/xtype_complex.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_complex.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_complex.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/xtype_complex.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/xtype_complex.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,128 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.10.3 XTYPE/COMPLEX<br>+<br>+# Complex add/sub halfwords<br>+# CHECK: 90 de 54 c1<br>+r17:16 = vxaddsubh(r21:20, r31:30):sat<br>+# CHECK: d0 de 54 c1<br>+r17:16 = vxsubaddh(r21:20, r31:30):sat<br>+# CHECK: 10 de d4 c1<br>+r17:16 = vxaddsubh(r21:20, r31:30):rnd:>>1:sat<br>+# CHECK: 50 de d4 c1<br>+r17:16 = vxsubaddh(r21:20, r31:30):rnd:>>1:sat<br>+<br>+# Complex add/sub words<br>+# CHECK: 10 de 54 c1<br>+r17:16 = vxaddsubw(r21:20, r31:30):sat<br>+# CHECK: 50 de 54 c1<br>+r17:16 = vxsubaddw(r21:20, r31:30):sat<br>+<br>+# Complex multiply<br>+# CHECK: d0 df 15 e5<br>+r17:16 = cmpy(r21, r31):sat<br>+# CHECK: d0 df 95 e5<br>+r17:16 = cmpy(r21, r31):<<1:sat<br>+# CHECK: d0 df 55 e5<br>+r17:16 = cmpy(r21, r31*):sat<br>+# CHECK: d0 df d5 e5<br>+r17:16 = cmpy(r21, r31*):<<1:sat<br>+# CHECK: d0 df 15 e7<br>+r17:16 += cmpy(r21, r31):sat<br>+# CHECK: d0 df 95 e7<br>+r17:16 += cmpy(r21, r31):<<1:sat<br>+# CHECK: f0 df 15 e7<br>+r17:16 -= cmpy(r21, r31):sat<br>+# CHECK: f0 df 95 e7<br>+r17:16 -= cmpy(r21, r31):<<1:sat<br>+# CHECK: d0 df 55 e7<br>+r17:16 += cmpy(r21, r31*):sat<br>+# CHECK: d0 df d5 e7<br>+r17:16 += cmpy(r21, r31*):<<1:sat<br>+# CHECK: f0 df 55 e7<br>+r17:16 -= cmpy(r21, r31*):sat<br>+# CHECK: f0 df d5 e7<br>+r17:16 -= cmpy(r21, r31*):<<1:sat<br>+<br>+# Complex multiply real or imaginary<br>+# CHECK: 30 df 15 e5<br>+r17:16 = cmpyi(r21, r31)<br>+# CHECK: 50 df 15 e5<br>+r17:16 = cmpyr(r21, r31)<br>+# CHECK: 30 df 15 e7<br>+r17:16 += cmpyi(r21, r31)<br>+# CHECK: 50 df 15 e7<br>+r17:16 += cmpyr(r21, r31)<br>+<br>+# Complex multiply with round and pack<br>+# CHECK: d1 df 35 ed<br>+r17 = cmpy(r21, r31):rnd:sat<br>+# CHECK: d1 df b5 ed<br>+r17 = cmpy(r21, r31):<<1:rnd:sat<br>+# CHECK: d1 df 75 ed<br>+r17 = cmpy(r21, r31*):rnd:sat<br>+# CHECK: d1 df f5 ed<br>+r17 = cmpy(r21, r31*):<<1:rnd:sat<br>+<br>+# Complex multiply 32x16<br>+# CHECK: 91 df 14 c5<br>+r17 = cmpyiwh(r21:20, r31):<<1:rnd:sat<br>+# CHECK: b1 df 14 c5<br>+r17 = cmpyiwh(r21:20, r31*):<<1:rnd:sat<br>+# CHECK: d1 df 14 c5<br>+r17 = cmpyrwh(r21:20, r31):<<1:rnd:sat<br>+# CHECK: f1 df 14 c5<br>+r17 = cmpyrwh(r21:20, r31*):<<1:rnd:sat<br>+<br>+# Vector complex multiply real or imaginary<br>+# CHECK: d0 de 34 e8<br>+r17:16 = vcmpyr(r21:20, r31:30):sat<br>+# CHECK: d0 de b4 e8<br>+r17:16 = vcmpyr(r21:20, r31:30):<<1:sat<br>+# CHECK: d0 de 54 e8<br>+r17:16 = vcmpyi(r21:20, r31:30):sat<br>+# CHECK: d0 de d4 e8<br>+r17:16 = vcmpyi(r21:20, r31:30):<<1:sat<br>+# CHECK: 90 de 34 ea<br>+r17:16 += vcmpyr(r21:20, r31:30):sat<br>+# CHECK: 90 de 54 ea<br>+r17:16 += vcmpyi(r21:20, r31:30):sat<br>+<br>+# Vector complex conjugate<br>+# CHECK: f0 c0 94 80<br>+r17:16 = vconj(r21:20):sat<br>+<br>+# Vector complex rotate<br>+# CHECK: 10 df d4 c3<br>+r17:16 = vcrotate(r21:20, r31)<br>+<br>+# Vector reduce complex multiply real or imaginary<br>+# CHECK: 10 de 14 e8<br>+r17:16 = vrcmpyi(r21:20, r31:30)<br>+# CHECK: 30 de 14 e8<br>+r17:16 = vrcmpyr(r21:20, r31:30)<br>+# CHECK: 10 de 54 e8<br>+r17:16 = vrcmpyi(r21:20, r31:30*)<br>+# CHECK: 30 de 74 e8<br>+r17:16 = vrcmpyr(r21:20, r31:30*)<br>+<br>+# Vector reduce complex multiply by scalar<br>+# CHECK: 90 de b4 e8<br>+r17:16 = vrcmpys(r21:20, r31:30):<<1:sat:raw:hi<br>+# CHECK: 90 de f4 e8<br>+r17:16 = vrcmpys(r21:20, r31:30):<<1:sat:raw:lo<br>+# CHECK: 90 de b4 ea<br>+r17:16 += vrcmpys(r21:20, r31:30):<<1:sat:raw:hi<br>+# CHECK: 90 de f4 ea<br>+r17:16 += vrcmpys(r21:20, r31:30):<<1:sat:raw:lo<br>+<br>+# Vector reduce complex multiply by scalar with round and pack<br>+# CHECK: d1 de b4 e9<br>+r17 = vrcmpys(r21:20, r31:30):<<1:rnd:sat:raw:hi<br>+# CHECK: f1 de b4 e9<br>+r17 = vrcmpys(r21:20, r31:30):<<1:rnd:sat:raw:lo<br>+<br>+# Vector reduce complex rotate<br>+# CHECK: f0 ff d4 c3<br>+r17:16 = vrcrotate(r21:20, r31, #3)<br>+# CHECK: 30 ff b4 cb<br>+r17:16 += vrcrotate(r21:20, r31, #3)<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/xtype_fp.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_fp.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_fp.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/xtype_fp.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/xtype_fp.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,146 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.10.4 XTYPE/FP<br>+<br>+# Floating point addition<br>+# CHECK: 11 df 15 eb<br>+r17 = sfadd(r21, r31)<br>+<br>+# Classify floating-point value<br>+# CHECK: 03 d5 f1 85<br>+p3 = sfclass(r17, #21)<br>+# CHECK: b3 c2 90 dc<br>+p3 = dfclass(r17:16, #21)<br>+<br>+# Compare floating-point value<br>+# CHECK: 03 d5 f1 c7<br>+p3 = <a href="http://sfcmp.ge" target="_blank">sfcmp.ge</a>(r17, r21)<br>+# CHECK: 23 d5 f1 c7<br>+p3 = sfcmp.uo(r17, r21)<br>+# CHECK: 63 d5 f1 c7<br>+p3 = sfcmp.eq(r17, r21)<br>+# CHECK: 83 d5 f1 c7<br>+p3 = <a href="http://sfcmp.gt" target="_blank">sfcmp.gt</a>(r17, r21)<br>+# CHECK: 03 d4 f0 d2<br>+p3 = dfcmp.eq(r17:16, r21:20)<br>+# CHECK: 23 d4 f0 d2<br>+p3 = <a href="http://dfcmp.gt" target="_blank">dfcmp.gt</a>(r17:16, r21:20)<br>+# CHECK: 43 d4 f0 d2<br>+p3 = <a href="http://dfcmp.ge" target="_blank">dfcmp.ge</a>(r17:16, r21:20)<br>+# CHECK: 63 d4 f0 d2<br>+p3 = dfcmp.uo(r17:16, r21:20)<br>+<br>+# Convert floating-point value to other format<br>+# CHECK: 10 c0 95 84<br>+r17:16 = convert_sf2df(r21)<br>+# CHECK: 31 c0 14 88<br>+r17 = convert_df2sf(r21:20)<br>+<br>+# Convert integer to floating-point value<br>+# CHECK: 50 c0 f4 80<br>+r17:16 = convert_ud2df(r21:20)<br>+# CHECK: 70 c0 f4 80<br>+r17:16 = convert_d2df(r21:20)<br>+# CHECK: 30 c0 95 84<br>+r17:16 = convert_uw2df(r21)<br>+# CHECK: 50 c0 95 84<br>+r17:16 = convert_w2df(r21)<br>+# CHECK: 31 c0 34 88<br>+r17 = convert_ud2sf(r21:20)<br>+# CHECK: 31 c0 54 88<br>+r17 = convert_d2sf(r21:20)<br>+# CHECK: 11 c0 35 8b<br>+r17 = convert_uw2sf(r21)<br>+# CHECK: 11 c0 55 8b<br>+r17 = convert_w2sf(r21)<br>+<br>+# Convert floating-point value to integer<br>+# CHECK: 10 c0 f4 80<br>+r17:16 = convert_df2d(r21:20)<br>+# CHECK: 30 c0 f4 80<br>+r17:16 = convert_df2ud(r21:20)<br>+# CHECK: d0 c0 f4 80<br>+r17:16 = convert_df2d(r21:20):chop<br>+# CHECK: f0 c0 f4 80<br>+r17:16 = convert_df2ud(r21:20):chop<br>+# CHECK: 70 c0 95 84<br>+r17:16 = convert_sf2ud(r21)<br>+# CHECK: 90 c0 95 84<br>+r17:16 = convert_sf2d(r21)<br>+# CHECK: b0 c0 95 84<br>+r17:16 = convert_sf2ud(r21):chop<br>+# CHECK: d0 c0 95 84<br>+r17:16 = convert_sf2d(r21):chop<br>+# CHECK: 31 c0 74 88<br>+r17 = convert_df2uw(r21:20)<br>+# CHECK: 31 c0 94 88<br>+r17 = convert_df2w(r21:20)<br>+# CHECK: 31 c0 b4 88<br>+r17 = convert_df2uw(r21:20):chop<br>+# CHECK: 31 c0 f4 88<br>+r17 = convert_df2w(r21:20):chop<br>+# CHECK: 11 c0 75 8b<br>+r17 = convert_sf2uw(r21)<br>+# CHECK: 31 c0 75 8b<br>+r17 = convert_sf2uw(r21):chop<br>+# CHECK: 11 c0 95 8b<br>+r17 = convert_sf2w(r21)<br>+# CHECK: 31 c0 95 8b<br>+r17 = convert_sf2w(r21):chop<br>+<br>+# Floating point extreme value assistance<br>+# CHECK: 11 c0 b5 8b<br>+r17 = sffixupr(r21)<br>+# CHECK: 11 df d5 eb<br>+r17 = sffixupn(r21, r31)<br>+# CHECK: 31 df d5 eb<br>+r17 = sffixupd(r21, r31)<br>+<br>+# Floating point fused multiply-add<br>+# CHECK: 91 df 15 ef<br>+r17 += sfmpy(r21, r31)<br>+# CHECK: b1 df 15 ef<br>+r17 -= sfmpy(r21, r31)<br>+<br>+# Floating point fused multiply-add with scaling<br>+# CHECK: f1 df 75 ef<br>+r17 += sfmpy(r21, r31, p3):scale<br>+<br>+# Floating point reciprocal square root approximation<br>+# CHECK: 71 c0 f5 8b<br>+r17, p3 = sfinvsqrta(r21)<br>+<br>+# Floating point fused multiply-add for library routines<br>+# CHECK: d1 df 15 ef<br>+r17 += sfmpy(r21, r31):lib<br>+# CHECK: f1 df 15 ef<br>+r17 -= sfmpy(r21, r31):lib<br>+<br>+# Create floating-point constant<br>+# CHECK: b1 c2 00 d6<br>+r17 = sfmake(#21):pos<br>+# CHECK: b1 c2 40 d6<br>+r17 = sfmake(#21):neg<br>+# CHECK: b0 c2 00 d9<br>+r17:16 = dfmake(#21):pos<br>+# CHECK: b0 c2 40 d9<br>+r17:16 = dfmake(#21):neg<br>+<br>+# Floating point maximum<br>+# CHECK: 11 df 95 eb<br>+r17 = sfmax(r21, r31)<br>+<br>+# Floating point minimum<br>+# CHECK: 31 df 95 eb<br>+r17 = sfmin(r21, r31)<br>+<br>+# Floating point multiply<br>+# CHECK: 11 df 55 eb<br>+r17 = sfmpy(r21, r31)<br>+<br>+# Floating point reciprocal approximation<br>+# CHECK: f1 df f5 eb<br>+r17, p3 = sfrecipa(r21, r31)<br>+<br>+# Floating point subtraction<br>+# CHECK: 31 df 15 eb<br>+r17 = sfsub(r21, r31)<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/xtype_mpy.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_mpy.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_mpy.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/xtype_mpy.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/xtype_mpy.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,400 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.10.5 XTYPE/MPY<br>+<br>+# Multiply and use lower result<br>+# CHECK: b1 df 35 d7<br>+r17 = add(#21, mpyi(r21, r31))<br>+# CHECK: bf d1 35 d8<br>+r17 = add(#21, mpyi(r21, #31))<br>+# CHECK: b5 d1 3f df<br>+r17 = add(r21, mpyi(#84, r31))<br>+# CHECK: f5 f1 b5 df<br>+r17 = add(r21, mpyi(r21, #31))<br>+# CHECK: 15 d1 1f e3<br>+r17 = add(r21, mpyi(r17, r31))<br>+# CHECK: f1 c3 15 e0<br>+r17 =+ mpyi(r21, #31)<br>+# CHECK: f1 c3 95 e0<br>+r17 =- mpyi(r21, #31)<br>+# CHECK: f1 c3 15 e1<br>+r17 += mpyi(r21, #31)<br>+# CHECK: f1 c3 95 e1<br>+r17 -= mpyi(r21, #31)<br>+# CHECK: 11 df 15 ed<br>+r17 = mpyi(r21, r31)<br>+# CHECK: 11 df 15 ef<br>+r17 += mpyi(r21, r31)<br>+<br>+# Vector multiply word by signed half (32x16)<br>+# CHECK: b0 de 14 e8<br>+r17:16 = vmpyweh(r21:20, r31:30):sat<br>+# CHECK: b0 de 94 e8<br>+r17:16 = vmpyweh(r21:20, r31:30):<<1:sat<br>+# CHECK: f0 de 14 e8<br>+r17:16 = vmpywoh(r21:20, r31:30):sat<br>+# CHECK: f0 de 94 e8<br>+r17:16 = vmpywoh(r21:20, r31:30):<<1:sat<br>+# CHECK: b0 de 34 e8<br>+r17:16 = vmpyweh(r21:20, r31:30):rnd:sat<br>+# CHECK: b0 de b4 e8<br>+r17:16 = vmpyweh(r21:20, r31:30):<<1:rnd:sat<br>+# CHECK: f0 de 34 e8<br>+r17:16 = vmpywoh(r21:20, r31:30):rnd:sat<br>+# CHECK: f0 de b4 e8<br>+r17:16 = vmpywoh(r21:20, r31:30):<<1:rnd:sat<br>+# CHECK: b0 de 14 ea<br>+r17:16 += vmpyweh(r21:20, r31:30):sat<br>+# CHECK: b0 de 94 ea<br>+r17:16 += vmpyweh(r21:20, r31:30):<<1:sat<br>+# CHECK: f0 de 14 ea<br>+r17:16 += vmpywoh(r21:20, r31:30):sat<br>+# CHECK: f0 de 94 ea<br>+r17:16 += vmpywoh(r21:20, r31:30):<<1:sat<br>+# CHECK: b0 de 34 ea<br>+r17:16 += vmpyweh(r21:20, r31:30):rnd:sat<br>+# CHECK: b0 de b4 ea<br>+r17:16 += vmpyweh(r21:20, r31:30):<<1:rnd:sat<br>+# CHECK: f0 de 34 ea<br>+r17:16 += vmpywoh(r21:20, r31:30):rnd:sat<br>+# CHECK: f0 de b4 ea<br>+r17:16 += vmpywoh(r21:20, r31:30):<<1:rnd:sat<br>+<br>+# Vector multiply word by unsigned half (32x16)<br>+# CHECK: b0 de 54 e8<br>+r17:16 = vmpyweuh(r21:20, r31:30):sat<br>+# CHECK: b0 de d4 e8<br>+r17:16 = vmpyweuh(r21:20, r31:30):<<1:sat<br>+# CHECK: f0 de 54 e8<br>+r17:16 = vmpywouh(r21:20, r31:30):sat<br>+# CHECK: f0 de d4 e8<br>+r17:16 = vmpywouh(r21:20, r31:30):<<1:sat<br>+# CHECK: b0 de 74 e8<br>+r17:16 = vmpyweuh(r21:20, r31:30):rnd:sat<br>+# CHECK: b0 de f4 e8<br>+r17:16 = vmpyweuh(r21:20, r31:30):<<1:rnd:sat<br>+# CHECK: f0 de 74 e8<br>+r17:16 = vmpywouh(r21:20, r31:30):rnd:sat<br>+# CHECK: f0 de f4 e8<br>+r17:16 = vmpywouh(r21:20, r31:30):<<1:rnd:sat<br>+# CHECK: b0 de 54 ea<br>+r17:16 += vmpyweuh(r21:20, r31:30):sat<br>+# CHECK: b0 de d4 ea<br>+r17:16 += vmpyweuh(r21:20, r31:30):<<1:sat<br>+# CHECK: f0 de 54 ea<br>+r17:16 += vmpywouh(r21:20, r31:30):sat<br>+# CHECK: f0 de d4 ea<br>+r17:16 += vmpywouh(r21:20, r31:30):<<1:sat<br>+# CHECK: b0 de 74 ea<br>+r17:16 += vmpyweuh(r21:20, r31:30):rnd:sat<br>+# CHECK: b0 de f4 ea<br>+r17:16 += vmpyweuh(r21:20, r31:30):<<1:rnd:sat<br>+# CHECK: f0 de 74 ea<br>+r17:16 += vmpywouh(r21:20, r31:30):rnd:sat<br>+# CHECK: f0 de f4 ea<br>+r17:16 += vmpywouh(r21:20, r31:30):<<1:rnd:sat<br>+<br>+# Multiply signed halfwords<br>+# CHECK: 10 df 95 e4<br>+r17:16 = mpy(r21.l, r31.l):<<1<br>+# CHECK: 30 df 95 e4<br>+r17:16 = mpy(r21.l, r31.h):<<1<br>+# CHECK: 50 df 95 e4<br>+r17:16 = mpy(r21.h, r31.l):<<1<br>+# CHECK: 70 df 95 e4<br>+r17:16 = mpy(r21.h, r31.h):<<1<br>+# CHECK: 10 df b5 e4<br>+r17:16 = mpy(r21.l, r31.l):<<1:rnd<br>+# CHECK: 30 df b5 e4<br>+r17:16 = mpy(r21.l, r31.h):<<1:rnd<br>+# CHECK: 50 df b5 e4<br>+r17:16 = mpy(r21.h, r31.l):<<1:rnd<br>+# CHECK: 70 df b5 e4<br>+r17:16 = mpy(r21.h, r31.h):<<1:rnd<br>+# CHECK: 10 df 95 e6<br>+r17:16 += mpy(r21.l, r31.l):<<1<br>+# CHECK: 30 df 95 e6<br>+r17:16 += mpy(r21.l, r31.h):<<1<br>+# CHECK: 50 df 95 e6<br>+r17:16 += mpy(r21.h, r31.l):<<1<br>+# CHECK: 70 df 95 e6<br>+r17:16 += mpy(r21.h, r31.h):<<1<br>+# CHECK: 10 df b5 e6<br>+r17:16 -= mpy(r21.l, r31.l):<<1<br>+# CHECK: 30 df b5 e6<br>+r17:16 -= mpy(r21.l, r31.h):<<1<br>+# CHECK: 50 df b5 e6<br>+r17:16 -= mpy(r21.h, r31.l):<<1<br>+# CHECK: 70 df b5 e6<br>+r17:16 -= mpy(r21.h, r31.h):<<1<br>+# CHECK: 11 df 95 ec<br>+r17 = mpy(r21.l, r31.l):<<1<br>+# CHECK: 31 df 95 ec<br>+r17 = mpy(r21.l, r31.h):<<1<br>+# CHECK: 51 df 95 ec<br>+r17 = mpy(r21.h, r31.l):<<1<br>+# CHECK: 71 df 95 ec<br>+r17 = mpy(r21.h, r31.h):<<1<br>+# CHECK: 91 df 95 ec<br>+r17 = mpy(r21.l, r31.l):<<1:sat<br>+# CHECK: b1 df 95 ec<br>+r17 = mpy(r21.l, r31.h):<<1:sat<br>+# CHECK: d1 df 95 ec<br>+r17 = mpy(r21.h, r31.l):<<1:sat<br>+# CHECK: f1 df 95 ec<br>+r17 = mpy(r21.h, r31.h):<<1:sat<br>+# CHECK: 11 df b5 ec<br>+r17 = mpy(r21.l, r31.l):<<1:rnd<br>+# CHECK: 31 df b5 ec<br>+r17 = mpy(r21.l, r31.h):<<1:rnd<br>+# CHECK: 51 df b5 ec<br>+r17 = mpy(r21.h, r31.l):<<1:rnd<br>+# CHECK: 71 df b5 ec<br>+r17 = mpy(r21.h, r31.h):<<1:rnd<br>+# CHECK: 91 df b5 ec<br>+r17 = mpy(r21.l, r31.l):<<1:rnd:sat<br>+# CHECK: b1 df b5 ec<br>+r17 = mpy(r21.l, r31.h):<<1:rnd:sat<br>+# CHECK: d1 df b5 ec<br>+r17 = mpy(r21.h, r31.l):<<1:rnd:sat<br>+# CHECK: f1 df b5 ec<br>+r17 = mpy(r21.h, r31.h):<<1:rnd:sat<br>+# CHECK: 11 df 95 ee<br>+r17 += mpy(r21.l, r31.l):<<1<br>+# CHECK: 31 df 95 ee<br>+r17 += mpy(r21.l, r31.h):<<1<br>+# CHECK: 51 df 95 ee<br>+r17 += mpy(r21.h, r31.l):<<1<br>+# CHECK: 71 df 95 ee<br>+r17 += mpy(r21.h, r31.h):<<1<br>+# CHECK: 91 df 95 ee<br>+r17 += mpy(r21.l, r31.l):<<1:sat<br>+# CHECK: b1 df 95 ee<br>+r17 += mpy(r21.l, r31.h):<<1:sat<br>+# CHECK: d1 df 95 ee<br>+r17 += mpy(r21.h, r31.l):<<1:sat<br>+# CHECK: f1 df 95 ee<br>+r17 += mpy(r21.h, r31.h):<<1:sat<br>+# CHECK: 11 df b5 ee<br>+r17 -= mpy(r21.l, r31.l):<<1<br>+# CHECK: 31 df b5 ee<br>+r17 -= mpy(r21.l, r31.h):<<1<br>+# CHECK: 51 df b5 ee<br>+r17 -= mpy(r21.h, r31.l):<<1<br>+# CHECK: 71 df b5 ee<br>+r17 -= mpy(r21.h, r31.h):<<1<br>+# CHECK: 91 df b5 ee<br>+r17 -= mpy(r21.l, r31.l):<<1:sat<br>+# CHECK: b1 df b5 ee<br>+r17 -= mpy(r21.l, r31.h):<<1:sat<br>+# CHECK: d1 df b5 ee<br>+r17 -= mpy(r21.h, r31.l):<<1:sat<br>+# CHECK: f1 df b5 ee<br>+r17 -= mpy(r21.h, r31.h):<<1:sat<br>+<br>+# Multiply unsigned halfwords<br>+# CHECK: 10 df d5 e4<br>+r17:16 = mpyu(r21.l, r31.l):<<1<br>+# CHECK: 30 df d5 e4<br>+r17:16 = mpyu(r21.l, r31.h):<<1<br>+# CHECK: 50 df d5 e4<br>+r17:16 = mpyu(r21.h, r31.l):<<1<br>+# CHECK: 70 df d5 e4<br>+r17:16 = mpyu(r21.h, r31.h):<<1<br>+# CHECK: 10 df d5 e6<br>+r17:16 += mpyu(r21.l, r31.l):<<1<br>+# CHECK: 30 df d5 e6<br>+r17:16 += mpyu(r21.l, r31.h):<<1<br>+# CHECK: 50 df d5 e6<br>+r17:16 += mpyu(r21.h, r31.l):<<1<br>+# CHECK: 70 df d5 e6<br>+r17:16 += mpyu(r21.h, r31.h):<<1<br>+# CHECK: 10 df f5 e6<br>+r17:16 -= mpyu(r21.l, r31.l):<<1<br>+# CHECK: 30 df f5 e6<br>+r17:16 -= mpyu(r21.l, r31.h):<<1<br>+# CHECK: 50 df f5 e6<br>+r17:16 -= mpyu(r21.h, r31.l):<<1<br>+# CHECK: 70 df f5 e6<br>+r17:16 -= mpyu(r21.h, r31.h):<<1<br>+# CHECK: 11 df d5 ec<br>+r17 = mpyu(r21.l, r31.l):<<1<br>+# CHECK: 31 df d5 ec<br>+r17 = mpyu(r21.l, r31.h):<<1<br>+# CHECK: 51 df d5 ec<br>+r17 = mpyu(r21.h, r31.l):<<1<br>+# CHECK: 71 df d5 ec<br>+r17 = mpyu(r21.h, r31.h):<<1<br>+# CHECK: 11 df d5 ee<br>+r17 += mpyu(r21.l, r31.l):<<1<br>+# CHECK: 31 df d5 ee<br>+r17 += mpyu(r21.l, r31.h):<<1<br>+# CHECK: 51 df d5 ee<br>+r17 += mpyu(r21.h, r31.l):<<1<br>+# CHECK: 71 df d5 ee<br>+r17 += mpyu(r21.h, r31.h):<<1<br>+# CHECK: 11 df f5 ee<br>+r17 -= mpyu(r21.l, r31.l):<<1<br>+# CHECK: 31 df f5 ee<br>+r17 -= mpyu(r21.l, r31.h):<<1<br>+# CHECK: 51 df f5 ee<br>+r17 -= mpyu(r21.h, r31.l):<<1<br>+# CHECK: 71 df f5 ee<br>+r17 -= mpyu(r21.h, r31.h):<<1<br>+<br>+# Polynomial multiply words<br>+# CHECK: f0 df 55 e5<br>+r17:16 = pmpyw(r21, r31)<br>+# CHECK: f0 df 35 e7<br>+r17:16 ^= pmpyw(r21, r31)<br>+<br>+# Vector reduce multiply word by signed half (32x16)<br>+# CHECK: 50 de 34 e8<br>+r17:16 = vrmpywoh(r21:20, r31:30)<br>+# CHECK: 50 de b4 e8<br>+r17:16 = vrmpywoh(r21:20, r31:30):<<1<br>+# CHECK: 90 de 54 e8<br>+r17:16 = vrmpyweh(r21:20, r31:30)<br>+# CHECK: 90 de d4 e8<br>+r17:16 = vrmpyweh(r21:20, r31:30):<<1<br>+# CHECK: d0 de 74 ea<br>+r17:16 += vrmpywoh(r21:20, r31:30)<br>+# CHECK: d0 de f4 ea<br>+r17:16 += vrmpywoh(r21:20, r31:30):<<1<br>+# CHECK: d0 de 34 ea<br>+r17:16 += vrmpyweh(r21:20, r31:30)<br>+# CHECK: d0 de b4 ea<br>+r17:16 += vrmpyweh(r21:20, r31:30):<<1<br>+<br>+# Multiply and use upper result<br>+# CHECK: 31 df 15 ed<br>+r17 = mpy(r21, r31)<br>+# CHECK: 31 df 35 ed<br>+r17 = mpy(r21, r31):rnd<br>+# CHECK: 31 df 55 ed<br>+r17 = mpyu(r21, r31)<br>+# CHECK: 31 df 75 ed<br>+r17 = mpysu(r21, r31)<br>+# CHECK: 11 df b5 ed<br>+r17 = mpy(r21, r31.h):<<1:sat<br>+# CHECK: 31 df b5 ed<br>+r17 = mpy(r21, r31.l):<<1:sat<br>+# CHECK: 91 df b5 ed<br>+r17 = mpy(r21, r31.h):<<1:rnd:sat<br>+# CHECK: 11 df f5 ed<br>+r17 = mpy(r21, r31):<<1:sat<br>+# CHECK: 91 df f5 ed<br>+r17 = mpy(r21, r31.l):<<1:rnd:sat<br>+# CHECK: 51 df b5 ed<br>+r17 = mpy(r21, r31):<<1<br>+# CHECK: 11 df 75 ef<br>+r17 += mpy(r21, r31):<<1:sat<br>+# CHECK: 31 df 75 ef<br>+r17 -= mpy(r21, r31):<<1:sat<br>+<br>+# Multiply and use full result<br>+# CHECK: 10 df 15 e5<br>+r17:16 = mpy(r21, r31)<br>+# CHECK: 10 df 55 e5<br>+r17:16 = mpyu(r21, r31)<br>+# CHECK: 10 df 15 e7<br>+r17:16 += mpy(r21, r31)<br>+# CHECK: 10 df 35 e7<br>+r17:16 -= mpy(r21, r31)<br>+# CHECK: 10 df 55 e7<br>+r17:16 += mpyu(r21, r31)<br>+# CHECK: 10 df 75 e7<br>+r17:16 -= mpyu(r21, r31)<br>+<br>+# Vector dual multiply<br>+# CHECK: 90 de 14 e8<br>+r17:16 = vdmpy(r21:20, r31:30):sat<br>+# CHECK: 90 de 94 e8<br>+r17:16 = vdmpy(r21:20, r31:30):<<1:sat<br>+# CHECK: 90 de 14 ea<br>+r17:16 += vdmpy(r21:20, r31:30):sat<br>+# CHECK: 90 de 94 ea<br>+r17:16 += vdmpy(r21:20, r31:30):<<1:sat<br>+<br>+# Vector dual multiply with round and pack<br>+# CHECK: 11 de 14 e9<br>+r17 = vdmpy(r21:20, r31:30):rnd:sat<br>+# CHECK: 11 de 94 e9<br>+r17 = vdmpy(r21:20, r31:30):<<1:rnd:sat<br>+<br>+# Vector reduce multiply bytes<br>+# CHECK: 30 de 94 e8<br>+r17:16 = vrmpybu(r21:20, r31:30)<br>+# CHECK: 30 de d4 e8<br>+r17:16 = vrmpybsu(r21:20, r31:30)<br>+# CHECK: 30 de 94 ea<br>+r17:16 += vrmpybu(r21:20, r31:30)<br>+# CHECK: 30 de d4 ea<br>+r17:16 += vrmpybsu(r21:20, r31:30)<br>+<br>+# Vector dual multiply signed by unsigned bytes<br>+# CHECK: 30 de b4 e8<br>+r17:16 = vdmpybsu(r21:20, r31:30):sat<br>+# CHECK: 30 de 34 ea<br>+r17:16 += vdmpybsu(r21:20, r31:30):sat<br>+<br>+# Vector multiply even haldwords<br>+# CHECK: d0 de 14 e8<br>+r17:16 = vmpyeh(r21:20, r31:30):sat<br>+# CHECK: d0 de 94 e8<br>+r17:16 = vmpyeh(r21:20, r31:30):<<1:sat<br>+# CHECK: 50 de 34 ea<br>+r17:16 += vmpyeh(r21:20, r31:30)<br>+# CHECK: d0 de 14 ea<br>+r17:16 += vmpyeh(r21:20, r31:30):sat<br>+# CHECK: d0 de 94 ea<br>+r17:16 += vmpyeh(r21:20, r31:30):<<1:sat<br>+<br>+# Vector multiply halfwords<br>+# CHECK: b0 df 15 e5<br>+r17:16 = vmpyh(r21, r31):sat<br>+# CHECK: b0 df 95 e5<br>+r17:16 = vmpyh(r21, r31):<<1:sat<br>+# CHECK: 30 df 35 e7<br>+r17:16 += vmpyh(r21, r31)<br>+# CHECK: b0 df 15 e7<br>+r17:16 += vmpyh(r21, r31):sat<br>+# CHECK: b0 df 95 e7<br>+r17:16 += vmpyh(r21, r31):<<1:sat<br>+<br>+# Vector multiply halfwords with round and pack<br>+# CHECK: f1 df 35 ed<br>+r17 = vmpyh(r21, r31):rnd:sat<br>+# CHECK: f1 df b5 ed<br>+r17 = vmpyh(r21, r31):<<1:rnd:sat<br>+<br>+# Vector multiply halfwords signed by unsigned<br>+# CHECK: f0 df 15 e5<br>+r17:16 = vmpyhsu(r21, r31):sat<br>+# CHECK: f0 df 95 e5<br>+r17:16 = vmpyhsu(r21, r31):<<1:sat<br>+# CHECK: b0 df 75 e7<br>+r17:16 += vmpyhsu(r21, r31):sat<br>+# CHECK: b0 df f5 e7<br>+r17:16 += vmpyhsu(r21, r31):<<1:sat<br>+<br>+# Vector reduce multiply halfwords<br>+# CHECK: 50 de 14 e8<br>+r17:16 = vrmpyh(r21:20, r31:30)<br>+# CHECK: 50 de 14 ea<br>+r17:16 += vrmpyh(r21:20, r31:30)<br>+<br>+# Vector multiply bytes<br>+# CHECK: 30 df 55 e5<br>+r17:16 = vmpybsu(r21, r31)<br>+# CHECK: 30 df 95 e5<br>+r17:16 = vmpybu(r21, r31)<br>+# CHECK: 30 df 95 e7<br>+r17:16 += vmpybu(r21, r31)<br>+# CHECK: 30 df d5 e7<br>+r17:16 += vmpybsu(r21, r31)<br>+<br>+# Vector polynomial multiply halfwords<br>+# CHECK: f0 df d5 e5<br>+r17:16 = vpmpyh(r21, r31)<br>+# CHECK: f0 df b5 e7<br>+r17:16 ^= vpmpyh(r21, r31)<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/xtype_perm.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_perm.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_perm.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/xtype_perm.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/xtype_perm.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,104 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.10.6 XTYPE/PERM<br>+<br>+# CABAC decode bin<br>+# CHECK: d0 de d4 c1<br>+r17:16 = decbin(r21:20, r31:30)<br>+<br>+# Saturate<br>+# CHECK: 11 c0 d4 88<br>+r17 = sat(r21:20)<br>+# CHECK: 91 c0 d5 8c<br>+r17 = sath(r21)<br>+# CHECK: b1 c0 d5 8c<br>+r17 = satuh(r21)<br>+# CHECK: d1 c0 d5 8c<br>+r17 = satub(r21)<br>+# CHECK: f1 c0 d5 8c<br>+r17 = satb(r21)<br>+<br>+# Swizzle bytes<br>+# CHECK: f1 c0 95 8c<br>+r17 = swiz(r21)<br>+<br>+# Vector align<br>+# CHECK: 70 d4 1e c2<br>+r17:16 = valignb(r21:20, r31:30, p3)<br>+# CHECK: 70 de 94 c2<br>+r17:16 = vspliceb(r21:20, r31:30, p3)<br>+<br>+# Vector round and pack<br>+# CHECK: 91 c0 94 88<br>+r17 = vrndwh(r21:20)<br>+# CHECK: d1 c0 94 88<br>+r17 = vrndwh(r21:20):sat<br>+<br>+# Vector saturate and pack<br>+# CHECK: 11 c0 14 88<br>+r17 = vsathub(r21:20)<br>+# CHECK: 51 c0 14 88<br>+r17 = vsatwh(r21:20)<br>+# CHECK: 91 c0 14 88<br>+r17 = vsatwuh(r21:20)<br>+# CHECK: d1 c0 14 88<br>+r17 = vsathb(r21:20)<br>+# CHECK: 11 c0 95 8c<br>+r17 = vsathb(r21)<br>+# CHECK: 51 c0 95 8c<br>+r17 = vsathub(r21)<br>+<br>+# Vector saturate without pack<br>+# CHECK: 90 c0 14 80<br>+r17:16 = vsathub(r21:20)<br>+# CHECK: b0 c0 14 80<br>+r17:16 = vsatwuh(r21:20)<br>+# CHECK: d0 c0 14 80<br>+r17:16 = vsatwh(r21:20)<br>+# CHECK: f0 c0 14 80<br>+r17:16 = vsathb(r21:20)<br>+<br>+# Vector shuffle<br>+# CHECK: 50 de 14 c1<br>+r17:16 = shuffeb(r21:20, r31:30)<br>+# CHECK: 90 d4 1e c1<br>+r17:16 = shuffob(r21:20, r31:30)<br>+# CHECK: d0 de 14 c1<br>+r17:16 = shuffeh(r21:20, r31:30)<br>+# CHECK: 10 d4 9e c1<br>+r17:16 = shuffoh(r21:20, r31:30)<br>+<br>+# Vector splat bytes<br>+# CHECK: f1 c0 55 8c<br>+r17 = vsplatb(r21)<br>+<br>+# Vector splat halfwords<br>+# CHECK: 50 c0 55 84<br>+r17:16 = vsplath(r21)<br>+<br>+# Vector splice<br>+# CHECK: 70 de 94 c0<br>+r17:16 = vspliceb(r21:20, r31:30, #3)<br>+# CHECK: 70 de 94 c2<br>+r17:16 = vspliceb(r21:20, r31:30, p3)<br>+<br>+# Vector sign extend<br>+# CHECK: 10 c0 15 84<br>+r17:16 = vsxtbh(r21)<br>+# CHECK: 90 c0 15 84<br>+r17:16 = vsxthw(r21)<br>+<br>+# Vector truncate<br>+# CHECK: 11 c0 94 88<br>+r17 = vtrunohb(r21:20)<br>+# CHECK: 51 c0 94 88<br>+r17 = vtrunehb(r21:20)<br>+# CHECK: 50 de 94 c1<br>+r17:16 = vtrunewh(r21:20, r31:30)<br>+# CHECK: 90 de 94 c1<br>+r17:16 = vtrunowh(r21:20, r31:30)<br>+<br>+# Vector zero extend<br>+# CHECK: 50 c0 15 84<br>+r17:16 = vzxtbh(r21)<br>+# CHECK: d0 c0 15 84<br>+r17:16 = vzxthw(r21)<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/xtype_pred.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_pred.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_pred.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/xtype_pred.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/xtype_pred.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,136 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.10.7 XTYPE/PRED<br>+<br>+# Bounds check<br>+# CHECK: 83 f4 10 d2<br>+p3 = boundscheck(r17:16, r21:20):raw:lo<br>+# CHECK: a3 f4 10 d2<br>+p3 = boundscheck(r17:16, r21:20):raw:hi<br>+<br>+# Compare byte<br>+# CHECK: 43 d5 d1 c7<br>+p3 = <a href="http://cmpb.gt" target="_blank">cmpb.gt</a>(r17, r21)<br>+# CHECK: c3 d5 d1 c7<br>+p3 = cmpb.eq(r17, r21)<br>+# CHECK: e3 d5 d1 c7<br>+p3 = cmpb.gtu(r17, r21)<br>+# CHECK: a3 c2 11 dd<br>+p3 = cmpb.eq(r17, #21)<br>+# CHECK: a3 c2 31 dd<br>+p3 = <a href="http://cmpb.gt" target="_blank">cmpb.gt</a>(r17, #21)<br>+# CHECK: a3 c2 51 dd<br>+p3 = cmpb.gtu(r17, #21)<br>+<br>+# Compare half<br>+# CHECK: 63 d5 d1 c7<br>+p3 = cmph.eq(r17, r21)<br>+# CHECK: 83 d5 d1 c7<br>+p3 = <a href="http://cmph.gt" target="_blank">cmph.gt</a>(r17, r21)<br>+# CHECK: a3 d5 d1 c7<br>+p3 = cmph.gtu(r17, r21)<br>+# CHECK: ab c2 11 dd<br>+p3 = cmph.eq(r17, #21)<br>+# CHECK: ab c2 31 dd<br>+p3 = <a href="http://cmph.gt" target="_blank">cmph.gt</a>(r17, #21)<br>+# CHECK: ab c2 51 dd<br>+p3 = cmph.gtu(r17, #21)<br>+<br>+# Compare doublewords<br>+# CHECK: 03 de 94 d2<br>+p3 = cmp.eq(r21:20, r31:30)<br>+# CHECK: 43 de 94 d2<br>+p3 = <a href="http://cmp.gt" target="_blank">cmp.gt</a>(r21:20, r31:30)<br>+# CHECK: 83 de 94 d2<br>+p3 = cmp.gtu(r21:20, r31:30)<br>+<br>+# Compare bitmask<br>+# CHECK: 03 d5 91 85<br>+p3 = bitsclr(r17, #21)<br>+# CHECK: 03 d5 b1 85<br>+p3 = !bitsclr(r17, #21)<br>+# CHECK: 03 d5 51 c7<br>+p3 = bitsset(r17, r21)<br>+# CHECK: 03 d5 71 c7<br>+p3 = !bitsset(r17, r21)<br>+# CHECK: 03 d5 91 c7<br>+p3 = bitsclr(r17, r21)<br>+# CHECK: 03 d5 b1 c7<br>+p3 = !bitsclr(r17, r21)<br>+<br>+# mask generate from predicate<br>+# CHECK: 10 c3 00 86<br>+r17:16 = mask(p3)<br>+<br>+# Check for TLB match<br>+# CHECK: 63 f5 10 d2<br>+p3 = tlbmatch(r17:16, r21)<br>+<br>+# Predicate Transfer<br>+# CHECK: 03 c0 45 85<br>+p3 = r5<br>+# CHECK: 05 c0 43 89<br>+r5 = p3<br>+<br>+# Test bit<br>+# CHECK: 03 d5 11 85<br>+p3 = tstbit(r17, #21)<br>+# CHECK: 03 d5 31 85<br>+p3 = !tstbit(r17, #21)<br>+# CHECK: 03 d5 11 c7<br>+p3 = tstbit(r17, r21)<br>+# CHECK: 03 d5 31 c7<br>+p3 = !tstbit(r17, r21)<br>+<br>+# Vector compare halfwords<br>+# CHECK: 63 de 14 d2<br>+p3 = vcmph.eq(r21:20, r31:30)<br>+# CHECK: 83 de 14 d2<br>+p3 = <a href="http://vcmph.gt" target="_blank">vcmph.gt</a>(r21:20, r31:30)<br>+# CHECK: a3 de 14 d2<br>+p3 = vcmph.gtu(r21:20, r31:30)<br>+# CHECK: eb c3 14 dc<br>+p3 = vcmph.eq(r21:20, #31)<br>+# CHECK: eb c3 34 dc<br>+p3 = <a href="http://vcmph.gt" target="_blank">vcmph.gt</a>(r21:20, #31)<br>+# CHECK: eb c3 54 dc<br>+p3 = vcmph.gtu(r21:20, #31)<br>+<br>+# Vector compare bytes for any match<br>+# CHECK: 03 fe 14 d2<br>+p3 = any8(vcmpb.eq(r21:20, r31:30))<br>+<br>+# Vector compare bytes<br>+# CHECK: 63 de 14 d2<br>+p3 = vcmph.eq(r21:20, r31:30)<br>+# CHECK: 83 de 14 d2<br>+p3 = <a href="http://vcmph.gt" target="_blank">vcmph.gt</a>(r21:20, r31:30)<br>+# CHECK: a3 de 14 d2<br>+p3 = vcmph.gtu(r21:20, r31:30)<br>+# CHECK: eb c3 14 dc<br>+p3 = vcmph.eq(r21:20, #31)<br>+# CHECK: eb c3 34 dc<br>+p3 = <a href="http://vcmph.gt" target="_blank">vcmph.gt</a>(r21:20, #31)<br>+# CHECK: eb c3 54 dc<br>+p3 = vcmph.gtu(r21:20, #31)<br>+<br>+# Vector compare words<br>+# CHECK: 03 de 14 d2<br>+p3 = vcmpw.eq(r21:20, r31:30)<br>+# CHECK: 23 de 14 d2<br>+p3 = <a href="http://vcmpw.gt" target="_blank">vcmpw.gt</a>(r21:20, r31:30)<br>+# CHECK: 43 de 14 d2<br>+p3 = vcmpw.gtu(r21:20, r31:30)<br>+# CHECK: f3 c3 14 dc<br>+p3 = vcmpw.eq(r21:20, #31)<br>+# CHECK: f3 c3 34 dc<br>+p3 = <a href="http://vcmpw.gt" target="_blank">vcmpw.gt</a>(r21:20, #31)<br>+# CHECK: f3 c3 54 dc<br>+p3 = vcmpw.gtu(r21:20, #31)<br>+<br>+# Viterbi pack even and odd predicate bits<br>+# CHECK: 11 c2 03 89<br>+r17 = vitpack(p3, p2)<br>+<br>+# Vector mux<br>+# CHECK: 70 de 14 d1<br>+r17:16 = vmux(p3, r21:20, r31:30)<br><br>Added: llvm/trunk/test/MC/Hexagon/instructions/xtype_shift.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_shift.s?rev=252443&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/xtype_shift.s?rev=252443&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/MC/Hexagon/instructions/xtype_shift.s (added)<br>+++ llvm/trunk/test/MC/Hexagon/instructions/xtype_shift.s Sun Nov 8 22:07:48 2015<br>@@ -0,0 +1,260 @@<br>+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s<br>+# Hexagon Programmer's Reference Manual 11.10.8 XTYPE/SHIFT<br>+<br>+# Shift by immediate<br>+# CHECK: 10 df 14 80<br>+r17:16 = asr(r21:20, #31)<br>+# CHECK: 30 df 14 80<br>+r17:16 = lsr(r21:20, #31)<br>+# CHECK: 50 df 14 80<br>+r17:16 = asl(r21:20, #31)<br>+# CHECK: 11 df 15 8c<br>+r17 = asr(r21, #31)<br>+# CHECK: 31 df 15 8c<br>+r17 = lsr(r21, #31)<br>+# CHECK: 51 df 15 8c<br>+r17 = asl(r21, #31)<br>+<br>+# Shift by immediate and accumulate<br>+# CHECK: 10 df 14 82<br>+r17:16 -= asr(r21:20, #31)<br>+# CHECK: 30 df 14 82<br>+r17:16 -= lsr(r21:20, #31)<br>+# CHECK: 50 df 14 82<br>+r17:16 -= asl(r21:20, #31)<br>+# CHECK: 90 df 14 82<br>+r17:16 += asr(r21:20, #31)<br>+# CHECK: b0 df 14 82<br>+r17:16 += lsr(r21:20, #31)<br>+# CHECK: d0 df 14 82<br>+r17:16 += asl(r21:20, #31)<br>+# CHECK: 11 df 15 8e<br>+r17 -= asr(r21, #31)<br>+# CHECK: 31 df 15 8e<br>+r17 -= lsr(r21, #31)<br>+# CHECK: 51 df 15 8e<br>+r17 -= asl(r21, #31)<br>+# CHECK: 91 df 15 8e<br>+r17 += asr(r21, #31)<br>+# CHECK: b1 df 15 8e<br>+r17 += lsr(r21, #31)<br>+# CHECK: d1 df 15 8e<br>+r17 += asl(r21, #31)<br>+# CHECK: 4c f7 11 de<br>+r17 = add(#21, asl(r17, #23))<br>+# CHECK: 4e f7 11 de<br>+r17 = sub(#21, asl(r17, #23))<br>+# CHECK: 5c f7 11 de<br>+r17 = add(#21, lsr(r17, #23))<br>+# CHECK: 5e f7 11 de<br>+r17 = sub(#21, lsr(r17, #23))<br>+<br>+# Shift by immediate and add<br>+# CHECK: f1 d5 1f c4<br>+r17 = addasl(r21, r31, #7)<br>+<br>+# Shift by immediate and logical<br>+# CHECK: 10 df 54 82<br>+r17:16 &= asr(r21:20, #31)<br>+# CHECK: 30 df 54 82<br>+r17:16 &= lsr(r21:20, #31)<br>+# CHECK: 50 df 54 82<br>+r17:16 &= asl(r21:20, #31)<br>+# CHECK: 90 df 54 82<br>+r17:16 |= asr(r21:20, #31)<br>+# CHECK: b0 df 54 82<br>+r17:16 |= lsr(r21:20, #31)<br>+# CHECK: d0 df 54 82<br>+r17:16 |= asl(r21:20, #31)<br>+# CHECK: 30 df 94 82<br>+r17:16 ^= lsr(r21:20, #31)<br>+# CHECK: 50 df 94 82<br>+r17:16 ^= asl(r21:20, #31)<br>+# CHECK: 11 df 55 8e<br>+r17 &= asr(r21, #31)<br>+# CHECK: 31 df 55 8e<br>+r17 &= lsr(r21, #31)<br>+# CHECK: 51 df 55 8e<br>+r17 &= asl(r21, #31)<br>+# CHECK: 91 df 55 8e<br>+r17 |= asr(r21, #31)<br>+# CHECK: b1 df 55 8e<br>+r17 |= lsr(r21, #31)<br>+# CHECK: d1 df 55 8e<br>+r17 |= asl(r21, #31)<br>+# CHECK: 31 df 95 8e<br>+r17 ^= lsr(r21, #31)<br>+# CHECK: 51 df 95 8e<br>+r17 ^= asl(r21, #31)<br>+# CHECK: 48 ff 11 de<br>+r17 = and(#21, asl(r17, #31))<br>+# CHECK: 4a ff 11 de<br>+r17 = or(#21, asl(r17, #31))<br>+# CHECK: 58 ff 11 de<br>+r17 = and(#21, lsr(r17, #31))<br>+# CHECK: 5a ff 11 de<br>+r17 = or(#21, lsr(r17, #31))<br>+<br>+# Shift right by immediate with rounding<br>+# CHECK: f0 df d4 80<br>+r17:16 = asr(r21:20, #31):rnd<br>+# CHECK: 11 df 55 8c<br>+r17 = asr(r21, #31):rnd<br>+<br>+# Shift left by immediate with saturation<br>+# CHECK: 51 df 55 8c<br>+r17 = asl(r21, #31):sat<br>+<br>+# Shift by register<br>+# CHECK: 10 df 94 c3<br>+r17:16 = asr(r21:20, r31)<br>+# CHECK: 50 df 94 c3<br>+r17:16 = lsr(r21:20, r31)<br>+# CHECK: 90 df 94 c3<br>+r17:16 = asl(r21:20, r31)<br>+# CHECK: d0 df 94 c3<br>+r17:16 = lsl(r21:20, r31)<br>+# CHECK: 11 df 55 c6<br>+r17 = asr(r21, r31)<br>+# CHECK: 51 df 55 c6<br>+r17 = lsr(r21, r31)<br>+# CHECK: 91 df 55 c6<br>+r17 = asl(r21, r31)<br>+# CHECK: d1 df 55 c6<br>+r17 = lsl(r21, r31)<br>+# CHECK: f1 df 8a c6<br>+r17 = lsl(#21, r31)<br>+<br>+# Shift by register and accumulate<br>+# CHECK: 10 df 94 cb<br>+r17:16 -= asr(r21:20, r31)<br>+# CHECK: 50 df 94 cb<br>+r17:16 -= lsr(r21:20, r31)<br>+# CHECK: 90 df 94 cb<br>+r17:16 -= asl(r21:20, r31)<br>+# CHECK: d0 df 94 cb<br>+r17:16 -= lsl(r21:20, r31)<br>+# CHECK: 10 df d4 cb<br>+r17:16 += asr(r21:20, r31)<br>+# CHECK: 50 df d4 cb<br>+r17:16 += lsr(r21:20, r31)<br>+# CHECK: 90 df d4 cb<br>+r17:16 += asl(r21:20, r31)<br>+# CHECK: d0 df d4 cb<br>+r17:16 += lsl(r21:20, r31)<br>+# CHECK: 11 df 95 cc<br>+r17 -= asr(r21, r31)<br>+# CHECK: 51 df 95 cc<br>+r17 -= lsr(r21, r31)<br>+# CHECK: 91 df 95 cc<br>+r17 -= asl(r21, r31)<br>+# CHECK: d1 df 95 cc<br>+r17 -= lsl(r21, r31)<br>+# CHECK: 11 df d5 cc<br>+r17 += asr(r21, r31)<br>+# CHECK: 51 df d5 cc<br>+r17 += lsr(r21, r31)<br>+# CHECK: 91 df d5 cc<br>+r17 += asl(r21, r31)<br>+# CHECK: d1 df d5 cc<br>+r17 += lsl(r21, r31)<br>+<br>+# Shift by register and logical<br>+# CHECK: 10 df 14 cb<br>+r17:16 |= asr(r21:20, r31)<br>+# CHECK: 50 df 14 cb<br>+r17:16 |= lsr(r21:20, r31)<br>+# CHECK: 90 df 14 cb<br>+r17:16 |= asl(r21:20, r31)<br>+# CHECK: d0 df 14 cb<br>+r17:16 |= lsl(r21:20, r31)<br>+# CHECK: 10 df 54 cb<br>+r17:16 &= asr(r21:20, r31)<br>+# CHECK: 50 df 54 cb<br>+r17:16 &= lsr(r21:20, r31)<br>+# CHECK: 90 df 54 cb<br>+r17:16 &= asl(r21:20, r31)<br>+# CHECK: d0 df 54 cb<br>+r17:16 &= lsl(r21:20, r31)<br>+# CHECK: 10 df 74 cb<br>+r17:16 ^= asr(r21:20, r31)<br>+# CHECK: 50 df 74 cb<br>+r17:16 ^= lsr(r21:20, r31)<br>+# CHECK: 90 df 74 cb<br>+r17:16 ^= asl(r21:20, r31)<br>+# CHECK: d0 df 74 cb<br>+r17:16 ^= lsl(r21:20, r31)<br>+# CHECK: 11 df 15 cc<br>+r17 |= asr(r21, r31)<br>+# CHECK: 51 df 15 cc<br>+r17 |= lsr(r21, r31)<br>+# CHECK: 91 df 15 cc<br>+r17 |= asl(r21, r31)<br>+# CHECK: d1 df 15 cc<br>+r17 |= lsl(r21, r31)<br>+# CHECK: 11 df 55 cc<br>+r17 &= asr(r21, r31)<br>+# CHECK: 51 df 55 cc<br>+r17 &= lsr(r21, r31)<br>+# CHECK: 91 df 55 cc<br>+r17 &= asl(r21, r31)<br>+# CHECK: d1 df 55 cc<br>+r17 &= lsl(r21, r31)<br>+<br>+# Shift by register with saturation<br>+# CHECK: 11 df 15 c6<br>+r17 = asr(r21, r31):sat<br>+# CHECK: 91 df 15 c6<br>+r17 = asl(r21, r31):sat<br>+<br>+# Vector shift halfwords by immediate<br>+# CHECK: 10 c5 94 80<br>+r17:16 = vasrh(r21:20, #5)<br>+# CHECK: 30 c5 94 80<br>+r17:16 = vlsrh(r21:20, #5)<br>+# CHECK: 50 c5 94 80<br>+r17:16 = vaslh(r21:20, #5)<br>+<br>+# Vector arithmetic shift halfwords with round<br>+# CHECK: 10 c5 34 80<br>+r17:16 = vasrh(r21:20, #5):raw<br>+<br>+# Vector arithmetic shift halfwords with saturate and pack<br>+# CHECK: 91 c5 74 88<br>+r17 = vasrhub(r21:20, #5):raw<br>+# CHECK: b1 c5 74 88<br>+r17 = vasrhub(r21:20, #5):sat<br>+<br>+# Vector shift halfwords by register<br>+# CHECK: 10 df 54 c3<br>+r17:16 = vasrh(r21:20, r31)<br>+# CHECK: 50 df 54 c3<br>+r17:16 = vlsrh(r21:20, r31)<br>+# CHECK: 90 df 54 c3<br>+r17:16 = vaslh(r21:20, r31)<br>+# CHECK: d0 df 54 c3<br>+r17:16 = vlslh(r21:20, r31)<br>+<br>+# Vector shift words by immediate<br>+# CHECK: 10 df 54 80<br>+r17:16 = vasrw(r21:20, #31)<br>+# CHECK: 30 df 54 80<br>+r17:16 = vlsrw(r21:20, #31)<br>+# CHECK: 50 df 54 80<br>+r17:16 = vaslw(r21:20, #31)<br>+<br>+# Vector shift words by register<br>+# CHECK: 10 df 14 c3<br>+r17:16 = vasrw(r21:20, r31)<br>+# CHECK: 50 df 14 c3<br>+r17:16 = vlsrw(r21:20, r31)<br>+# CHECK: 90 df 14 c3<br>+r17:16 = vaslw(r21:20, r31)<br>+# CHECK: d0 df 14 c3<br>+r17:16 = vlslw(r21:20, r31)<br>+<br>+# Vector shift words with truncate and pack<br>+# CHECK: 51 df d4 88<br>+r17 = vasrw(r21:20, #31)<br>+# CHECK: 51 df 14 c5<br>+r17 = vasrw(r21:20, r31)<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><o:p></o:p></p></blockquote></div><p class=MsoNormal><o:p> </o:p></p></div></div></body></html>