<div dir="ltr">Given that there are hundreds of other lines of code that explicitly hardcode MVTs into calls to setOperationAction this seemed no worse to make these sequences explicitly mentioned near the calls that are in loops. These list aren't going to change as they are vector types supported in SSE, AVX, and AVX2 which are defined by hardware.<div><br></div><div>Same with the integer ones in the other commit. We aren't suddenly going to be able to support a different size operation.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Oct 28, 2015 at 9:35 AM, David Blaikie <span dir="ltr"><<a href="mailto:dblaikie@gmail.com" target="_blank">dblaikie@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Oct 27, 2015 at 10:48 PM, Craig Topper via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ctopper<br>
Date: Wed Oct 28 00:48:32 2015<br>
New Revision: 251500<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=251500&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=251500&view=rev</a><br>
Log:<br>
[X86] Make some for loops over MVTs more explicit (and shorter) by just mentioning all the relevant types in an initializer list. NFC<br></blockquote><div><br></div><div>More duplication of this sequence - I'm still not sure that's an improvement? (but perhaps there's existing precedent that shows this is the right way)</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=251500&r1=251499&r2=251500&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=251500&r1=251499&r2=251500&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Oct 28 00:48:32 2015<br>
@@ -858,14 +858,7 @@ X86TargetLowering::X86TargetLowering(con<br>
// ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.<br>
<br>
// Custom lower build_vector, vector_shuffle, and extract_vector_elt.<br>
- for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {<br>
- MVT VT = (MVT::SimpleValueType)i;<br>
- // Do not attempt to custom lower non-power-of-2 vectors<br>
- if (!isPowerOf2_32(VT.getVectorNumElements()))<br>
- continue;<br>
- // Do not attempt to custom lower non-128-bit vectors<br>
- if (!VT.is128BitVector())<br>
- continue;<br>
+ for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {<br>
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);<br>
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);<br>
setOperationAction(ISD::VSELECT, VT, Custom);<br>
@@ -903,13 +896,7 @@ X86TargetLowering::X86TargetLowering(con<br>
}<br>
<br>
// Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.<br>
- for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {<br>
- MVT VT = (MVT::SimpleValueType)i;<br>
-<br>
- // Do not attempt to promote non-128-bit vectors<br>
- if (!VT.is128BitVector())<br>
- continue;<br>
-<br>
+ for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {<br>
setOperationAction(ISD::AND, VT, Promote);<br>
AddPromotedToType (ISD::AND, VT, MVT::v2i64);<br>
setOperationAction(ISD::OR, VT, Promote);<br>
@@ -1288,13 +1275,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);<br>
<br>
// Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.<br>
- for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {<br>
- MVT VT = (MVT::SimpleValueType)i;<br>
-<br>
- // Do not attempt to promote non-256-bit vectors<br>
- if (!VT.is256BitVector())<br>
- continue;<br>
-<br>
+ for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {<br>
setOperationAction(ISD::AND, VT, Promote);<br>
AddPromotedToType (ISD::AND, VT, MVT::v4i64);<br>
setOperationAction(ISD::OR, VT, Promote);<br>
@@ -1602,13 +1583,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::MSTORE, VT, Legal);<br>
}<br>
}<br>
- for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {<br>
- MVT VT = (MVT::SimpleValueType)i;<br>
-<br>
- // Do not attempt to promote non-512-bit vectors.<br>
- if (!VT.is512BitVector())<br>
- continue;<br>
-<br>
+ for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {<br>
setOperationAction(ISD::SELECT, VT, Promote);<br>
AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);<br>
}<br>
@@ -1685,19 +1660,9 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);<br>
}<br>
<br>
- for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {<br>
- const MVT VT = (MVT::SimpleValueType)i;<br>
-<br>
- const unsigned EltSize = VT.getVectorElementType().getSizeInBits();<br>
-<br>
- // Do not attempt to promote non-512-bit vectors.<br>
- if (!VT.is512BitVector())<br>
- continue;<br>
-<br>
- if (EltSize < 32) {<br>
- setOperationAction(ISD::BUILD_VECTOR, VT, Custom);<br>
- setOperationAction(ISD::VSELECT, VT, Legal);<br>
- }<br>
+ for (auto VT : { MVT::v64i8, MVT::v32i16 }) {<br>
+ setOperationAction(ISD::BUILD_VECTOR, VT, Custom);<br>
+ setOperationAction(ISD::VSELECT, VT, Legal);<br>
}<br>
}<br>
<br>
<br>
<br>
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</blockquote></div><br></div></div>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature">~Craig</div>
</div>