<div dir="ltr">Interesting, were these getting called from the front end correctly?<div><br></div><div>-eric</div></div><br><div class="gmail_quote"><div dir="ltr">On Tue, Oct 20, 2015 at 4:22 AM Andrea Di Biagio via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: adibiagio<br>
Date: Tue Oct 20 06:20:13 2015<br>
New Revision: 250817<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=250817&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=250817&view=rev</a><br>
Log:<br>
[x86] Fix AVX maskload/store intrinsic prototypes.<br>
<br>
The mask value type for maskload/maskstore GCC builtins is never a vector of<br>
packed floats/doubles.<br>
<br>
This patch fixes the following issues:<br>
1. The mask argument for builtin_ia32_maskloadpd and builtin_ia32_maskstorepd<br>
should be of type llvm_v2i64_ty and not llvm_v2f64_ty.<br>
2. The mask argument for builtin_ia32_maskloadpd256 and<br>
builtin_ia32_maskstorepd256 should be of type llvm_v4i64_ty and not<br>
llvm_v4f64_ty.<br>
3. The mask argument for builtin_ia32_maskloadps and builtin_ia32_maskstoreps<br>
should be of type llvm_v4i32_ty and not llvm_v4f32_ty.<br>
4. The mask argument for builtin_ia32_maskloadps256 and<br>
builtin_ia32_maskstoreps256 should be of type llvm_v8i32_ty and not<br>
llvm_v8f32_ty.<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D13776" rel="noreferrer" target="_blank">http://reviews.llvm.org/D13776</a><br>
<br>
Modified:<br>
llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll<br>
llvm/trunk/test/CodeGen/X86/avx-load-store.ll<br>
llvm/trunk/test/CodeGen/X86/avx-win64.ll<br>
<br>
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=250817&r1=250816&r2=250817&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=250817&r1=250816&r2=250817&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)<br>
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Tue Oct 20 06:20:13 2015<br>
@@ -1760,16 +1760,16 @@ let TargetPrefix = "x86" in { // All in<br>
// Conditional load ops<br>
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".<br>
def int_x86_avx_maskload_pd : GCCBuiltin<"__builtin_ia32_maskloadpd">,<br>
- Intrinsic<[llvm_v2f64_ty], [llvm_ptr_ty, llvm_v2f64_ty],<br>
+ Intrinsic<[llvm_v2f64_ty], [llvm_ptr_ty, llvm_v2i64_ty],<br>
[IntrReadArgMem]>;<br>
def int_x86_avx_maskload_ps : GCCBuiltin<"__builtin_ia32_maskloadps">,<br>
- Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty, llvm_v4f32_ty],<br>
+ Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty, llvm_v4i32_ty],<br>
[IntrReadArgMem]>;<br>
def int_x86_avx_maskload_pd_256 : GCCBuiltin<"__builtin_ia32_maskloadpd256">,<br>
- Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty, llvm_v4f64_ty],<br>
+ Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty, llvm_v4i64_ty],<br>
[IntrReadArgMem]>;<br>
def int_x86_avx_maskload_ps_256 : GCCBuiltin<"__builtin_ia32_maskloadps256">,<br>
- Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty, llvm_v8f32_ty],<br>
+ Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty, llvm_v8i32_ty],<br>
[IntrReadArgMem]>;<br>
def int_x86_avx512_mask_loadu_ps_512 : GCCBuiltin<"__builtin_ia32_loadups512_mask">,<br>
Intrinsic<[llvm_v16f32_ty], [llvm_ptr_ty, llvm_v16f32_ty, llvm_i16_ty],<br>
@@ -1789,18 +1789,18 @@ let TargetPrefix = "x86" in { // All in<br>
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".<br>
def int_x86_avx_maskstore_pd : GCCBuiltin<"__builtin_ia32_maskstorepd">,<br>
Intrinsic<[], [llvm_ptr_ty,<br>
- llvm_v2f64_ty, llvm_v2f64_ty], [IntrReadWriteArgMem]>;<br>
+ llvm_v2i64_ty, llvm_v2f64_ty], [IntrReadWriteArgMem]>;<br>
def int_x86_avx_maskstore_ps : GCCBuiltin<"__builtin_ia32_maskstoreps">,<br>
Intrinsic<[], [llvm_ptr_ty,<br>
- llvm_v4f32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>;<br>
+ llvm_v4i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>;<br>
def int_x86_avx_maskstore_pd_256 :<br>
GCCBuiltin<"__builtin_ia32_maskstorepd256">,<br>
Intrinsic<[], [llvm_ptr_ty,<br>
- llvm_v4f64_ty, llvm_v4f64_ty], [IntrReadWriteArgMem]>;<br>
+ llvm_v4i64_ty, llvm_v4f64_ty], [IntrReadWriteArgMem]>;<br>
def int_x86_avx_maskstore_ps_256 :<br>
GCCBuiltin<"__builtin_ia32_maskstoreps256">,<br>
Intrinsic<[], [llvm_ptr_ty,<br>
- llvm_v8f32_ty, llvm_v8f32_ty], [IntrReadWriteArgMem]>;<br>
+ llvm_v8i32_ty, llvm_v8f32_ty], [IntrReadWriteArgMem]>;<br>
def int_x86_avx512_mask_storeu_ps_512 :<br>
GCCBuiltin<"__builtin_ia32_storeups512_mask">,<br>
Intrinsic<[], [llvm_ptr_ty, llvm_v16f32_ty, llvm_i16_ty],<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=250817&r1=250816&r2=250817&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=250817&r1=250816&r2=250817&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Tue Oct 20 06:20:13 2015<br>
@@ -2536,102 +2536,102 @@ define <32 x i8> @test_x86_avx_ldu_dq_25<br>
declare <32 x i8> @llvm.x86.avx.ldu.dq.256(i8*) nounwind readonly<br>
<br>
<br>
-define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x double> %a1) {<br>
+define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x i64> %mask) {<br>
; CHECK-LABEL: test_x86_avx_maskload_pd:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
; CHECK-NEXT: vmaskmovpd (%eax), %xmm0, %xmm0<br>
; CHECK-NEXT: retl<br>
- %res = call <2 x double> @llvm.x86.avx.maskload.pd(i8* %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]<br>
+ %res = call <2 x double> @llvm.x86.avx.maskload.pd(i8* %a0, <2 x i64> %mask) ; <<2 x double>> [#uses=1]<br>
ret <2 x double> %res<br>
}<br>
-declare <2 x double> @llvm.x86.avx.maskload.pd(i8*, <2 x double>) nounwind readonly<br>
+declare <2 x double> @llvm.x86.avx.maskload.pd(i8*, <2 x i64>) nounwind readonly<br>
<br>
<br>
-define <4 x double> @test_x86_avx_maskload_pd_256(i8* %a0, <4 x double> %a1) {<br>
+define <4 x double> @test_x86_avx_maskload_pd_256(i8* %a0, <4 x i64> %mask) {<br>
; CHECK-LABEL: test_x86_avx_maskload_pd_256:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
; CHECK-NEXT: vmaskmovpd (%eax), %ymm0, %ymm0<br>
; CHECK-NEXT: retl<br>
- %res = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]<br>
+ %res = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* %a0, <4 x i64> %mask) ; <<4 x double>> [#uses=1]<br>
ret <4 x double> %res<br>
}<br>
-declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8*, <4 x double>) nounwind readonly<br>
+declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8*, <4 x i64>) nounwind readonly<br>
<br>
<br>
-define <4 x float> @test_x86_avx_maskload_ps(i8* %a0, <4 x float> %a1) {<br>
+define <4 x float> @test_x86_avx_maskload_ps(i8* %a0, <4 x i32> %mask) {<br>
; CHECK-LABEL: test_x86_avx_maskload_ps:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
; CHECK-NEXT: vmaskmovps (%eax), %xmm0, %xmm0<br>
; CHECK-NEXT: retl<br>
- %res = call <4 x float> @<a href="http://llvm.x86.avx.maskload.ps" rel="noreferrer" target="_blank">llvm.x86.avx.maskload.ps</a>(i8* %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]<br>
+ %res = call <4 x float> @<a href="http://llvm.x86.avx.maskload.ps" rel="noreferrer" target="_blank">llvm.x86.avx.maskload.ps</a>(i8* %a0, <4 x i32> %mask) ; <<4 x float>> [#uses=1]<br>
ret <4 x float> %res<br>
}<br>
-declare <4 x float> @<a href="http://llvm.x86.avx.maskload.ps" rel="noreferrer" target="_blank">llvm.x86.avx.maskload.ps</a>(i8*, <4 x float>) nounwind readonly<br>
+declare <4 x float> @<a href="http://llvm.x86.avx.maskload.ps" rel="noreferrer" target="_blank">llvm.x86.avx.maskload.ps</a>(i8*, <4 x i32>) nounwind readonly<br>
<br>
<br>
-define <8 x float> @test_x86_avx_maskload_ps_256(i8* %a0, <8 x float> %a1) {<br>
+define <8 x float> @test_x86_avx_maskload_ps_256(i8* %a0, <8 x i32> %mask) {<br>
; CHECK-LABEL: test_x86_avx_maskload_ps_256:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
; CHECK-NEXT: vmaskmovps (%eax), %ymm0, %ymm0<br>
; CHECK-NEXT: retl<br>
- %res = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]<br>
+ %res = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* %a0, <8 x i32> %mask) ; <<8 x float>> [#uses=1]<br>
ret <8 x float> %res<br>
}<br>
-declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x float>) nounwind readonly<br>
+declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x i32>) nounwind readonly<br>
<br>
<br>
-define void @test_x86_avx_maskstore_pd(i8* %a0, <2 x double> %a1, <2 x double> %a2) {<br>
+define void @test_x86_avx_maskstore_pd(i8* %a0, <2 x i64> %mask, <2 x double> %a2) {<br>
; CHECK-LABEL: test_x86_avx_maskstore_pd:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
; CHECK-NEXT: vmaskmovpd %xmm1, %xmm0, (%eax)<br>
; CHECK-NEXT: retl<br>
- call void @llvm.x86.avx.maskstore.pd(i8* %a0, <2 x double> %a1, <2 x double> %a2)<br>
+ call void @llvm.x86.avx.maskstore.pd(i8* %a0, <2 x i64> %mask, <2 x double> %a2)<br>
ret void<br>
}<br>
-declare void @llvm.x86.avx.maskstore.pd(i8*, <2 x double>, <2 x double>) nounwind<br>
+declare void @llvm.x86.avx.maskstore.pd(i8*, <2 x i64>, <2 x double>) nounwind<br>
<br>
<br>
-define void @test_x86_avx_maskstore_pd_256(i8* %a0, <4 x double> %a1, <4 x double> %a2) {<br>
+define void @test_x86_avx_maskstore_pd_256(i8* %a0, <4 x i64> %mask, <4 x double> %a2) {<br>
; CHECK-LABEL: test_x86_avx_maskstore_pd_256:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
; CHECK-NEXT: vmaskmovpd %ymm1, %ymm0, (%eax)<br>
; CHECK-NEXT: vzeroupper<br>
; CHECK-NEXT: retl<br>
- call void @llvm.x86.avx.maskstore.pd.256(i8* %a0, <4 x double> %a1, <4 x double> %a2)<br>
+ call void @llvm.x86.avx.maskstore.pd.256(i8* %a0, <4 x i64> %mask, <4 x double> %a2)<br>
ret void<br>
}<br>
-declare void @llvm.x86.avx.maskstore.pd.256(i8*, <4 x double>, <4 x double>) nounwind<br>
+declare void @llvm.x86.avx.maskstore.pd.256(i8*, <4 x i64>, <4 x double>) nounwind<br>
<br>
<br>
-define void @test_x86_avx_maskstore_ps(i8* %a0, <4 x float> %a1, <4 x float> %a2) {<br>
+define void @test_x86_avx_maskstore_ps(i8* %a0, <4 x i32> %mask, <4 x float> %a2) {<br>
; CHECK-LABEL: test_x86_avx_maskstore_ps:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
; CHECK-NEXT: vmaskmovps %xmm1, %xmm0, (%eax)<br>
; CHECK-NEXT: retl<br>
- call void @<a href="http://llvm.x86.avx.maskstore.ps" rel="noreferrer" target="_blank">llvm.x86.avx.maskstore.ps</a>(i8* %a0, <4 x float> %a1, <4 x float> %a2)<br>
+ call void @<a href="http://llvm.x86.avx.maskstore.ps" rel="noreferrer" target="_blank">llvm.x86.avx.maskstore.ps</a>(i8* %a0, <4 x i32> %mask, <4 x float> %a2)<br>
ret void<br>
}<br>
-declare void @<a href="http://llvm.x86.avx.maskstore.ps" rel="noreferrer" target="_blank">llvm.x86.avx.maskstore.ps</a>(i8*, <4 x float>, <4 x float>) nounwind<br>
+declare void @<a href="http://llvm.x86.avx.maskstore.ps" rel="noreferrer" target="_blank">llvm.x86.avx.maskstore.ps</a>(i8*, <4 x i32>, <4 x float>) nounwind<br>
<br>
<br>
-define void @test_x86_avx_maskstore_ps_256(i8* %a0, <8 x float> %a1, <8 x float> %a2) {<br>
+define void @test_x86_avx_maskstore_ps_256(i8* %a0, <8 x i32> %mask, <8 x float> %a2) {<br>
; CHECK-LABEL: test_x86_avx_maskstore_ps_256:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
; CHECK-NEXT: vmaskmovps %ymm1, %ymm0, (%eax)<br>
; CHECK-NEXT: vzeroupper<br>
; CHECK-NEXT: retl<br>
- call void @<a href="http://llvm.x86.avx.maskstore.ps" target="_blank">llvm.x86.avx.maskstore.ps</a>.256(i8* %a0, <8 x float> %a1, <8 x float> %a2)<br>
+ call void @<a href="http://llvm.x86.avx.maskstore.ps" target="_blank">llvm.x86.avx.maskstore.ps</a>.256(i8* %a0, <8 x i32> %mask, <8 x float> %a2)<br>
ret void<br>
}<br>
-declare void @<a href="http://llvm.x86.avx.maskstore.ps" target="_blank">llvm.x86.avx.maskstore.ps</a>.256(i8*, <8 x float>, <8 x float>) nounwind<br>
+declare void @<a href="http://llvm.x86.avx.maskstore.ps" target="_blank">llvm.x86.avx.maskstore.ps</a>.256(i8*, <8 x i32>, <8 x float>) nounwind<br>
<br>
<br>
define <4 x double> @test_x86_avx_max_pd_256(<4 x double> %a0, <4 x double> %a1) {<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx-load-store.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-load-store.ll?rev=250817&r1=250816&r2=250817&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-load-store.ll?rev=250817&r1=250816&r2=250817&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-load-store.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-load-store.ll Tue Oct 20 06:20:13 2015<br>
@@ -88,7 +88,7 @@ entry:<br>
ret void<br>
}<br>
<br>
-declare void @<a href="http://llvm.x86.avx.maskstore.ps" target="_blank">llvm.x86.avx.maskstore.ps</a>.256(i8*, <8 x float>, <8 x float>) nounwind<br>
+declare void @<a href="http://llvm.x86.avx.maskstore.ps" target="_blank">llvm.x86.avx.maskstore.ps</a>.256(i8*, <8 x i32>, <8 x float>) nounwind<br>
<br>
; CHECK_O0: _f_f<br>
; CHECK-O0: vmovss LCPI<br>
@@ -105,7 +105,7 @@ cif_mask_mixed:<br>
br i1 undef, label %cif_mixed_test_all, label %cif_mixed_test_any_check<br>
<br>
cif_mixed_test_all: ; preds = %cif_mask_mixed<br>
- call void @<a href="http://llvm.x86.avx.maskstore.ps" target="_blank">llvm.x86.avx.maskstore.ps</a>.256(i8* undef, <8 x float> <float 0xFFFFFFFFE0000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, <8 x float> undef) nounwind<br>
+ call void @<a href="http://llvm.x86.avx.maskstore.ps" target="_blank">llvm.x86.avx.maskstore.ps</a>.256(i8* undef, <8 x i32> <i32 -1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <8 x float> undef) nounwind<br>
unreachable<br>
<br>
cif_mixed_test_any_check: ; preds = %cif_mask_mixed<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx-win64.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-win64.ll?rev=250817&r1=250816&r2=250817&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-win64.ll?rev=250817&r1=250816&r2=250817&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-win64.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-win64.ll Tue Oct 20 06:20:13 2015<br>
@@ -42,6 +42,4 @@ safe_if_after_false:<br>
}<br>
<br>
declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone<br>
-declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x float>) nounwind readonly<br>
-declare void @<a href="http://llvm.x86.avx.maskstore.ps" target="_blank">llvm.x86.avx.maskstore.ps</a>.256(i8*, <8 x float>, <8 x float>) nounwind<br>
declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone<br>
<br>
<br>
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</blockquote></div>