<div dir="ltr">Seems like the CodeGen/X86/absdiff_expand.ll test should have been updated. It started failing: <a href="http://lab.llvm.org:8011/builders/llvm-ppc64-linux1/builds/19689">http://lab.llvm.org:8011/builders/llvm-ppc64-linux1/builds/19689</a><div><br></div><div>Please fix or revert.<br><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Sep 24, 2015 at 12:35 PM, Mohammad Shahid via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Author: ashahid<br>
Date: Thu Sep 24 05:35:03 2015<br>
New Revision: 248483<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=248483&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=248483&view=rev</a><br>
Log:<br>
Codegen: Fix llvm.*absdiff semantic.<br>
<br>
Fixes the overflow case of llvm.*absdiff intrinsic also updats the tests and LangRef.rst accordingly.<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D11678" rel="noreferrer" target="_blank">http://reviews.llvm.org/D11678</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/absdiff_128.ll<br>
llvm/trunk/test/CodeGen/X86/absdiff_256.ll<br>
Modified:<br>
llvm/trunk/docs/LangRef.rst<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp<br>
<br>
Modified: llvm/trunk/docs/LangRef.rst<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.rst?rev=248483&r1=248482&r2=248483&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.rst?rev=248483&r1=248482&r2=248483&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/docs/LangRef.rst (original)<br>
+++ llvm/trunk/docs/LangRef.rst Thu Sep 24 05:35:03 2015<br>
@@ -10920,16 +10920,19 @@ This is an overloaded intrinsic. The loa<br>
Overview:<br>
"""""""""<br>
<br>
-The ``llvm.uabsdiff`` intrinsic returns a vector result of the absolute difference of<br>
-the two operands, treating them both as unsigned integers.<br>
+The ``llvm.uabsdiff`` intrinsic returns a vector result of the absolute difference<br>
+of the two operands, treating them both as unsigned integers. The intermediate<br>
+calculations are computed using infinitely precise unsigned arithmetic. The final<br>
+result will be truncated to the given type.<br>
<br>
The ``llvm.sabsdiff`` intrinsic returns a vector result of the absolute difference of<br>
-the two operands, treating them both as signed integers.<br>
+the two operands, treating them both as signed integers. If the result overflows, the<br>
+behavior is undefined.<br>
<br>
.. note::<br>
<br>
These intrinsics are primarily used during the code generation stage of compilation.<br>
- They are generated by compiler passes such as the Loop and SLP <a href="http://vectorizers.it" rel="noreferrer" target="_blank">vectorizers.it</a> is not<br>
+ They are generated by compiler passes such as the Loop and SLP vectorizers. It is not<br>
recommended for users to create them manually.<br>
<br>
Arguments:<br>
@@ -10946,19 +10949,19 @@ The expression::<br>
<br>
is equivalent to::<br>
<br>
- %sub = sub <4 x i32> %a, %b<br>
- %ispos = icmp ugt <4 x i32> %sub, <i32 -1, i32 -1, i32 -1, i32 -1><br>
- %neg = sub <4 x i32> zeroinitializer, %sub<br>
- %1 = select <4 x i1> %ispos, <4 x i32> %sub, <4 x i32> %neg<br>
+ %1 = zext <4 x i32> %a to <4 x i64><br>
+ %2 = zext <4 x i32> %b to <4 x i64><br>
+ %sub = sub <4 x i64> %1, %2<br>
+ %trunc = trunc <4 x i64> to <4 x i32><br>
<br>
-Similarly the expression::<br>
+and the expression::<br>
<br>
call <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32> %a, <4 x i32> %b)<br>
<br>
is equivalent to::<br>
<br>
%sub = sub nsw <4 x i32> %a, %b<br>
- %ispos = icmp sgt <4 x i32> %sub, <i32 -1, i32 -1, i32 -1, i32 -1><br>
+ %ispos = icmp sge <4 x i32> %sub, zeroinitializer<br>
%neg = sub nsw <4 x i32> zeroinitializer, %sub<br>
%1 = select <4 x i1> %ispos, <4 x i32> %sub, <4 x i32> %neg<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=248483&r1=248482&r2=248483&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=248483&r1=248482&r2=248483&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Thu Sep 24 05:35:03 2015<br>
@@ -723,24 +723,30 @@ SDValue VectorLegalizer::Expand(SDValue<br>
<br>
SDValue VectorLegalizer::ExpandABSDIFF(SDValue Op) {<br>
SDLoc dl(Op);<br>
- SDValue Tmp1, Tmp2, Tmp3, Tmp4;<br>
+ SDValue Op0 = Op.getOperand(0);<br>
+ SDValue Op1 = Op.getOperand(1);<br>
EVT VT = Op.getValueType();<br>
+<br>
+ // For unsigned intrinsic, promote the type to handle unsigned overflow.<br>
+ bool isUabsdiff = (Op->getOpcode() == ISD::UABSDIFF);<br>
+ if (isUabsdiff) {<br>
+ VT = VT.widenIntegerVectorElementType(*DAG.getContext());<br>
+ Op0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op0);<br>
+ Op1 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op1);<br>
+ }<br>
+<br>
SDNodeFlags Flags;<br>
- Flags.setNoSignedWrap(Op->getOpcode() == ISD::SABSDIFF);<br>
+ Flags.setNoSignedWrap(!isUabsdiff);<br>
+ SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op0, Op1, &Flags);<br>
+ if (isUabsdiff)<br>
+ return DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Sub);<br>
<br>
- Tmp2 = Op.getOperand(0);<br>
- Tmp3 = Op.getOperand(1);<br>
- Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp3, &Flags);<br>
- Tmp2 =<br>
- DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), Tmp1, &Flags);<br>
- Tmp4 = DAG.getNode(<br>
- ISD::SETCC, dl,<br>
- TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), Tmp2,<br>
- DAG.getConstant(0, dl, VT),<br>
- DAG.getCondCode(Op->getOpcode() == ISD::SABSDIFF ? ISD::SETLT<br>
- : ISD::SETULT));<br>
- Tmp1 = DAG.getNode(ISD::VSELECT, dl, VT, Tmp4, Tmp1, Tmp2);<br>
- return Tmp1;<br>
+ SDValue Cmp =<br>
+ DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(DAG.getDataLayout(),<br>
+ *DAG.getContext(), VT),<br>
+ Sub, DAG.getConstant(0, dl, VT), DAG.getCondCode(ISD::SETGE));<br>
+ SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), Sub, &Flags);<br>
+ return DAG.getNode(ISD::VSELECT, dl, VT, Cmp, Sub, Neg);<br>
}<br>
<br>
SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/absdiff_128.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/absdiff_128.ll?rev=248483&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/absdiff_128.ll?rev=248483&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/absdiff_128.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/absdiff_128.ll Thu Sep 24 05:35:03 2015<br>
@@ -0,0 +1,181 @@<br>
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s<br>
+<br>
+declare <4 x i8> @llvm.uabsdiff.v4i8(<4 x i8>, <4 x i8>)<br>
+<br>
+define <4 x i8> @test_uabsdiff_v4i8_expand(<4 x i8> %a1, <4 x i8> %a2) {<br>
+; CHECK-LABEL: test_uabsdiff_v4i8_expand<br>
+; CHECK: pshufd<br>
+; CHECK: movd<br>
+; CHECK: subl<br>
+; CHECK: punpckldq<br>
+; CHECK-DAG: movd %xmm1, [[SRC:%.*]]<br>
+; CHECK-DAG: movd %xmm0, [[DST:%.*]]<br>
+; CHECK: subl [[SRC]], [[DST]]<br>
+; CHECK: movd<br>
+; CHECK: pshufd<br>
+; CHECK: movd<br>
+; CHECK: punpckldq<br>
+; CHECK: movdqa<br>
+; CHECK: retq<br>
+<br>
+ %1 = call <4 x i8> @llvm.uabsdiff.v4i8(<4 x i8> %a1, <4 x i8> %a2)<br>
+ ret <4 x i8> %1<br>
+}<br>
+<br>
+declare <4 x i8> @llvm.sabsdiff.v4i8(<4 x i8>, <4 x i8>)<br>
+<br>
+define <4 x i8> @test_sabsdiff_v4i8_expand(<4 x i8> %a1, <4 x i8> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v4i8_expand<br>
+; CHECK: psubd<br>
+; CHECK: pcmpgtd<br>
+; CHECK: pcmpeqd<br>
+; CHECK: pxor<br>
+; CHECK-DAG: psubd {{%xmm[0-9]+}}, [[SRC1:%xmm[0-9]+]]<br>
+; CHECK-DAG: pandn {{%xmm[0-9]+}}, [[SRC2:%xmm[0-9]+]]<br>
+; CHECK-DAG: pandn [[SRC1]], [[DST:%xmm[0-9]+]]<br>
+; CHECK: por [[SRC2]], [[DST]]<br>
+; CHECK: retq<br>
+<br>
+ %1 = call <4 x i8> @llvm.sabsdiff.v4i8(<4 x i8> %a1, <4 x i8> %a2)<br>
+ ret <4 x i8> %1<br>
+}<br>
+<br>
+declare <8 x i8> @llvm.sabsdiff.v8i8(<8 x i8>, <8 x i8>)<br>
+<br>
+define <8 x i8> @test_sabsdiff_v8i8_expand(<8 x i8> %a1, <8 x i8> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v8i8_expand<br>
+; CHECK: psubw<br>
+; CHECK: pcmpgtw<br>
+; CHECK: pcmpeqd<br>
+; CHECK: pxor<br>
+; CHECK-DAG: psubw {{%xmm[0-9]+}}, [[SRC1:%xmm[0-9]+]]<br>
+; CHECK-DAG: pandn {{%xmm[0-9]+}}, [[SRC2:%xmm[0-9]+]]<br>
+; CHECK-DAG: pandn [[SRC1]], [[DST:%xmm[0-9]+]]<br>
+; CHECK: por [[SRC2]], [[DST]]<br>
+; CHECK: retq<br>
+<br>
+ %1 = call <8 x i8> @llvm.sabsdiff.v8i8(<8 x i8> %a1, <8 x i8> %a2)<br>
+ ret <8 x i8> %1<br>
+}<br>
+<br>
+declare <16 x i8> @llvm.uabsdiff.v16i8(<16 x i8>, <16 x i8>)<br>
+<br>
+define <16 x i8> @test_uabsdiff_v16i8_expand(<16 x i8> %a1, <16 x i8> %a2) {<br>
+; CHECK-LABEL: test_uabsdiff_v16i8_expand<br>
+; CHECK: movd<br>
+; CHECK: movzbl<br>
+; CHECK: movzbl<br>
+; CHECK: subl<br>
+; CHECK: punpcklbw<br>
+; CHECK: retq<br>
+<br>
+ %1 = call <16 x i8> @llvm.uabsdiff.v16i8(<16 x i8> %a1, <16 x i8> %a2)<br>
+ ret <16 x i8> %1<br>
+}<br>
+<br>
+declare <8 x i16> @llvm.uabsdiff.v8i16(<8 x i16>, <8 x i16>)<br>
+<br>
+define <8 x i16> @test_uabsdiff_v8i16_expand(<8 x i16> %a1, <8 x i16> %a2) {<br>
+; CHECK-LABEL: test_uabsdiff_v8i16_expand<br>
+; CHECK: pextrw<br>
+; CHECK: pextrw<br>
+; CHECK: subl<br>
+; CHECK: punpcklwd<br>
+; CHECK: retq<br>
+<br>
+ %1 = call <8 x i16> @llvm.uabsdiff.v8i16(<8 x i16> %a1, <8 x i16> %a2)<br>
+ ret <8 x i16> %1<br>
+}<br>
+<br>
+declare <8 x i16> @llvm.sabsdiff.v8i16(<8 x i16>, <8 x i16>)<br>
+<br>
+define <8 x i16> @test_sabsdiff_v8i16_expand(<8 x i16> %a1, <8 x i16> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v8i16_expand<br>
+; CHECK: psubw<br>
+; CHECK: pcmpgtw<br>
+; CHECK: pcmpeqd<br>
+; CHECK: pxor<br>
+; CHECK-DAG: psubw {{%xmm[0-9]+}}, [[SRC1:%xmm[0-9]+]]<br>
+; CHECK-DAG: pandn {{%xmm[0-9]+}}, [[SRC2:%xmm[0-9]+]]<br>
+; CHECK-DAG: pandn [[SRC1]], [[DST:%xmm[0-9]+]]<br>
+; CHECK: por [[SRC2]], [[DST]]<br>
+; CHECK: retq<br>
+<br>
+ %1 = call <8 x i16> @llvm.sabsdiff.v8i16(<8 x i16> %a1, <8 x i16> %a2)<br>
+ ret <8 x i16> %1<br>
+}<br>
+<br>
+declare <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32>, <4 x i32>)<br>
+<br>
+define <4 x i32> @test_sabsdiff_v4i32_expand(<4 x i32> %a1, <4 x i32> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v4i32_expand<br>
+; CHECK: psubd<br>
+; CHECK: pcmpgtd<br>
+; CHECK: pcmpeqd<br>
+; CHECK: pxor<br>
+; CHECK-DAG: psubd {{%xmm[0-9]+}}, [[SRC1:%xmm[0-9]+]]<br>
+; CHECK-DAG: pandn {{%xmm[0-9]+}}, [[SRC2:%xmm[0-9]+]]<br>
+; CHECK-DAG: pandn [[SRC1]], [[DST:%xmm[0-9]+]]<br>
+; CHECK: por [[SRC2]], [[DST]]<br>
+; CHECK: retq<br>
+ %1 = call <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32> %a1, <4 x i32> %a2)<br>
+ ret <4 x i32> %1<br>
+}<br>
+<br>
+declare <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32>, <4 x i32>)<br>
+<br>
+define <4 x i32> @test_uabsdiff_v4i32_expand(<4 x i32> %a1, <4 x i32> %a2) {<br>
+; CHECK-LABEL: test_uabsdiff_v4i32_expand<br>
+; CHECK: pshufd<br>
+; CHECK: movd<br>
+; CHECK: subl<br>
+; CHECK: punpckldq<br>
+; CHECK-DAG: movd %xmm1, [[SRC:%.*]]<br>
+; CHECK-DAG: movd %xmm0, [[DST:%.*]]<br>
+; CHECK: subl [[SRC]], [[DST]]<br>
+; CHECK: movd<br>
+; CHECK: pshufd<br>
+; CHECK: movd<br>
+; CHECK: punpckldq<br>
+; CHECK: movdqa<br>
+; CHECK: retq<br>
+<br>
+ %1 = call <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32> %a1, <4 x i32> %a2)<br>
+ ret <4 x i32> %1<br>
+}<br>
+<br>
+declare <2 x i32> @llvm.sabsdiff.v2i32(<2 x i32>, <2 x i32>)<br>
+<br>
+define <2 x i32> @test_sabsdiff_v2i32_expand(<2 x i32> %a1, <2 x i32> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v2i32_expand<br>
+; CHECK: psubq<br>
+; CHECK: pcmpgtd<br>
+; CHECK: pcmpeqd<br>
+; CHECK: pxor<br>
+; CHECK-DAG: psubq {{%xmm[0-9]+}}, [[SRC1:%xmm[0-9]+]]<br>
+; CHECK-DAG: pandn {{%xmm[0-9]+}}, [[SRC2:%xmm[0-9]+]]<br>
+; CHECK-DAG: pandn [[SRC1]], [[DST:%xmm[0-9]+]]<br>
+; CHECK: por [[SRC2]], [[DST]]<br>
+; CHECK: retq<br>
+<br>
+ %1 = call <2 x i32> @llvm.sabsdiff.v2i32(<2 x i32> %a1, <2 x i32> %a2)<br>
+ ret <2 x i32> %1<br>
+}<br>
+<br>
+declare <2 x i64> @llvm.sabsdiff.v2i64(<2 x i64>, <2 x i64>)<br>
+<br>
+define <2 x i64> @test_sabsdiff_v2i64_expand(<2 x i64> %a1, <2 x i64> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v2i64_expand<br>
+; CHECK: psubq<br>
+; CHECK: pcmpgtd<br>
+; CHECK: pcmpeqd<br>
+; CHECK: pxor<br>
+; CHECK-DAG: psubq {{%xmm[0-9]+}}, [[SRC1:%xmm[0-9]+]]<br>
+; CHECK-DAG: pandn {{%xmm[0-9]+}}, [[SRC2:%xmm[0-9]+]]<br>
+; CHECK-DAG: pandn [[SRC1]], [[DST:%xmm[0-9]+]]<br>
+; CHECK: por [[SRC2]], [[DST]]<br>
+; CHECK: retq<br>
+<br>
+ %1 = call <2 x i64> @llvm.sabsdiff.v2i64(<2 x i64> %a1, <2 x i64> %a2)<br>
+ ret <2 x i64> %1<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/absdiff_256.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/absdiff_256.ll?rev=248483&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/absdiff_256.ll?rev=248483&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/absdiff_256.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/absdiff_256.ll Thu Sep 24 05:35:03 2015<br>
@@ -0,0 +1,29 @@<br>
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s<br>
+<br>
+declare <16 x i16> @llvm.sabsdiff.v16i16(<16 x i16>, <16 x i16>)<br>
+<br>
+define <16 x i16> @test_sabsdiff_v16i16_expand(<16 x i16> %a1, <16 x i16> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v16i16_expand:<br>
+; CHECK: # BB#0:<br>
+; CHECK: psubw<br>
+; CHECK: pxor<br>
+; CHECK: pcmpgtw<br>
+; CHECK: movdqa<br>
+; CHECK: pandn<br>
+; CHECK: pxor<br>
+; CHECK: psubw<br>
+; CHECK: pcmpeqd<br>
+; CHECK: pxor<br>
+; CHECK: pandn<br>
+; CHECK: por<br>
+; CHECK: pcmpgtw<br>
+; CHECK-DAG: psubw {{%xmm[0-9]+}}, [[SRC:%xmm[0-9]+]]<br>
+; CHECK-DAG: pxor {{%xmm[0-9]+}}, [[DST:%xmm[0-9]+]]<br>
+; CHECK: pandn [[SRC]], [[DST]]<br>
+; CHECK: por<br>
+; CHECK: movdqa<br>
+; CHECK: retq<br>
+ %1 = call <16 x i16> @llvm.sabsdiff.v16i16(<16 x i16> %a1, <16 x i16> %a2)<br>
+ ret <16 x i16> %1<br>
+}<br>
+<br>
<br>
<br>
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