<div dir="ltr">See my response on the other thread.<div><br></div><div>I don't see any activity to actually address the FIXMEs, and the macro generated approach seems substantially better (less repetition, less prone to error).</div><div><br>I'm not even clear what realistic tablegen you are hoping to do here. I found it hard to build an efficient parser for this using *any* technique.</div><div><br></div><div>But arguing that we should keep the code in a bad and hard to maintain state because of some hypothetical future design seems... not really a good strategy.</div></div><br><div class="gmail_quote"><div dir="ltr">On Sun, Aug 30, 2015 at 3:15 AM Renato Golin via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Chandler,<br>
<br>
Again, pretty please, revert this change.<br>
<br>
This "class" will be table-generated and is in this form<br>
"temporarily". We have moved away from macros for a very good reason,<br>
and I don't want to go back to it.<br>
<br>
Please, don't touch a core part of the ARM parsing without even<br>
asking, that was rude to begin with. I'd appreciate if you could<br>
revert all changes back to the original form (except the clean ups in<br>
Clang), so we can discuss this in an RFC on the list.<br>
<br>
Thank you,<br>
--renato<br>
<br>
On 30 August 2015 at 06:27, Chandler Carruth via llvm-commits<br>
<<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br>
> Author: chandlerc<br>
> Date: Sun Aug 30 00:27:31 2015<br>
> New Revision: 246370<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=246370&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=246370&view=rev</a><br>
> Log:<br>
> Refactor the ARM target parsing to use a def file with macros to expand<br>
> the necessary tables.<br>
><br>
> This will allow me to restructure the code and structures using this to<br>
> be significantly more efficient. It also removes the duplication of the<br>
> list of several enumerators. It also enshrines that the order of<br>
> enumerators match the order of the entries in the tables, something the<br>
> implementation code actually uses.<br>
><br>
> No functionality changed (yet).<br>
><br>
> Added:<br>
> llvm/trunk/include/llvm/Support/ARMTargetParser.def<br>
> Modified:<br>
> llvm/trunk/include/llvm/Support/TargetParser.h<br>
> llvm/trunk/lib/Support/TargetParser.cpp<br>
><br>
> Added: llvm/trunk/include/llvm/Support/ARMTargetParser.def<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMTargetParser.def?rev=246370&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMTargetParser.def?rev=246370&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/include/llvm/Support/ARMTargetParser.def (added)<br>
> +++ llvm/trunk/include/llvm/Support/ARMTargetParser.def Sun Aug 30 00:27:31 2015<br>
> @@ -0,0 +1,204 @@<br>
> +//===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//<br>
> +//<br>
> +// The LLVM Compiler Infrastructure<br>
> +//<br>
> +// This file is distributed under the University of Illinois Open Source<br>
> +// License. See LICENSE.TXT for details.<br>
> +//<br>
> +//===----------------------------------------------------------------------===//<br>
> +//<br>
> +// This file provides defines to build up the ARM target parser's logic.<br>
> +//<br>
> +//===----------------------------------------------------------------------===//<br>
> +<br>
> +// NOTE: NO INCLUDE GUARD DESIRED!<br>
> +<br>
> +#ifndef ARM_FPU<br>
> +#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION)<br>
> +#endif<br>
> +ARM_FPU("invalid", FK_INVALID, FV_NONE, NS_None, FR_None)<br>
> +ARM_FPU("none", FK_NONE, FV_NONE, NS_None, FR_None)<br>
> +ARM_FPU("vfp", FK_VFP, FV_VFPV2, NS_None, FR_None)<br>
> +ARM_FPU("vfpv2", FK_VFPV2, FV_VFPV2, NS_None, FR_None)<br>
> +ARM_FPU("vfpv3", FK_VFPV3, FV_VFPV3, NS_None, FR_None)<br>
> +ARM_FPU("vfpv3-fp16", FK_VFPV3_FP16, FV_VFPV3_FP16, NS_None, FR_None)<br>
> +ARM_FPU("vfpv3-d16", FK_VFPV3_D16, FV_VFPV3, NS_None, FR_D16)<br>
> +ARM_FPU("vfpv3-d16-fp16", FK_VFPV3_D16_FP16, FV_VFPV3_FP16, NS_None, FR_D16)<br>
> +ARM_FPU("vfpv3xd", FK_VFPV3XD, FV_VFPV3, NS_None, FR_SP_D16)<br>
> +ARM_FPU("vfpv3xd-fp16", FK_VFPV3XD_FP16, FV_VFPV3_FP16, NS_None, FR_SP_D16)<br>
> +ARM_FPU("vfpv4", FK_VFPV4, FV_VFPV4, NS_None, FR_None)<br>
> +ARM_FPU("vfpv4-d16", FK_VFPV4_D16, FV_VFPV4, NS_None, FR_D16)<br>
> +ARM_FPU("fpv4-sp-d16", FK_FPV4_SP_D16, FV_VFPV4, NS_None, FR_SP_D16)<br>
> +ARM_FPU("fpv5-d16", FK_FPV5_D16, FV_VFPV5, NS_None, FR_D16)<br>
> +ARM_FPU("fpv5-sp-d16", FK_FPV5_SP_D16, FV_VFPV5, NS_None, FR_SP_D16)<br>
> +ARM_FPU("fp-armv8", FK_FP_ARMV8, FV_VFPV5, NS_None, FR_None)<br>
> +ARM_FPU("neon", FK_NEON, FV_VFPV3, NS_Neon, FR_None)<br>
> +ARM_FPU("neon-fp16", FK_NEON_FP16, FV_VFPV3_FP16, NS_Neon, FR_None)<br>
> +ARM_FPU("neon-vfpv4", FK_NEON_VFPV4, FV_VFPV4, NS_Neon, FR_None)<br>
> +ARM_FPU("neon-fp-armv8", FK_NEON_FP_ARMV8, FV_VFPV5, NS_Neon, FR_None)<br>
> +ARM_FPU("crypto-neon-fp-armv8", FK_CRYPTO_NEON_FP_ARMV8, FV_VFPV5, NS_Crypto,<br>
> + FR_None)<br>
> +ARM_FPU("softvfp", FK_SOFTVFP, FV_NONE, NS_None, FR_None)<br>
> +#undef ARM_FPU<br>
> +<br>
> +#ifndef ARM_ARCH<br>
> +#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR)<br>
> +#endif<br>
> +ARM_ARCH("invalid", AK_INVALID, nullptr, nullptr,<br>
> + ARMBuildAttrs::CPUArch::Pre_v4)<br>
> +ARM_ARCH("armv2", AK_ARMV2, "2", "v2", ARMBuildAttrs::CPUArch::Pre_v4)<br>
> +ARM_ARCH("armv2a", AK_ARMV2A, "2A", "v2a", ARMBuildAttrs::CPUArch::Pre_v4)<br>
> +ARM_ARCH("armv3", AK_ARMV3, "3", "v3", ARMBuildAttrs::CPUArch::Pre_v4)<br>
> +ARM_ARCH("armv3m", AK_ARMV3M, "3M", "v3m", ARMBuildAttrs::CPUArch::Pre_v4)<br>
> +ARM_ARCH("armv4", AK_ARMV4, "4", "v4", ARMBuildAttrs::CPUArch::v4)<br>
> +ARM_ARCH("armv4t", AK_ARMV4T, "4T", "v4t", ARMBuildAttrs::CPUArch::v4T)<br>
> +ARM_ARCH("armv5t", AK_ARMV5T, "5T", "v5", ARMBuildAttrs::CPUArch::v5T)<br>
> +ARM_ARCH("armv5te", AK_ARMV5TE, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE)<br>
> +ARM_ARCH("armv5tej", AK_ARMV5TEJ, "5TEJ", "v5e", ARMBuildAttrs::CPUArch::v5TEJ)<br>
> +ARM_ARCH("armv6", AK_ARMV6, "6", "v6", ARMBuildAttrs::CPUArch::v6)<br>
> +ARM_ARCH("armv6k", AK_ARMV6K, "6K", "v6k", ARMBuildAttrs::CPUArch::v6K)<br>
> +ARM_ARCH("armv6t2", AK_ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2)<br>
> +ARM_ARCH("armv6z", AK_ARMV6Z, "6Z", "v6z", ARMBuildAttrs::CPUArch::v6KZ)<br>
> +ARM_ARCH("armv6zk", AK_ARMV6ZK, "6ZK", "v6zk", ARMBuildAttrs::CPUArch::v6KZ)<br>
> +ARM_ARCH("armv6-m", AK_ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M)<br>
> +ARM_ARCH("armv6s-m", AK_ARMV6SM, "6S-M", "v6sm", ARMBuildAttrs::CPUArch::v6S_M)<br>
> +ARM_ARCH("armv7-a", AK_ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7)<br>
> +ARM_ARCH("armv7-r", AK_ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7)<br>
> +ARM_ARCH("armv7-m", AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7)<br>
> +ARM_ARCH("armv7e-m", AK_ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M)<br>
> +ARM_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8)<br>
> +ARM_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a", ARMBuildAttrs::CPUArch::v8)<br>
> +// Non-standard Arch names.<br>
> +ARM_ARCH("iwmmxt", AK_IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE)<br>
> +ARM_ARCH("iwmmxt2", AK_IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE)<br>
> +ARM_ARCH("xscale", AK_XSCALE, "xscale", "", ARMBuildAttrs::CPUArch::v5TE)<br>
> +ARM_ARCH("armv5", AK_ARMV5, "5T", "v5", ARMBuildAttrs::CPUArch::v5T)<br>
> +ARM_ARCH("armv5e", AK_ARMV5E, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE)<br>
> +ARM_ARCH("armv6j", AK_ARMV6J, "6J", "v6", ARMBuildAttrs::CPUArch::v6)<br>
> +ARM_ARCH("armv6hl", AK_ARMV6HL, "6-M", "v6hl", ARMBuildAttrs::CPUArch::v6_M)<br>
> +ARM_ARCH("armv7", AK_ARMV7, "7", "v7", ARMBuildAttrs::CPUArch::v7)<br>
> +ARM_ARCH("armv7l", AK_ARMV7L, "7-L", "v7l", ARMBuildAttrs::CPUArch::v7)<br>
> +ARM_ARCH("armv7hl", AK_ARMV7HL, "7-L", "v7hl", ARMBuildAttrs::CPUArch::v7)<br>
> +ARM_ARCH("armv7s", AK_ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7)<br>
> +ARM_ARCH("armv7k", AK_ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7)<br>
> +#undef ARM_ARCH<br>
> +<br>
> +#ifndef ARM_ARCH_EXT_NAME<br>
> +#define ARM_ARCH_EXT_NAME(NAME, ID)<br>
> +#endif<br>
> +ARM_ARCH_EXT_NAME("invalid", AEK_INVALID)<br>
> +ARM_ARCH_EXT_NAME("none", AEK_NONE)<br>
> +ARM_ARCH_EXT_NAME("crc", AEK_CRC)<br>
> +ARM_ARCH_EXT_NAME("crypto", AEK_CRYPTO)<br>
> +ARM_ARCH_EXT_NAME("fp", AEK_FP)<br>
> +ARM_ARCH_EXT_NAME("idiv", (AEK_HWDIVARM | AEK_HWDIV))<br>
> +ARM_ARCH_EXT_NAME("mp", AEK_MP)<br>
> +ARM_ARCH_EXT_NAME("simd", AEK_SIMD)<br>
> +ARM_ARCH_EXT_NAME("sec", AEK_SEC)<br>
> +ARM_ARCH_EXT_NAME("virt", AEK_VIRT)<br>
> +ARM_ARCH_EXT_NAME("os", AEK_OS)<br>
> +ARM_ARCH_EXT_NAME("iwmmxt", AEK_IWMMXT)<br>
> +ARM_ARCH_EXT_NAME("iwmmxt2", AEK_IWMMXT2)<br>
> +ARM_ARCH_EXT_NAME("maverick", AEK_MAVERICK)<br>
> +ARM_ARCH_EXT_NAME("xscale", AEK_XSCALE)<br>
> +#undef ARM_ARCH_EXT_NAME<br>
> +<br>
> +#ifndef ARM_HW_DIV_NAME<br>
> +#define ARM_HW_DIV_NAME(NAME, ID)<br>
> +#endif<br>
> +ARM_HW_DIV_NAME("invalid", AEK_INVALID)<br>
> +ARM_HW_DIV_NAME("none", AEK_NONE)<br>
> +ARM_HW_DIV_NAME("thumb", AEK_HWDIV)<br>
> +ARM_HW_DIV_NAME("arm", AEK_HWDIVARM)<br>
> +ARM_HW_DIV_NAME("arm,thumb", (AEK_HWDIVARM | AEK_HWDIV))<br>
> +#undef ARM_HW_DIV_NAME<br>
> +<br>
> +#ifndef ARM_CPU_NAME<br>
> +#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT)<br>
> +#endif<br>
> +ARM_CPU_NAME("arm2", AK_ARMV2, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm3", AK_ARMV2A, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm6", AK_ARMV3, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm7m", AK_ARMV3M, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm8", AK_ARMV4, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm810", AK_ARMV4, FK_NONE, false)<br>
> +ARM_CPU_NAME("strongarm", AK_ARMV4, FK_NONE, true)<br>
> +ARM_CPU_NAME("strongarm110", AK_ARMV4, FK_NONE, false)<br>
> +ARM_CPU_NAME("strongarm1100", AK_ARMV4, FK_NONE, false)<br>
> +ARM_CPU_NAME("strongarm1110", AK_ARMV4, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm7tdmi", AK_ARMV4T, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm7tdmi-s", AK_ARMV4T, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm710t", AK_ARMV4T, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm720t", AK_ARMV4T, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm9", AK_ARMV4T, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm9tdmi", AK_ARMV4T, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm920", AK_ARMV4T, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm920t", AK_ARMV4T, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm922t", AK_ARMV4T, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm9312", AK_ARMV4T, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm940t", AK_ARMV4T, FK_NONE, false)<br>
> +ARM_CPU_NAME("ep9312", AK_ARMV4T, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm10tdmi", AK_ARMV5T, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm1020t", AK_ARMV5T, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm9e", AK_ARMV5TE, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm946e-s", AK_ARMV5TE, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm966e-s", AK_ARMV5TE, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm968e-s", AK_ARMV5TE, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm10e", AK_ARMV5TE, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm1020e", AK_ARMV5TE, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm1022e", AK_ARMV5TE, FK_NONE, true)<br>
> +ARM_CPU_NAME("iwmmxt", AK_ARMV5TE, FK_NONE, false)<br>
> +ARM_CPU_NAME("xscale", AK_ARMV5TE, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm926ej-s", AK_ARMV5TEJ, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm1136jf-s", AK_ARMV6, FK_VFPV2, true)<br>
> +ARM_CPU_NAME("arm1176j-s", AK_ARMV6K, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm1176jz-s", AK_ARMV6K, FK_NONE, false)<br>
> +ARM_CPU_NAME("mpcore", AK_ARMV6K, FK_VFPV2, false)<br>
> +ARM_CPU_NAME("mpcorenovfp", AK_ARMV6K, FK_NONE, false)<br>
> +ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6K, FK_VFPV2, true)<br>
> +ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6Z, FK_VFPV2, true)<br>
> +ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6ZK, FK_VFPV2, true)<br>
> +ARM_CPU_NAME("arm1156t2-s", AK_ARMV6T2, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm1156t2f-s", AK_ARMV6T2, FK_VFPV2, false)<br>
> +ARM_CPU_NAME("cortex-m0", AK_ARMV6M, FK_NONE, true)<br>
> +ARM_CPU_NAME("cortex-m0plus", AK_ARMV6M, FK_NONE, false)<br>
> +ARM_CPU_NAME("cortex-m1", AK_ARMV6M, FK_NONE, false)<br>
> +ARM_CPU_NAME("sc000", AK_ARMV6M, FK_NONE, false)<br>
> +ARM_CPU_NAME("cortex-a5", AK_ARMV7A, FK_NEON_VFPV4, false)<br>
> +ARM_CPU_NAME("cortex-a7", AK_ARMV7A, FK_NEON_VFPV4, false)<br>
> +ARM_CPU_NAME("cortex-a8", AK_ARMV7A, FK_NEON, true)<br>
> +ARM_CPU_NAME("cortex-a9", AK_ARMV7A, FK_NEON_FP16, false)<br>
> +ARM_CPU_NAME("cortex-a12", AK_ARMV7A, FK_NEON_VFPV4, false)<br>
> +ARM_CPU_NAME("cortex-a15", AK_ARMV7A, FK_NEON_VFPV4, false)<br>
> +ARM_CPU_NAME("cortex-a17", AK_ARMV7A, FK_NEON_VFPV4, false)<br>
> +ARM_CPU_NAME("krait", AK_ARMV7A, FK_NEON_VFPV4, false)<br>
> +ARM_CPU_NAME("cortex-r4", AK_ARMV7R, FK_NONE, true)<br>
> +ARM_CPU_NAME("cortex-r4f", AK_ARMV7R, FK_VFPV3_D16, false)<br>
> +ARM_CPU_NAME("cortex-r5", AK_ARMV7R, FK_VFPV3_D16, false)<br>
> +ARM_CPU_NAME("cortex-r7", AK_ARMV7R, FK_VFPV3_D16_FP16, false)<br>
> +ARM_CPU_NAME("sc300", AK_ARMV7M, FK_NONE, false)<br>
> +ARM_CPU_NAME("cortex-m3", AK_ARMV7M, FK_NONE, true)<br>
> +ARM_CPU_NAME("cortex-m4", AK_ARMV7EM, FK_FPV4_SP_D16, true)<br>
> +ARM_CPU_NAME("cortex-m7", AK_ARMV7EM, FK_FPV5_D16, false)<br>
> +ARM_CPU_NAME("cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true)<br>
> +ARM_CPU_NAME("cortex-a57", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false)<br>
> +ARM_CPU_NAME("cortex-a72", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false)<br>
> +ARM_CPU_NAME("cyclone", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false)<br>
> +ARM_CPU_NAME("generic", AK_ARMV8_1A, FK_NEON_FP_ARMV8, true)<br>
> +// Non-standard Arch names.<br>
> +ARM_CPU_NAME("iwmmxt", AK_IWMMXT, FK_NONE, true)<br>
> +ARM_CPU_NAME("xscale", AK_XSCALE, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm10tdmi", AK_ARMV5, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm1022e", AK_ARMV5E, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm1136j-s", AK_ARMV6J, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm1136jz-s", AK_ARMV6J, FK_NONE, false)<br>
> +ARM_CPU_NAME("cortex-m0", AK_ARMV6SM, FK_NONE, true)<br>
> +ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6HL, FK_VFPV2, true)<br>
> +ARM_CPU_NAME("cortex-a8", AK_ARMV7, FK_NEON, true)<br>
> +ARM_CPU_NAME("cortex-a8", AK_ARMV7L, FK_NEON, true)<br>
> +ARM_CPU_NAME("cortex-a8", AK_ARMV7HL, FK_NEON, true)<br>
> +ARM_CPU_NAME("cortex-m4", AK_ARMV7EM, FK_NONE, true)<br>
> +ARM_CPU_NAME("swift", AK_ARMV7S, FK_NEON_VFPV4, true)<br>
> +// Invalid CPU<br>
> +ARM_CPU_NAME("invalid", AK_INVALID, FK_INVALID, true)<br>
> +#undef ARM_CPU_NAME<br>
><br>
> Modified: llvm/trunk/include/llvm/Support/TargetParser.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetParser.h?rev=246370&r1=246369&r2=246370&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetParser.h?rev=246370&r1=246369&r2=246370&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/include/llvm/Support/TargetParser.h (original)<br>
> +++ llvm/trunk/include/llvm/Support/TargetParser.h Sun Aug 30 00:27:31 2015<br>
> @@ -32,28 +32,8 @@ namespace ARM {<br>
><br>
> // FPU names.<br>
> enum FPUKind {<br>
> - FK_INVALID = 0,<br>
> - FK_NONE,<br>
> - FK_VFP,<br>
> - FK_VFPV2,<br>
> - FK_VFPV3,<br>
> - FK_VFPV3_FP16,<br>
> - FK_VFPV3_D16,<br>
> - FK_VFPV3_D16_FP16,<br>
> - FK_VFPV3XD,<br>
> - FK_VFPV3XD_FP16,<br>
> - FK_VFPV4,<br>
> - FK_VFPV4_D16,<br>
> - FK_FPV4_SP_D16,<br>
> - FK_FPV5_D16,<br>
> - FK_FPV5_SP_D16,<br>
> - FK_FP_ARMV8,<br>
> - FK_NEON,<br>
> - FK_NEON_FP16,<br>
> - FK_NEON_VFPV4,<br>
> - FK_NEON_FP_ARMV8,<br>
> - FK_CRYPTO_NEON_FP_ARMV8,<br>
> - FK_SOFTVFP,<br>
> +#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND,<br>
> +#include "ARMTargetParser.def"<br>
> FK_LAST<br>
> };<br>
><br>
> @@ -83,42 +63,8 @@ enum FPURestriction {<br>
><br>
> // Arch names.<br>
> enum ArchKind {<br>
> - AK_INVALID = 0,<br>
> - AK_ARMV2,<br>
> - AK_ARMV2A,<br>
> - AK_ARMV3,<br>
> - AK_ARMV3M,<br>
> - AK_ARMV4,<br>
> - AK_ARMV4T,<br>
> - AK_ARMV5T,<br>
> - AK_ARMV5TE,<br>
> - AK_ARMV5TEJ,<br>
> - AK_ARMV6,<br>
> - AK_ARMV6K,<br>
> - AK_ARMV6T2,<br>
> - AK_ARMV6Z,<br>
> - AK_ARMV6ZK,<br>
> - AK_ARMV6M,<br>
> - AK_ARMV6SM,<br>
> - AK_ARMV7A,<br>
> - AK_ARMV7R,<br>
> - AK_ARMV7M,<br>
> - AK_ARMV7EM,<br>
> - AK_ARMV8A,<br>
> - AK_ARMV8_1A,<br>
> - // Non-standard Arch names.<br>
> - AK_IWMMXT,<br>
> - AK_IWMMXT2,<br>
> - AK_XSCALE,<br>
> - AK_ARMV5,<br>
> - AK_ARMV5E,<br>
> - AK_ARMV6J,<br>
> - AK_ARMV6HL,<br>
> - AK_ARMV7,<br>
> - AK_ARMV7L,<br>
> - AK_ARMV7HL,<br>
> - AK_ARMV7S,<br>
> - AK_ARMV7K,<br>
> +#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR) ID,<br>
> +#include "ARMTargetParser.def"<br>
> AK_LAST<br>
> };<br>
><br>
><br>
> Modified: llvm/trunk/lib/Support/TargetParser.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=246370&r1=246369&r2=246370&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=246370&r1=246369&r2=246370&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Support/TargetParser.cpp (original)<br>
> +++ llvm/trunk/lib/Support/TargetParser.cpp Sun Aug 30 00:27:31 2015<br>
> @@ -19,6 +19,7 @@<br>
> #include <cctype><br>
><br>
> using namespace llvm;<br>
> +using namespace ARM;<br>
><br>
> namespace {<br>
><br>
> @@ -33,29 +34,9 @@ struct {<br>
> ARM::NeonSupportLevel NeonSupport;<br>
> ARM::FPURestriction Restriction;<br>
> } FPUNames[] = {<br>
> - { "invalid", ARM::FK_INVALID, ARM::FV_NONE, ARM::NS_None, ARM::FR_None},<br>
> - { "none", ARM::FK_NONE, ARM::FV_NONE, ARM::NS_None, ARM::FR_None},<br>
> - { "vfp", ARM::FK_VFP, ARM::FV_VFPV2, ARM::NS_None, ARM::FR_None},<br>
> - { "vfpv2", ARM::FK_VFPV2, ARM::FV_VFPV2, ARM::NS_None, ARM::FR_None},<br>
> - { "vfpv3", ARM::FK_VFPV3, ARM::FV_VFPV3, ARM::NS_None, ARM::FR_None},<br>
> - { "vfpv3-fp16", ARM::FK_VFPV3_FP16, ARM::FV_VFPV3_FP16, ARM::NS_None, ARM::FR_None},<br>
> - { "vfpv3-d16", ARM::FK_VFPV3_D16, ARM::FV_VFPV3, ARM::NS_None, ARM::FR_D16},<br>
> - { "vfpv3-d16-fp16", ARM::FK_VFPV3_D16_FP16, ARM::FV_VFPV3_FP16, ARM::NS_None, ARM::FR_D16},<br>
> - { "vfpv3xd", ARM::FK_VFPV3XD, ARM::FV_VFPV3, ARM::NS_None, ARM::FR_SP_D16},<br>
> - { "vfpv3xd-fp16", ARM::FK_VFPV3XD_FP16, ARM::FV_VFPV3_FP16, ARM::NS_None, ARM::FR_SP_D16},<br>
> - { "vfpv4", ARM::FK_VFPV4, ARM::FV_VFPV4, ARM::NS_None, ARM::FR_None},<br>
> - { "vfpv4-d16", ARM::FK_VFPV4_D16, ARM::FV_VFPV4, ARM::NS_None, ARM::FR_D16},<br>
> - { "fpv4-sp-d16", ARM::FK_FPV4_SP_D16, ARM::FV_VFPV4, ARM::NS_None, ARM::FR_SP_D16},<br>
> - { "fpv5-d16", ARM::FK_FPV5_D16, ARM::FV_VFPV5, ARM::NS_None, ARM::FR_D16},<br>
> - { "fpv5-sp-d16", ARM::FK_FPV5_SP_D16, ARM::FV_VFPV5, ARM::NS_None, ARM::FR_SP_D16},<br>
> - { "fp-armv8", ARM::FK_FP_ARMV8, ARM::FV_VFPV5, ARM::NS_None, ARM::FR_None},<br>
> - { "neon", ARM::FK_NEON, ARM::FV_VFPV3, ARM::NS_Neon, ARM::FR_None},<br>
> - { "neon-fp16", ARM::FK_NEON_FP16, ARM::FV_VFPV3_FP16, ARM::NS_Neon, ARM::FR_None},<br>
> - { "neon-vfpv4", ARM::FK_NEON_VFPV4, ARM::FV_VFPV4, ARM::NS_Neon, ARM::FR_None},<br>
> - { "neon-fp-armv8", ARM::FK_NEON_FP_ARMV8, ARM::FV_VFPV5, ARM::NS_Neon, ARM::FR_None},<br>
> - { "crypto-neon-fp-armv8",<br>
> - ARM::FK_CRYPTO_NEON_FP_ARMV8, ARM::FV_VFPV5, ARM::NS_Crypto, ARM::FR_None},<br>
> - { "softvfp", ARM::FK_SOFTVFP, ARM::FV_NONE, ARM::NS_None, ARM::FR_None},<br>
> +#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) \<br>
> + { NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION },<br>
> +#include "llvm/Support/ARMTargetParser.def"<br>
> };<br>
><br>
> // List of canonical arch names (use getArchSynonym).<br>
> @@ -73,42 +54,9 @@ struct {<br>
> const char *SubArch; // Sub-Arch name.<br>
> ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.<br>
> } ARCHNames[] = {<br>
> - { "invalid", ARM::AK_INVALID, nullptr, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },<br>
> - { "armv2", ARM::AK_ARMV2, "2", "v2", ARMBuildAttrs::CPUArch::Pre_v4 },<br>
> - { "armv2a", ARM::AK_ARMV2A, "2A", "v2a", ARMBuildAttrs::CPUArch::Pre_v4 },<br>
> - { "armv3", ARM::AK_ARMV3, "3", "v3", ARMBuildAttrs::CPUArch::Pre_v4 },<br>
> - { "armv3m", ARM::AK_ARMV3M, "3M", "v3m", ARMBuildAttrs::CPUArch::Pre_v4 },<br>
> - { "armv4", ARM::AK_ARMV4, "4", "v4", ARMBuildAttrs::CPUArch::v4 },<br>
> - { "armv4t", ARM::AK_ARMV4T, "4T", "v4t", ARMBuildAttrs::CPUArch::v4T },<br>
> - { "armv5t", ARM::AK_ARMV5T, "5T", "v5", ARMBuildAttrs::CPUArch::v5T },<br>
> - { "armv5te", ARM::AK_ARMV5TE, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE },<br>
> - { "armv5tej", ARM::AK_ARMV5TEJ, "5TEJ", "v5e", ARMBuildAttrs::CPUArch::v5TEJ },<br>
> - { "armv6", ARM::AK_ARMV6, "6", "v6", ARMBuildAttrs::CPUArch::v6 },<br>
> - { "armv6k", ARM::AK_ARMV6K, "6K", "v6k", ARMBuildAttrs::CPUArch::v6K },<br>
> - { "armv6t2", ARM::AK_ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2 },<br>
> - { "armv6z", ARM::AK_ARMV6Z, "6Z", "v6z", ARMBuildAttrs::CPUArch::v6KZ },<br>
> - { "armv6zk", ARM::AK_ARMV6ZK, "6ZK", "v6zk", ARMBuildAttrs::CPUArch::v6KZ },<br>
> - { "armv6-m", ARM::AK_ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M },<br>
> - { "armv6s-m", ARM::AK_ARMV6SM, "6S-M", "v6sm", ARMBuildAttrs::CPUArch::v6S_M },<br>
> - { "armv7-a", ARM::AK_ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7 },<br>
> - { "armv7-r", ARM::AK_ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7 },<br>
> - { "armv7-m", ARM::AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7 },<br>
> - { "armv7e-m", ARM::AK_ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M },<br>
> - { "armv8-a", ARM::AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8 },<br>
> - { "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", "v8.1a", ARMBuildAttrs::CPUArch::v8 },<br>
> - // Non-standard Arch names.<br>
> - { "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE },<br>
> - { "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE },<br>
> - { "xscale", ARM::AK_XSCALE, "xscale", "", ARMBuildAttrs::CPUArch::v5TE },<br>
> - { "armv5", ARM::AK_ARMV5, "5T", "v5", ARMBuildAttrs::CPUArch::v5T },<br>
> - { "armv5e", ARM::AK_ARMV5E, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE },<br>
> - { "armv6j", ARM::AK_ARMV6J, "6J", "v6", ARMBuildAttrs::CPUArch::v6 },<br>
> - { "armv6hl", ARM::AK_ARMV6HL, "6-M", "v6hl", ARMBuildAttrs::CPUArch::v6_M },<br>
> - { "armv7", ARM::AK_ARMV7, "7", "v7", ARMBuildAttrs::CPUArch::v7 },<br>
> - { "armv7l", ARM::AK_ARMV7L, "7-L", "v7l", ARMBuildAttrs::CPUArch::v7 },<br>
> - { "armv7hl", ARM::AK_ARMV7HL, "7-L", "v7hl", ARMBuildAttrs::CPUArch::v7 },<br>
> - { "armv7s", ARM::AK_ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7 },<br>
> - { "armv7k", ARM::AK_ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7 }<br>
> +#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR) \<br>
> + { NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR },<br>
> +#include "llvm/Support/ARMTargetParser.def"<br>
> };<br>
> // List of Arch Extension names.<br>
> // FIXME: TableGen this.<br>
> @@ -116,21 +64,8 @@ struct {<br>
> const char *Name;<br>
> unsigned ID;<br>
> } ARCHExtNames[] = {<br>
> - { "invalid", ARM::AEK_INVALID },<br>
> - { "none", ARM::AEK_NONE },<br>
> - { "crc", ARM::AEK_CRC },<br>
> - { "crypto", ARM::AEK_CRYPTO },<br>
> - { "fp", ARM::AEK_FP },<br>
> - { "idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV) },<br>
> - { "mp", ARM::AEK_MP },<br>
> - { "simd", ARM::AEK_SIMD },<br>
> - { "sec", ARM::AEK_SEC },<br>
> - { "virt", ARM::AEK_VIRT },<br>
> - { "os", ARM::AEK_OS },<br>
> - { "iwmmxt", ARM::AEK_IWMMXT },<br>
> - { "iwmmxt2", ARM::AEK_IWMMXT2 },<br>
> - { "maverick", ARM::AEK_MAVERICK },<br>
> - { "xscale", ARM::AEK_XSCALE }<br>
> +#define ARM_ARCH_EXT_NAME(NAME, ID) { NAME, ID },<br>
> +#include "llvm/Support/ARMTargetParser.def"<br>
> };<br>
> // List of HWDiv names (use getHWDivSynonym) and which architectural<br>
> // features they correspond to (use getHWDivFeatures).<br>
> @@ -139,11 +74,8 @@ struct {<br>
> const char *Name;<br>
> unsigned ID;<br>
> } HWDivNames[] = {<br>
> - { "invalid", ARM::AEK_INVALID },<br>
> - { "none", ARM::AEK_NONE },<br>
> - { "thumb", ARM::AEK_HWDIV },<br>
> - { "arm", ARM::AEK_HWDIVARM },<br>
> - { "arm,thumb", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV) }<br>
> +#define ARM_HW_DIV_NAME(NAME, ID) { NAME, ID },<br>
> +#include "llvm/Support/ARMTargetParser.def"<br>
> };<br>
> // List of CPU names and their arches.<br>
> // The same CPU can have multiple arches and can be default on multiple arches.<br>
> @@ -156,91 +88,9 @@ struct {<br>
> ARM::FPUKind DefaultFPU;<br>
> bool Default; // is $Name the default CPU for $ArchID ?<br>
> } CPUNames[] = {<br>
> - { "arm2", ARM::AK_ARMV2, ARM::FK_NONE, true },<br>
> - { "arm3", ARM::AK_ARMV2A, ARM::FK_NONE, true },<br>
> - { "arm6", ARM::AK_ARMV3, ARM::FK_NONE, true },<br>
> - { "arm7m", ARM::AK_ARMV3M, ARM::FK_NONE, true },<br>
> - { "arm8", ARM::AK_ARMV4, ARM::FK_NONE, false },<br>
> - { "arm810", ARM::AK_ARMV4, ARM::FK_NONE, false },<br>
> - { "strongarm", ARM::AK_ARMV4, ARM::FK_NONE, true },<br>
> - { "strongarm110", ARM::AK_ARMV4, ARM::FK_NONE, false },<br>
> - { "strongarm1100", ARM::AK_ARMV4, ARM::FK_NONE, false },<br>
> - { "strongarm1110", ARM::AK_ARMV4, ARM::FK_NONE, false },<br>
> - { "arm7tdmi", ARM::AK_ARMV4T, ARM::FK_NONE, true },<br>
> - { "arm7tdmi-s", ARM::AK_ARMV4T, ARM::FK_NONE, false },<br>
> - { "arm710t", ARM::AK_ARMV4T, ARM::FK_NONE, false },<br>
> - { "arm720t", ARM::AK_ARMV4T, ARM::FK_NONE, false },<br>
> - { "arm9", ARM::AK_ARMV4T, ARM::FK_NONE, false },<br>
> - { "arm9tdmi", ARM::AK_ARMV4T, ARM::FK_NONE, false },<br>
> - { "arm920", ARM::AK_ARMV4T, ARM::FK_NONE, false },<br>
> - { "arm920t", ARM::AK_ARMV4T, ARM::FK_NONE, false },<br>
> - { "arm922t", ARM::AK_ARMV4T, ARM::FK_NONE, false },<br>
> - { "arm9312", ARM::AK_ARMV4T, ARM::FK_NONE, false },<br>
> - { "arm940t", ARM::AK_ARMV4T, ARM::FK_NONE, false },<br>
> - { "ep9312", ARM::AK_ARMV4T, ARM::FK_NONE, false },<br>
> - { "arm10tdmi", ARM::AK_ARMV5T, ARM::FK_NONE, true },<br>
> - { "arm1020t", ARM::AK_ARMV5T, ARM::FK_NONE, false },<br>
> - { "arm9e", ARM::AK_ARMV5TE, ARM::FK_NONE, false },<br>
> - { "arm946e-s", ARM::AK_ARMV5TE, ARM::FK_NONE, false },<br>
> - { "arm966e-s", ARM::AK_ARMV5TE, ARM::FK_NONE, false },<br>
> - { "arm968e-s", ARM::AK_ARMV5TE, ARM::FK_NONE, false },<br>
> - { "arm10e", ARM::AK_ARMV5TE, ARM::FK_NONE, false },<br>
> - { "arm1020e", ARM::AK_ARMV5TE, ARM::FK_NONE, false },<br>
> - { "arm1022e", ARM::AK_ARMV5TE, ARM::FK_NONE, true },<br>
> - { "iwmmxt", ARM::AK_ARMV5TE, ARM::FK_NONE, false },<br>
> - { "xscale", ARM::AK_ARMV5TE, ARM::FK_NONE, false },<br>
> - { "arm926ej-s", ARM::AK_ARMV5TEJ, ARM::FK_NONE, true },<br>
> - { "arm1136jf-s", ARM::AK_ARMV6, ARM::FK_VFPV2, true },<br>
> - { "arm1176j-s", ARM::AK_ARMV6K, ARM::FK_NONE, false },<br>
> - { "arm1176jz-s", ARM::AK_ARMV6K, ARM::FK_NONE, false },<br>
> - { "mpcore", ARM::AK_ARMV6K, ARM::FK_VFPV2, false },<br>
> - { "mpcorenovfp", ARM::AK_ARMV6K, ARM::FK_NONE, false },<br>
> - { "arm1176jzf-s", ARM::AK_ARMV6K, ARM::FK_VFPV2, true },<br>
> - { "arm1176jzf-s", ARM::AK_ARMV6Z, ARM::FK_VFPV2, true },<br>
> - { "arm1176jzf-s", ARM::AK_ARMV6ZK, ARM::FK_VFPV2, true },<br>
> - { "arm1156t2-s", ARM::AK_ARMV6T2, ARM::FK_NONE, true },<br>
> - { "arm1156t2f-s", ARM::AK_ARMV6T2, ARM::FK_VFPV2, false },<br>
> - { "cortex-m0", ARM::AK_ARMV6M, ARM::FK_NONE, true },<br>
> - { "cortex-m0plus", ARM::AK_ARMV6M, ARM::FK_NONE, false },<br>
> - { "cortex-m1", ARM::AK_ARMV6M, ARM::FK_NONE, false },<br>
> - { "sc000", ARM::AK_ARMV6M, ARM::FK_NONE, false },<br>
> - { "cortex-a5", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },<br>
> - { "cortex-a7", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },<br>
> - { "cortex-a8", ARM::AK_ARMV7A, ARM::FK_NEON, true },<br>
> - { "cortex-a9", ARM::AK_ARMV7A, ARM::FK_NEON_FP16, false },<br>
> - { "cortex-a12", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },<br>
> - { "cortex-a15", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },<br>
> - { "cortex-a17", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },<br>
> - { "krait", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },<br>
> - { "cortex-r4", ARM::AK_ARMV7R, ARM::FK_NONE, true },<br>
> - { "cortex-r4f", ARM::AK_ARMV7R, ARM::FK_VFPV3_D16, false },<br>
> - { "cortex-r5", ARM::AK_ARMV7R, ARM::FK_VFPV3_D16, false },<br>
> - { "cortex-r7", ARM::AK_ARMV7R, ARM::FK_VFPV3_D16_FP16, false },<br>
> - { "sc300", ARM::AK_ARMV7M, ARM::FK_NONE, false },<br>
> - { "cortex-m3", ARM::AK_ARMV7M, ARM::FK_NONE, true },<br>
> - { "cortex-m4", ARM::AK_ARMV7EM, ARM::FK_FPV4_SP_D16, true },<br>
> - { "cortex-m7", ARM::AK_ARMV7EM, ARM::FK_FPV5_D16, false },<br>
> - { "cortex-a53", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, true },<br>
> - { "cortex-a57", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false },<br>
> - { "cortex-a72", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false },<br>
> - { "cyclone", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false },<br>
> - { "generic", ARM::AK_ARMV8_1A, ARM::FK_NEON_FP_ARMV8, true },<br>
> - // Non-standard Arch names.<br>
> - { "iwmmxt", ARM::AK_IWMMXT, ARM::FK_NONE, true },<br>
> - { "xscale", ARM::AK_XSCALE, ARM::FK_NONE, true },<br>
> - { "arm10tdmi", ARM::AK_ARMV5, ARM::FK_NONE, true },<br>
> - { "arm1022e", ARM::AK_ARMV5E, ARM::FK_NONE, true },<br>
> - { "arm1136j-s", ARM::AK_ARMV6J, ARM::FK_NONE, true },<br>
> - { "arm1136jz-s", ARM::AK_ARMV6J, ARM::FK_NONE, false },<br>
> - { "cortex-m0", ARM::AK_ARMV6SM, ARM::FK_NONE, true },<br>
> - { "arm1176jzf-s", ARM::AK_ARMV6HL, ARM::FK_VFPV2, true },<br>
> - { "cortex-a8", ARM::AK_ARMV7, ARM::FK_NEON, true },<br>
> - { "cortex-a8", ARM::AK_ARMV7L, ARM::FK_NEON, true },<br>
> - { "cortex-a8", ARM::AK_ARMV7HL, ARM::FK_NEON, true },<br>
> - { "cortex-m4", ARM::AK_ARMV7EM, ARM::FK_NONE, true },<br>
> - { "swift", ARM::AK_ARMV7S, ARM::FK_NEON_VFPV4, true },<br>
> - // Invalid CPU<br>
> - { "invalid", ARM::AK_INVALID, ARM::FK_INVALID, true }<br>
> +#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT) \<br>
> + { NAME, ID, DEFAULT_FPU, IS_DEFAULT },<br>
> +#include "llvm/Support/ARMTargetParser.def"<br>
> };<br>
><br>
> } // namespace<br>
><br>
><br>
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</blockquote></div>