<p dir="ltr">Bike shed: how about pass the function around instead. </p>
<br><div class="gmail_quote"><div dir="ltr">On Mon, Aug 24, 2015, 7:32 PM Steve King via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: srking<br>
Date: Mon Aug 24 21:31:21 2015<br>
New Revision: 245921<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=245921&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=245921&view=rev</a><br>
Log:<br>
Pass function attributes instead of boolean in isIntDivCheap().<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/sdiv-pow2.ll<br>
Modified:<br>
llvm/trunk/include/llvm/Target/TargetLowering.h<br>
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
<br>
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=245921&r1=245920&r2=245921&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=245921&r1=245920&r2=245921&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)<br>
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Aug 24 21:31:21 2015<br>
@@ -228,7 +228,7 @@ public:<br>
/// several shifts, adds, and multiplies for this target.<br>
/// The definition of "cheaper" may depend on whether we're optimizing<br>
/// for speed or for size.<br>
- virtual bool isIntDivCheap(EVT VT, bool OptSize) const {<br>
+ virtual bool isIntDivCheap(EVT VT, AttributeSet Attr) const {<br>
return false;<br>
}<br>
<br>
@@ -2719,11 +2719,14 @@ public:<br>
SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,<br>
bool IsAfterLegalization,<br>
std::vector<SDNode *> *Created) const;<br>
+<br>
+ /// Targets may override this function to provide custom SDIV lowering for<br>
+ /// power-of-2 denominators. If the target returns an empty SDValue, LLVM<br>
+ /// assumes SDIV is expensive and replaces it with a series of other integer<br>
+ /// operations.<br>
virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,<br>
SelectionDAG &DAG,<br>
- std::vector<SDNode *> *Created) const {<br>
- return SDValue();<br>
- }<br>
+ std::vector<SDNode *> *Created) const;<br>
<br>
/// Indicate whether this target prefers to combine FDIVs with the same<br>
/// divisor. If the transform should never be done, return zero. If the<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=245921&r1=245920&r2=245921&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=245921&r1=245920&r2=245921&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Aug 24 21:31:21 2015<br>
@@ -2183,7 +2183,6 @@ SDValue DAGCombiner::visitSDIV(SDNode *N<br>
N0, N1);<br>
}<br>
<br>
- bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();<br>
// fold (sdiv X, pow2) -> simple ops after legalize<br>
// FIXME: We check for the exact bit here because the generic lowering gives<br>
// better results in that case. The target-specific lowering should learn how<br>
@@ -2192,10 +2191,6 @@ SDValue DAGCombiner::visitSDIV(SDNode *N<br>
!cast<BinaryWithFlagsSDNode>(N)->Flags.hasExact() &&<br>
(N1C->getAPIntValue().isPowerOf2() ||<br>
(-N1C->getAPIntValue()).isPowerOf2())) {<br>
- // If integer division is cheap, then don't perform the following fold.<br>
- if (TLI.isIntDivCheap(N->getValueType(0), MinSize))<br>
- return SDValue();<br>
-<br>
// Target-specific implementation of sdiv x, pow2.<br>
if (SDValue Res = BuildSDIVPow2(N))<br>
return Res;<br>
@@ -2232,8 +2227,10 @@ SDValue DAGCombiner::visitSDIV(SDNode *N<br>
}<br>
<br>
// If integer divide is expensive and we satisfy the requirements, emit an<br>
- // alternate sequence.<br>
- if (N1C && !TLI.isIntDivCheap(N->getValueType(0), MinSize))<br>
+ // alternate sequence. Targets may check function attributes for size/speed<br>
+ // trade-offs.<br>
+ AttributeSet Attr = DAG.getMachineFunction().getFunction()->getAttributes();<br>
+ if (N1C && !TLI.isIntDivCheap(N->getValueType(0), Attr))<br>
if (SDValue Op = BuildSDIV(N))<br>
return Op;<br>
<br>
@@ -2289,8 +2286,8 @@ SDValue DAGCombiner::visitUDIV(SDNode *N<br>
}<br>
<br>
// fold (udiv x, c) -> alternate<br>
- bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();<br>
- if (N1C && !TLI.isIntDivCheap(N->getValueType(0), MinSize))<br>
+ AttributeSet Attr = DAG.getMachineFunction().getFunction()->getAttributes();<br>
+ if (N1C && !TLI.isIntDivCheap(N->getValueType(0), Attr))<br>
if (SDValue Op = BuildUDIV(N))<br>
return Op;<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=245921&r1=245920&r2=245921&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=245921&r1=245920&r2=245921&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Aug 24 21:31:21 2015<br>
@@ -2725,6 +2725,16 @@ static SDValue BuildExactSDIV(const Targ<br>
return Mul;<br>
}<br>
<br>
+SDValue TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,<br>
+ SelectionDAG &DAG,<br>
+ std::vector<SDNode *> *Created) const {<br>
+ AttributeSet Attr = DAG.getMachineFunction().getFunction()->getAttributes();<br>
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();<br>
+ if (TLI.isIntDivCheap(N->getValueType(0), Attr))<br>
+ return SDValue(N,0); // Lower SDIV as SDIV<br>
+ return SDValue();<br>
+}<br>
+<br>
/// \brief Given an ISD::SDIV node expressing a divide by constant,<br>
/// return a DAG expression to select that will generate the same value by<br>
/// multiplying by a magic number.<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=245921&r1=245920&r2=245921&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=245921&r1=245920&r2=245921&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Aug 24 21:31:21 2015<br>
@@ -26511,7 +26511,7 @@ bool X86TargetLowering::isTargetFTOL() c<br>
return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();<br>
}<br>
<br>
-bool X86TargetLowering::isIntDivCheap(EVT VT, bool OptSize) const {<br>
+bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {<br>
// Integer division on x86 is expensive. However, when aggressively optimizing<br>
// for code size, we prefer to use a div instruction, as it is usually smaller<br>
// than the alternative sequence.<br>
@@ -26519,5 +26519,7 @@ bool X86TargetLowering::isIntDivCheap(EV<br>
// integer division, leaving the division as-is is a loss even in terms of<br>
// size, because it will have to be scalarized, while the alternative code<br>
// sequence can be performed in vector form.<br>
+ bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,<br>
+ Attribute::MinSize);<br>
return OptSize && !VT.isVector();<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=245921&r1=245920&r2=245921&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=245921&r1=245920&r2=245921&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Aug 24 21:31:21 2015<br>
@@ -902,7 +902,7 @@ namespace llvm {<br>
/// \brief Customize the preferred legalization strategy for certain types.<br>
LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;<br>
<br>
- bool isIntDivCheap(EVT VT, bool OptSize) const override;<br>
+ bool isIntDivCheap(EVT VT, AttributeSet Attr) const override;<br>
<br>
protected:<br>
std::pair<const TargetRegisterClass *, uint8_t><br>
<br>
Added: llvm/trunk/test/CodeGen/X86/sdiv-pow2.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sdiv-pow2.ll?rev=245921&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sdiv-pow2.ll?rev=245921&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sdiv-pow2.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/sdiv-pow2.ll Mon Aug 24 21:31:21 2015<br>
@@ -0,0 +1,33 @@<br>
+; RUN: llc -march=x86 < %s | FileCheck %s<br>
+<br>
+; No attributes, should not use idiv<br>
+define i32 @test1(i32 inreg %x) {<br>
+entry:<br>
+ %div = sdiv i32 %x, 16<br>
+ ret i32 %div<br>
+; CHECK-LABEL: test1:<br>
+; CHECK-NOT: idivl<br>
+; CHECK: ret<br>
+}<br>
+<br>
+; Has minsize (-Oz) attribute, should generate idiv<br>
+define i32 @test2(i32 inreg %x) minsize {<br>
+entry:<br>
+ %div = sdiv i32 %x, 16<br>
+ ret i32 %div<br>
+; CHECK-LABEL: test2:<br>
+; CHECK: idivl<br>
+; CHECK: ret<br>
+}<br>
+<br>
+; Has optsize (-Os) attribute, should not generate idiv<br>
+define i32 @test3(i32 inreg %x) optsize {<br>
+entry:<br>
+ %div = sdiv i32 %x, 16<br>
+ ret i32 %div<br>
+; CHECK-LABEL: test3:<br>
+; CHECK-NOT: idivl<br>
+; CHECK: ret<br>
+}<br>
+<br>
+<br>
<br>
<br>
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</blockquote></div>