<p dir="ltr">Yes, we're trying to move as much as possible in before we start the TableGen work, so not to re-engineer it too much later. </p>
<p dir="ltr">It'd be good to get more MachO support in here, too. </p>
<p dir="ltr">Cheers, <br>
Renato </p>
<div class="gmail_quote">On 21 Aug 2015 11:49 pm, "Vedant Kumar" <<a href="mailto:vsk@apple.com">vsk@apple.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">IIRC, Renato mentioned in an earlier thread that there are plans to transition TargetParser to tablegen. I think so far ARMAsmParser and ARMAsmBackend are the only clients.<br>
<br>
If there's a change in TargetParser, there's a script that'll ping me. I'll make sure to clean up any affected MachO stuff.<br>
<br>
vedant<br>
<br>
> On Aug 21, 2015, at 3:44 PM, Eric Christopher <<a href="mailto:echristo@gmail.com">echristo@gmail.com</a>> wrote:<br>
><br>
> I think the TargetParser is a work in progress and not ready for general use yet? Renato?<br>
><br>
> -eric<br>
><br>
> On Fri, Aug 21, 2015 at 2:53 PM Vedant Kumar via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br>
> Author: vedantk<br>
> Date: Fri Aug 21 16:52:48 2015<br>
> New Revision: 245744<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=245744&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=245744&view=rev</a><br>
> Log:<br>
> [ARM] Fix MachO CPU Subtype selection<br>
><br>
> Differential Revision: <a href="http://reviews.llvm.org/D12040" rel="noreferrer" target="_blank">http://reviews.llvm.org/D12040</a><br>
><br>
> Added:<br>
>     llvm/trunk/test/CodeGen/ARM/MachO-subtypes.ll<br>
> Modified:<br>
>     llvm/trunk/include/llvm/Support/TargetParser.h<br>
>     llvm/trunk/lib/Support/TargetParser.cpp<br>
>     llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp<br>
><br>
> Modified: llvm/trunk/include/llvm/Support/TargetParser.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetParser.h?rev=245744&r1=245743&r2=245744&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetParser.h?rev=245744&r1=245743&r2=245744&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/include/llvm/Support/TargetParser.h (original)<br>
> +++ llvm/trunk/include/llvm/Support/TargetParser.h Fri Aug 21 16:52:48 2015<br>
> @@ -117,6 +117,7 @@ namespace ARM {<br>
>      AK_ARMV7L,<br>
>      AK_ARMV7HL,<br>
>      AK_ARMV7S,<br>
> +    AK_ARMV7K,<br>
>      AK_LAST<br>
>    };<br>
><br>
><br>
> Modified: llvm/trunk/lib/Support/TargetParser.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=245744&r1=245743&r2=245744&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=245744&r1=245743&r2=245744&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Support/TargetParser.cpp (original)<br>
> +++ llvm/trunk/lib/Support/TargetParser.cpp Fri Aug 21 16:52:48 2015<br>
> @@ -107,7 +107,8 @@ struct {<br>
>    { "armv7",     ARM::AK_ARMV7,    "7",       "v7",    ARMBuildAttrs::CPUArch::v7 },<br>
>    { "armv7l",    ARM::AK_ARMV7L,   "7-L",     "v7l",   ARMBuildAttrs::CPUArch::v7 },<br>
>    { "armv7hl",   ARM::AK_ARMV7HL,  "7-L",     "v7hl",  ARMBuildAttrs::CPUArch::v7 },<br>
> -  { "armv7s",    ARM::AK_ARMV7S,   "7-S",     "v7s",   ARMBuildAttrs::CPUArch::v7 }<br>
> +  { "armv7s",    ARM::AK_ARMV7S,   "7-S",     "v7s",   ARMBuildAttrs::CPUArch::v7 },<br>
> +  { "armv7k",    ARM::AK_ARMV7K,   "7-K",     "v7k",   ARMBuildAttrs::CPUArch::v7 }<br>
>  };<br>
>  // List of Arch Extension names.<br>
>  // FIXME: TableGen this.<br>
> @@ -662,6 +663,7 @@ unsigned ARMTargetParser::parseArchVersi<br>
>    case ARM::AK_ARMV7HL:<br>
>    case ARM::AK_ARMV7S:<br>
>    case ARM::AK_ARMV7EM:<br>
> +  case ARM::AK_ARMV7K:<br>
>      return 7;<br>
>    case ARM::AK_ARMV8A:<br>
>    case ARM::AK_ARMV8_1A:<br>
><br>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=245744&r1=245743&r2=245744&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=245744&r1=245743&r2=245744&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)<br>
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Fri Aug 21 16:52:48 2015<br>
> @@ -32,6 +32,7 @@<br>
>  #include "llvm/Support/ELF.h"<br>
>  #include "llvm/Support/ErrorHandling.h"<br>
>  #include "llvm/Support/MachO.h"<br>
> +#include "llvm/Support/TargetParser.h"<br>
>  #include "llvm/Support/raw_ostream.h"<br>
>  using namespace llvm;<br>
><br>
> @@ -743,6 +744,39 @@ void ARMAsmBackend::applyFixup(const MCF<br>
>    }<br>
>  }<br>
><br>
> +static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) {<br>
> +  unsigned AK = ARMTargetParser::parseArch(Arch);<br>
> +  switch (AK) {<br>
> +  default:<br>
> +    return MachO::CPU_SUBTYPE_ARM_V7;<br>
> +  case ARM::AK_ARMV4T:<br>
> +    return MachO::CPU_SUBTYPE_ARM_V4T;<br>
> +  case ARM::AK_ARMV6:<br>
> +  case ARM::AK_ARMV6K:<br>
> +    return MachO::CPU_SUBTYPE_ARM_V6;<br>
> +  case ARM::AK_ARMV5:<br>
> +    return MachO::CPU_SUBTYPE_ARM_V5;<br>
> +  case ARM::AK_ARMV5T:<br>
> +  case ARM::AK_ARMV5E:<br>
> +  case ARM::AK_ARMV5TE:<br>
> +  case ARM::AK_ARMV5TEJ:<br>
> +    return MachO::CPU_SUBTYPE_ARM_V5TEJ;<br>
> +  case ARM::AK_ARMV7:<br>
> +    return MachO::CPU_SUBTYPE_ARM_V7;<br>
> +  case ARM::AK_ARMV7S:<br>
> +    return MachO::CPU_SUBTYPE_ARM_V7S;<br>
> +  case ARM::AK_ARMV7K:<br>
> +    return MachO::CPU_SUBTYPE_ARM_V7K;<br>
> +  case ARM::AK_ARMV6M:<br>
> +  case ARM::AK_ARMV6SM:<br>
> +    return MachO::CPU_SUBTYPE_ARM_V6M;<br>
> +  case ARM::AK_ARMV7M:<br>
> +    return MachO::CPU_SUBTYPE_ARM_V7M;<br>
> +  case ARM::AK_ARMV7EM:<br>
> +    return MachO::CPU_SUBTYPE_ARM_V7EM;<br>
> +  }<br>
> +}<br>
> +<br>
>  MCAsmBackend *llvm::createARMAsmBackend(const Target &T,<br>
>                                          const MCRegisterInfo &MRI,<br>
>                                          const Triple &TheTriple, StringRef CPU,<br>
> @@ -751,18 +785,7 @@ MCAsmBackend *llvm::createARMAsmBackend(<br>
>    default:<br>
>      llvm_unreachable("unsupported object format");<br>
>    case Triple::MachO: {<br>
> -    MachO::CPUSubTypeARM CS =<br>
> -        StringSwitch<MachO::CPUSubTypeARM>(TheTriple.getArchName())<br>
> -            .Cases("armv4t", "thumbv4t", MachO::CPU_SUBTYPE_ARM_V4T)<br>
> -            .Cases("armv5e", "thumbv5e", MachO::CPU_SUBTYPE_ARM_V5TEJ)<br>
> -            .Cases("armv6", "thumbv6", MachO::CPU_SUBTYPE_ARM_V6)<br>
> -            .Cases("armv6m", "thumbv6m", MachO::CPU_SUBTYPE_ARM_V6M)<br>
> -            .Cases("armv7em", "thumbv7em", MachO::CPU_SUBTYPE_ARM_V7EM)<br>
> -            .Cases("armv7k", "thumbv7k", MachO::CPU_SUBTYPE_ARM_V7K)<br>
> -            .Cases("armv7m", "thumbv7m", MachO::CPU_SUBTYPE_ARM_V7M)<br>
> -            .Cases("armv7s", "thumbv7s", MachO::CPU_SUBTYPE_ARM_V7S)<br>
> -            .Default(MachO::CPU_SUBTYPE_ARM_V7);<br>
> -<br>
> +    MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName());<br>
>      return new ARMAsmBackendDarwin(T, TheTriple, CS);<br>
>    }<br>
>    case Triple::COFF:<br>
><br>
> Added: llvm/trunk/test/CodeGen/ARM/MachO-subtypes.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/MachO-subtypes.ll?rev=245744&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/MachO-subtypes.ll?rev=245744&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/ARM/MachO-subtypes.ll (added)<br>
> +++ llvm/trunk/test/CodeGen/ARM/MachO-subtypes.ll Fri Aug 21 16:52:48 2015<br>
> @@ -0,0 +1,68 @@<br>
> +; Check that MachO ARM CPU Subtypes are respected<br>
> +<br>
> +; RUN: llc -mtriple=armv4t-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V4T<br>
> +<br>
> +; RUN: llc -mtriple=armv5-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5<br>
> +; RUN: llc -mtriple=armv5e-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5<br>
> +; RUN: llc -mtriple=armv5t-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5<br>
> +; RUN: llc -mtriple=armv5te-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5<br>
> +; RUN: llc -mtriple=armv5tej-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5<br>
> +<br>
> +; RUN: llc -mtriple=armv6-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V6<br>
> +; RUN: llc -mtriple=armv6k-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V6<br>
> +; RUN: llc -mtriple=thumbv6-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V6<br>
> +; RUN: llc -mtriple=thumbv6k-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V6<br>
> +<br>
> +; RUN: llc -mtriple=armv6m-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V6M<br>
> +; RUN: llc -mtriple=thumbv6m-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V6M<br>
> +<br>
> +; RUN: llc -mtriple=armv7-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7<br>
> +; RUN: llc -mtriple=thumbv7-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7<br>
> +<br>
> +; RUN: llc -mtriple=thumbv7em-apple-darwin -mcpu=cortex-m4 -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7EM<br>
> +; RUN: llc -mtriple=thumbv7em-apple-darwin -mcpu=cortex-m7 -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7EM<br>
> +<br>
> +; RUN: llc -mtriple=armv7k-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7K<br>
> +; RUN: llc -mtriple=thumbv7k-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7K<br>
> +<br>
> +; RUN: llc -mtriple=thumbv7m-apple-darwin -mcpu=sc300 -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7M<br>
> +; RUN: llc -mtriple=thumbv7m-apple-darwin -mcpu=cortex-m3 -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7M<br>
> +<br>
> +; RUN: llc -mtriple=armv7s-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7S<br>
> +; RUN: llc -mtriple=thumbv7s-apple-darwin -filetype=obj -o - < %s \<br>
> +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7S<br>
> +<br>
> +define void @_test() {<br>
> +  ret void<br>
> +}<br>
> +<br>
> +; CHECK-V4T:   CpuSubType: CPU_SUBTYPE_ARM_V4T (0x5)<br>
> +; CHECK-V5:   CpuSubType: CPU_SUBTYPE_ARM_V5 (0x7)<br>
> +; CHECK-V6:   CpuSubType: CPU_SUBTYPE_ARM_V6 (0x6)<br>
> +; CHECK-V6M:   CpuSubType: CPU_SUBTYPE_ARM_V6M (0xE)<br>
> +; CHECK-V7:   CpuSubType: CPU_SUBTYPE_ARM_V7 (0x9)<br>
> +; CHECK-V7EM:   CpuSubType: CPU_SUBTYPE_ARM_V7EM (0x10)<br>
> +; CHECK-V7K:   CpuSubType: CPU_SUBTYPE_ARM_V7K (0xC)<br>
> +; CHECK-V7M:   CpuSubType: CPU_SUBTYPE_ARM_V7M (0xF)<br>
> +; CHECK-V7S:   CpuSubType: CPU_SUBTYPE_ARM_V7S (0xB)<br>
><br>
><br>
> _______________________________________________<br>
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<br>
</blockquote></div>