<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
</head>
<body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">
Hi Ahmed,
<div class=""><br class="">
</div>
<div class="">Nice catch, thanks!</div>
<div class=""><br class="">
</div>
<div class="">I’ve conditionalised this for non-f16 in r245035 and added a test.</div>
<div class=""><br class="">
</div>
<div class="">fmin/fmax won’t be generated for f16 now and won’t currently be when D12015 lands, as D12015 checks that fmin/fmax is legal or custom - it doesn’t handle promoted types. This is an obvious improvement I could make.</div>
<div class=""><br class="">
</div>
<div class="">Cheers,</div>
<div class=""><br class="">
</div>
<div class="">James</div>
<div class=""><br class="">
<div class="">
<div>
<blockquote type="cite" class="">
<div class="">On 13 Aug 2015, at 23:32, Ahmed Bougacha <<a href="mailto:ahmed.bougacha@gmail.com" class="">ahmed.bougacha@gmail.com</a>> wrote:</div>
<br class="Apple-interchange-newline">
<div class=""><br class="Apple-interchange-newline">
<span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">On
Tue, Aug 11, 2015 at 5:06 AM, James Molloy via llvm-commits<span class="Apple-converted-space"> </span></span><span dir="ltr" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a>></span><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class=""></span><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">wrote:</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">
<blockquote class="gmail_quote" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex;">
Author: jamesm<br class="">
Date: Tue Aug 11 07:06:33 2015<br class="">
New Revision: 244594<br class="">
<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project?rev=244594&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=244594&view=rev</a><br class="">
Log:<br class="">
[AArch64] Replace the custom AArch64ISD::FMIN/MAX nodes with ISD::FMINNAN/MAXNAN<br class="">
<br class="">
NFCI. This just removes custom ISDNodes that are no longer needed.<br class="">
<br class="">
Modified:<br class="">
<span class="Apple-converted-space"> </span>llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br class="">
<span class="Apple-converted-space"> </span>llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h<br class="">
<span class="Apple-converted-space"> </span>llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=244594&r1=244593&r2=244594&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=244594&r1=244593&r2=244594&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Aug 11 07:06:33 2015<br class="">
@@ -679,6 +679,11 @@ void AArch64TargetLowering::addTypeForNE<br class="">
ISD::SABSDIFF, ISD::UABSDIFF})<br class="">
setOperationAction(Opcode, VT.getSimpleVT(), Legal);<br class="">
<br class="">
+ // F[MIN|MAX]NAN are available for all FP NEON types.<br class="">
+ if (VT.isFloatingPoint())<br class="">
+ for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN})<br class="">
+ setOperationAction(Opcode, VT.getSimpleVT(), Legal);<br class="">
+<br class="">
</blockquote>
<div style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">
<br class="">
</div>
<div style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">
f16 shouldn't be Legal (the Expand default is fine, but Promote with the other f16 setOperationActions is better).</div>
<div style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">
<br class="">
</div>
<div style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">
I guess this can't fire without D12015; when you land that, can you fix this and add an f{min,max}nan testcase to f16-instructions.ll (or elsewhere)?</div>
<div style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">
<br class="">
</div>
<div style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">
Thanks!</div>
<div style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">
<br class="">
</div>
<div style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">
-Ahmed</div>
<div style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">
</div>
<blockquote class="gmail_quote" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex;">
if (Subtarget->isLittleEndian()) {<br class="">
for (unsigned im = (unsigned)ISD::PRE_INC;<br class="">
<span class="Apple-converted-space"> </span>im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {<br class="">
@@ -818,8 +823,6 @@ const char *AArch64TargetLowering::getTa<br class="">
case AArch64ISD::CCMN: return "AArch64ISD::CCMN";<br class="">
case AArch64ISD::FCCMP: return "AArch64ISD::FCCMP";<br class="">
case AArch64ISD::FCMP: return "AArch64ISD::FCMP";<br class="">
- case AArch64ISD::FMIN: return "AArch64ISD::FMIN";<br class="">
- case AArch64ISD::FMAX: return "AArch64ISD::FMAX";<br class="">
case AArch64ISD::DUP: return "AArch64ISD::DUP";<br class="">
case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";<br class="">
case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";<br class="">
@@ -8219,10 +8222,10 @@ static SDValue performIntrinsicCombine(S<br class="">
case Intrinsic::aarch64_neon_umaxv:<br class="">
return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);<br class="">
case Intrinsic::aarch64_neon_fmax:<br class="">
- return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),<br class="">
+ return DAG.getNode(ISD::FMAXNAN, SDLoc(N), N->getValueType(0),<br class="">
<span class="Apple-converted-space"> </span>N->getOperand(1), N->getOperand(2));<br class="">
case Intrinsic::aarch64_neon_fmin:<br class="">
- return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),<br class="">
+ return DAG.getNode(ISD::FMINNAN, SDLoc(N), N->getValueType(0),<br class="">
<span class="Apple-converted-space"> </span>N->getOperand(1), N->getOperand(2));<br class="">
case Intrinsic::aarch64_neon_sabd:<br class="">
return DAG.getNode(ISD::SABSDIFF, SDLoc(N), N->getValueType(0),<br class="">
@@ -9147,7 +9150,7 @@ static SDValue performSelectCCCombine(SD<br class="">
case ISD::SETLT:<br class="">
case ISD::SETLE:<br class="">
IsOrEqual = (CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE);<br class="">
- Opcode = IsReversed ? AArch64ISD::FMAX : AArch64ISD::FMIN;<br class="">
+ Opcode = IsReversed ? ISD::FMAXNAN : ISD::FMINNAN;<br class="">
break;<br class="">
<br class="">
case ISD::SETUGT:<br class="">
@@ -9158,7 +9161,7 @@ static SDValue performSelectCCCombine(SD<br class="">
case ISD::SETGT:<br class="">
case ISD::SETGE:<br class="">
IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE);<br class="">
- Opcode = IsReversed ? AArch64ISD::FMIN : AArch64ISD::FMAX;<br class="">
+ Opcode = IsReversed ? ISD::FMINNAN : ISD::FMAXNAN;<br class="">
break;<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=244594&r1=244593&r2=244594&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=244594&r1=244593&r2=244594&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h Tue Aug 11 07:06:33 2015<br class="">
@@ -66,10 +66,6 @@ enum NodeType : unsigned {<br class="">
// Floating point comparison<br class="">
FCMP,<br class="">
<br class="">
- // Floating point max and min instructions.<br class="">
- FMAX,<br class="">
- FMIN,<br class="">
-<br class="">
// Scalar extract<br class="">
EXTR,<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td<br class="">
URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=244594&r1=244593&r2=244594&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=244594&r1=244593&r2=244594&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Tue Aug 11 07:06:33 2015<br class="">
@@ -182,9 +182,6 @@ def AArch64threadpointer : SDNode<"AArch<br class="">
<br class="">
def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;<br class="">
<br class="">
-def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;<br class="">
-def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;<br class="">
-<br class="">
def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;<br class="">
def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;<br class="">
def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;<br class="">
@@ -2506,18 +2503,18 @@ let SchedRW = [WriteFDiv] in {<br class="">
defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;<br class="">
}<br class="">
defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;<br class="">
-defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;<br class="">
+defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>;<br class="">
defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;<br class="">
-defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;<br class="">
+defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>;<br class="">
let SchedRW = [WriteFMul] in {<br class="">
defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;<br class="">
defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;<br class="">
}<br class="">
defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;<br class="">
<br class="">
-def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),<br class="">
+def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),<br class="">
(FMAXDrr FPR64:$Rn, FPR64:$Rm)>;<br class="">
-def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),<br class="">
+def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),<br class="">
(FMINDrr FPR64:$Rn, FPR64:$Rm)>;<br class="">
def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),<br class="">
(FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;<br class="">
@@ -2809,11 +2806,11 @@ defm FDIV : SIMDThreeSameVectorFP<1,0<br class="">
defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;<br class="">
defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;<br class="">
defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;<br class="">
-defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;<br class="">
+defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", fmaxnan>;<br class="">
defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;<br class="">
defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;<br class="">
defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;<br class="">
-defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;<br class="">
+defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", fminnan>;<br class="">
<br class="">
// NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the<br class="">
// instruction expects the addend first, while the fma intrinsic puts it last.<br class="">
<br class="">
<br class="">
_______________________________________________<br class="">
llvm-commits mailing list<br class="">
<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class="">
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank" class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a></blockquote>
</div>
</blockquote>
</div>
<br class="">
</div>
</div>
<br>
<font face="Arial" color="Black" size="2">-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents
to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.<br>
<br>
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590<br>
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782<br>
</font>
</body>
</html>