<div dir="ltr">I've attached the Ruby script that I mentioned in the commit message. <span style="line-height:normal">It converts from the old syntax to the new one.</span><div><div>Usage: upgradeTests.rb [options] files...</div><div> -i, --[no-]inplace Save the file inplace instead of printing it out</div><div><br></div></div><div>It doesn't convert the MBB successor weights, or MBB scalar attributes - it just prints out a FIXME for that line, so you have to do it manually for these things.</div><div><br></div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">2015-08-13 16:10 GMT-07:00 Alex Lorenz via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: arphaman<br>
Date: Thu Aug 13 18:10:16 2015<br>
New Revision: 244982<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=244982&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=244982&view=rev</a><br>
Log:<br>
MIR Serialization: Change MIR syntax - use custom syntax for MBBs.<br>
<br>
This commit modifies the way the machine basic blocks are serialized - now the<br>
machine basic blocks are serialized using a custom syntax instead of relying on<br>
YAML primitives. Instead of using YAML mappings to represent the individual<br>
machine basic blocks in a machine function's body, the new syntax uses a single<br>
YAML block scalar which contains all of the machine basic blocks and<br>
instructions for that function.<br>
<br>
This is an example of a function's body that uses the old syntax:<br>
<br>
body:<br>
- id: 0<br>
name: entry<br>
instructions:<br>
- '%eax = MOV32r0 implicit-def %eflags'<br>
- 'RETQ %eax'<br>
...<br>
<br>
The same body is now written like this:<br>
<br>
body: |<br>
bb.0.entry:<br>
%eax = MOV32r0 implicit-def %eflags<br>
RETQ %eax<br>
...<br>
<br>
This syntax change is motivated by the fact that the bundled machine<br>
instructions didn't map that well to the old syntax which was using a single<br>
YAML sequence to store all of the machine instructions in a block. The bundled<br>
machine instructions internally use flags like BundledPred and BundledSucc to<br>
determine the bundles, and serializing them as MI flags using the old syntax<br>
would have had a negative impact on the readability and the ease of editing<br>
for MIR files. The new syntax allows me to serialize the bundled machine<br>
instructions using a block construct without relying on the internal flags,<br>
for example:<br>
<br>
BUNDLE implicit-def dead %itstate, implicit-def %s1 ... {<br>
t2IT 1, 24, implicit-def %itstate<br>
%s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate<br>
}<br>
<br>
This commit also converts the MIR testcases to the new syntax. I developed<br>
a script that can convert from the old syntax to the new one. I will post the<br>
script on the llvm-commits mailing list in the thread for this commit.<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir<br>
Removed:<br>
llvm/trunk/test/CodeGen/MIR/Generic/expected-eof-after-successor-mbb.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-expected-ir-block.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/missing-instruction.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-few-weights.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-many-weights.mir<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h<br>
llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h<br>
llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp<br>
llvm/trunk/lib/CodeGen/MIRParser/MILexer.h<br>
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp<br>
llvm/trunk/lib/CodeGen/MIRParser/MIParser.h<br>
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br>
llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br>
llvm/trunk/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir<br>
llvm/trunk/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/basic-blocks.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/llvmIR.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/llvmIRMissing.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/machine-function-missing-function.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/machine-function-missing-name.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/machine-function.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir<br>
llvm/trunk/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir<br>
llvm/trunk/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/block-address-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/cfi-offset.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/constant-pool.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/constant-value-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/dead-register-flag.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-flags.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-target-flag-name.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/global-value-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/immediate-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/invalid-target-flag-name.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/large-immediate-operand-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/large-offset-number-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/machine-instructions.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/machine-verifier.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/missing-closing-quote.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/register-mask-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/stack-object-invalid-name.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/undef-register-flag.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/undefined-global-value.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/undefined-named-global-value.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/unknown-instruction.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/unrecognized-character.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/used-physical-register-info.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir<br>
llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir<br>
llvm/trunk/test/CodeGen/X86/expand-vr64-gr64-copy.mir<br>
llvm/trunk/test/CodeGen/X86/patchpoint-verifiable.mir<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Thu Aug 13 18:10:16 2015<br>
@@ -73,6 +73,20 @@ template <> struct ScalarTraits<FlowStri<br>
static bool mustQuote(StringRef Scalar) { return needsQuotes(Scalar); }<br>
};<br>
<br>
+struct BlockStringValue {<br>
+ StringValue Value;<br>
+};<br>
+<br>
+template <> struct BlockScalarTraits<BlockStringValue> {<br>
+ static void output(const BlockStringValue &S, void *Ctx, raw_ostream &OS) {<br>
+ return ScalarTraits<StringValue>::output(S.Value, Ctx, OS);<br>
+ }<br>
+<br>
+ static StringRef input(StringRef Scalar, void *Ctx, BlockStringValue &S) {<br>
+ return ScalarTraits<StringValue>::input(Scalar, Ctx, S.Value);<br>
+ }<br>
+};<br>
+<br>
/// A wrapper around unsigned which contains a source range that's being set<br>
/// during parsing.<br>
struct UnsignedValue {<br>
@@ -164,36 +178,6 @@ template <> struct MappingTraits<Machine<br>
static const bool flow = true;<br>
};<br>
<br>
-struct MachineBasicBlock {<br>
- unsigned ID;<br>
- StringValue Name;<br>
- StringValue IRBlock;<br>
- unsigned Alignment = 0;<br>
- bool IsLandingPad = false;<br>
- bool AddressTaken = false;<br>
- std::vector<FlowStringValue> Successors;<br>
- std::vector<UnsignedValue> SuccessorWeights;<br>
- std::vector<FlowStringValue> LiveIns;<br>
- std::vector<StringValue> Instructions;<br>
-};<br>
-<br>
-template <> struct MappingTraits<MachineBasicBlock> {<br>
- static void mapping(IO &YamlIO, MachineBasicBlock &MBB) {<br>
- YamlIO.mapRequired("id", <a href="http://MBB.ID" rel="noreferrer" target="_blank">MBB.ID</a>);<br>
- YamlIO.mapOptional("name", MBB.Name,<br>
- StringValue()); // Don't print out an empty name.<br>
- YamlIO.mapOptional("ir-block", MBB.IRBlock,<br>
- StringValue()); // Don't print out an empty BB reference.<br>
- YamlIO.mapOptional("alignment", MBB.Alignment);<br>
- YamlIO.mapOptional("isLandingPad", MBB.IsLandingPad);<br>
- YamlIO.mapOptional("addressTaken", MBB.AddressTaken);<br>
- YamlIO.mapOptional("successors", MBB.Successors);<br>
- YamlIO.mapOptional("weights", MBB.SuccessorWeights);<br>
- YamlIO.mapOptional("liveins", MBB.LiveIns);<br>
- YamlIO.mapOptional("instructions", MBB.Instructions);<br>
- }<br>
-};<br>
-<br>
/// Serializable representation of stack object from the MachineFrameInfo class.<br>
///<br>
/// The flags 'isImmutable' and 'isAliased' aren't serialized, as they are<br>
@@ -320,7 +304,6 @@ template <> struct MappingTraits<Machine<br>
<br>
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineFunctionLiveIn)<br>
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::VirtualRegisterDefinition)<br>
-LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineBasicBlock)<br>
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineStackObject)<br>
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::FixedMachineStackObject)<br>
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineConstantPoolValue)<br>
@@ -404,8 +387,7 @@ struct MachineFunction {<br>
std::vector<MachineStackObject> StackObjects;<br>
std::vector<MachineConstantPoolValue> Constants; /// Constant pool.<br>
MachineJumpTable JumpTableInfo;<br>
-<br>
- std::vector<MachineBasicBlock> BasicBlocks;<br>
+ BlockStringValue Body;<br>
};<br>
<br>
template <> struct MappingTraits<MachineFunction> {<br>
@@ -426,7 +408,7 @@ template <> struct MappingTraits<Machine<br>
YamlIO.mapOptional("constants", MF.Constants);<br>
if (!YamlIO.outputting() || !MF.JumpTableInfo.Entries.empty())<br>
YamlIO.mapOptional("jumpTable", MF.JumpTableInfo);<br>
- YamlIO.mapOptional("body", MF.BasicBlocks);<br>
+ YamlIO.mapOptional("body", MF.Body);<br>
}<br>
};<br>
<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Thu Aug 13 18:10:16 2015<br>
@@ -25,7 +25,7 @@ class Pass;<br>
class BasicBlock;<br>
class MachineFunction;<br>
class MCSymbol;<br>
-class MIRPrinter;<br>
+class MIPrinter;<br>
class SlotIndexes;<br>
class StringRef;<br>
class raw_ostream;<br>
@@ -660,7 +660,7 @@ private:<br>
const_weight_iterator getWeightIterator(const_succ_iterator I) const;<br>
<br>
friend class MachineBranchProbabilityInfo;<br>
- friend class MIRPrinter;<br>
+ friend class MIPrinter;<br>
<br>
/// Return weight of the edge from this block to MBB. This method should NOT<br>
/// be called directly, but by using getEdgeWeight method from<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp Thu Aug 13 18:10:16 2015<br>
@@ -79,7 +79,18 @@ MIToken &MIToken::setIntegerValue(APSInt<br>
<br>
/// Skip the leading whitespace characters and return the updated cursor.<br>
static Cursor skipWhitespace(Cursor C) {<br>
- while (isspace(C.peek()))<br>
+ while (isblank(C.peek()))<br>
+ C.advance();<br>
+ return C;<br>
+}<br>
+<br>
+static bool isNewlineChar(char C) { return C == '\n' || C == '\r'; }<br>
+<br>
+/// Skip a line comment and return the updated cursor.<br>
+static Cursor skipComment(Cursor C) {<br>
+ if (C.peek() != ';')<br>
+ return C;<br>
+ while (!isNewlineChar(C.peek()) && !C.isEOF())<br>
C.advance();<br>
return C;<br>
}<br>
@@ -127,7 +138,7 @@ static Cursor lexStringConstant(<br>
function_ref<void(StringRef::iterator Loc, const Twine &)> ErrorCallback) {<br>
assert(C.peek() == '"');<br>
for (C.advance(); C.peek() != '"'; C.advance()) {<br>
- if (C.isEOF()) {<br>
+ if (C.isEOF() || isNewlineChar(C.peek())) {<br>
ErrorCallback(<br>
C.location(),<br>
"end of machine instruction reached before the closing '\"'");<br>
@@ -206,6 +217,10 @@ static MIToken::TokenKind getIdentifierK<br>
.Case("jump-table", MIToken::kw_jump_table)<br>
.Case("constant-pool", MIToken::kw_constant_pool)<br>
.Case("liveout", MIToken::kw_liveout)<br>
+ .Case("address-taken", MIToken::kw_address_taken)<br>
+ .Case("landing-pad", MIToken::kw_landing_pad)<br>
+ .Case("liveins", MIToken::kw_liveins)<br>
+ .Case("successors", MIToken::kw_successors)<br>
.Default(MIToken::Identifier);<br>
}<br>
<br>
@@ -224,10 +239,12 @@ static Cursor maybeLexIdentifier(Cursor<br>
static Cursor maybeLexMachineBasicBlock(<br>
Cursor C, MIToken &Token,<br>
function_ref<void(StringRef::iterator Loc, const Twine &)> ErrorCallback) {<br>
- if (!C.remaining().startswith("%bb."))<br>
+ bool IsReference = C.remaining().startswith("%bb.");<br>
+ if (!IsReference && !C.remaining().startswith("bb."))<br>
return None;<br>
auto Range = C;<br>
- C.advance(4); // Skip '%bb.'<br>
+ unsigned PrefixLength = IsReference ? 4 : 3;<br>
+ C.advance(PrefixLength); // Skip '%bb.' or 'bb.'<br>
if (!isdigit(C.peek())) {<br>
Token.reset(MIToken::Error, C.remaining());<br>
ErrorCallback(C.location(), "expected a number after '%bb.'");<br>
@@ -237,14 +254,16 @@ static Cursor maybeLexMachineBasicBlock(<br>
while (isdigit(C.peek()))<br>
C.advance();<br>
StringRef Number = NumberRange.upto(C);<br>
- unsigned StringOffset = 4 + Number.size(); // Drop '%bb.<id>'<br>
+ unsigned StringOffset = PrefixLength + Number.size(); // Drop '%bb.<id>'<br>
if (C.peek() == '.') {<br>
C.advance(); // Skip '.'<br>
++StringOffset;<br>
while (isIdentifierChar(C.peek()))<br>
C.advance();<br>
}<br>
- Token.reset(MIToken::MachineBasicBlock, Range.upto(C))<br>
+ Token.reset(IsReference ? MIToken::MachineBasicBlock<br>
+ : MIToken::MachineBasicBlockLabel,<br>
+ Range.upto(C))<br>
.setIntegerValue(APSInt(Number))<br>
.setStringValue(Range.upto(C).drop_front(StringOffset));<br>
return C;<br>
@@ -460,10 +479,19 @@ static Cursor maybeLexSymbol(Cursor C, M<br>
return C;<br>
}<br>
<br>
+static Cursor maybeLexNewline(Cursor C, MIToken &Token) {<br>
+ if (!isNewlineChar(C.peek()))<br>
+ return None;<br>
+ auto Range = C;<br>
+ C.advance();<br>
+ Token.reset(MIToken::Newline, Range.upto(C));<br>
+ return C;<br>
+}<br>
+<br>
StringRef llvm::lexMIToken(<br>
StringRef Source, MIToken &Token,<br>
function_ref<void(StringRef::iterator Loc, const Twine &)> ErrorCallback) {<br>
- auto C = skipWhitespace(Cursor(Source));<br>
+ auto C = skipComment(skipWhitespace(Cursor(Source)));<br>
if (C.isEOF()) {<br>
Token.reset(MIToken::Eof, C.remaining());<br>
return C.remaining();<br>
@@ -471,10 +499,10 @@ StringRef llvm::lexMIToken(<br>
<br>
if (Cursor R = maybeLexIntegerType(C, Token))<br>
return R.remaining();<br>
- if (Cursor R = maybeLexIdentifier(C, Token))<br>
- return R.remaining();<br>
if (Cursor R = maybeLexMachineBasicBlock(C, Token, ErrorCallback))<br>
return R.remaining();<br>
+ if (Cursor R = maybeLexIdentifier(C, Token))<br>
+ return R.remaining();<br>
if (Cursor R = maybeLexJumpTableIndex(C, Token))<br>
return R.remaining();<br>
if (Cursor R = maybeLexStackObject(C, Token))<br>
@@ -499,6 +527,8 @@ StringRef llvm::lexMIToken(<br>
return R.remaining();<br>
if (Cursor R = maybeLexSymbol(C, Token))<br>
return R.remaining();<br>
+ if (Cursor R = maybeLexNewline(C, Token))<br>
+ return R.remaining();<br>
<br>
Token.reset(MIToken::Error, C.remaining());<br>
ErrorCallback(C.location(),<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MILexer.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.h?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.h?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.h (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.h Thu Aug 13 18:10:16 2015<br>
@@ -30,6 +30,7 @@ struct MIToken {<br>
// Markers<br>
Eof,<br>
Error,<br>
+ Newline,<br>
<br>
// Tokens with no info.<br>
comma,<br>
@@ -75,11 +76,16 @@ struct MIToken {<br>
kw_jump_table,<br>
kw_constant_pool,<br>
kw_liveout,<br>
+ kw_address_taken,<br>
+ kw_landing_pad,<br>
+ kw_liveins,<br>
+ kw_successors,<br>
<br>
// Identifier tokens<br>
Identifier,<br>
IntegerType,<br>
NamedRegister,<br>
+ MachineBasicBlockLabel,<br>
MachineBasicBlock,<br>
StackObject,<br>
FixedStackObject,<br>
@@ -118,6 +124,10 @@ public:<br>
<br>
bool isError() const { return Kind == Error; }<br>
<br>
+ bool isNewlineOrEOF() const { return Kind == Newline || Kind == Eof; }<br>
+<br>
+ bool isErrorOrEOF() const { return Kind == Error || Kind == Eof; }<br>
+<br>
bool isRegister() const {<br>
return Kind == NamedRegister || Kind == underscore ||<br>
Kind == VirtualRegister;<br>
@@ -149,10 +159,10 @@ public:<br>
<br>
bool hasIntegerValue() const {<br>
return Kind == IntegerLiteral || Kind == MachineBasicBlock ||<br>
- Kind == StackObject || Kind == FixedStackObject ||<br>
- Kind == GlobalValue || Kind == VirtualRegister ||<br>
- Kind == ConstantPoolItem || Kind == JumpTableIndex ||<br>
- Kind == IRBlock;<br>
+ Kind == MachineBasicBlockLabel || Kind == StackObject ||<br>
+ Kind == FixedStackObject || Kind == GlobalValue ||<br>
+ Kind == VirtualRegister || Kind == ConstantPoolItem ||<br>
+ Kind == JumpTableIndex || Kind == IRBlock;<br>
}<br>
};<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Thu Aug 13 18:10:16 2015<br>
@@ -90,11 +90,19 @@ public:<br>
/// This function always return true.<br>
bool error(StringRef::iterator Loc, const Twine &Msg);<br>
<br>
+ bool<br>
+ parseBasicBlockDefinitions(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);<br>
+ bool parseBasicBlocks();<br>
bool parse(MachineInstr *&MI);<br>
bool parseStandaloneMBB(MachineBasicBlock *&MBB);<br>
bool parseStandaloneNamedRegister(unsigned &Reg);<br>
bool parseStandaloneVirtualRegister(unsigned &Reg);<br>
- bool parseStandaloneIRBlockReference(const BasicBlock *&BB);<br>
+<br>
+ bool<br>
+ parseBasicBlockDefinition(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);<br>
+ bool parseBasicBlock(MachineBasicBlock &MBB);<br>
+ bool parseBasicBlockLiveins(MachineBasicBlock &MBB);<br>
+ bool parseBasicBlockSuccessors(MachineBasicBlock &MBB);<br>
<br>
bool parseRegister(unsigned &Reg);<br>
bool parseRegisterFlag(unsigned &Flags);<br>
@@ -149,6 +157,10 @@ private:<br>
/// Otherwise report an error and return true.<br>
bool expectAndConsume(MIToken::TokenKind TokenKind);<br>
<br>
+ /// If the current token is of the given kind, consume it and return true.<br>
+ /// Otherwise return false.<br>
+ bool consumeIfPresent(MIToken::TokenKind TokenKind);<br>
+<br>
void initNames2InstrOpCodes();<br>
<br>
/// Try to convert an instruction name to an opcode. Return true if the<br>
@@ -217,10 +229,17 @@ bool MIParser::error(const Twine &Msg) {<br>
<br>
bool MIParser::error(StringRef::iterator Loc, const Twine &Msg) {<br>
assert(Loc >= Source.data() && Loc <= (Source.data() + Source.size()));<br>
- Error = SMDiagnostic(<br>
- SM, SMLoc(),<br>
- SM.getMemoryBuffer(SM.getMainFileID())->getBufferIdentifier(), 1,<br>
- Loc - Source.data(), SourceMgr::DK_Error, Msg.str(), Source, None, None);<br>
+ const MemoryBuffer &Buffer = *SM.getMemoryBuffer(SM.getMainFileID());<br>
+ if (Loc >= Buffer.getBufferStart() && Loc <= Buffer.getBufferEnd()) {<br>
+ // Create an ordinary diagnostic when the source manager's buffer is the<br>
+ // source string.<br>
+ Error = SM.GetMessage(SMLoc::getFromPointer(Loc), SourceMgr::DK_Error, Msg);<br>
+ return true;<br>
+ }<br>
+ // Create a diagnostic for a YAML string literal.<br>
+ Error = SMDiagnostic(SM, SMLoc(), Buffer.getBufferIdentifier(), 1,<br>
+ Loc - Source.data(), SourceMgr::DK_Error, Msg.str(),<br>
+ Source, None, None);<br>
return true;<br>
}<br>
<br>
@@ -230,6 +249,8 @@ static const char *toString(MIToken::Tok<br>
return "','";<br>
case MIToken::equal:<br>
return "'='";<br>
+ case MIToken::colon:<br>
+ return "':'";<br>
case MIToken::lparen:<br>
return "'('";<br>
case MIToken::rparen:<br>
@@ -246,9 +267,236 @@ bool MIParser::expectAndConsume(MIToken:<br>
return false;<br>
}<br>
<br>
-bool MIParser::parse(MachineInstr *&MI) {<br>
+bool MIParser::consumeIfPresent(MIToken::TokenKind TokenKind) {<br>
+ if (Token.isNot(TokenKind))<br>
+ return false;<br>
lex();<br>
+ return true;<br>
+}<br>
<br>
+bool MIParser::parseBasicBlockDefinition(<br>
+ DenseMap<unsigned, MachineBasicBlock *> &MBBSlots) {<br>
+ assert(Token.is(MIToken::MachineBasicBlockLabel));<br>
+ unsigned ID = 0;<br>
+ if (getUnsigned(ID))<br>
+ return true;<br>
+ auto Loc = Token.location();<br>
+ auto Name = Token.stringValue();<br>
+ lex();<br>
+ bool HasAddressTaken = false;<br>
+ bool IsLandingPad = false;<br>
+ unsigned Alignment = 0;<br>
+ BasicBlock *BB = nullptr;<br>
+ if (consumeIfPresent(MIToken::lparen)) {<br>
+ do {<br>
+ // TODO: Report an error when multiple same attributes are specified.<br>
+ switch (Token.kind()) {<br>
+ case MIToken::kw_address_taken:<br>
+ HasAddressTaken = true;<br>
+ lex();<br>
+ break;<br>
+ case MIToken::kw_landing_pad:<br>
+ IsLandingPad = true;<br>
+ lex();<br>
+ break;<br>
+ case MIToken::kw_align:<br>
+ if (parseAlignment(Alignment))<br>
+ return true;<br>
+ break;<br>
+ case MIToken::IRBlock:<br>
+ // TODO: Report an error when both name and ir block are specified.<br>
+ if (parseIRBlock(BB, *MF.getFunction()))<br>
+ return true;<br>
+ lex();<br>
+ break;<br>
+ default:<br>
+ break;<br>
+ }<br>
+ } while (consumeIfPresent(MIToken::comma));<br>
+ if (expectAndConsume(MIToken::rparen))<br>
+ return true;<br>
+ }<br>
+ if (expectAndConsume(MIToken::colon))<br>
+ return true;<br>
+<br>
+ if (!Name.empty()) {<br>
+ BB = dyn_cast_or_null<BasicBlock>(<br>
+ MF.getFunction()->getValueSymbolTable().lookup(Name));<br>
+ if (!BB)<br>
+ return error(Loc, Twine("basic block '") + Name +<br>
+ "' is not defined in the function '" +<br>
+ MF.getName() + "'");<br>
+ }<br>
+ auto *MBB = MF.CreateMachineBasicBlock(BB);<br>
+ MF.insert(MF.end(), MBB);<br>
+ bool WasInserted = MBBSlots.insert(std::make_pair(ID, MBB)).second;<br>
+ if (!WasInserted)<br>
+ return error(Loc, Twine("redefinition of machine basic block with id #") +<br>
+ Twine(ID));<br>
+ if (Alignment)<br>
+ MBB->setAlignment(Alignment);<br>
+ if (HasAddressTaken)<br>
+ MBB->setHasAddressTaken();<br>
+ MBB->setIsLandingPad(IsLandingPad);<br>
+ return false;<br>
+}<br>
+<br>
+bool MIParser::parseBasicBlockDefinitions(<br>
+ DenseMap<unsigned, MachineBasicBlock *> &MBBSlots) {<br>
+ lex();<br>
+ // Skip until the first machine basic block.<br>
+ while (Token.is(MIToken::Newline))<br>
+ lex();<br>
+ if (Token.isErrorOrEOF())<br>
+ return Token.isError();<br>
+ if (Token.isNot(MIToken::MachineBasicBlockLabel))<br>
+ return error("expected a basic block definition before instructions");<br>
+ do {<br>
+ if (parseBasicBlockDefinition(MBBSlots))<br>
+ return true;<br>
+ bool IsAfterNewline = false;<br>
+ // Skip until the next machine basic block.<br>
+ while (true) {<br>
+ if ((Token.is(MIToken::MachineBasicBlockLabel) && IsAfterNewline) ||<br>
+ Token.isErrorOrEOF())<br>
+ break;<br>
+ else if (Token.is(MIToken::MachineBasicBlockLabel))<br>
+ return error("basic block definition should be located at the start of "<br>
+ "the line");<br>
+ if (Token.is(MIToken::Newline))<br>
+ IsAfterNewline = true;<br>
+ else<br>
+ IsAfterNewline = false;<br>
+ lex();<br>
+ }<br>
+ } while (!Token.isErrorOrEOF());<br>
+ return Token.isError();<br>
+}<br>
+<br>
+bool MIParser::parseBasicBlockLiveins(MachineBasicBlock &MBB) {<br>
+ assert(Token.is(MIToken::kw_liveins));<br>
+ lex();<br>
+ if (expectAndConsume(MIToken::colon))<br>
+ return true;<br>
+ if (Token.isNewlineOrEOF()) // Allow an empty list of liveins.<br>
+ return false;<br>
+ do {<br>
+ if (Token.isNot(MIToken::NamedRegister))<br>
+ return error("expected a named register");<br>
+ unsigned Reg = 0;<br>
+ if (parseRegister(Reg))<br>
+ return true;<br>
+ MBB.addLiveIn(Reg);<br>
+ lex();<br>
+ } while (consumeIfPresent(MIToken::comma));<br>
+ return false;<br>
+}<br>
+<br>
+bool MIParser::parseBasicBlockSuccessors(MachineBasicBlock &MBB) {<br>
+ assert(Token.is(MIToken::kw_successors));<br>
+ lex();<br>
+ if (expectAndConsume(MIToken::colon))<br>
+ return true;<br>
+ if (Token.isNewlineOrEOF()) // Allow an empty list of successors.<br>
+ return false;<br>
+ do {<br>
+ if (Token.isNot(MIToken::MachineBasicBlock))<br>
+ return error("expected a machine basic block reference");<br>
+ MachineBasicBlock *SuccMBB = nullptr;<br>
+ if (parseMBBReference(SuccMBB))<br>
+ return true;<br>
+ lex();<br>
+ unsigned Weight = 0;<br>
+ if (consumeIfPresent(MIToken::lparen)) {<br>
+ if (Token.isNot(MIToken::IntegerLiteral))<br>
+ return error("expected an integer literal after '('");<br>
+ if (getUnsigned(Weight))<br>
+ return true;<br>
+ lex();<br>
+ if (expectAndConsume(MIToken::rparen))<br>
+ return true;<br>
+ }<br>
+ MBB.addSuccessor(SuccMBB, Weight);<br>
+ } while (consumeIfPresent(MIToken::comma));<br>
+ return false;<br>
+}<br>
+<br>
+bool MIParser::parseBasicBlock(MachineBasicBlock &MBB) {<br>
+ // Skip the definition.<br>
+ assert(Token.is(MIToken::MachineBasicBlockLabel));<br>
+ lex();<br>
+ if (consumeIfPresent(MIToken::lparen)) {<br>
+ while (Token.isNot(MIToken::rparen) && !Token.isErrorOrEOF())<br>
+ lex();<br>
+ consumeIfPresent(MIToken::rparen);<br>
+ }<br>
+ consumeIfPresent(MIToken::colon);<br>
+<br>
+ // Parse the liveins and successors.<br>
+ // N.B: Multiple lists of successors and liveins are allowed and they're<br>
+ // merged into one.<br>
+ // Example:<br>
+ // liveins: %edi<br>
+ // liveins: %esi<br>
+ //<br>
+ // is equivalent to<br>
+ // liveins: %edi, %esi<br>
+ while (true) {<br>
+ if (Token.is(MIToken::kw_successors)) {<br>
+ if (parseBasicBlockSuccessors(MBB))<br>
+ return true;<br>
+ } else if (Token.is(MIToken::kw_liveins)) {<br>
+ if (parseBasicBlockLiveins(MBB))<br>
+ return true;<br>
+ } else if (consumeIfPresent(MIToken::Newline)) {<br>
+ continue;<br>
+ } else<br>
+ break;<br>
+ if (!Token.isNewlineOrEOF())<br>
+ return error("expected line break at the end of a list");<br>
+ lex();<br>
+ }<br>
+<br>
+ // Parse the instructions.<br>
+ while (true) {<br>
+ if (Token.is(MIToken::MachineBasicBlockLabel) || Token.is(MIToken::Eof))<br>
+ return false;<br>
+ else if (consumeIfPresent(MIToken::Newline))<br>
+ continue;<br>
+ MachineInstr *MI = nullptr;<br>
+ if (parse(MI))<br>
+ return true;<br>
+ MBB.insert(MBB.end(), MI);<br>
+ assert(Token.isNewlineOrEOF() && "MI is not fully parsed");<br>
+ lex();<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+bool MIParser::parseBasicBlocks() {<br>
+ lex();<br>
+ // Skip until the first machine basic block.<br>
+ while (Token.is(MIToken::Newline))<br>
+ lex();<br>
+ if (Token.isErrorOrEOF())<br>
+ return Token.isError();<br>
+ // The first parsing pass should have verified that this token is a MBB label<br>
+ // in the 'parseBasicBlockDefinitions' method.<br>
+ assert(Token.is(MIToken::MachineBasicBlockLabel));<br>
+ do {<br>
+ MachineBasicBlock *MBB = nullptr;<br>
+ if (parseMBBReference(MBB))<br>
+ return true;<br>
+ if (parseBasicBlock(*MBB))<br>
+ return true;<br>
+ // The method 'parseBasicBlock' should parse the whole block until the next<br>
+ // block or the end of file.<br>
+ assert(Token.is(MIToken::MachineBasicBlockLabel) || Token.is(MIToken::Eof));<br>
+ } while (Token.isNot(MIToken::Eof));<br>
+ return false;<br>
+}<br>
+<br>
+bool MIParser::parse(MachineInstr *&MI) {<br>
// Parse any register operands before '='<br>
MachineOperand MO = MachineOperand::CreateImm(0);<br>
SmallVector<MachineOperandWithLocation, 8> Operands;<br>
@@ -271,13 +519,13 @@ bool MIParser::parse(MachineInstr *&MI)<br>
// TODO: Parse the bundle instruction flags.<br>
<br>
// Parse the remaining machine operands.<br>
- while (Token.isNot(MIToken::Eof) && Token.isNot(MIToken::kw_debug_location) &&<br>
+ while (!Token.isNewlineOrEOF() && Token.isNot(MIToken::kw_debug_location) &&<br>
Token.isNot(MIToken::coloncolon)) {<br>
auto Loc = Token.location();<br>
if (parseMachineOperandAndTargetFlags(MO))<br>
return true;<br>
Operands.push_back(MachineOperandWithLocation(MO, Loc, Token.location()));<br>
- if (Token.is(MIToken::Eof) || Token.is(MIToken::coloncolon))<br>
+ if (Token.isNewlineOrEOF() || Token.is(MIToken::coloncolon))<br>
break;<br>
if (Token.isNot(MIToken::comma))<br>
return error("expected ',' before the next machine operand");<br>
@@ -299,12 +547,12 @@ bool MIParser::parse(MachineInstr *&MI)<br>
SmallVector<MachineMemOperand *, 2> MemOperands;<br>
if (Token.is(MIToken::coloncolon)) {<br>
lex();<br>
- while (Token.isNot(MIToken::Eof)) {<br>
+ while (!Token.isNewlineOrEOF()) {<br>
MachineMemOperand *MemOp = nullptr;<br>
if (parseMachineMemoryOperand(MemOp))<br>
return true;<br>
MemOperands.push_back(MemOp);<br>
- if (Token.is(MIToken::Eof))<br>
+ if (Token.isNewlineOrEOF())<br>
break;<br>
if (Token.isNot(MIToken::comma))<br>
return error("expected ',' before the next machine memory operand");<br>
@@ -370,23 +618,6 @@ bool MIParser::parseStandaloneVirtualReg<br>
return false;<br>
}<br>
<br>
-bool MIParser::parseStandaloneIRBlockReference(const BasicBlock *&BB) {<br>
- lex();<br>
- if (Token.isNot(MIToken::IRBlock))<br>
- return error("expected an IR block reference");<br>
- unsigned SlotNumber = 0;<br>
- if (getUnsigned(SlotNumber))<br>
- return true;<br>
- BB = getIRBlock(SlotNumber);<br>
- if (!BB)<br>
- return error(Twine("use of undefined IR block '%ir-block.") +<br>
- Twine(SlotNumber) + "'");<br>
- lex();<br>
- if (Token.isNot(MIToken::Eof))<br>
- return error("expected end of string after the IR block reference");<br>
- return false;<br>
-}<br>
-<br>
static const char *printImplicitRegisterFlag(const MachineOperand &MO) {<br>
assert(MO.isImplicit());<br>
return MO.isDef() ? "implicit-def" : "implicit";<br>
@@ -621,7 +852,8 @@ bool MIParser::getUnsigned(unsigned &Res<br>
}<br>
<br>
bool MIParser::parseMBBReference(MachineBasicBlock *&MBB) {<br>
- assert(Token.is(MIToken::MachineBasicBlock));<br>
+ assert(Token.is(MIToken::MachineBasicBlock) ||<br>
+ Token.is(MIToken::MachineBasicBlockLabel));<br>
unsigned Number;<br>
if (getUnsigned(Number))<br>
return true;<br>
@@ -1406,11 +1638,27 @@ bool MIParser::getDirectTargetFlag(Strin<br>
return false;<br>
}<br>
<br>
-bool llvm::parseMachineInstr(MachineInstr *&MI, SourceMgr &SM,<br>
- MachineFunction &MF, StringRef Src,<br>
- const PerFunctionMIParsingState &PFS,<br>
- const SlotMapping &IRSlots, SMDiagnostic &Error) {<br>
- return MIParser(SM, MF, Error, Src, PFS, IRSlots).parse(MI);<br>
+bool llvm::parseMachineBasicBlockDefinitions(MachineFunction &MF, StringRef Src,<br>
+ PerFunctionMIParsingState &PFS,<br>
+ const SlotMapping &IRSlots,<br>
+ SMDiagnostic &Error) {<br>
+ SourceMgr SM;<br>
+ SM.AddNewSourceBuffer(<br>
+ MemoryBuffer::getMemBuffer(Src, "", /*RequiresNullTerminator=*/false),<br>
+ SMLoc());<br>
+ return MIParser(SM, MF, Error, Src, PFS, IRSlots)<br>
+ .parseBasicBlockDefinitions(PFS.MBBSlots);<br>
+}<br>
+<br>
+bool llvm::parseMachineInstructions(MachineFunction &MF, StringRef Src,<br>
+ const PerFunctionMIParsingState &PFS,<br>
+ const SlotMapping &IRSlots,<br>
+ SMDiagnostic &Error) {<br>
+ SourceMgr SM;<br>
+ SM.AddNewSourceBuffer(<br>
+ MemoryBuffer::getMemBuffer(Src, "", /*RequiresNullTerminator=*/false),<br>
+ SMLoc());<br>
+ return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseBasicBlocks();<br>
}<br>
<br>
bool llvm::parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM,<br>
@@ -1437,12 +1685,3 @@ bool llvm::parseVirtualRegisterReference<br>
return MIParser(SM, MF, Error, Src, PFS, IRSlots)<br>
.parseStandaloneVirtualRegister(Reg);<br>
}<br>
-<br>
-bool llvm::parseIRBlockReference(const BasicBlock *&BB, SourceMgr &SM,<br>
- MachineFunction &MF, StringRef Src,<br>
- const PerFunctionMIParsingState &PFS,<br>
- const SlotMapping &IRSlots,<br>
- SMDiagnostic &Error) {<br>
- return MIParser(SM, MF, Error, Src, PFS, IRSlots)<br>
- .parseStandaloneIRBlockReference(BB);<br>
-}<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.h?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.h?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.h (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.h Thu Aug 13 18:10:16 2015<br>
@@ -36,9 +36,36 @@ struct PerFunctionMIParsingState {<br>
DenseMap<unsigned, unsigned> JumpTableSlots;<br>
};<br>
<br>
-bool parseMachineInstr(MachineInstr *&MI, SourceMgr &SM, MachineFunction &MF,<br>
- StringRef Src, const PerFunctionMIParsingState &PFS,<br>
- const SlotMapping &IRSlots, SMDiagnostic &Error);<br>
+/// Parse the machine basic block definitions, and skip the machine<br>
+/// instructions.<br>
+///<br>
+/// This function runs the first parsing pass on the machine function's body.<br>
+/// It parses only the machine basic block definitions and creates the machine<br>
+/// basic blocks in the given machine function.<br>
+///<br>
+/// The machine instructions aren't parsed during the first pass because all<br>
+/// the machine basic blocks aren't defined yet - this makes it impossible to<br>
+/// resolve the machine basic block references.<br>
+///<br>
+/// Return true if an error occurred.<br>
+bool parseMachineBasicBlockDefinitions(MachineFunction &MF, StringRef Src,<br>
+ PerFunctionMIParsingState &PFS,<br>
+ const SlotMapping &IRSlots,<br>
+ SMDiagnostic &Error);<br>
+<br>
+/// Parse the machine instructions.<br>
+///<br>
+/// This function runs the second parsing pass on the machine function's body.<br>
+/// It skips the machine basic block definitions and parses only the machine<br>
+/// instructions and basic block attributes like liveins and successors.<br>
+///<br>
+/// The second parsing pass assumes that the first parsing pass already ran<br>
+/// on the given source string.<br>
+///<br>
+/// Return true if an error occurred.<br>
+bool parseMachineInstructions(MachineFunction &MF, StringRef Src,<br>
+ const PerFunctionMIParsingState &PFS,<br>
+ const SlotMapping &IRSlots, SMDiagnostic &Error);<br>
<br>
bool parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM,<br>
MachineFunction &MF, StringRef Src,<br>
@@ -57,11 +84,6 @@ bool parseVirtualRegisterReference(unsig<br>
const SlotMapping &IRSlots,<br>
SMDiagnostic &Error);<br>
<br>
-bool parseIRBlockReference(const BasicBlock *&BB, SourceMgr &SM,<br>
- MachineFunction &MF, StringRef Src,<br>
- const PerFunctionMIParsingState &PFS,<br>
- const SlotMapping &IRSlots, SMDiagnostic &Error);<br>
-<br>
} // end namespace llvm<br>
<br>
#endif<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Thu Aug 13 18:10:16 2015<br>
@@ -96,13 +96,6 @@ public:<br>
/// Return true if error occurred.<br>
bool initializeMachineFunction(MachineFunction &MF);<br>
<br>
- /// Initialize the machine basic block using it's YAML representation.<br>
- ///<br>
- /// Return true if an error occurred.<br>
- bool initializeMachineBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,<br>
- const yaml::MachineBasicBlock &YamlMBB,<br>
- const PerFunctionMIParsingState &PFS);<br>
-<br>
bool initializeRegisterInfo(MachineFunction &MF,<br>
const yaml::MachineFunction &YamlMF,<br>
PerFunctionMIParsingState &PFS);<br>
@@ -294,36 +287,15 @@ bool MIRParserImpl::initializeMachineFun<br>
return true;<br>
}<br>
<br>
- const auto &F = *MF.getFunction();<br>
- for (const auto &YamlMBB : YamlMF.BasicBlocks) {<br>
- const BasicBlock *BB = nullptr;<br>
- const yaml::StringValue &Name = YamlMBB.Name;<br>
- const yaml::StringValue &IRBlock = YamlMBB.IRBlock;<br>
- if (!Name.Value.empty()) {<br>
- BB = dyn_cast_or_null<BasicBlock>(<br>
- F.getValueSymbolTable().lookup(Name.Value));<br>
- if (!BB)<br>
- return error(Name.SourceRange.Start,<br>
- Twine("basic block '") + Name.Value +<br>
- "' is not defined in the function '" + MF.getName() +<br>
- "'");<br>
- }<br>
- if (!IRBlock.Value.empty()) {<br>
- // TODO: Report an error when both name and ir block are specified.<br>
- SMDiagnostic Error;<br>
- if (parseIRBlockReference(BB, SM, MF, IRBlock.Value, PFS, IRSlots, Error))<br>
- return error(Error, IRBlock.SourceRange);<br>
- }<br>
- auto *MBB = MF.CreateMachineBasicBlock(BB);<br>
- MF.insert(MF.end(), MBB);<br>
- bool WasInserted =<br>
- PFS.MBBSlots.insert(std::make_pair(YamlMBB.ID, MBB)).second;<br>
- if (!WasInserted)<br>
- return error(Twine("redefinition of machine basic block with id #") +<br>
- Twine(YamlMBB.ID));<br>
+ SMDiagnostic Error;<br>
+ if (parseMachineBasicBlockDefinitions(MF, YamlMF.Body.Value.Value, PFS,<br>
+ IRSlots, Error)) {<br>
+ reportDiagnostic(<br>
+ diagFromBlockStringDiag(Error, YamlMF.Body.Value.SourceRange));<br>
+ return true;<br>
}<br>
<br>
- if (YamlMF.BasicBlocks.empty())<br>
+ if (MF.empty())<br>
return error(Twine("machine function '") + Twine(MF.getName()) +<br>
"' requires at least one machine basic block in its body");<br>
// Initialize the frame information after creating all the MBBs so that the<br>
@@ -335,13 +307,13 @@ bool MIRParserImpl::initializeMachineFun<br>
if (!YamlMF.JumpTableInfo.Entries.empty() &&<br>
initializeJumpTableInfo(MF, YamlMF.JumpTableInfo, PFS))<br>
return true;<br>
- // Initialize the machine basic blocks after creating them all so that the<br>
- // machine instructions parser can resolve the MBB references.<br>
- unsigned I = 0;<br>
- for (const auto &YamlMBB : YamlMF.BasicBlocks) {<br>
- if (initializeMachineBasicBlock(MF, *MF.getBlockNumbered(I++), YamlMBB,<br>
- PFS))<br>
- return true;<br>
+ // Parse the machine instructions after creating all of the MBBs so that the<br>
+ // parser can resolve the MBB references.<br>
+ if (parseMachineInstructions(MF, YamlMF.Body.Value.Value, PFS, IRSlots,<br>
+ Error)) {<br>
+ reportDiagnostic(<br>
+ diagFromBlockStringDiag(Error, YamlMF.Body.Value.SourceRange));<br>
+ return true;<br>
}<br>
inferRegisterInfo(MF, YamlMF);<br>
// FIXME: This is a temporary workaround until the reserved registers can be<br>
@@ -351,53 +323,6 @@ bool MIRParserImpl::initializeMachineFun<br>
return false;<br>
}<br>
<br>
-bool MIRParserImpl::initializeMachineBasicBlock(<br>
- MachineFunction &MF, MachineBasicBlock &MBB,<br>
- const yaml::MachineBasicBlock &YamlMBB,<br>
- const PerFunctionMIParsingState &PFS) {<br>
- MBB.setAlignment(YamlMBB.Alignment);<br>
- if (YamlMBB.AddressTaken)<br>
- MBB.setHasAddressTaken();<br>
- MBB.setIsLandingPad(YamlMBB.IsLandingPad);<br>
- SMDiagnostic Error;<br>
- // Parse the successors.<br>
- const auto &Weights = YamlMBB.SuccessorWeights;<br>
- bool HasWeights = !Weights.empty();<br>
- if (HasWeights && Weights.size() != YamlMBB.Successors.size()) {<br>
- bool IsFew = Weights.size() < YamlMBB.Successors.size();<br>
- return error(IsFew ? Weights.back().SourceRange.End<br>
- : Weights[YamlMBB.Successors.size()].SourceRange.Start,<br>
- Twine("too ") + (IsFew ? "few" : "many") +<br>
- " successor weights, expected " +<br>
- Twine(YamlMBB.Successors.size()) + ", have " +<br>
- Twine(Weights.size()));<br>
- }<br>
- size_t SuccessorIndex = 0;<br>
- for (const auto &MBBSource : YamlMBB.Successors) {<br>
- MachineBasicBlock *SuccMBB = nullptr;<br>
- if (parseMBBReference(SuccMBB, MBBSource, MF, PFS))<br>
- return true;<br>
- // TODO: Report an error when adding the same successor more than once.<br>
- MBB.addSuccessor(SuccMBB, HasWeights ? Weights[SuccessorIndex++].Value : 0);<br>
- }<br>
- // Parse the liveins.<br>
- for (const auto &LiveInSource : YamlMBB.LiveIns) {<br>
- unsigned Reg = 0;<br>
- if (parseNamedRegisterReference(Reg, SM, MF, LiveInSource.Value, PFS,<br>
- IRSlots, Error))<br>
- return error(Error, LiveInSource.SourceRange);<br>
- MBB.addLiveIn(Reg);<br>
- }<br>
- // Parse the instructions.<br>
- for (const auto &MISource : YamlMBB.Instructions) {<br>
- MachineInstr *MI = nullptr;<br>
- if (parseMachineInstr(MI, SM, MF, MISource.Value, PFS, IRSlots, Error))<br>
- return error(Error, MISource.SourceRange);<br>
- MBB.insert(MBB.end(), MI);<br>
- }<br>
- return false;<br>
-}<br>
-<br>
bool MIRParserImpl::initializeRegisterInfo(MachineFunction &MF,<br>
const yaml::MachineFunction &YamlMF,<br>
PerFunctionMIParsingState &PFS) {<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Thu Aug 13 18:10:16 2015<br>
@@ -83,8 +83,6 @@ public:<br>
const MachineConstantPool &ConstantPool);<br>
void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,<br>
const MachineJumpTableInfo &JTI);<br>
- void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,<br>
- const MachineBasicBlock &MBB);<br>
void convertStackObjects(yaml::MachineFunction &MF,<br>
const MachineFrameInfo &MFI,<br>
const TargetRegisterInfo *TRI);<br>
@@ -93,10 +91,6 @@ private:<br>
void initRegisterMaskIds(const MachineFunction &MF);<br>
};<br>
<br>
-} // end namespace llvm<br>
-<br>
-namespace {<br>
-<br>
/// This class prints out the machine instructions using the MIR serialization<br>
/// format.<br>
class MIPrinter {<br>
@@ -112,6 +106,8 @@ public:<br>
: OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),<br>
StackObjectOperandMapping(StackObjectOperandMapping) {}<br>
<br>
+ void print(const MachineBasicBlock &MBB);<br>
+<br>
void print(const MachineInstr &MI);<br>
void printMBBReference(const MachineBasicBlock &MBB);<br>
void printIRBlockReference(const BasicBlock &BB);<br>
@@ -125,7 +121,7 @@ public:<br>
void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);<br>
};<br>
<br>
-} // end anonymous namespace<br>
+} // end namespace llvm<br>
<br>
namespace llvm {<br>
namespace yaml {<br>
@@ -181,11 +177,16 @@ void MIRPrinter::print(const MachineFunc<br>
convert(YamlMF, *ConstantPool);<br>
if (const auto *JumpTableInfo = MF.getJumpTableInfo())<br>
convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);<br>
+ raw_string_ostream StrOS(YamlMF.Body.Value.Value);<br>
+ bool IsNewlineNeeded = false;<br>
for (const auto &MBB : MF) {<br>
- yaml::MachineBasicBlock YamlMBB;<br>
- convert(MST, YamlMBB, MBB);<br>
- YamlMF.BasicBlocks.push_back(YamlMBB);<br>
+ if (IsNewlineNeeded)<br>
+ StrOS << "\n";<br>
+ MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)<br>
+ .print(MBB);<br>
+ IsNewlineNeeded = true;<br>
}<br>
+ StrOS.flush();<br>
yaml::Output Out(OS);<br>
Out << YamlMF;<br>
}<br>
@@ -364,64 +365,87 @@ void MIRPrinter::convert(ModuleSlotTrack<br>
}<br>
}<br>
<br>
-void MIRPrinter::convert(ModuleSlotTracker &MST,<br>
- yaml::MachineBasicBlock &YamlMBB,<br>
- const MachineBasicBlock &MBB) {<br>
+void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {<br>
+ const auto *TRI = MF.getSubtarget().getRegisterInfo();<br>
+ unsigned I = 0;<br>
+ for (const uint32_t *Mask : TRI->getRegMasks())<br>
+ RegisterMaskIds.insert(std::make_pair(Mask, I++));<br>
+}<br>
+<br>
+void MIPrinter::print(const MachineBasicBlock &MBB) {<br>
assert(MBB.getNumber() >= 0 && "Invalid MBB number");<br>
- YamlMBB.ID = (unsigned)MBB.getNumber();<br>
+ OS << "bb." << MBB.getNumber();<br>
+ bool HasAttributes = false;<br>
if (const auto *BB = MBB.getBasicBlock()) {<br>
if (BB->hasName()) {<br>
- YamlMBB.Name.Value = BB->getName();<br>
+ OS << "." << BB->getName();<br>
} else {<br>
+ HasAttributes = true;<br>
+ OS << " (";<br>
int Slot = MST.getLocalSlot(BB);<br>
if (Slot == -1)<br>
- YamlMBB.IRBlock.Value = "<badref>";<br>
+ OS << "<ir-block badref>";<br>
else<br>
- YamlMBB.IRBlock.Value = (Twine("%ir-block.") + Twine(Slot)).str();<br>
+ OS << (Twine("%ir-block.") + Twine(Slot)).str();<br>
}<br>
}<br>
- YamlMBB.Alignment = MBB.getAlignment();<br>
- YamlMBB.AddressTaken = MBB.hasAddressTaken();<br>
- YamlMBB.IsLandingPad = MBB.isLandingPad();<br>
- for (const auto *SuccMBB : MBB.successors()) {<br>
- std::string Str;<br>
- raw_string_ostream StrOS(Str);<br>
- MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)<br>
- .printMBBReference(*SuccMBB);<br>
- YamlMBB.Successors.push_back(StrOS.str());<br>
- }<br>
- if (MBB.hasSuccessorWeights()) {<br>
- for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I)<br>
- YamlMBB.SuccessorWeights.push_back(<br>
- yaml::UnsignedValue(MBB.getSuccWeight(I)));<br>
+ if (MBB.hasAddressTaken()) {<br>
+ OS << (HasAttributes ? ", " : " (");<br>
+ OS << "address-taken";<br>
+ HasAttributes = true;<br>
+ }<br>
+ if (MBB.isLandingPad()) {<br>
+ OS << (HasAttributes ? ", " : " (");<br>
+ OS << "landing-pad";<br>
+ HasAttributes = true;<br>
+ }<br>
+ if (MBB.getAlignment()) {<br>
+ OS << (HasAttributes ? ", " : " (");<br>
+ OS << "align " << MBB.getAlignment();<br>
+ HasAttributes = true;<br>
+ }<br>
+ if (HasAttributes)<br>
+ OS << ")";<br>
+ OS << ":\n";<br>
+<br>
+ bool HasLineAttributes = false;<br>
+ // Print the successors<br>
+ if (!MBB.succ_empty()) {<br>
+ OS.indent(2) << "successors: ";<br>
+ for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {<br>
+ if (I != MBB.succ_begin())<br>
+ OS << ", ";<br>
+ printMBBReference(**I);<br>
+ if (MBB.hasSuccessorWeights())<br>
+ OS << '(' << MBB.getSuccWeight(I) << ')';<br>
+ }<br>
+ OS << "\n";<br>
+ HasLineAttributes = true;<br>
}<br>
+<br>
// Print the live in registers.<br>
const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();<br>
assert(TRI && "Expected target register info");<br>
- for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {<br>
- std::string Str;<br>
- raw_string_ostream StrOS(Str);<br>
- printReg(*I, StrOS, TRI);<br>
- YamlMBB.LiveIns.push_back(StrOS.str());<br>
+ if (!MBB.livein_empty()) {<br>
+ OS.indent(2) << "liveins: ";<br>
+ for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {<br>
+ if (I != MBB.livein_begin())<br>
+ OS << ", ";<br>
+ printReg(*I, OS, TRI);<br>
+ }<br>
+ OS << "\n";<br>
+ HasLineAttributes = true;<br>
}<br>
- // Print the machine instructions.<br>
- YamlMBB.Instructions.reserve(MBB.size());<br>
- std::string Str;<br>
+<br>
+ if (HasLineAttributes)<br>
+ OS << "\n";<br>
for (const auto &MI : MBB) {<br>
- raw_string_ostream StrOS(Str);<br>
- MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping).print(MI);<br>
- YamlMBB.Instructions.push_back(StrOS.str());<br>
- Str.clear();<br>
+ OS.indent(2);<br>
+ print(MI);<br>
+ OS << "\n";<br>
}<br>
}<br>
<br>
-void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {<br>
- const auto *TRI = MF.getSubtarget().getRegisterInfo();<br>
- unsigned I = 0;<br>
- for (const uint32_t *Mask : TRI->getRegMasks())<br>
- RegisterMaskIds.insert(std::make_pair(Mask, I++));<br>
-}<br>
-<br>
void MIPrinter::print(const MachineInstr &MI) {<br>
const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();<br>
const auto *TRI = SubTarget.getRegisterInfo();<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir Thu Aug 13 18:10:16 2015<br>
@@ -15,18 +15,17 @@<br>
...<br>
---<br>
name: trivial_fp_func<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%lr', '%fp', '%lr', '%fp' ]<br>
- instructions:<br>
- - '%sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2'<br>
- - '%fp = frame-setup ADDXri %sp, 0, 0'<br>
- # CHECK: CFI_INSTRUCTION .cfi_def_cfa %w29, 16<br>
- - 'frame-setup CFI_INSTRUCTION .cfi_def_cfa %w29, 16'<br>
- - 'frame-setup CFI_INSTRUCTION .cfi_offset %w30, -8'<br>
- - 'frame-setup CFI_INSTRUCTION .cfi_offset %w29, -16'<br>
- - 'BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp'<br>
- - '%sp, %fp, %lr = LDPXpost %sp, 2'<br>
- - RET_ReallyLR<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %lr, %fp, %lr, %fp<br>
+<br>
+ %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2<br>
+ %fp = frame-setup ADDXri %sp, 0, 0<br>
+ ; CHECK: CFI_INSTRUCTION .cfi_def_cfa %w29, 16<br>
+ frame-setup CFI_INSTRUCTION .cfi_def_cfa %w29, 16<br>
+ frame-setup CFI_INSTRUCTION .cfi_offset %w30, -8<br>
+ frame-setup CFI_INSTRUCTION .cfi_offset %w29, -16<br>
+ BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp<br>
+ %sp, %fp, %lr = LDPXpost %sp, 2<br>
+ RET_ReallyLR<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -15,15 +15,14 @@<br>
...<br>
---<br>
name: trivial_fp_func<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%lr', '%fp', '%lr', '%fp' ]<br>
- instructions:<br>
- - '%sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2'<br>
- - '%fp = frame-setup ADDXri %sp, 0, 0'<br>
- - 'BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp'<br>
-# CHECK: %sp, %fp, %lr = LDPXpost %sp, 2<br>
- - '%sp, %fp, %lr = LDPXpost %sp, 2'<br>
- - RET_ReallyLR<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %lr, %fp, %lr, %fp<br>
+<br>
+ %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2<br>
+ %fp = frame-setup ADDXri %sp, 0, 0<br>
+ BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp<br>
+ ; CHECK: %sp, %fp, %lr = LDPXpost %sp, 2<br>
+ %sp, %fp, %lr = LDPXpost %sp, 2<br>
+ RET_ReallyLR<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir Thu Aug 13 18:10:16 2015<br>
@@ -38,28 +38,27 @@ liveins:<br>
- { reg: '%sgpr0_sgpr1' }<br>
frameInfo:<br>
maxAlignment: 8<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%sgpr0_sgpr1' ]<br>
- instructions:<br>
- - '%sgpr2_sgpr3 = S_GETPC_B64'<br>
-# CHECK: [[@LINE+1]]:50: expected the name of the target index<br>
- - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc'<br>
- - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'<br>
- - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'<br>
- - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'<br>
- - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'<br>
- - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'<br>
- - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'<br>
- - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'<br>
- - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'<br>
- - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'<br>
- - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'<br>
- - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'<br>
- - '%sgpr7 = S_MOV_B32 61440'<br>
- - '%sgpr6 = S_MOV_B32 -1'<br>
- - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'<br>
- - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'<br>
- - S_ENDPGM<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %sgpr0_sgpr1<br>
+<br>
+ %sgpr2_sgpr3 = S_GETPC_B64<br>
+ ; CHECK: [[@LINE+1]]:45: expected the name of the target index<br>
+ %sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc<br>
+ %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc<br>
+ %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc<br>
+ %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11<br>
+ %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc<br>
+ %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc<br>
+ %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc<br>
+ %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc<br>
+ %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc<br>
+ %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc<br>
+ %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0<br>
+ %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9<br>
+ %sgpr7 = S_MOV_B32 61440<br>
+ %sgpr6 = S_MOV_B32 -1<br>
+ %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec<br>
+ BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec<br>
+ S_ENDPGM<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -38,28 +38,27 @@ liveins:<br>
- { reg: '%sgpr0_sgpr1' }<br>
frameInfo:<br>
maxAlignment: 8<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%sgpr0_sgpr1' ]<br>
- instructions:<br>
- - '%sgpr2_sgpr3 = S_GETPC_B64'<br>
-# CHECK: [[@LINE+1]]:50: use of undefined target index 'constdata-start'<br>
- - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc'<br>
- - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'<br>
- - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'<br>
- - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'<br>
- - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'<br>
- - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'<br>
- - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'<br>
- - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'<br>
- - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'<br>
- - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'<br>
- - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'<br>
- - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'<br>
- - '%sgpr7 = S_MOV_B32 61440'<br>
- - '%sgpr6 = S_MOV_B32 -1'<br>
- - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'<br>
- - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'<br>
- - S_ENDPGM<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %sgpr0_sgpr1<br>
+<br>
+ %sgpr2_sgpr3 = S_GETPC_B64<br>
+ ; CHECK: [[@LINE+1]]:45: use of undefined target index 'constdata-start'<br>
+ %sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc<br>
+ %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc<br>
+ %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc<br>
+ %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11<br>
+ %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc<br>
+ %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc<br>
+ %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc<br>
+ %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc<br>
+ %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc<br>
+ %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc<br>
+ %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0<br>
+ %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9<br>
+ %sgpr7 = S_MOV_B32 61440<br>
+ %sgpr6 = S_MOV_B32 -1<br>
+ %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec<br>
+ BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec<br>
+ S_ENDPGM<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -47,30 +47,29 @@ liveins:<br>
- { reg: '%sgpr0_sgpr1' }<br>
frameInfo:<br>
maxAlignment: 8<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%sgpr0_sgpr1' ]<br>
- instructions:<br>
- - '%sgpr2_sgpr3 = S_GETPC_B64'<br>
-# CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc<br>
- - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc'<br>
- - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'<br>
- - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'<br>
- - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'<br>
- - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'<br>
- - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'<br>
- - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'<br>
- - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'<br>
- - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'<br>
- - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'<br>
- - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'<br>
- - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'<br>
- - '%sgpr7 = S_MOV_B32 61440'<br>
- - '%sgpr6 = S_MOV_B32 -1'<br>
- - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'<br>
- - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'<br>
- - S_ENDPGM<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %sgpr0_sgpr1<br>
+<br>
+ %sgpr2_sgpr3 = S_GETPC_B64<br>
+ ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc<br>
+ %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc<br>
+ %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc<br>
+ %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc<br>
+ %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11<br>
+ %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc<br>
+ %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc<br>
+ %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc<br>
+ %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc<br>
+ %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc<br>
+ %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc<br>
+ %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0<br>
+ %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9<br>
+ %sgpr7 = S_MOV_B32 61440<br>
+ %sgpr6 = S_MOV_B32 -1<br>
+ %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec<br>
+ BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec<br>
+ S_ENDPGM<br>
...<br>
---<br>
name: float2<br>
@@ -79,28 +78,27 @@ liveins:<br>
- { reg: '%sgpr0_sgpr1' }<br>
frameInfo:<br>
maxAlignment: 8<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%sgpr0_sgpr1' ]<br>
- instructions:<br>
- - '%sgpr2_sgpr3 = S_GETPC_B64'<br>
-# CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc<br>
- - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc'<br>
- - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'<br>
- - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'<br>
- - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'<br>
- - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'<br>
- - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'<br>
- - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'<br>
- - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'<br>
- - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'<br>
- - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'<br>
- - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'<br>
- - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'<br>
- - '%sgpr7 = S_MOV_B32 61440'<br>
- - '%sgpr6 = S_MOV_B32 -1'<br>
- - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'<br>
- - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'<br>
- - S_ENDPGM<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %sgpr0_sgpr1<br>
+<br>
+ %sgpr2_sgpr3 = S_GETPC_B64<br>
+ ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc<br>
+ %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc<br>
+ %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc<br>
+ %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc<br>
+ %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11<br>
+ %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc<br>
+ %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc<br>
+ %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc<br>
+ %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc<br>
+ %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc<br>
+ %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc<br>
+ %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0<br>
+ %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9<br>
+ %sgpr7 = S_MOV_B32 61440<br>
+ %sgpr6 = S_MOV_B32 -1<br>
+ %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec<br>
+ BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec<br>
+ S_ENDPGM<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/basic-blocks.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/basic-blocks.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/basic-blocks.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/basic-blocks.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/basic-blocks.mir Thu Aug 13 18:10:16 2015<br>
@@ -13,37 +13,37 @@<br>
ret i32 0<br>
}<br>
<br>
+ define i32 @test() {<br>
+ start:<br>
+ ret i32 0<br>
+ }<br>
+<br>
...<br>
---<br>
-# CHECK: name: foo<br>
+# CHECK-LABEL: name: foo<br>
# CHECK: body:<br>
-# CHECK-NEXT: - id: 0<br>
-# CHECK-NEXT: name: entry<br>
-# CHECK-NEXT: alignment: 0<br>
-# CHECK-NEXT: isLandingPad: false<br>
-# CHECK-NEXT: addressTaken: false<br>
+# CHECK-NEXT: bb.0.entry:<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
+body: |<br>
+ bb.0.entry:<br>
...<br>
---<br>
-# CHECK: name: bar<br>
+# CHECK-LABEL: name: bar<br>
# CHECK: body:<br>
-# CHECK-NEXT: - id: 0<br>
-# CHECK-NEXT: name: start<br>
-# CHECK-NEXT: alignment: 4<br>
-# CHECK-NEXT: isLandingPad: false<br>
-# CHECK-NEXT: addressTaken: false<br>
-# CHECK-NEXT: - id: 1<br>
-# CHECK-NEXT: alignment: 0<br>
-# CHECK-NEXT: isLandingPad: false<br>
-# CHECK-NEXT: addressTaken: true<br>
+# CHECK-NEXT: bb.0.start (align 4):<br>
+# CHECK: bb.1 (address-taken):<br>
name: bar<br>
-body:<br>
- - id: 0<br>
- name: start<br>
- alignment: 4<br>
- - id: 1<br>
- addressTaken: true<br>
+body: |<br>
+ bb.0.start (align 4):<br>
+ bb.1 (address-taken):<br>
+...<br>
+---<br>
+# CHECK-LABEL: name: test<br>
+# CHECK: body:<br>
+# CHECK-NEXT: bb.0.start (address-taken, align 4):<br>
+# CHECK: bb.1 (address-taken, align 4):<br>
+name: test<br>
+body: |<br>
+ bb.0.start (align 4, address-taken):<br>
+ bb.1 (address-taken, align 4):<br>
...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir?rev=244982&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir?rev=244982&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir Thu Aug 13 18:10:16 2015<br>
@@ -0,0 +1,16 @@<br>
+# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
+<br>
+--- |<br>
+<br>
+ define i32 @foo() {<br>
+ entry:<br>
+ ret i32 0<br>
+ }<br>
+<br>
+...<br>
+---<br>
+name: foo<br>
+body: |<br>
+ ; CHECK: [[@LINE+1]]:13: expected ':'<br>
+ bb.0.entry<br>
+...<br>
<br>
Removed: llvm/trunk/test/CodeGen/MIR/Generic/expected-eof-after-successor-mbb.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/expected-eof-after-successor-mbb.mir?rev=244981&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/expected-eof-after-successor-mbb.mir?rev=244981&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/expected-eof-after-successor-mbb.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/expected-eof-after-successor-mbb.mir (removed)<br>
@@ -1,29 +0,0 @@<br>
-# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
-<br>
---- |<br>
-<br>
- define i32 @foo(i32 %a) {<br>
- entry:<br>
- %0 = icmp sle i32 %a, 10<br>
- br i1 %0, label %less, label %exit<br>
-<br>
- less:<br>
- ret i32 0<br>
-<br>
- exit:<br>
- ret i32 %a<br>
- }<br>
-<br>
-...<br>
----<br>
-name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- # CHECK: [[@LINE+1]]:46: expected end of string after the machine basic block reference<br>
- successors: [ '%bb.1.less', '%bb.2.exit 2' ]<br>
- - id: 1<br>
- name: less<br>
- - id: 2<br>
- name: exit<br>
-...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,13 +17,12 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- # CHECK: [[@LINE+1]]:35: expected a machine basic block reference<br>
- successors: [ '%bb.1.less', '2' ]<br>
- - id: 1<br>
- name: less<br>
- - id: 2<br>
- name: exit<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:29: expected a machine basic block reference<br>
+ successors: %bb.1.less, 2<br>
+<br>
+ bb.1.less:<br>
+<br>
+ bb.2.exit:<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir Thu Aug 13 18:10:16 2015<br>
@@ -44,9 +44,8 @@ tracksRegLiveness: true<br>
# CHECK: body<br>
frameInfo:<br>
maxAlignment: 4<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
+body: |<br>
+ bb.0.entry:<br>
...<br>
---<br>
name: test2<br>
@@ -84,8 +83,7 @@ frameInfo:<br>
hasOpaqueSPAdjustment: true<br>
hasVAStart: true<br>
hasMustTailInVarArgFunc: true<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
+body: |<br>
+ bb.0.entry:<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir Thu Aug 13 18:10:16 2015<br>
@@ -36,19 +36,18 @@ jumpTable:<br>
entries:<br>
- id: 0<br>
blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- - id: 1<br>
- name: entry<br>
- - id: 2<br>
- name: def<br>
- - id: 3<br>
- name: lbl1<br>
- - id: 4<br>
- name: lbl2<br>
- - id: 5<br>
- name: lbl3<br>
- - id: 6<br>
- name: lbl4<br>
+body: |<br>
+ bb.0.entry:<br>
+<br>
+ bb.1.entry:<br>
+<br>
+ bb.2.def:<br>
+<br>
+ bb.3.lbl1:<br>
+<br>
+ bb.4.lbl2:<br>
+<br>
+ bb.5.lbl3:<br>
+<br>
+ bb.6.lbl4:<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/llvmIR.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/llvmIR.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/llvmIR.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/llvmIR.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/llvmIR.mir Thu Aug 13 18:10:16 2015<br>
@@ -32,6 +32,6 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
+body: |<br>
+ bb.0:<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/llvmIRMissing.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/llvmIRMissing.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/llvmIRMissing.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/llvmIRMissing.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/llvmIRMissing.mir Thu Aug 13 18:10:16 2015<br>
@@ -4,6 +4,6 @@<br>
---<br>
# CHECK: name: foo<br>
name: foo<br>
-body:<br>
- - id: 0<br>
+body: |<br>
+ bb.0:<br>
...<br>
<br>
Removed: llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-expected-ir-block.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-expected-ir-block.mir?rev=244981&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-expected-ir-block.mir?rev=244981&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-expected-ir-block.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-expected-ir-block.mir (removed)<br>
@@ -1,16 +0,0 @@<br>
-# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
-<br>
---- |<br>
-<br>
- define i32 @foo() {<br>
- ret i32 0<br>
- }<br>
-<br>
-...<br>
----<br>
-name: foo<br>
-body:<br>
- - id: 0<br>
-# CHECK: [[@LINE+1]]:19: expected an IR block reference<br>
- ir-block: '0'<br>
-...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir Thu Aug 13 18:10:16 2015<br>
@@ -11,9 +11,7 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
-# CHECK: id: 0<br>
-# CHECK: ir-block: '%ir-block.0'<br>
- - id: 0<br>
- ir-block: '%ir-block.0'<br>
+body: |<br>
+ ; CHECK: bb.0 (%ir-block.0):<br>
+ bb.0 (%ir-block.0):<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -10,8 +10,9 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- # CHECK: redefinition of machine basic block with id #0<br>
- - id: 0<br>
- - id: 0<br>
+body: |<br>
+ ; CHECK: [[@LINE+3]]:3: redefinition of machine basic block with id #0<br>
+ bb.0:<br>
+<br>
+ bb.0:<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir Thu Aug 13 18:10:16 2015<br>
@@ -9,8 +9,7 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
-# CHECK: [[@LINE+1]]:19: use of undefined IR block '%ir-block.10'<br>
- ir-block: '%ir-block.10'<br>
+body: |<br>
+ ; CHECK: [[@LINE+1]]:9: use of undefined IR block '%ir-block.10'<br>
+ bb.0 (%ir-block.10):<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir Thu Aug 13 18:10:16 2015<br>
@@ -12,8 +12,7 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- # CHECK: [[@LINE+2]]:18: basic block 'entrie' is not defined in the function 'foo'<br>
- - id: 0<br>
- name: entrie<br>
+body: |<br>
+ ; CHECK: [[@LINE+1]]:3: basic block 'entrie' is not defined in the function 'foo'<br>
+ bb.0.entrie:<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/machine-function-missing-function.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-function-missing-function.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-function-missing-function.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/machine-function-missing-function.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/machine-function-missing-function.mir Thu Aug 13 18:10:16 2015<br>
@@ -12,12 +12,12 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
+body: |<br>
+ bb.0:<br>
...<br>
---<br>
# CHECK: function 'faa' isn't defined in the provided LLVM IR<br>
name: faa<br>
-body:<br>
- - id: 0<br>
+body: |<br>
+ bb.0:<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/machine-function-missing-name.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-function-missing-name.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-function-missing-name.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/machine-function-missing-name.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/machine-function-missing-name.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,11 +16,11 @@<br>
---<br>
# CHECK: [[@LINE+1]]:1: missing required key 'name'<br>
nme: foo<br>
-body:<br>
- - id: 0<br>
+body: |<br>
+ bb.0:<br>
...<br>
---<br>
name: bar<br>
-body:<br>
- - id: 0<br>
+body: |<br>
+ bb.0:<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/machine-function.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-function.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-function.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/machine-function.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/machine-function.mir Thu Aug 13 18:10:16 2015<br>
@@ -27,8 +27,8 @@<br>
# CHECK-NEXT: hasInlineAsm: false<br>
# CHECK: ...<br>
name: foo<br>
-body:<br>
- - id: 0<br>
+body: |<br>
+ bb.0:<br>
...<br>
---<br>
# CHECK: name: bar<br>
@@ -37,8 +37,8 @@ body:<br>
# CHECK-NEXT: hasInlineAsm: false<br>
# CHECK: ...<br>
name: bar<br>
-body:<br>
- - id: 0<br>
+body: |<br>
+ bb.0:<br>
...<br>
---<br>
# CHECK: name: func<br>
@@ -48,8 +48,8 @@ body:<br>
# CHECK: ...<br>
name: func<br>
alignment: 8<br>
-body:<br>
- - id: 0<br>
+body: |<br>
+ bb.0:<br>
...<br>
---<br>
# CHECK: name: func2<br>
@@ -61,6 +61,6 @@ name: func2<br>
alignment: 16<br>
exposesReturnsTwice: true<br>
hasInlineAsm: true<br>
-body:<br>
- - id: 0<br>
+body: |<br>
+ bb.0:<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir Thu Aug 13 18:10:16 2015<br>
@@ -22,8 +22,8 @@<br>
# CHECK-NEXT: tracksSubRegLiveness: false<br>
# CHECK: ...<br>
name: foo<br>
-body:<br>
- - id: 0<br>
+body: |<br>
+ bb.0:<br>
...<br>
---<br>
# CHECK: name: bar<br>
@@ -35,6 +35,6 @@ name: bar<br>
isSSA: false<br>
tracksRegLiveness: true<br>
tracksSubRegLiveness: true<br>
-body:<br>
- - id: 0<br>
+body: |<br>
+ bb.0:<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@ name: test<br>
registers:<br>
- { id: 0, class: float32regs }<br>
- { id: 1, class: float32regs }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'<br>
-# CHECK: [[@LINE+1]]:38: expected a floating point literal<br>
- - '%1 = FADD_rnf32ri %0, float 3'<br>
- - 'StoreRetvalF32 %1, 0'<br>
- - Return<br>
+body: |<br>
+ bb.0.entry:<br>
+ %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0<br>
+ ; CHECK: [[@LINE+1]]:33: expected a floating point literal<br>
+ %1 = FADD_rnf32ri %0, float 3<br>
+ StoreRetvalF32 %1, 0<br>
+ Return<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -38,22 +38,20 @@ registers:<br>
- { id: 5, class: float32regs }<br>
- { id: 6, class: float32regs }<br>
- { id: 7, class: float32regs }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'<br>
- - '%1 = CVT_f64_f32 %0, 0'<br>
- - '%2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1'<br>
-# CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00<br>
- - '%3 = FADD_rnf64ri %1, double 3.250000e+00'<br>
- - '%4 = CVT_f32_f64 %3, 5'<br>
- - '%5 = CVT_f32_s32 %2, 5'<br>
-# CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00<br>
- - '%6 = FADD_rnf32ri %5, float 6.250000e+00'<br>
- - '%7 = FMUL_rnf32rr %6, %4'<br>
- - 'StoreRetvalF32 %7, 0'<br>
- - Return<br>
+body: |<br>
+ bb.0.entry:<br>
+ %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0<br>
+ %1 = CVT_f64_f32 %0, 0<br>
+ %2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1<br>
+ ; CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00<br>
+ %3 = FADD_rnf64ri %1, double 3.250000e+00<br>
+ %4 = CVT_f32_f64 %3, 5<br>
+ %5 = CVT_f32_s32 %2, 5<br>
+ ; CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00<br>
+ %6 = FADD_rnf32ri %5, float 6.250000e+00<br>
+ %7 = FMUL_rnf32rr %6, %4<br>
+ StoreRetvalF32 %7, 0<br>
+ Return<br>
...<br>
---<br>
name: test2<br>
@@ -66,20 +64,18 @@ registers:<br>
- { id: 5, class: float32regs }<br>
- { id: 6, class: float32regs }<br>
- { id: 7, class: float32regs }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0'<br>
- - '%1 = CVT_f64_f32 %0, 0'<br>
- - '%2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1'<br>
-# CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000<br>
- - '%3 = FADD_rnf64ri %1, double 0x7FF8000000000000'<br>
- - '%4 = CVT_f32_f64 %3, 5'<br>
- - '%5 = CVT_f32_s32 %2, 5'<br>
-# CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000<br>
- - '%6 = FADD_rnf32ri %5, float 0x7FF8000000000000'<br>
- - '%7 = FMUL_rnf32rr %6, %4'<br>
- - 'StoreRetvalF32 %7, 0'<br>
- - Return<br>
+body: |<br>
+ bb.0.entry:<br>
+ %0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0<br>
+ %1 = CVT_f64_f32 %0, 0<br>
+ %2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1<br>
+ ; CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000<br>
+ %3 = FADD_rnf64ri %1, double 0x7FF8000000000000<br>
+ %4 = CVT_f32_f64 %3, 5<br>
+ %5 = CVT_f32_s32 %2, 5<br>
+ ; CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000<br>
+ %6 = FADD_rnf32ri %5, float 0x7FF8000000000000<br>
+ %7 = FMUL_rnf32rr %6, %4<br>
+ StoreRetvalF32 %7, 0<br>
+ Return<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@ name: test<br>
registers:<br>
- { id: 0, class: float32regs }<br>
- { id: 1, class: float32regs }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'<br>
-# CHECK: [[@LINE+1]]:38: floating point constant does not have type 'float'<br>
- - '%1 = FADD_rnf32ri %0, float 0xH3C00'<br>
- - 'StoreRetvalF32 %1, 0'<br>
- - Return<br>
+body: |<br>
+ bb.0.entry:<br>
+ %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0<br>
+ ; CHECK: [[@LINE+1]]:33: floating point constant does not have type 'float'<br>
+ %1 = FADD_rnf32ri %0, float 0xH3C00<br>
+ StoreRetvalF32 %1, 0<br>
+ Return<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir Thu Aug 13 18:10:16 2015<br>
@@ -9,17 +9,54 @@<br>
ret i32 %c<br>
}<br>
<br>
+ define i32 @test2(i32 %a, i32 %b) {<br>
+ body:<br>
+ %c = add i32 %a, %b<br>
+ ret i32 %c<br>
+ }<br>
+<br>
+ define i32 @test3() {<br>
+ body:<br>
+ ret i32 0<br>
+ }<br>
+<br>
...<br>
---<br>
name: test<br>
-body:<br>
- # CHECK: name: body<br>
- # CHECK: liveins: [ '%edi', '%esi' ]<br>
- # CHECK-NEXT: instructions:<br>
- - id: 0<br>
- name: body<br>
- liveins: [ '%edi', '%esi' ]<br>
- instructions:<br>
- - '%eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ ; CHECK-LABEL: bb.0.body:<br>
+ ; CHECK-NEXT: liveins: %edi, %esi<br>
+ bb.0.body:<br>
+ liveins: %edi, %esi<br>
+<br>
+ %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _<br>
+ RETQ %eax<br>
+...<br>
+---<br>
+name: test2<br>
+body: |<br>
+ ; CHECK-LABEL: name: test2<br>
+ ; Verify that we can have multiple lists of liveins that will be merged into<br>
+ ; one.<br>
+ ; CHECK: bb.0.body:<br>
+ ; CHECK-NEXT: liveins: %edi, %esi<br>
+ bb.0.body:<br>
+ liveins: %edi<br>
+ liveins: %esi<br>
+<br>
+ %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _<br>
+ RETQ %eax<br>
+...<br>
+---<br>
+name: test3<br>
+body: |<br>
+ ; Verify that we can have an empty list of liveins.<br>
+ ; CHECK-LABEL: name: test3<br>
+ ; CHECK: bb.0.body:<br>
+ ; CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags<br>
+ bb.0.body:<br>
+ liveins:<br>
+<br>
+ %eax = MOV32r0 implicit-def dead %eflags<br>
+ RETQ killed %eax<br>
...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir?rev=244982&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir?rev=244982&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -0,0 +1,41 @@<br>
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
+<br>
+--- |<br>
+<br>
+ define i32 @foo(i32 %a) {<br>
+ entry:<br>
+ %0 = icmp sle i32 %a, 10<br>
+ br i1 %0, label %less, label %exit<br>
+<br>
+ less: ; preds = %entry<br>
+ ret i32 0<br>
+<br>
+ exit: ; preds = %entry<br>
+ ret i32 %a<br>
+ }<br>
+<br>
+...<br>
+---<br>
+name: foo<br>
+tracksRegLiveness: true<br>
+liveins:<br>
+ - { reg: '%edi' }<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.less, %bb.2.exit<br>
+ liveins: %edi 44<br>
+<br>
+ CMP32ri8 %edi, 10, implicit-def %eflags<br>
+ JG_1 %bb.2.exit, implicit killed %eflags<br>
+<br>
+ ; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line<br>
+ less bb.1:<br>
+ %eax = MOV32r0 implicit-def dead %eflags<br>
+ RETQ killed %eax<br>
+<br>
+ bb.2.exit:<br>
+ liveins: %edi<br>
+<br>
+ %eax = COPY killed %edi<br>
+ RETQ killed %eax<br>
+...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/block-address-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/block-address-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/block-address-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/block-address-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/block-address-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -54,84 +54,68 @@<br>
...<br>
---<br>
name: test<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.block' ]<br>
- instructions:<br>
- # CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _<br>
- - '%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _'<br>
- - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'<br>
- - 'JMP64m %rip, 1, _, @addr, _'<br>
- - id: 1<br>
- name: block<br>
- addressTaken: true<br>
- instructions:<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.block<br>
+ ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _<br>
+ %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _<br>
+ MOV64mr %rip, 1, _, @addr, _, killed %rax<br>
+ JMP64m %rip, 1, _, @addr, _<br>
+<br>
+ bb.1.block (address-taken):<br>
+ RETQ<br>
...<br>
---<br>
name: test2<br>
tracksRegLiveness: true<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1' ]<br>
- instructions:<br>
- # CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _<br>
- - '%rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _'<br>
- - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'<br>
- - 'JMP64m %rip, 1, _, @addr, _'<br>
- - id: 1<br>
- addressTaken: true<br>
- instructions:<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1<br>
+ ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _<br>
+ %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _<br>
+ MOV64mr %rip, 1, _, @addr, _, killed %rax<br>
+ JMP64m %rip, 1, _, @addr, _<br>
+<br>
+ bb.1 (address-taken):<br>
+ RETQ<br>
...<br>
---<br>
name: slot_in_other_function<br>
tracksRegLiveness: true<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: name: slot_in_other_function<br>
-# CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _<br>
- - '%rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _'<br>
- - 'MOV64mr killed %rdi, 1, _, 0, _, killed %rax'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK-LABEL: name: slot_in_other_function<br>
+ ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _<br>
+ %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _<br>
+ MOV64mr killed %rdi, 1, _, 0, _, killed %rax<br>
+ RETQ<br>
...<br>
---<br>
name: test3<br>
tracksRegLiveness: true<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1' ]<br>
- instructions:<br>
-# CHECK: name: test3<br>
-# CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _<br>
- - '%rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _'<br>
- - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'<br>
- - 'JMP64m %rip, 1, _, @addr, _'<br>
- - id: 1<br>
- addressTaken: true<br>
- instructions:<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1<br>
+ ; CHECK-LABEL: name: test3<br>
+ ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _<br>
+ %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _<br>
+ MOV64mr %rip, 1, _, @addr, _, killed %rax<br>
+ JMP64m %rip, 1, _, @addr, _<br>
+<br>
+ bb.1 (address-taken):<br>
+ RETQ<br>
...<br>
---<br>
name: test4<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.block' ]<br>
- instructions:<br>
- # CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _<br>
- - '%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _'<br>
- - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'<br>
- - 'JMP64m %rip, 1, _, @addr, _'<br>
- - id: 1<br>
- name: block<br>
- addressTaken: true<br>
- instructions:<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.block<br>
+ ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _<br>
+ %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _<br>
+ MOV64mr %rip, 1, _, @addr, _, killed %rax<br>
+ JMP64m %rip, 1, _, @addr, _<br>
+<br>
+ bb.1.block (address-taken):<br>
+ RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir Thu Aug 13 18:10:16 2015<br>
@@ -34,13 +34,12 @@<br>
---<br>
name: compute<br>
tracksRegLiveness: true<br>
-body:<br>
- - id: 0<br>
- name: body<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%eax = COPY killed %edi'<br>
- - 'RETQ killed %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ liveins: %edi<br>
+<br>
+ %eax = COPY killed %edi<br>
+ RETQ killed %eax<br>
...<br>
---<br>
name: func<br>
@@ -60,39 +59,37 @@ fixedStack:<br>
stack:<br>
- { id: 0, name: b, offset: -20, size: 4, alignment: 4 }<br>
- { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.check' ]<br>
- liveins: [ '%edi', '%rbx' ]<br>
- instructions:<br>
- - 'frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'<br>
- - '%rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags'<br>
- - '%ebx = COPY %edi'<br>
- - 'MOV32mr %rsp, 1, _, 12, _, %ebx'<br>
- - id: 1<br>
- name: check<br>
- successors: [ '%bb.2.loop', '%bb.3.exit' ]<br>
- liveins: [ '%ebx' ]<br>
- instructions:<br>
- - 'CMP32ri8 %ebx, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.3.exit, implicit killed %eflags'<br>
- - 'JMP_1 %bb.2.loop'<br>
- - id: 2<br>
- name: loop<br>
- successors: [ '%bb.1.check' ]<br>
- liveins: [ '%ebx' ]<br>
- instructions:<br>
- - '%edi = MOV32rm %rsp, 1, _, 12, _'<br>
- - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'<br>
- - '%eax = DEC32r killed %eax, implicit-def dead %eflags'<br>
- - 'MOV32mr %rsp, 1, _, 12, _, killed %eax'<br>
- - 'JMP_1 %bb.1.check'<br>
- - id: 3<br>
- name: exit<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def dead %eflags'<br>
- - '%rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags'<br>
- - '%rbx = POP64r implicit-def %rsp, implicit %rsp'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.check<br>
+ liveins: %edi, %rbx<br>
+<br>
+ frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp<br>
+ %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags<br>
+ %ebx = COPY %edi<br>
+ MOV32mr %rsp, 1, _, 12, _, %ebx<br>
+<br>
+ bb.1.check:<br>
+ successors: %bb.2.loop, %bb.3.exit<br>
+ liveins: %ebx<br>
+<br>
+ CMP32ri8 %ebx, 10, implicit-def %eflags<br>
+ JG_1 %bb.3.exit, implicit killed %eflags<br>
+ JMP_1 %bb.2.loop<br>
+<br>
+ bb.2.loop:<br>
+ successors: %bb.1.check<br>
+ liveins: %ebx<br>
+<br>
+ %edi = MOV32rm %rsp, 1, _, 12, _<br>
+ CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax<br>
+ %eax = DEC32r killed %eax, implicit-def dead %eflags<br>
+ MOV32mr %rsp, 1, _, 12, _, killed %eax<br>
+ JMP_1 %bb.1.check<br>
+<br>
+ bb.3.exit:<br>
+ %eax = MOV32r0 implicit-def dead %eflags<br>
+ %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags<br>
+ %rbx = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir Thu Aug 13 18:10:16 2015<br>
@@ -18,14 +18,12 @@ frameInfo:<br>
stackSize: 4040<br>
stack:<br>
- { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags'<br>
- # CHECK: CFI_INSTRUCTION .cfi_def_cfa_offset 4048<br>
- - 'CFI_INSTRUCTION .cfi_def_cfa_offset 4048'<br>
- - '%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags'<br>
- - 'RETQ'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags<br>
+ ; CHECK: CFI_INSTRUCTION .cfi_def_cfa_offset 4048<br>
+ CFI_INSTRUCTION .cfi_def_cfa_offset 4048<br>
+ %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags<br>
+ RETQ<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir Thu Aug 13 18:10:16 2015<br>
@@ -19,15 +19,14 @@ frameInfo:<br>
stackSize: 8<br>
fixedStack:<br>
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rbp' ]<br>
- instructions:<br>
- - 'PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp'<br>
- - 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'<br>
- - 'CFI_INSTRUCTION .cfi_offset %rbp, -16'<br>
- - '%rbp = MOV64rr %rsp'<br>
- # CHECK: CFI_INSTRUCTION .cfi_def_cfa_register %rbp<br>
- - 'CFI_INSTRUCTION .cfi_def_cfa_register %rbp'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rbp<br>
+<br>
+ PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp<br>
+ CFI_INSTRUCTION .cfi_def_cfa_offset 16<br>
+ CFI_INSTRUCTION .cfi_offset %rbp, -16<br>
+ %rbp = MOV64rr %rsp<br>
+ ; CHECK: CFI_INSTRUCTION .cfi_def_cfa_register %rbp<br>
+ CFI_INSTRUCTION .cfi_def_cfa_register %rbp<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/cfi-offset.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/cfi-offset.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/cfi-offset.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/cfi-offset.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/cfi-offset.mir Thu Aug 13 18:10:16 2015<br>
@@ -26,23 +26,22 @@ frameInfo:<br>
hasCalls: true<br>
fixedStack:<br>
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%ecx', '%edi', '%edx', '%esi', '%rbx' ]<br>
- instructions:<br>
- - 'PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'<br>
- - 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'<br>
- # CHECK: CFI_INSTRUCTION .cfi_offset %rbx, -16<br>
- - 'CFI_INSTRUCTION .cfi_offset %rbx, -16'<br>
- - '%ebx = COPY %edi, implicit-def %rbx'<br>
- - '%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags'<br>
- - '%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags'<br>
- - '%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags'<br>
- - '%edi = COPY %ebx'<br>
- - 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'<br>
- - '%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _'<br>
- - '%rbx = POP64r implicit-def %rsp, implicit %rsp'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %ecx, %edi, %edx, %esi, %rbx<br>
+<br>
+ PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp<br>
+ CFI_INSTRUCTION .cfi_def_cfa_offset 16<br>
+ ; CHECK: CFI_INSTRUCTION .cfi_offset %rbx, -16<br>
+ CFI_INSTRUCTION .cfi_offset %rbx, -16<br>
+ %ebx = COPY %edi, implicit-def %rbx<br>
+ %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags<br>
+ %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags<br>
+ %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags<br>
+ %edi = COPY %ebx<br>
+ CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp<br>
+ %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _<br>
+ %rbx = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ %eax<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,11 +17,9 @@ constants:<br>
# CHECK: [[@LINE+1]]:18: redefinition of constant pool item '%const.0'<br>
- id: 0<br>
value: 'double 3.250000e+00'<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'<br>
- - 'RETQ %xmm0'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _<br>
+ RETQ %xmm0<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/constant-pool.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/constant-pool.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/constant-pool.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/constant-pool.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/constant-pool.mir Thu Aug 13 18:10:16 2015<br>
@@ -57,17 +57,15 @@ constants:<br>
- id: 1<br>
value: 'float 6.250000e+00'<br>
alignment: 4<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _<br>
- # CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _<br>
- - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'<br>
- - '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _'<br>
- - '%xmm1 = CVTSS2SDrr killed %xmm1'<br>
- - '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'<br>
- - 'RETQ %xmm0'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _<br>
+ ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _<br>
+ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _<br>
+ %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _<br>
+ %xmm1 = CVTSS2SDrr killed %xmm1<br>
+ %xmm0 = MULSDrr killed %xmm0, killed %xmm1<br>
+ RETQ %xmm0<br>
...<br>
---<br>
# Verify that alignment can be inferred:<br>
@@ -85,15 +83,13 @@ constants:<br>
value: 'double 3.250000e+00'<br>
- id: 1<br>
value: 'float 6.250000e+00'<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'<br>
- - '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _'<br>
- - '%xmm1 = CVTSS2SDrr killed %xmm1'<br>
- - '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'<br>
- - 'RETQ %xmm0'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _<br>
+ %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _<br>
+ %xmm1 = CVTSS2SDrr killed %xmm1<br>
+ %xmm0 = MULSDrr killed %xmm0, killed %xmm1<br>
+ RETQ %xmm0<br>
...<br>
---<br>
# Verify that the non-standard alignments are respected:<br>
@@ -113,17 +109,15 @@ constants:<br>
- id: 1<br>
value: 'float 6.250000e+00'<br>
alignment: 1<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _<br>
- # CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _<br>
- - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'<br>
- - '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _'<br>
- - '%xmm1 = CVTSS2SDrr killed %xmm1'<br>
- - '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'<br>
- - 'RETQ %xmm0'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _<br>
+ ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _<br>
+ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _<br>
+ %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _<br>
+ %xmm1 = CVTSS2SDrr killed %xmm1<br>
+ %xmm0 = MULSDrr killed %xmm0, killed %xmm1<br>
+ RETQ %xmm0<br>
...<br>
---<br>
# CHECK: name: test4<br>
@@ -133,15 +127,13 @@ constants:<br>
value: 'double 3.250000e+00'<br>
- id: 1<br>
value: 'float 6.250000e+00'<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _<br>
- # CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _<br>
- - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _'<br>
- - '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _'<br>
- - '%xmm1 = CVTSS2SDrr killed %xmm1'<br>
- - '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'<br>
- - 'RETQ %xmm0'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _<br>
+ ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _<br>
+ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _<br>
+ %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _<br>
+ %xmm1 = CVTSS2SDrr killed %xmm1<br>
+ %xmm0 = MULSDrr killed %xmm0, killed %xmm1<br>
+ RETQ %xmm0<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/constant-value-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/constant-value-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/constant-value-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/constant-value-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/constant-value-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,11 +17,9 @@ constants:<br>
- id: 0<br>
# CHECK: [[@LINE+1]]:19: expected type<br>
value: 'dub 3.250000e+00'<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'<br>
- - 'RETQ %xmm0'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _<br>
+ RETQ %xmm0<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/dead-register-flag.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/dead-register-flag.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/dead-register-flag.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/dead-register-flag.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/dead-register-flag.mir Thu Aug 13 18:10:16 2015<br>
@@ -15,12 +15,10 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- # CHECK: name: body<br>
- - id: 0<br>
- name: body<br>
- instructions:<br>
- # CHECK: - '%eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags'<br>
- - '%eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ ; CHECK: bb.0.body:<br>
+ bb.0.body:<br>
+ ; CHECK: %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags<br>
+ %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,14 +16,12 @@ name: volatile_inc<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:55: duplicate 'volatile' memory operand flag<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x)'<br>
- - '%eax = INC32r killed %eax, implicit-def dead %eflags'<br>
- - 'MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: [[@LINE+1]]:50: duplicate 'volatile' memory operand flag<br>
+ %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x)<br>
+ %eax = INC32r killed %eax, implicit-def dead %eflags<br>
+ MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,22 +17,19 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.less', '%bb.2.exit' ]<br>
- instructions:<br>
- - 'CMP32ri8 %edi, 10, implicit-def %eflags'<br>
-# CHECK: [[@LINE+1]]:36: duplicate 'implicit' register flag<br>
- - 'JG_1 %bb.2.exit, implicit implicit %eflags'<br>
- - id: 1<br>
- name: less<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
- - id: 2<br>
- name: exit<br>
- instructions:<br>
- - '%eax = COPY %edi'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.less, %bb.2.exit<br>
+<br>
+ CMP32ri8 %edi, 10, implicit-def %eflags<br>
+ ; CHECK: [[@LINE+1]]:31: duplicate 'implicit' register flag<br>
+ JG_1 %bb.2.exit, implicit implicit %eflags<br>
+<br>
+ bb.1.less:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+ RETQ %eax<br>
+<br>
+ bb.2.exit:<br>
+ %eax = COPY %edi<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir Thu Aug 13 18:10:16 2015<br>
@@ -28,19 +28,18 @@ frameInfo:<br>
stackSize: 8<br>
adjustsStack: true<br>
hasCalls: true<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%edi', '%esi' ]<br>
- instructions:<br>
- - 'frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp'<br>
- - CFI_INSTRUCTION .cfi_def_cfa_offset 16<br>
- - '%ecx = COPY %edi'<br>
- - '%ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags'<br>
-# CHECK: INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di<br>
- - 'INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di'<br>
- - '%edi = COPY killed %ecx'<br>
- - 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'<br>
- - '%rax = POP64r implicit-def %rsp, implicit %rsp'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %edi, %esi<br>
+<br>
+ frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp<br>
+ CFI_INSTRUCTION .cfi_def_cfa_offset 16<br>
+ %ecx = COPY %edi<br>
+ %ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags<br>
+ ; CHECK: INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di<br>
+ INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di<br>
+ %edi = COPY killed %ecx<br>
+ CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp<br>
+ %rax = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,17 +16,15 @@ name: memory_alignment<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:70: expected 'align'<br>
- - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32)'<br>
- - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'<br>
- - '%xmm2 = FsFLD0SS'<br>
- - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'<br>
- - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'<br>
- - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: [[@LINE+1]]:65: expected 'align'<br>
+ %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32)<br>
+ %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)<br>
+ %xmm2 = FsFLD0SS<br>
+ %xmm1 = MOVSSrr killed %xmm1, killed %xmm2<br>
+ MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)<br>
+ MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)<br>
+ RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,17 +16,15 @@ name: memory_alignment<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:75: expected an integer literal after 'align'<br>
- - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align)'<br>
- - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'<br>
- - '%xmm2 = FsFLD0SS'<br>
- - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'<br>
- - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'<br>
- - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: [[@LINE+1]]:70: expected an integer literal after 'align'<br>
+ %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align)<br>
+ %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)<br>
+ %xmm2 = FsFLD0SS<br>
+ %xmm1 = MOVSSrr killed %xmm1, killed %xmm2<br>
+ MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)<br>
+ MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)<br>
+ RETQ<br>
...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir?rev=244982&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir?rev=244982&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir Thu Aug 13 18:10:16 2015<br>
@@ -0,0 +1,40 @@<br>
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
+<br>
+--- |<br>
+<br>
+ define i32 @foo(i32 %a) {<br>
+ entry:<br>
+ %0 = icmp sle i32 %a, 10<br>
+ br i1 %0, label %less, label %exit<br>
+<br>
+ less: ; preds = %entry<br>
+ ret i32 0<br>
+<br>
+ exit: ; preds = %entry<br>
+ ret i32 %a<br>
+ }<br>
+<br>
+...<br>
+---<br>
+name: foo<br>
+tracksRegLiveness: true<br>
+liveins:<br>
+ - { reg: '%edi' }<br>
+body: |<br>
+ ; CHECK: [[@LINE+1]]:3: expected a basic block definition before instructions<br>
+ successors: %bb.1.less, %bb.2.exit<br>
+ liveins: %edi 44<br>
+<br>
+ CMP32ri8 %edi, 10, implicit-def %eflags<br>
+ JG_1 %bb.2.exit, implicit killed %eflags<br>
+<br>
+ bb.1.less:<br>
+ %eax = MOV32r0 implicit-def dead %eflags<br>
+ RETQ killed %eax<br>
+<br>
+ bb.2.exit:<br>
+ liveins: %edi<br>
+<br>
+ %eax = COPY killed %edi<br>
+ RETQ killed %eax<br>
+...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,18 +17,14 @@<br>
...<br>
---<br>
name: test<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.block' ]<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:56: expected an IR block reference<br>
- - '%rax = LEA64r %rip, 1, _, blockaddress(@test, _), _'<br>
- - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'<br>
- - 'JMP64m %rip, 1, _, @addr, _'<br>
- - id: 1<br>
- name: block<br>
- addressTaken: true<br>
- instructions:<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.block<br>
+ ; CHECK: [[@LINE+1]]:51: expected an IR block reference<br>
+ %rax = LEA64r %rip, 1, _, blockaddress(@test, _), _<br>
+ MOV64mr %rip, 1, _, @addr, _, killed %rax<br>
+ JMP64m %rip, 1, _, @addr, _<br>
+<br>
+ bb.1.block (address-taken):<br>
+ RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir Thu Aug 13 18:10:16 2015<br>
@@ -24,21 +24,19 @@ frameInfo:<br>
hasCalls: true<br>
fixedStack:<br>
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - 'PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'<br>
- - 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'<br>
- # CHECK: [[@LINE+1]]:43: expected ','<br>
- - 'CFI_INSTRUCTION .cfi_offset %rbx -16'<br>
- - '%ebx = COPY %edi, implicit-def %rbx'<br>
- - '%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags'<br>
- - '%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags'<br>
- - '%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags'<br>
- - '%edi = COPY %ebx'<br>
- - 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'<br>
- - '%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _'<br>
- - '%rbx = POP64r implicit-def %rsp, implicit %rsp'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp<br>
+ CFI_INSTRUCTION .cfi_def_cfa_offset 16<br>
+ ; CHECK: [[@LINE+1]]:38: expected ','<br>
+ CFI_INSTRUCTION .cfi_offset %rbx -16<br>
+ %ebx = COPY %edi, implicit-def %rbx<br>
+ %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags<br>
+ %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags<br>
+ %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags<br>
+ %edi = COPY %ebx<br>
+ CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp<br>
+ %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _<br>
+ %rbx = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,12 +16,10 @@ name: test<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry2<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:92: expected ',' before the next machine memory operand<br>
- - 'INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir.a) (load 4 from %ir.a)'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry2:<br>
+ liveins: %rdi<br>
+ ; CHECK: [[@LINE+1]]:87: expected ',' before the next machine memory operand<br>
+ INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir.a) (load 4 from %ir.a)<br>
+ RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -19,20 +19,16 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, _'<br>
- - 'CMP32ri8 %eax, 10, implicit-def %eflags'<br>
-# CHECK: [[@LINE+1]]:26: expected an implicit register operand 'implicit %eflags'<br>
- - 'JG_1 %bb.2.exit, implicit %eax'<br>
- - id: 1<br>
- name: less<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - id: 2<br>
- name: exit<br>
- instructions:<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %eax = MOV32rm %rdi, 1, _, 0, _<br>
+ CMP32ri8 %eax, 10, implicit-def %eflags<br>
+ ; CHECK: [[@LINE+1]]:22: expected an implicit register operand 'implicit %eflags'<br>
+ JG_1 %bb.2.exit, implicit %eax<br>
+<br>
+ bb.1.less:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+<br>
+ bb.2.exit:<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir Thu Aug 13 18:10:16 2015<br>
@@ -19,20 +19,16 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, _'<br>
- - 'CMP32ri8 %eax, 10, implicit-def %eflags'<br>
-# CHECK: [[@LINE+1]]:26: expected an implicit register operand 'implicit %eflags'<br>
- - 'JG_1 %bb.2.exit, implicit-def %eflags'<br>
- - id: 1<br>
- name: less<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - id: 2<br>
- name: exit<br>
- instructions:<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %eax = MOV32rm %rdi, 1, _, 0, _<br>
+ CMP32ri8 %eax, 10, implicit-def %eflags<br>
+ ; CHECK: [[@LINE+1]]:22: expected an implicit register operand 'implicit %eflags'<br>
+ JG_1 %bb.2.exit, implicit-def %eflags<br>
+<br>
+ bb.1.less:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+<br>
+ bb.2.exit:<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@ name: test<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:60: expected 'from'<br>
- - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 %ir.a)'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: [[@LINE+1]]:55: expected 'from'<br>
+ %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 %ir.a)<br>
+ RETQ %eax<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,18 +17,14 @@<br>
...<br>
---<br>
name: test<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.block' ]<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:49: expected an IR function reference<br>
- - '%rax = LEA64r %rip, 1, _, blockaddress(@addr, %ir-block.block), _'<br>
- - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'<br>
- - 'JMP64m %rip, 1, _, @addr, _'<br>
- - id: 1<br>
- name: block<br>
- addressTaken: true<br>
- instructions:<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.block<br>
+ ; CHECK: [[@LINE+1]]:44: expected an IR function reference<br>
+ %rax = LEA64r %rip, 1, _, blockaddress(@addr, %ir-block.block), _<br>
+ MOV64mr %rip, 1, _, @addr, _, killed %rax<br>
+ JMP64m %rip, 1, _, @addr, _<br>
+<br>
+ bb.1.block (address-taken):<br>
+ RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,18 +17,14 @@<br>
...<br>
---<br>
name: test<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.block' ]<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:49: expected a global value<br>
- - '%rax = LEA64r %rip, 1, _, blockaddress(0, %ir-block.block), _'<br>
- - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'<br>
- - 'JMP64m %rip, 1, _, @addr, _'<br>
- - id: 1<br>
- name: block<br>
- addressTaken: true<br>
- instructions:<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.block<br>
+ ; CHECK: [[@LINE+1]]:44: expected a global value<br>
+ %rax = LEA64r %rip, 1, _, blockaddress(0, %ir-block.block), _<br>
+ MOV64mr %rip, 1, _, @addr, _, killed %rax<br>
+ JMP64m %rip, 1, _, @addr, _<br>
+<br>
+ bb.1.block (address-taken):<br>
+ RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@<br>
...<br>
---<br>
name: inc<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:42: expected an integer literal after '+'<br>
- - '%rax = MOV64rm %rip, 1, _, @G + , _'<br>
- - '%eax = MOV32rm %rax, 1, _, 0, _'<br>
- - '%eax = INC32r %eax, implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:37: expected an integer literal after '+'<br>
+ %rax = MOV64rm %rip, 1, _, @G + , _<br>
+ %eax = MOV32rm %rax, 1, _, 0, _<br>
+ %eax = INC32r %eax, implicit-def %eflags<br>
+ RETQ %eax<br>
...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir?rev=244982&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir?rev=244982&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir Thu Aug 13 18:10:16 2015<br>
@@ -0,0 +1,38 @@<br>
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
+<br>
+--- |<br>
+<br>
+ define i32 @foo(i32 %a) {<br>
+ entry:<br>
+ %0 = icmp sle i32 %a, 10<br>
+ br i1 %0, label %less, label %exit<br>
+<br>
+ less:<br>
+ ret i32 0<br>
+<br>
+ exit:<br>
+ ret i32 %a<br>
+ }<br>
+<br>
+...<br>
+---<br>
+name: foo<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:29: expected an integer literal after '('<br>
+ successors: %bb.1.less (_), %bb.2.exit(32)<br>
+ liveins: %edi<br>
+<br>
+ CMP32ri8 %edi, 10, implicit-def %eflags<br>
+ JG_1 %bb.2.exit, implicit killed %eflags<br>
+<br>
+ bb.1.less:<br>
+ %eax = MOV32r0 implicit-def dead %eflags<br>
+ RETQ killed %eax<br>
+<br>
+ bb.2.exit:<br>
+ liveins: %edi<br>
+<br>
+ %eax = COPY killed %edi<br>
+ RETQ killed %eax<br>
+...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,12 +14,10 @@ name: test<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:53: expected 'load' or 'store' memory operation<br>
- - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (4 from %ir.a)'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: [[@LINE+1]]:48: expected 'load' or 'store' memory operation<br>
+ %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (4 from %ir.a)<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -10,12 +10,10 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:24: expected a machine operand<br>
- - '%eax = XOR32rr ='<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:20: expected a machine operand<br>
+ %eax = XOR32rr =<br>
+ RETQ %eax<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir Thu Aug 13 18:10:16 2015<br>
@@ -48,14 +48,12 @@ frameInfo:<br>
maxAlignment: 4<br>
stack:<br>
- { id: 0, name: x.addr, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
- # CHECK: [[@LINE+1]]:51: expected a metadata node after 'debug-location'<br>
- - 'DBG_VALUE _, 0, !12, !13, debug-location 14'<br>
- - 'MOV32mr %stack.x.addr, 1, _, 0, _, %0'<br>
- - '%eax = COPY %0'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %0 = COPY %edi<br>
+ ; CHECK: [[@LINE+1]]:46: expected a metadata node after 'debug-location'<br>
+ DBG_VALUE _, 0, !12, !13, debug-location 14<br>
+ MOV32mr %stack.x.addr, 1, _, 0, _, %0<br>
+ %eax = COPY %0<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir Thu Aug 13 18:10:16 2015<br>
@@ -48,14 +48,12 @@ frameInfo:<br>
maxAlignment: 4<br>
stack:<br>
- { id: 0, name: x.addr, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
- # CHECK: [[@LINE+1]]:33: expected metadata id after '!'<br>
- - 'DBG_VALUE _, 0, !12, ! _'<br>
- - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'<br>
- - '%eax = COPY %0'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %0 = COPY %edi<br>
+ ; CHECK: [[@LINE+1]]:28: expected metadata id after '!'<br>
+ DBG_VALUE _, 0, !12, ! _<br>
+ MOV32mr %stack.0.x.addr, 1, _, 0, _, %0<br>
+ %eax = COPY %0<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,14 +17,13 @@ registers:<br>
# CHECK: [[@LINE+1]]:48: expected a named register<br>
- { id: 1, class: gr32, preferred-register: '%0' }<br>
- { id: 2, class: gr32, preferred-register: '%edi' }<br>
-body:<br>
- - id: 0<br>
- name: body<br>
- liveins: [ '%edi', '%esi' ]<br>
- instructions:<br>
- - '%1 = COPY %esi'<br>
- - '%2 = COPY %edi'<br>
- - '%2 = IMUL32rr %2, %1, implicit-def dead %eflags'<br>
- - '%eax = COPY %2'<br>
- - 'RETQ killed %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ liveins: %edi, %esi<br>
+<br>
+ %1 = COPY %esi<br>
+ %2 = COPY %edi<br>
+ %2 = IMUL32rr %2, %1, implicit-def dead %eflags<br>
+ %eax = COPY %2<br>
+ RETQ killed %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir Thu Aug 13 18:10:16 2015<br>
@@ -32,13 +32,12 @@<br>
---<br>
name: compute<br>
tracksRegLiveness: true<br>
-body:<br>
- - id: 0<br>
- name: body<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%eax = COPY killed %edi'<br>
- - 'RETQ killed %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ liveins: %edi<br>
+<br>
+ %eax = COPY killed %edi<br>
+ RETQ killed %eax<br>
...<br>
---<br>
name: func<br>
@@ -53,39 +52,37 @@ fixedStack:<br>
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%0' }<br>
stack:<br>
- { id: 0, name: b, offset: -20, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.check' ]<br>
- liveins: [ '%edi', '%rbx' ]<br>
- instructions:<br>
- - 'frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'<br>
- - '%rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags'<br>
- - '%ebx = COPY %edi'<br>
- - 'MOV32mr %rsp, 1, _, 12, _, %ebx'<br>
- - id: 1<br>
- name: check<br>
- successors: [ '%bb.2.loop', '%bb.3.exit' ]<br>
- liveins: [ '%ebx' ]<br>
- instructions:<br>
- - 'CMP32ri8 %ebx, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.3.exit, implicit killed %eflags'<br>
- - 'JMP_1 %bb.2.loop'<br>
- - id: 2<br>
- name: loop<br>
- successors: [ '%bb.1.check' ]<br>
- liveins: [ '%ebx' ]<br>
- instructions:<br>
- - '%edi = MOV32rm %rsp, 1, _, 12, _'<br>
- - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'<br>
- - '%eax = DEC32r killed %eax, implicit-def dead %eflags'<br>
- - 'MOV32mr %rsp, 1, _, 12, _, killed %eax'<br>
- - 'JMP_1 %bb.1.check'<br>
- - id: 3<br>
- name: exit<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def dead %eflags'<br>
- - '%rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags'<br>
- - '%rbx = POP64r implicit-def %rsp, implicit %rsp'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.check<br>
+ liveins: %edi, %rbx<br>
+<br>
+ frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp<br>
+ %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags<br>
+ %ebx = COPY %edi<br>
+ MOV32mr %rsp, 1, _, 12, _, %ebx<br>
+<br>
+ bb.1.check:<br>
+ successors: %bb.2.loop, %bb.3.exit<br>
+ liveins: %ebx<br>
+<br>
+ CMP32ri8 %ebx, 10, implicit-def %eflags<br>
+ JG_1 %bb.3.exit, implicit killed %eflags<br>
+ JMP_1 %bb.2.loop<br>
+<br>
+ bb.2.loop:<br>
+ successors: %bb.1.check<br>
+ liveins: %ebx<br>
+<br>
+ %edi = MOV32rm %rsp, 1, _, 12, _<br>
+ CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax<br>
+ %eax = DEC32r killed %eax, implicit-def dead %eflags<br>
+ MOV32mr %rsp, 1, _, 12, _, killed %eax<br>
+ JMP_1 %bb.1.check<br>
+<br>
+ bb.3.exit:<br>
+ %eax = MOV32r0 implicit-def dead %eflags<br>
+ %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags<br>
+ %rbx = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,12 +17,11 @@ registers:<br>
liveins:<br>
# CHECK: [[@LINE+1]]:13: expected a named register<br>
- { reg: '%0' }<br>
-body:<br>
- - id: 0<br>
- name: body<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
- - '%eax = COPY %0'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ liveins: %edi<br>
+<br>
+ %0 = COPY %edi<br>
+ %eax = COPY %0<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir Thu Aug 13 18:10:16 2015<br>
@@ -10,12 +10,11 @@<br>
...<br>
---<br>
name: test<br>
-body:<br>
- - id: 0<br>
- name: body<br>
- # CHECK: [[@LINE+1]]:21: expected a named register<br>
- liveins: [ '%0' ]<br>
- instructions:<br>
- - '%eax = COPY %edi'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ ; CHECK: [[@LINE+1]]:14: expected a named register<br>
+ liveins: %0<br>
+<br>
+ %eax = COPY %edi<br>
+ RETQ %eax<br>
...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir?rev=244982&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir?rev=244982&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir Thu Aug 13 18:10:16 2015<br>
@@ -0,0 +1,41 @@<br>
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
+<br>
+--- |<br>
+<br>
+ define i32 @foo(i32 %a) {<br>
+ entry:<br>
+ %0 = icmp sle i32 %a, 10<br>
+ br i1 %0, label %less, label %exit<br>
+<br>
+ less: ; preds = %entry<br>
+ ret i32 0<br>
+<br>
+ exit: ; preds = %entry<br>
+ ret i32 %a<br>
+ }<br>
+<br>
+...<br>
+---<br>
+name: foo<br>
+tracksRegLiveness: true<br>
+liveins:<br>
+ - { reg: '%edi' }<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.less, %bb.2.exit<br>
+ ; CHECK: [[@LINE+1]]:19: expected line break at the end of a list<br>
+ liveins: %edi 44<br>
+<br>
+ CMP32ri8 %edi, 10, implicit-def %eflags<br>
+ JG_1 %bb.2.exit, implicit killed %eflags<br>
+<br>
+ bb.1.less:<br>
+ %eax = MOV32r0 implicit-def dead %eflags<br>
+ RETQ killed %eax<br>
+<br>
+ bb.2.exit:<br>
+ liveins: %edi<br>
+<br>
+ %eax = COPY killed %edi<br>
+ RETQ killed %eax<br>
+...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir Thu Aug 13 18:10:16 2015<br>
@@ -18,20 +18,16 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, _'<br>
- - 'CMP32ri8 %eax, 10, implicit-def %eflags'<br>
- # CHECK: [[@LINE+1]]:18: expected a number after '%bb.'<br>
- - 'JG_1 %bb.nah, implicit %eflags'<br>
- - id: 1<br>
- name: yes<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - id: 2<br>
- name: nah<br>
- instructions:<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %eax = MOV32rm %rdi, 1, _, 0, _<br>
+ CMP32ri8 %eax, 10, implicit-def %eflags<br>
+ ; CHECK: [[@LINE+1]]:14: expected a number after '%bb.'<br>
+ JG_1 %bb.nah, implicit %eflags<br>
+<br>
+ bb.1.true:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+<br>
+ bb.2.nah:<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,14 +16,12 @@ frameInfo:<br>
stackSize: 4040<br>
stack:<br>
- { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags'<br>
- # CHECK: [[@LINE+1]]:46: expected a cfi offset<br>
- - 'CFI_INSTRUCTION .cfi_def_cfa_offset _'<br>
- - '%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags'<br>
- - 'RETQ'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags<br>
+ ; CHECK: [[@LINE+1]]:41: expected a cfi offset<br>
+ CFI_INSTRUCTION .cfi_def_cfa_offset _<br>
+ %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags<br>
+ RETQ<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@ name: test<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:65: expected a pointer IR value<br>
- - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.b)'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: [[@LINE+1]]:60: expected a pointer IR value<br>
+ %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.b)<br>
+ RETQ %eax<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,17 +16,15 @@ name: memory_alignment<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:76: expected an integer literal after 'align'<br>
- - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32)'<br>
- - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'<br>
- - '%xmm2 = FsFLD0SS'<br>
- - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'<br>
- - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'<br>
- - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: [[@LINE+1]]:71: expected an integer literal after 'align'<br>
+ %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32)<br>
+ %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)<br>
+ %xmm2 = FsFLD0SS<br>
+ %xmm1 = MOVSSrr killed %xmm1, killed %xmm2<br>
+ MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)<br>
+ MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)<br>
+ RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -24,21 +24,19 @@ frameInfo:<br>
hasCalls: true<br>
fixedStack:<br>
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - 'PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'<br>
- - 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'<br>
- # CHECK: [[@LINE+1]]:38: expected a cfi register<br>
- - 'CFI_INSTRUCTION .cfi_offset %0, -16'<br>
- - '%ebx = COPY %edi, implicit-def %rbx'<br>
- - '%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags'<br>
- - '%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags'<br>
- - '%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags'<br>
- - '%edi = COPY %ebx'<br>
- - 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'<br>
- - '%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _'<br>
- - '%rbx = POP64r implicit-def %rsp, implicit %rsp'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp<br>
+ CFI_INSTRUCTION .cfi_def_cfa_offset 16<br>
+ ; CHECK: [[@LINE+1]]:33: expected a cfi register<br>
+ CFI_INSTRUCTION .cfi_offset %0, -16<br>
+ %ebx = COPY %edi, implicit-def %rbx<br>
+ %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags<br>
+ %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags<br>
+ %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags<br>
+ %edi = COPY %ebx<br>
+ CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp<br>
+ %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _<br>
+ %rbx = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-flags.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-flags.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-flags.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-flags.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-flags.mir Thu Aug 13 18:10:16 2015<br>
@@ -12,11 +12,9 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:37: expected a register after register flags<br>
- - '%eax = MOV32r0 implicit-def 2'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:33: expected a register after register flags<br>
+ %eax = MOV32r0 implicit-def 2<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@ name: test<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:58: expected the size integer literal after memory operation<br>
- - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load from %ir.a)'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: [[@LINE+1]]:53: expected the size integer literal after memory operation<br>
+ %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load from %ir.a)<br>
+ RETQ %eax<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,14 +16,12 @@ registers:<br>
- { id: 0, class: gr32 }<br>
- { id: 1, class: gr8 }<br>
- { id: 2, class: gr8 }<br>
-body:<br>
- - name: entry<br>
- id: 0<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
- # CHECK: [[@LINE+1]]:25: expected a subregister index after ':'<br>
- - '%1 = COPY %0 : 42'<br>
- - '%2 = AND8ri %1, 1, implicit-def %eflags'<br>
- - '%al = COPY %2'<br>
- - 'RETQ %al'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %0 = COPY %edi<br>
+ ; CHECK: [[@LINE+1]]:20: expected a subregister index after ':'<br>
+ %1 = COPY %0 : 42<br>
+ %2 = AND8ri %1, 1, implicit-def %eflags<br>
+ %al = COPY %2<br>
+ RETQ %al<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-target-flag-name.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-target-flag-name.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-target-flag-name.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-target-flag-name.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-target-flag-name.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@<br>
...<br>
---<br>
name: inc<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:51: expected the name of the target flag<br>
- - '%rax = MOV64rm %rip, 1, _, target-flags( ) @G, _'<br>
- - '%eax = MOV32rm killed %rax, 1, _, 0, _'<br>
- - '%eax = INC32r killed %eax, implicit-def dead %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:46: expected the name of the target flag<br>
+ %rax = MOV64rm %rip, 1, _, target-flags( ) @G, _<br>
+ %eax = MOV32rm killed %rax, 1, _, 0, _<br>
+ %eax = INC32r killed %eax, implicit-def dead %eflags<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@ name: test<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:65: expected an IR value reference<br>
- - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from a)'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: [[@LINE+1]]:60: expected an IR value reference<br>
+ %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from a)<br>
+ RETQ %eax<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,12 +17,11 @@ registers:<br>
liveins:<br>
# CHECK: [[@LINE+1]]:34: expected a virtual register<br>
- { reg: '%edi', virtual-reg: '%edi' }<br>
-body:<br>
- - id: 0<br>
- name: body<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
- - '%eax = COPY %0'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ liveins: %edi<br>
+<br>
+ %0 = COPY %edi<br>
+ %eax = COPY %0<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -29,38 +29,36 @@<br>
---<br>
name: test<br>
tracksRegLiveness: true<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.entry', '%bb.2.entry' ]<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%rsp = SUB64ri32 %rsp, 520, implicit-def %eflags'<br>
- - '%rcx = LOAD_STACK_GUARD'<br>
- - 'MOV64mr %rsp, 1, _, 512, _, %rcx'<br>
- - '%rax = MOVSX64rr32 %edi'<br>
- - '%eax = MOV32rm %rsp, 4, %rax, 0, _'<br>
- - 'CMP64rm %rcx, %rsp, 1, _, 512, _, implicit-def %eflags'<br>
- - 'JNE_1 %bb.2.entry, implicit %eflags'<br>
- - id: 1<br>
- name: entry<br>
- liveins: [ '%eax' ]<br>
- instructions:<br>
- - '%rsp = ADD64ri32 %rsp, 520, implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
- - id: 2<br>
- name: entry<br>
- instructions:<br>
- # CHECK: CALL64pcrel32 $__stack_chk_fail,<br>
- # CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail.09-_,<br>
- # CHECK-NEXT: CALL64pcrel32 $"__stack_chk_fail$",<br>
- # CHECK-NEXT: CALL64pcrel32 $"$Quoted \09 External symbol \11 ",<br>
- # CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail + 2,<br>
- # CHECK-NEXT: CALL64pcrel32 $" check stack - 20" - 20,<br>
- - 'CALL64pcrel32 $__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp'<br>
- - 'CALL64pcrel32 $__stack_chk_fail.09-_, csr_64, implicit %rsp, implicit-def %rsp'<br>
- - 'CALL64pcrel32 $__stack_chk_fail$, csr_64, implicit %rsp, implicit-def %rsp'<br>
- - 'CALL64pcrel32 $"$Quoted \09 External symbol \11 ", csr_64, implicit %rsp, implicit-def %rsp'<br>
- - 'CALL64pcrel32 $__stack_chk_fail + 2, csr_64, implicit %rsp, implicit-def %rsp'<br>
- - 'CALL64pcrel32 $" check stack - 20" - 20, csr_64, implicit %rsp, implicit-def %rsp'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.entry, %bb.2.entry<br>
+ liveins: %edi<br>
+<br>
+ %rsp = SUB64ri32 %rsp, 520, implicit-def %eflags<br>
+ %rcx = LOAD_STACK_GUARD<br>
+ MOV64mr %rsp, 1, _, 512, _, %rcx<br>
+ %rax = MOVSX64rr32 %edi<br>
+ %eax = MOV32rm %rsp, 4, %rax, 0, _<br>
+ CMP64rm %rcx, %rsp, 1, _, 512, _, implicit-def %eflags<br>
+ JNE_1 %bb.2.entry, implicit %eflags<br>
+<br>
+ bb.1.entry:<br>
+ liveins: %eax<br>
+<br>
+ %rsp = ADD64ri32 %rsp, 520, implicit-def %eflags<br>
+ RETQ %eax<br>
+<br>
+ bb.2.entry:<br>
+ ; CHECK: CALL64pcrel32 $__stack_chk_fail,<br>
+ ; CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail.09-_,<br>
+ ; CHECK-NEXT: CALL64pcrel32 $"__stack_chk_fail$",<br>
+ ; CHECK-NEXT: CALL64pcrel32 $"$Quoted \09 External symbol \11 ",<br>
+ ; CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail + 2,<br>
+ ; CHECK-NEXT: CALL64pcrel32 $" check stack - 20" - 20,<br>
+ CALL64pcrel32 $__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp<br>
+ CALL64pcrel32 $__stack_chk_fail.09-_, csr_64, implicit %rsp, implicit-def %rsp<br>
+ CALL64pcrel32 $__stack_chk_fail$, csr_64, implicit %rsp, implicit-def %rsp<br>
+ CALL64pcrel32 $"$Quoted \09 External symbol \11 ", csr_64, implicit %rsp, implicit-def %rsp<br>
+ CALL64pcrel32 $__stack_chk_fail + 2, csr_64, implicit %rsp, implicit-def %rsp<br>
+ CALL64pcrel32 $" check stack - 20" - 20, csr_64, implicit %rsp, implicit-def %rsp<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -26,16 +26,14 @@ fixedStack:<br>
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true }<br>
stack:<br>
- { id: 0, name: b, offset: -8, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - 'frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp'<br>
- - CFI_INSTRUCTION .cfi_def_cfa_offset 8<br>
-# CHECK: name: test<br>
-# CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)<br>
- - '%eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)'<br>
- - 'MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b)'<br>
- - '%edx = POP32r implicit-def %esp, implicit %esp'<br>
- - 'RETL %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp<br>
+ CFI_INSTRUCTION .cfi_def_cfa_offset 8<br>
+ ; CHECK: name: test<br>
+ ; CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)<br>
+ %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)<br>
+ MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b)<br>
+ %edx = POP32r implicit-def %esp, implicit %esp<br>
+ RETL %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -20,11 +20,9 @@ fixedStack:<br>
- { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }<br>
# CHECK: [[@LINE+1]]:11: redefinition of fixed stack object '%fixed-stack.0'<br>
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%eax = MOV32rm %esp, 1, _, 4, _'<br>
- - '%eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags'<br>
- - 'RETL %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %eax = MOV32rm %esp, 1, _, 4, _<br>
+ %eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags<br>
+ RETL %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir Thu Aug 13 18:10:16 2015<br>
@@ -25,11 +25,9 @@ fixedStack:<br>
- { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }<br>
stack:<br>
- { id: 0, offset: -8, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%eax = MOV32rm %esp, 1, _, 8, _'<br>
- - 'MOV32mr %esp, 1, _, 0, _, %eax'<br>
- - 'RETL %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %eax = MOV32rm %esp, 1, _, 8, _<br>
+ MOV32mr %esp, 1, _, 0, _, %eax<br>
+ RETL %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir Thu Aug 13 18:10:16 2015<br>
@@ -40,33 +40,34 @@ frameInfo:<br>
restorePoint: '%bb.2.true'<br>
stack:<br>
- { id: 0, name: tmp, offset: 0, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- successors: [ '%bb.2.true', '%bb.1' ]<br>
- liveins: [ '%edi', '%esi' ]<br>
- instructions:<br>
- - '%eax = COPY %edi'<br>
- - 'CMP32rr %eax, killed %esi, implicit-def %eflags'<br>
- - 'JL_1 %bb.2.true, implicit killed %eflags'<br>
- - id: 1<br>
- successors: [ '%bb.3.false' ]<br>
- liveins: [ '%eax' ]<br>
- instructions:<br>
- - 'JMP_1 %bb.3.false'<br>
- - id: 2<br>
- name: 'true'<br>
- successors: [ '%bb.3.false' ]<br>
- liveins: [ '%eax' ]<br>
- instructions:<br>
- - 'MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax'<br>
- - 'ADJCALLSTACKDOWN64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp'<br>
- - '%rsi = LEA64r %stack.0.tmp, 1, _, 0, _'<br>
- - '%edi = MOV32r0 implicit-def dead %eflags'<br>
- - 'CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %eax'<br>
- - 'ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp'<br>
- - id: 3<br>
- name: 'false'<br>
- liveins: [ '%eax' ]<br>
- instructions:<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0:<br>
+ successors: %bb.2.true, %bb.1<br>
+ liveins: %edi, %esi<br>
+<br>
+ %eax = COPY %edi<br>
+ CMP32rr %eax, killed %esi, implicit-def %eflags<br>
+ JL_1 %bb.2.true, implicit killed %eflags<br>
+<br>
+ bb.1:<br>
+ successors: %bb.3.false<br>
+ liveins: %eax<br>
+<br>
+ JMP_1 %bb.3.false<br>
+<br>
+ bb.2.true:<br>
+ successors: %bb.3.false<br>
+ liveins: %eax<br>
+<br>
+ MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax<br>
+ ADJCALLSTACKDOWN64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp<br>
+ %rsi = LEA64r %stack.0.tmp, 1, _, 0, _<br>
+ %edi = MOV32r0 implicit-def dead %eflags<br>
+ CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %eax<br>
+ ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp<br>
+<br>
+ bb.3.false:<br>
+ liveins: %eax<br>
+<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir Thu Aug 13 18:10:16 2015<br>
@@ -18,22 +18,18 @@<br>
...<br>
---<br>
name: compute<br>
-body:<br>
- - name: body<br>
- id: 0<br>
- instructions:<br>
- - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ %eax = IMUL32rri8 %edi, 11, implicit-def %eflags<br>
+ RETQ %eax<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - name: entry<br>
- id: 0<br>
- instructions:<br>
- # CHECK: frame-setup PUSH64r %rax<br>
- - 'frame-setup PUSH64r %rax, implicit-def %rsp, implicit %rsp'<br>
- - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'<br>
- - '%rdx = POP64r implicit-def %rsp, implicit %rsp'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: frame-setup PUSH64r %rax<br>
+ frame-setup PUSH64r %rax, implicit-def %rsp, implicit %rsp<br>
+ CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax<br>
+ %rdx = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir Thu Aug 13 18:10:16 2015<br>
@@ -25,14 +25,13 @@ registers:<br>
liveins:<br>
- { reg: '%edi', virtual-reg: '%0' }<br>
- { reg: '%esi', virtual-reg: '%1' }<br>
-body:<br>
- - id: 0<br>
- name: body<br>
- liveins: [ '%edi', '%esi' ]<br>
- instructions:<br>
- - '%1 = COPY %esi'<br>
- - '%0 = COPY %edi'<br>
- - '%2 = ADD32rr %0, %1, implicit-def dead %eflags'<br>
- - '%eax = COPY %2'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ liveins: %edi, %esi<br>
+<br>
+ %1 = COPY %esi<br>
+ %0 = COPY %edi<br>
+ %2 = ADD32rr %0, %1, implicit-def dead %eflags<br>
+ %eax = COPY %2<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/global-value-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/global-value-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/global-value-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/global-value-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/global-value-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -62,91 +62,79 @@<br>
---<br>
# CHECK: name: inc<br>
name: inc<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: - '%rax = MOV64rm %rip, 1, _, @G, _'<br>
- - '%rax = MOV64rm %rip, 1, _, @G, _'<br>
- - '%eax = MOV32rm %rax, 1, _, 0, _'<br>
- - '%eax = INC32r %eax, implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: %rax = MOV64rm %rip, 1, _, @G, _<br>
+ %rax = MOV64rm %rip, 1, _, @G, _<br>
+ %eax = MOV32rm %rax, 1, _, 0, _<br>
+ %eax = INC32r %eax, implicit-def %eflags<br>
+ RETQ %eax<br>
...<br>
---<br>
# CHECK: name: inc2<br>
name: inc2<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: - '%rax = MOV64rm %rip, 1, _, @0, _'<br>
- - '%rax = MOV64rm %rip, 1, _, @0, _'<br>
- - '%eax = MOV32rm %rax, 1, _, 0, _'<br>
- - '%eax = INC32r %eax, implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: %rax = MOV64rm %rip, 1, _, @0, _<br>
+ %rax = MOV64rm %rip, 1, _, @0, _<br>
+ %eax = MOV32rm %rax, 1, _, 0, _<br>
+ %eax = INC32r %eax, implicit-def %eflags<br>
+ RETQ %eax<br>
...<br>
---<br>
name: test<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: , @".$0",<br>
- # CHECK: , @-_-,<br>
- # CHECK: , @_-_a,<br>
- # CHECK: , @"$.-B",<br>
- - '%rax = MOV64rm %rip, 1, _, @.$0, _'<br>
- - '%eax = MOV32rm killed %rax, 1, _, 0, _'<br>
- - '%rcx = MOV64rm %rip, 1, _, @-_-, _'<br>
- - 'MOV32mr killed %rcx, 1, _, 0, _, killed %eax'<br>
- - '%rax = MOV64rm %rip, 1, _, @_-_a, _'<br>
- - '%eax = MOV32rm killed %rax, 1, _, 0, _'<br>
- - '%rcx = MOV64rm %rip, 1, _, @$.-B, _'<br>
- - 'MOV32mr killed %rcx, 1, _, 0, _, %eax'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: , @".$0",<br>
+ ; CHECK: , @-_-,<br>
+ ; CHECK: , @_-_a,<br>
+ ; CHECK: , @"$.-B",<br>
+ %rax = MOV64rm %rip, 1, _, @.$0, _<br>
+ %eax = MOV32rm killed %rax, 1, _, 0, _<br>
+ %rcx = MOV64rm %rip, 1, _, @-_-, _<br>
+ MOV32mr killed %rcx, 1, _, 0, _, killed %eax<br>
+ %rax = MOV64rm %rip, 1, _, @_-_a, _<br>
+ %eax = MOV32rm killed %rax, 1, _, 0, _<br>
+ %rcx = MOV64rm %rip, 1, _, @$.-B, _<br>
+ MOV32mr killed %rcx, 1, _, 0, _, %eax<br>
+ RETQ %eax<br>
...<br>
---<br>
name: test2<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: , @"\01Hello@$%09 \5C World,",<br>
- - '%rax = MOV64rm %rip, 1, _, @"\01Hello@$%09 \\ World,", _'<br>
- - '%eax = MOV32rm killed %rax, 1, _, 0, _'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: , @"\01Hello@$%09 \5C World,",<br>
+ %rax = MOV64rm %rip, 1, _, @"\01Hello@$%09 \\ World,", _<br>
+ %eax = MOV32rm killed %rax, 1, _, 0, _<br>
+ RETQ %eax<br>
...<br>
---<br>
# CHECK: name: test3<br>
name: test3<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: , @".$0",<br>
- # CHECK: , @-_-,<br>
- # CHECK: , @_-_a + 4,<br>
- # CHECK: , @"$.-B" - 8,<br>
- - '%rax = MOV64rm %rip, 1, _, @.$0 + 0, _'<br>
- - '%eax = MOV32rm killed %rax, 1, _, 0, _'<br>
- - '%rcx = MOV64rm %rip, 1, _, @-_- - 0, _'<br>
- - 'MOV32mr killed %rcx, 1, _, 0, _, killed %eax'<br>
- - '%rax = MOV64rm %rip, 1, _, @_-_a + 4, _'<br>
- - '%eax = MOV32rm killed %rax, 1, _, 0, _'<br>
- - '%rcx = MOV64rm %rip, 1, _, @$.-B - 8, _'<br>
- - 'MOV32mr killed %rcx, 1, _, 0, _, %eax'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: , @".$0",<br>
+ ; CHECK: , @-_-,<br>
+ ; CHECK: , @_-_a + 4,<br>
+ ; CHECK: , @"$.-B" - 8,<br>
+ %rax = MOV64rm %rip, 1, _, @.$0 + 0, _<br>
+ %eax = MOV32rm killed %rax, 1, _, 0, _<br>
+ %rcx = MOV64rm %rip, 1, _, @-_- - 0, _<br>
+ MOV32mr killed %rcx, 1, _, 0, _, killed %eax<br>
+ %rax = MOV64rm %rip, 1, _, @_-_a + 4, _<br>
+ %eax = MOV32rm killed %rax, 1, _, 0, _<br>
+ %rcx = MOV64rm %rip, 1, _, @$.-B - 8, _<br>
+ MOV32mr killed %rcx, 1, _, 0, _, %eax<br>
+ RETQ %eax<br>
...<br>
---<br>
# CHECK: name: tf<br>
name: tf<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
-# CHECK: %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _<br>
- - '%rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _'<br>
- - '%eax = MOV32rm %rax, 1, _, 0, _'<br>
- - '%eax = INC32r %eax, implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _<br>
+ %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _<br>
+ %eax = MOV32rm %rax, 1, _, 0, _<br>
+ %eax = INC32r %eax, implicit-def %eflags<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/immediate-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/immediate-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/immediate-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/immediate-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/immediate-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,24 +17,20 @@<br>
---<br>
# CHECK: name: foo<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: - '%eax = MOV32ri 42'<br>
- # CHECK-NEXT: - 'RETQ %eax'<br>
- - '%eax = MOV32ri 42'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: %eax = MOV32ri 42<br>
+ ; CHECK-NEXT: RETQ %eax<br>
+ %eax = MOV32ri 42<br>
+ RETQ %eax<br>
...<br>
---<br>
# CHECK: name: bar<br>
name: bar<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: - '%eax = MOV32ri -11'<br>
- # CHECK-NEXT: - 'RETQ %eax'<br>
- - '%eax = MOV32ri -11'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: %eax = MOV32ri -11<br>
+ ; CHECK-NEXT: RETQ %eax<br>
+ %eax = MOV32ri -11<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir Thu Aug 13 18:10:16 2015<br>
@@ -19,24 +19,20 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.less', '%bb.2.exit' ]<br>
- instructions:<br>
- # CHECK: - 'CMP32ri8 %edi, 10, implicit-def %eflags'<br>
- # CHECK-NEXT: - 'JG_1 %bb.2.exit, implicit %eflags'<br>
- - 'CMP32ri8 %edi, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.2.exit, implicit %eflags'<br>
- - id: 1<br>
- name: less<br>
- instructions:<br>
- # CHECK: - '%eax = MOV32r0 implicit-def %eflags'<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
- - id: 2<br>
- name: exit<br>
- instructions:<br>
- - '%eax = COPY %edi'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.less, %bb.2.exit<br>
+ ; CHECK: CMP32ri8 %edi, 10, implicit-def %eflags<br>
+ ; CHECK-NEXT: JG_1 %bb.2.exit, implicit %eflags<br>
+ CMP32ri8 %edi, 10, implicit-def %eflags<br>
+ JG_1 %bb.2.exit, implicit %eflags<br>
+<br>
+ bb.1.less:<br>
+ ; CHECK: %eax = MOV32r0 implicit-def %eflags<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+ RETQ %eax<br>
+<br>
+ bb.2.exit:<br>
+ %eax = COPY %edi<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir Thu Aug 13 18:10:16 2015<br>
@@ -59,19 +59,17 @@ frameInfo:<br>
maxAlignment: 4<br>
stack:<br>
- { id: 0, name: x.addr, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- # CHECK: DBG_VALUE debug-use _, 0, !12, !13, debug-location !14<br>
- # CHECK: %eax = COPY %0, debug-location !15<br>
- # CHECK: RETQ %eax, debug-location !15<br>
- - '%0 = COPY %edi'<br>
- - 'DBG_VALUE debug-use _, 0, !12, !13, debug-location !14'<br>
- - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'<br>
- - '%eax = COPY %0, debug-location !15'<br>
- - 'RETQ %eax, debug-location !15'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %edi<br>
+ ; CHECK: DBG_VALUE debug-use _, 0, !12, !13, debug-location !14<br>
+ ; CHECK: %eax = COPY %0, debug-location !15<br>
+ ; CHECK: RETQ %eax, debug-location !15<br>
+ %0 = COPY %edi<br>
+ DBG_VALUE debug-use _, 0, !12, !13, debug-location !14<br>
+ MOV32mr %stack.0.x.addr, 1, _, 0, _, %0<br>
+ %eax = COPY %0, debug-location !15<br>
+ RETQ %eax, debug-location !15<br>
...<br>
---<br>
name: test_typed_immediates<br>
@@ -83,19 +81,18 @@ frameInfo:<br>
maxAlignment: 4<br>
stack:<br>
- { id: 0, name: x.addr, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
-# CHECK: DBG_VALUE _, i32 0, !12, !13<br>
-# CHECK-NEXT: DBG_VALUE _, i64 -22, !12, !13<br>
-# CHECK-NEXT: DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13<br>
- - 'DBG_VALUE _, i32 0, !12, !13'<br>
- - 'DBG_VALUE _, i64 -22, !12, !13'<br>
- - 'DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13'<br>
- - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'<br>
- - '%eax = COPY %0'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %edi<br>
+<br>
+ %0 = COPY %edi<br>
+ ; CHECK: DBG_VALUE _, i32 0, !12, !13<br>
+ ; CHECK-NEXT: DBG_VALUE _, i64 -22, !12, !13<br>
+ ; CHECK-NEXT: DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13<br>
+ DBG_VALUE _, i32 0, !12, !13<br>
+ DBG_VALUE _, i64 -22, !12, !13<br>
+ DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13<br>
+ MOV32mr %stack.0.x.addr, 1, _, 0, _, %0<br>
+ %eax = COPY %0<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,12 +16,10 @@ name: test<br>
constants:<br>
- id: 0<br>
value: 'double 3.250000e+00'<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:52: use of undefined constant '%const.10'<br>
- - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.10, _'<br>
- - 'RETQ %xmm0'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:47: use of undefined constant '%const.10'<br>
+ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.10, _<br>
+ RETQ %xmm0<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/invalid-target-flag-name.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/invalid-target-flag-name.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/invalid-target-flag-name.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/invalid-target-flag-name.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/invalid-target-flag-name.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@<br>
...<br>
---<br>
name: inc<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:50: use of undefined target flag 'x86-test'<br>
- - '%rax = MOV64rm %rip, 1, _, target-flags(x86-test) @G, _'<br>
- - '%eax = MOV32rm killed %rax, 1, _, 0, _'<br>
- - '%eax = INC32r killed %eax, implicit-def dead %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:45: use of undefined target flag 'x86-test'<br>
+ %rax = MOV64rm %rip, 1, _, target-flags(x86-test) @G, _<br>
+ %eax = MOV32rm killed %rax, 1, _, 0, _<br>
+ %eax = INC32r killed %eax, implicit-def dead %eflags<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir Thu Aug 13 18:10:16 2015<br>
@@ -68,48 +68,41 @@ jumpTable:<br>
entries:<br>
- id: 0<br>
blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.2.def', '%bb.1.entry' ]<br>
- instructions:<br>
- - '%eax = MOV32rr %edi, implicit-def %rax'<br>
- - 'CMP32ri8 %edi, 3, implicit-def %eflags'<br>
- - 'JA_1 %bb.2.def, implicit %eflags'<br>
- - id: 1<br>
- name: entry<br>
- successors: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]<br>
- instructions:<br>
- # CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _<br>
- - '%rcx = LEA64r %rip, 1, _, %jump-table.0, _'<br>
- - '%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _'<br>
- - '%rax = ADD64rr %rax, %rcx, implicit-def %eflags'<br>
- - 'JMP64r %rax'<br>
- - id: 2<br>
- name: def<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
- - id: 3<br>
- name: lbl1<br>
- instructions:<br>
- - '%eax = MOV32ri 1'<br>
- - 'RETQ %eax'<br>
- - id: 4<br>
- name: lbl2<br>
- instructions:<br>
- - '%eax = MOV32ri 2'<br>
- - 'RETQ %eax'<br>
- - id: 5<br>
- name: lbl3<br>
- instructions:<br>
- - '%eax = MOV32ri 4'<br>
- - 'RETQ %eax'<br>
- - id: 6<br>
- name: lbl4<br>
- instructions:<br>
- - '%eax = MOV32ri 8'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.2.def, %bb.1.entry<br>
+<br>
+ %eax = MOV32rr %edi, implicit-def %rax<br>
+ CMP32ri8 %edi, 3, implicit-def %eflags<br>
+ JA_1 %bb.2.def, implicit %eflags<br>
+<br>
+ bb.1.entry:<br>
+ successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4<br>
+ ; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _<br>
+ %rcx = LEA64r %rip, 1, _, %jump-table.0, _<br>
+ %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _<br>
+ %rax = ADD64rr %rax, %rcx, implicit-def %eflags<br>
+ JMP64r %rax<br>
+<br>
+ bb.2.def:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+ RETQ %eax<br>
+<br>
+ bb.3.lbl1:<br>
+ %eax = MOV32ri 1<br>
+ RETQ %eax<br>
+<br>
+ bb.4.lbl2:<br>
+ %eax = MOV32ri 2<br>
+ RETQ %eax<br>
+<br>
+ bb.5.lbl3:<br>
+ %eax = MOV32ri 4<br>
+ RETQ %eax<br>
+<br>
+ bb.6.lbl4:<br>
+ %eax = MOV32ri 8<br>
+ RETQ %eax<br>
...<br>
---<br>
name: test_jumptable2<br>
@@ -118,47 +111,40 @@ jumpTable:<br>
entries:<br>
- id: 1<br>
blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.2.def', '%bb.1.entry' ]<br>
- instructions:<br>
- - '%eax = MOV32rr %edi, implicit-def %rax'<br>
- - 'CMP32ri8 %edi, 3, implicit-def %eflags'<br>
- - 'JA_1 %bb.2.def, implicit %eflags'<br>
- - id: 1<br>
- name: entry<br>
- successors: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]<br>
- instructions:<br>
- # Verify that the printer will use an id of 0 for this jump table:<br>
- # CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _<br>
- - '%rcx = LEA64r %rip, 1, _, %jump-table.1, _'<br>
- - '%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _'<br>
- - '%rax = ADD64rr %rax, %rcx, implicit-def %eflags'<br>
- - 'JMP64r %rax'<br>
- - id: 2<br>
- name: def<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
- - id: 3<br>
- name: lbl1<br>
- instructions:<br>
- - '%eax = MOV32ri 1'<br>
- - 'RETQ %eax'<br>
- - id: 4<br>
- name: lbl2<br>
- instructions:<br>
- - '%eax = MOV32ri 2'<br>
- - 'RETQ %eax'<br>
- - id: 5<br>
- name: lbl3<br>
- instructions:<br>
- - '%eax = MOV32ri 4'<br>
- - 'RETQ %eax'<br>
- - id: 6<br>
- name: lbl4<br>
- instructions:<br>
- - '%eax = MOV32ri 8'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.2.def, %bb.1.entry<br>
+<br>
+ %eax = MOV32rr %edi, implicit-def %rax<br>
+ CMP32ri8 %edi, 3, implicit-def %eflags<br>
+ JA_1 %bb.2.def, implicit %eflags<br>
+<br>
+ bb.1.entry:<br>
+ successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4<br>
+ ; Verify that the printer will use an id of 0 for this jump table:<br>
+ ; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _<br>
+ %rcx = LEA64r %rip, 1, _, %jump-table.1, _<br>
+ %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _<br>
+ %rax = ADD64rr %rax, %rcx, implicit-def %eflags<br>
+ JMP64r %rax<br>
+<br>
+ bb.2.def:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+ RETQ %eax<br>
+<br>
+ bb.3.lbl1:<br>
+ %eax = MOV32ri 1<br>
+ RETQ %eax<br>
+<br>
+ bb.4.lbl2:<br>
+ %eax = MOV32ri 2<br>
+ RETQ %eax<br>
+<br>
+ bb.5.lbl3:<br>
+ %eax = MOV32ri 4<br>
+ RETQ %eax<br>
+<br>
+ bb.6.lbl4:<br>
+ %eax = MOV32ri 8<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -38,45 +38,39 @@ jumpTable:<br>
# CHECK: [[@LINE+1]]:18: redefinition of jump table entry '%jump-table.0'<br>
- id: 0<br>
blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.2.def', '%bb.1.entry' ]<br>
- instructions:<br>
- - '%eax = MOV32rr %edi, implicit-def %rax'<br>
- - 'CMP32ri8 %edi, 3, implicit-def %eflags'<br>
- - 'JA_1 %bb.2.def, implicit %eflags'<br>
- - id: 1<br>
- name: entry<br>
- successors: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]<br>
- instructions:<br>
- - '%rcx = LEA64r %rip, 1, _, %jump-table.0, _'<br>
- - '%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _'<br>
- - '%rax = ADD64rr %rax, %rcx, implicit-def %eflags'<br>
- - 'JMP64r %rax'<br>
- - id: 2<br>
- name: def<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
- - id: 3<br>
- name: lbl1<br>
- instructions:<br>
- - '%eax = MOV32ri 1'<br>
- - 'RETQ %eax'<br>
- - id: 4<br>
- name: lbl2<br>
- instructions:<br>
- - '%eax = MOV32ri 2'<br>
- - 'RETQ %eax'<br>
- - id: 5<br>
- name: lbl3<br>
- instructions:<br>
- - '%eax = MOV32ri 4'<br>
- - 'RETQ %eax'<br>
- - id: 6<br>
- name: lbl4<br>
- instructions:<br>
- - '%eax = MOV32ri 8'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.2.def, %bb.1.entry<br>
+<br>
+ %eax = MOV32rr %edi, implicit-def %rax<br>
+ CMP32ri8 %edi, 3, implicit-def %eflags<br>
+ JA_1 %bb.2.def, implicit %eflags<br>
+<br>
+ bb.1.entry:<br>
+ successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4<br>
+<br>
+ %rcx = LEA64r %rip, 1, _, %jump-table.0, _<br>
+ %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _<br>
+ %rax = ADD64rr %rax, %rcx, implicit-def %eflags<br>
+ JMP64r %rax<br>
+<br>
+ bb.2.def:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+ RETQ %eax<br>
+<br>
+ bb.3.lbl1:<br>
+ %eax = MOV32ri 1<br>
+ RETQ %eax<br>
+<br>
+ bb.4.lbl2:<br>
+ %eax = MOV32ri 2<br>
+ RETQ %eax<br>
+<br>
+ bb.5.lbl3:<br>
+ %eax = MOV32ri 4<br>
+ RETQ %eax<br>
+<br>
+ bb.6.lbl4:<br>
+ %eax = MOV32ri 8<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir Thu Aug 13 18:10:16 2015<br>
@@ -19,25 +19,22 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.less', '%bb.2.exit' ]<br>
- instructions:<br>
- - 'CMP32ri8 %edi, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.2.exit, implicit %eflags'<br>
- - id: 1<br>
- name: less<br>
- instructions:<br>
- # CHECK: - '%eax = MOV32r0<br>
- # CHECK-NEXT: - 'RETQ killed %eax<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - 'RETQ killed %eax'<br>
- - id: 2<br>
- name: exit<br>
- instructions:<br>
- # CHECK: - '%eax = COPY killed %edi<br>
- # CHECK-NEXT: - 'RETQ killed %eax<br>
- - '%eax = COPY killed %edi'<br>
- - 'RETQ killed %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.less, %bb.2.exit<br>
+<br>
+ CMP32ri8 %edi, 10, implicit-def %eflags<br>
+ JG_1 %bb.2.exit, implicit %eflags<br>
+<br>
+ bb.1.less:<br>
+ ; CHECK: %eax = MOV32r0<br>
+ ; CHECK-NEXT: RETQ killed %eax<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+ RETQ killed %eax<br>
+<br>
+ bb.2.exit:<br>
+ ; CHECK: %eax = COPY killed %edi<br>
+ ; CHECK-NEXT: RETQ killed %eax<br>
+ %eax = COPY killed %edi<br>
+ RETQ killed %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,14 +16,12 @@ frameInfo:<br>
stackSize: 4040<br>
stack:<br>
- { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags'<br>
- # CHECK: [[@LINE+1]]:46: expected a 32 bit integer (the cfi offset is too large)<br>
- - 'CFI_INSTRUCTION .cfi_def_cfa_offset 123456789123456'<br>
- - '%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags'<br>
- - 'RETQ'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags<br>
+ ; CHECK: [[@LINE+1]]:41: expected a 32 bit integer (the cfi offset is too large)<br>
+ CFI_INSTRUCTION .cfi_def_cfa_offset 123456789123456<br>
+ %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags<br>
+ RETQ<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/large-immediate-operand-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-immediate-operand-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-immediate-operand-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/large-immediate-operand-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/large-immediate-operand-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -10,11 +10,9 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:24: integer literal is too large to be an immediate operand<br>
- - '%eax = MOV32ri 12346127502983478823754212949184914'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:20: integer literal is too large to be an immediate operand<br>
+ %eax = MOV32ri 12346127502983478823754212949184914<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -18,18 +18,16 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, _'<br>
- - 'CMP32ri8 %eax, 10, implicit-def %eflags'<br>
- # CHECK: [[@LINE+1]]:14: expected 32-bit integer (too large)<br>
- - 'JG_1 %bb.123456789123456, implicit %eflags'<br>
- - id: 1<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - id: 2<br>
- instructions:<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %eax = MOV32rm %rdi, 1, _, 0, _<br>
+ CMP32ri8 %eax, 10, implicit-def %eflags<br>
+ ; CHECK: [[@LINE+1]]:10: expected 32-bit integer (too large)<br>
+ JG_1 %bb.123456789123456, implicit %eflags<br>
+<br>
+ bb.1:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+<br>
+ bb.2:<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/large-offset-number-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-offset-number-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-offset-number-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/large-offset-number-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/large-offset-number-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@<br>
...<br>
---<br>
name: inc<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:42: expected 64-bit integer (too large)<br>
- - '%rax = MOV64rm %rip, 1, _, @G + 123456789123456789123456789, _'<br>
- - '%eax = MOV32rm %rax, 1, _, 0, _'<br>
- - '%eax = INC32r %eax implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:37: expected 64-bit integer (too large)<br>
+ %rax = MOV64rm %rip, 1, _, @G + 123456789123456789123456789, _<br>
+ %eax = MOV32rm %rax, 1, _, 0, _<br>
+ %eax = INC32r %eax implicit-def %eflags<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@ name: test<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:58: expected 64-bit integer (too large)<br>
- - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a)'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: [[@LINE+1]]:53: expected 64-bit integer (too large)<br>
+ %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a)<br>
+ RETQ %eax<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir Thu Aug 13 18:10:16 2015<br>
@@ -26,18 +26,17 @@ frameInfo:<br>
hasCalls: true<br>
fixedStack:<br>
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi', '%rsi', '%rbp' ]<br>
- instructions:<br>
- - 'frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp'<br>
- - CFI_INSTRUCTION .cfi_def_cfa_offset 16<br>
- - 'CFI_INSTRUCTION .cfi_offset %rbp, -16'<br>
- - '%rbp = frame-setup MOV64rr %rsp'<br>
- - 'CFI_INSTRUCTION .cfi_def_cfa_register %rbp'<br>
-# CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl),<br>
- - 'PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax'<br>
- - '%rbp = POP64r implicit-def %rsp, implicit %rsp'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi, %rsi, %rbp<br>
+<br>
+ frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp<br>
+ CFI_INSTRUCTION .cfi_def_cfa_offset 16<br>
+ CFI_INSTRUCTION .cfi_offset %rbp, -16<br>
+ %rbp = frame-setup MOV64rr %rsp<br>
+ CFI_INSTRUCTION .cfi_def_cfa_register %rbp<br>
+ ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl),<br>
+ PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax<br>
+ %rbp = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -33,45 +33,41 @@<br>
---<br>
# CHECK: name: foo<br>
name: foo<br>
-body:<br>
- # CHECK: name: entry<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.less', '%bb.2.exit' ]<br>
- instructions:<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, _'<br>
- # CHECK: - 'CMP32ri8 %eax, 10<br>
- # CHECK-NEXT: - 'JG_1 %bb.2.exit<br>
- - 'CMP32ri8 %eax, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.2.exit, implicit %eflags'<br>
- # CHECK: name: less<br>
- - id: 1<br>
- name: less<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - id: 2<br>
- name: exit<br>
- instructions:<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ ; CHECK: bb.0.entry<br>
+ bb.0.entry:<br>
+ successors: %bb.1.less, %bb.2.exit<br>
+<br>
+ %eax = MOV32rm %rdi, 1, _, 0, _<br>
+ ; CHECK: CMP32ri8 %eax, 10<br>
+ ; CHECK-NEXT: JG_1 %bb.2.exit<br>
+ CMP32ri8 %eax, 10, implicit-def %eflags<br>
+ JG_1 %bb.2.exit, implicit %eflags<br>
+ ; CHECK: bb.1.less:<br>
+<br>
+ bb.1.less:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+<br>
+ bb.2.exit:<br>
+ RETQ %eax<br>
...<br>
---<br>
# CHECK: name: bar<br>
name: bar<br>
-body:<br>
- # CHECK: name: entry<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1', '%bb.3' ]<br>
- instructions:<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, _'<br>
- # CHECK: - 'CMP32ri8 %eax, 10<br>
- # CHECK-NEXT: - 'JG_1 %bb.2<br>
- - 'CMP32ri8 %eax, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.3, implicit %eflags'<br>
- - id: 1<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - id: 3<br>
- instructions:<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ ; CHECK: bb.0.entry:<br>
+ bb.0.entry:<br>
+ successors: %bb.1, %bb.3<br>
+<br>
+ %eax = MOV32rm %rdi, 1, _, 0, _<br>
+ ; CHECK: CMP32ri8 %eax, 10<br>
+ ; CHECK-NEXT: JG_1 %bb.2<br>
+ CMP32ri8 %eax, 10, implicit-def %eflags<br>
+ JG_1 %bb.3, implicit %eflags<br>
+<br>
+ bb.1:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+<br>
+ bb.3:<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/machine-instructions.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/machine-instructions.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/machine-instructions.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/machine-instructions.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/machine-instructions.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,12 +14,10 @@<br>
---<br>
# CHECK: name: inc<br>
name: inc<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: MOV32rr<br>
- # CHECK-NEXT: RETQ<br>
- - '%eax = MOV32rr %eax'<br>
- - ' RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: MOV32rr<br>
+ ; CHECK-NEXT: RETQ<br>
+ %eax = MOV32rr %eax<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/machine-verifier.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/machine-verifier.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/machine-verifier.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/machine-verifier.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/machine-verifier.mir Thu Aug 13 18:10:16 2015<br>
@@ -11,13 +11,11 @@<br>
...<br>
---<br>
name: inc<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- # CHECK: *** Bad machine code: Too few operands ***<br>
- # CHECK: instruction: COPY2 operands expected, but 0 given.<br>
- - 'COPY'<br>
- - 'RETQ'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %edi<br>
+ ; CHECK: *** Bad machine code: Too few operands ***<br>
+ ; CHECK: instruction: COPY2 operands expected, but 0 given.<br>
+ COPY<br>
+ RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -117,48 +117,42 @@ name: test<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a)<br>
-# CHECK-NEXT: MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a)'<br>
- - 'MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a)<br>
+ ; CHECK-NEXT: MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)<br>
+ %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a)<br>
+ MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)<br>
+ RETQ %eax<br>
...<br>
---<br>
name: test2<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry2<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")<br>
- - 'INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry2:<br>
+ liveins: %rdi<br>
+ ; CHECK: INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")<br>
+ INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")<br>
+ RETQ<br>
...<br>
---<br>
name: volatile_inc<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
- # CHECK: name: volatile_inc<br>
- # CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)<br>
- # CHECK: MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)'<br>
- - '%eax = INC32r killed %eax, implicit-def dead %eflags'<br>
- - 'MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: name: volatile_inc<br>
+ ; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)<br>
+ ; CHECK: MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)<br>
+ %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)<br>
+ %eax = INC32r killed %eax, implicit-def dead %eflags<br>
+ MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)<br>
+ RETQ %eax<br>
...<br>
---<br>
name: non_temporal_store<br>
@@ -166,76 +160,68 @@ tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
- { reg: '%esi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%esi', '%rdi' ]<br>
- instructions:<br>
-# CHECK: name: non_temporal_store<br>
-# CHECK: MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a)<br>
- - 'MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a)'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %esi, %rdi<br>
+ ; CHECK: name: non_temporal_store<br>
+ ; CHECK: MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a)<br>
+ MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a)<br>
+ RETQ<br>
...<br>
---<br>
name: invariant_load<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: name: invariant_load<br>
-# CHECK: %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)<br>
- - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: name: invariant_load<br>
+ ; CHECK: %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)<br>
+ %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)<br>
+ RETQ %eax<br>
...<br>
---<br>
name: memory_offset<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: name: memory_offset<br>
-# CHECK: %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec)<br>
-# CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)<br>
-# CHECK: MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec)<br>
-# CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16)<br>
- - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec)'<br>
- - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)'<br>
- - '%xmm2 = FsFLD0SS'<br>
- - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'<br>
- - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec)'<br>
- - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16)'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: name: memory_offset<br>
+ ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec)<br>
+ ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)<br>
+ ; CHECK: MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec)<br>
+ ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16)<br>
+ %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec)<br>
+ %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)<br>
+ %xmm2 = FsFLD0SS<br>
+ %xmm1 = MOVSSrr killed %xmm1, killed %xmm2<br>
+ MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec)<br>
+ MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16)<br>
+ RETQ<br>
...<br>
---<br>
name: memory_alignment<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: name: memory_alignment<br>
-# CHECK: %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)<br>
-# CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)<br>
-# CHECK: MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)<br>
-# CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)<br>
- - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)'<br>
- - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'<br>
- - '%xmm2 = FsFLD0SS'<br>
- - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'<br>
- - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'<br>
- - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: name: memory_alignment<br>
+ ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)<br>
+ ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)<br>
+ ; CHECK: MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)<br>
+ ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)<br>
+ %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)<br>
+ %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)<br>
+ %xmm2 = FsFLD0SS<br>
+ %xmm1 = MOVSSrr killed %xmm1, killed %xmm2<br>
+ MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)<br>
+ MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)<br>
+ RETQ<br>
...<br>
---<br>
name: constant_pool_psv<br>
@@ -245,17 +231,15 @@ liveins:<br>
constants:<br>
- id: 0<br>
value: 'double 3.250000e+00'<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%xmm0' ]<br>
- instructions:<br>
-# CHECK: name: constant_pool_psv<br>
-# CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool)<br>
-# CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)<br>
- - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool)'<br>
- - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)'<br>
- - 'RETQ %xmm0'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %xmm0<br>
+ ; CHECK: name: constant_pool_psv<br>
+ ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool)<br>
+ ; CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)<br>
+ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool)<br>
+ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)<br>
+ RETQ %xmm0<br>
...<br>
---<br>
name: stack_psv<br>
@@ -268,47 +252,41 @@ frameInfo:<br>
maxCallFrameSize: 16<br>
fixedStack:<br>
- { id: 0, offset: 0, size: 10, alignment: 16, isImmutable: true, isAliased: false }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags'<br>
- - CFI_INSTRUCTION .cfi_def_cfa_offset 32<br>
- - 'LD_F80m %rsp, 1, _, 32, _, implicit-def dead %fpsw'<br>
-# CHECK: name: stack_psv<br>
-# CHECK: ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)<br>
- - 'ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)'<br>
- - 'CALL64pcrel32 $cosl, csr_64, implicit %rsp, implicit-def %rsp, implicit-def %fp0'<br>
- - '%rsp = ADD64ri8 %rsp, 24, implicit-def dead %eflags'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ %rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags<br>
+ CFI_INSTRUCTION .cfi_def_cfa_offset 32<br>
+ LD_F80m %rsp, 1, _, 32, _, implicit-def dead %fpsw<br>
+ ; CHECK: name: stack_psv<br>
+ ; CHECK: ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)<br>
+ ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)<br>
+ CALL64pcrel32 $cosl, csr_64, implicit %rsp, implicit-def %rsp, implicit-def %fp0<br>
+ %rsp = ADD64ri8 %rsp, 24, implicit-def dead %eflags<br>
+ RETQ<br>
...<br>
---<br>
name: got_psv<br>
tracksRegLiveness: true<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
-# CHECK: name: got_psv<br>
-# CHECK: %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got)<br>
- - '%rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got)'<br>
- - '%eax = MOV32rm killed %rax, 1, _, 0, _'<br>
- - '%eax = INC32r killed %eax, implicit-def dead %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: name: got_psv<br>
+ ; CHECK: %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got)<br>
+ %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got)<br>
+ %eax = MOV32rm killed %rax, 1, _, 0, _<br>
+ %eax = INC32r killed %eax, implicit-def dead %eflags<br>
+ RETQ %eax<br>
...<br>
---<br>
name: global_value<br>
tracksRegLiveness: true<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%rax = MOV64rm %rip, 1, _, @G, _'<br>
-# CHECK: name: global_value<br>
-# CHECK: %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.G)<br>
- - '%eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.G)'<br>
- - '%eax = INC32r killed %eax, implicit-def dead %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %rax = MOV64rm %rip, 1, _, @G, _<br>
+ ; CHECK: name: global_value<br>
+ ; CHECK: %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.G)<br>
+ %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.G)<br>
+ %eax = INC32r killed %eax, implicit-def dead %eflags<br>
+ RETQ %eax<br>
...<br>
---<br>
name: jumptable_psv<br>
@@ -320,49 +298,43 @@ jumpTable:<br>
entries:<br>
- id: 0<br>
blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.2.def', '%bb.1.entry' ]<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%eax = MOV32rr %edi, implicit-def %rax'<br>
- - 'CMP32ri8 killed %edi, 3, implicit-def %eflags'<br>
- - 'JA_1 %bb.2.def, implicit killed %eflags'<br>
- - id: 1<br>
- name: entry<br>
- successors: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]<br>
- liveins: [ '%rax' ]<br>
- instructions:<br>
- - '%rcx = LEA64r %rip, 1, _, %jump-table.0, _'<br>
-# CHECK: name: jumptable_psv<br>
-# CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8)<br>
- - '%rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8)'<br>
- - '%rax = ADD64rr killed %rax, killed %rcx, implicit-def dead %eflags'<br>
- - 'JMP64r killed %rax'<br>
- - id: 2<br>
- name: def<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def dead %eflags'<br>
- - 'RETQ %eax'<br>
- - id: 3<br>
- name: lbl1<br>
- instructions:<br>
- - '%eax = MOV32ri 1'<br>
- - 'RETQ %eax'<br>
- - id: 4<br>
- name: lbl2<br>
- instructions:<br>
- - '%eax = MOV32ri 2'<br>
- - 'RETQ %eax'<br>
- - id: 5<br>
- name: lbl3<br>
- instructions:<br>
- - '%eax = MOV32ri 4'<br>
- - 'RETQ %eax'<br>
- - id: 6<br>
- name: lbl4<br>
- instructions:<br>
- - '%eax = MOV32ri 8'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.2.def, %bb.1.entry<br>
+ liveins: %edi<br>
+<br>
+ %eax = MOV32rr %edi, implicit-def %rax<br>
+ CMP32ri8 killed %edi, 3, implicit-def %eflags<br>
+ JA_1 %bb.2.def, implicit killed %eflags<br>
+<br>
+ bb.1.entry:<br>
+ successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4<br>
+ liveins: %rax<br>
+<br>
+ %rcx = LEA64r %rip, 1, _, %jump-table.0, _<br>
+ ; CHECK: name: jumptable_psv<br>
+ ; CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8)<br>
+ %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8)<br>
+ %rax = ADD64rr killed %rax, killed %rcx, implicit-def dead %eflags<br>
+ JMP64r killed %rax<br>
+<br>
+ bb.2.def:<br>
+ %eax = MOV32r0 implicit-def dead %eflags<br>
+ RETQ %eax<br>
+<br>
+ bb.3.lbl1:<br>
+ %eax = MOV32ri 1<br>
+ RETQ %eax<br>
+<br>
+ bb.4.lbl2:<br>
+ %eax = MOV32ri 2<br>
+ RETQ %eax<br>
+<br>
+ bb.5.lbl3:<br>
+ %eax = MOV32ri 4<br>
+ RETQ %eax<br>
+<br>
+ bb.6.lbl4:<br>
+ %eax = MOV32ri 8<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -50,16 +50,14 @@ frameInfo:<br>
maxAlignment: 4<br>
stack:<br>
- { id: 0, name: x.addr, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- # CHECK: %0 = COPY %edi<br>
- # CHECK-NEXT: DBG_VALUE _, 0, !12, !13<br>
- - '%0 = COPY %edi'<br>
- - 'DBG_VALUE _, 0, !12, ! 13'<br>
- - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'<br>
- - '%eax = COPY %0'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %edi<br>
+ ; CHECK: %0 = COPY %edi<br>
+ ; CHECK-NEXT: DBG_VALUE _, 0, !12, !13<br>
+ %0 = COPY %edi<br>
+ DBG_VALUE _, 0, !12, ! 13<br>
+ MOV32mr %stack.0.x.addr, 1, _, 0, _, %0<br>
+ %eax = COPY %0<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/missing-closing-quote.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-closing-quote.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-closing-quote.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/missing-closing-quote.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/missing-closing-quote.mir Thu Aug 13 18:10:16 2015<br>
@@ -13,12 +13,10 @@<br>
...<br>
---<br>
name: test<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:53: end of machine instruction reached before the closing '"'<br>
- - '%rax = MOV64rm %rip, 1, _, @"quoted name, _'<br>
- - '%eax = MOV32rm killed %rax, 1, _, 0, _'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:48: end of machine instruction reached before the closing '"'<br>
+ %rax = MOV64rm %rip, 1, _, @"quoted name, _<br>
+ %eax = MOV32rm killed %rax, 1, _, 0, _<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir Thu Aug 13 18:10:16 2015<br>
@@ -10,12 +10,10 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:29: expected ',' before the next machine operand<br>
- - '%eax = XOR32rr %eax %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:25: expected ',' before the next machine operand<br>
+ %eax = XOR32rr %eax %eflags<br>
+ RETQ %eax<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -21,21 +21,18 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.less', '%bb.2.exit' ]<br>
- instructions:<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, _'<br>
- - 'CMP32ri8 %eax, 10, implicit-def %eflags'<br>
-# CHECK: [[@LINE+1]]:24: missing implicit register operand 'implicit %eflags'<br>
- - 'JG_1 %bb.2.exit'<br>
- - id: 1<br>
- name: less<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - id: 2<br>
- name: exit<br>
- instructions:<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.less, %bb.2.exit<br>
+<br>
+ %eax = MOV32rm %rdi, 1, _, 0, _<br>
+ CMP32ri8 %eax, 10, implicit-def %eflags<br>
+ ; CHECK: [[@LINE+1]]:20: missing implicit register operand 'implicit %eflags'<br>
+ JG_1 %bb.2.exit<br>
+<br>
+ bb.1.less:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+<br>
+ bb.2.exit:<br>
+ RETQ %eax<br>
...<br>
<br>
Removed: llvm/trunk/test/CodeGen/MIR/X86/missing-instruction.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-instruction.mir?rev=244981&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-instruction.mir?rev=244981&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/missing-instruction.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/missing-instruction.mir (removed)<br>
@@ -1,19 +0,0 @@<br>
-# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
-<br>
---- |<br>
-<br>
- define void @foo() {<br>
- entry:<br>
- ret void<br>
- }<br>
-<br>
-...<br>
----<br>
-name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:9: expected a machine instruction<br>
- - ''<br>
-...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir Thu Aug 13 18:10:16 2015<br>
@@ -12,12 +12,10 @@<br>
---<br>
# CHECK: name: foo<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: - '%eax = MOV32r0<br>
- # CHECK-NEXT: - 'RETQ %eax<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: %eax = MOV32r0<br>
+ ; CHECK-NEXT: RETQ %eax<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+ RETQ %eax<br>
...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir?rev=244982&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir?rev=244982&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir Thu Aug 13 18:10:16 2015<br>
@@ -0,0 +1,109 @@<br>
+# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s<br>
+<br>
+--- |<br>
+<br>
+ define i32 @foo(i32 %a) {<br>
+ entry:<br>
+ %0 = icmp sle i32 %a, 10<br>
+ br i1 %0, label %less, label %exit<br>
+<br>
+ less:<br>
+ ret i32 0<br>
+<br>
+ exit:<br>
+ ret i32 %a<br>
+ }<br>
+<br>
+ define i32 @bar(i32 %a) {<br>
+ entry:<br>
+ %0 = icmp sle i32 %a, 10<br>
+ br i1 %0, label %less, label %exit<br>
+<br>
+ less:<br>
+ ret i32 0<br>
+<br>
+ exit:<br>
+ ret i32 %a<br>
+ }<br>
+<br>
+...<br>
+---<br>
+name: foo<br>
+tracksRegLiveness: true<br>
+liveins:<br>
+ - { reg: '%edi' }<br>
+# CHECK-LABEL: name: foo<br>
+# CHECK: body: |<br>
+# CHECK-NEXT: bb.0.entry:<br>
+# CHECK-NEXT: successors: %bb.1.less, %bb.2.exit<br>
+# CHECK-NEXT: liveins: %edi<br>
+# CHECK: CMP32ri8 %edi, 10, implicit-def %eflags<br>
+# CHECK-NEXT: JG_1 %bb.2.exit, implicit killed %eflags<br>
+<br>
+# CHECK: bb.1.less:<br>
+# CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags<br>
+# CHECK-NEXT: RETQ killed %eax<br>
+<br>
+# CHECK: bb.2.exit:<br>
+# CHECK-NEXT: liveins: %edi<br>
+# CHECK: %eax = COPY killed %edi<br>
+# CHECK-NEXT: RETQ killed %eax<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.less, %bb.2.exit<br>
+<br>
+ liveins: %edi<br>
+<br>
+ CMP32ri8 %edi, 10, implicit-def %eflags<br>
+<br>
+ JG_1 %bb.2.exit, implicit killed %eflags<br>
+<br>
+ bb.1.less:<br>
+<br>
+<br>
+ %eax = MOV32r0 implicit-def dead %eflags<br>
+ RETQ killed %eax<br>
+ bb.2.exit:<br>
+<br>
+<br>
+ liveins: %edi<br>
+ %eax = COPY killed %edi<br>
+ RETQ killed %eax<br>
+<br>
+...<br>
+---<br>
+name: bar<br>
+tracksRegLiveness: true<br>
+liveins:<br>
+ - { reg: '%edi' }<br>
+# CHECK-LABEL: name: bar<br>
+# CHECK: body: |<br>
+# CHECK-NEXT: bb.0.entry:<br>
+# CHECK-NEXT: successors: %bb.1.less, %bb.2.exit<br>
+# CHECK-NEXT: liveins: %edi<br>
+# CHECK: CMP32ri8 %edi, 10, implicit-def %eflags<br>
+# CHECK-NEXT: JG_1 %bb.2.exit, implicit killed %eflags<br>
+<br>
+# CHECK: bb.1.less:<br>
+# CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags<br>
+# CHECK-NEXT: RETQ killed %eax<br>
+<br>
+# CHECK: bb.2.exit:<br>
+# CHECK-NEXT: liveins: %edi<br>
+# CHECK: %eax = COPY killed %edi<br>
+# CHECK-NEXT: RETQ killed %eax<br>
+body: |<br>
+<br>
+ bb.0.entry:<br>
+ successors: %bb.1.less, %bb.2.exit<br>
+ liveins: %edi<br>
+ CMP32ri8 %edi, 10, implicit-def %eflags<br>
+ JG_1 %bb.2.exit, implicit killed %eflags<br>
+ bb.1.less: %eax = MOV32r0 implicit-def dead %eflags<br>
+ RETQ killed %eax<br>
+<br>
+ bb.2.exit: liveins: %edi<br>
+ %eax = COPY killed %edi<br>
+ RETQ killed %eax<br>
+<br>
+...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -13,12 +13,10 @@<br>
---<br>
# CHECK: name: deref<br>
name: deref<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: - '%eax = MOV32rm %rdi, 1, _, 0, _'<br>
- # CHECK-NEXT: - 'RETQ %eax'<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, %noreg'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _<br>
+ ; CHECK-NEXT: RETQ %eax<br>
+ %eax = MOV32rm %rdi, 1, _, 0, %noreg<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/register-mask-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/register-mask-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/register-mask-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/register-mask-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/register-mask-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -20,24 +20,20 @@<br>
...<br>
---<br>
name: compute<br>
-body:<br>
- - id: 0<br>
- name: body<br>
- instructions:<br>
- - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ %eax = IMUL32rri8 %edi, 11, implicit-def %eflags<br>
+ RETQ %eax<br>
...<br>
---<br>
# CHECK: name: foo<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: - 'PUSH64r %rax<br>
- # CHECK-NEXT: - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'<br>
- - 'PUSH64r %rax, implicit-def %rsp, implicit %rsp'<br>
- - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'<br>
- - '%rdx = POP64r implicit-def %rsp, implicit %rsp'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: PUSH64r %rax<br>
+ ; CHECK-NEXT: CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax<br>
+ PUSH64r %rax, implicit-def %rsp, implicit %rsp<br>
+ CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax<br>
+ %rdx = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@<br>
...<br>
---<br>
name: inc<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:47: register operands can't have target flags<br>
- - '%rax = MOV64rm target-flags(x86-got) %rip, 1, _, @G, _'<br>
- - '%eax = MOV32rm killed %rax, 1, _, 0, _'<br>
- - '%eax = INC32r killed %eax, implicit-def dead %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:42: register operands can't have target flags<br>
+ %rax = MOV64rm target-flags(x86-got) %rip, 1, _, @G, _<br>
+ %eax = MOV32rm killed %rax, 1, _, 0, _<br>
+ %eax = INC32r killed %eax, implicit-def dead %eflags<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir Thu Aug 13 18:10:16 2015<br>
@@ -22,14 +22,13 @@ registers:<br>
- { id: 0, class: gr32 }<br>
- { id: 1, class: gr32, preferred-register: '%esi' }<br>
- { id: 2, class: gr32, preferred-register: '%edi' }<br>
-body:<br>
- - id: 0<br>
- name: body<br>
- liveins: [ '%edi', '%esi' ]<br>
- instructions:<br>
- - '%1 = COPY %esi'<br>
- - '%2 = COPY %edi'<br>
- - '%2 = IMUL32rr %2, %1, implicit-def dead %eflags'<br>
- - '%eax = COPY %2'<br>
- - 'RETQ killed %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ liveins: %edi, %esi<br>
+<br>
+ %1 = COPY %esi<br>
+ %2 = COPY %edi<br>
+ %2 = IMUL32rr %2, %1, implicit-def dead %eflags<br>
+ %eax = COPY %2<br>
+ RETQ killed %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir Thu Aug 13 18:10:16 2015<br>
@@ -22,11 +22,9 @@ fixedStack:<br>
- { id: 0, type: spill-slot, offset: 0, size: 4, isAliased: true }<br>
stack:<br>
- { id: 0, offset: -12, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - 'MOV32mr %rsp, 1, _, -4, _, %edi'<br>
- - '%eax = COPY %edi'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ MOV32mr %rsp, 1, _, -4, _, %edi<br>
+ %eax = COPY %edi<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir Thu Aug 13 18:10:16 2015<br>
@@ -22,11 +22,9 @@ fixedStack:<br>
- { id: 0, type: spill-slot, offset: 0, size: 4, isImmutable: true }<br>
stack:<br>
- { id: 0, offset: -12, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - 'MOV32mr %rsp, 1, _, -4, _, %edi'<br>
- - '%eax = COPY %edi'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ MOV32mr %rsp, 1, _, -4, _, %edi<br>
+ %eax = COPY %edi<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir Thu Aug 13 18:10:16 2015<br>
@@ -24,11 +24,9 @@ fixedStack:<br>
- { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }<br>
stack:<br>
- { id: 0, offset: -12, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - 'MOV32mr %rsp, 1, _, -4, _, %edi'<br>
- - '%eax = COPY %edi'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ MOV32mr %rsp, 1, _, -4, _, %edi<br>
+ %eax = COPY %edi<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-object-invalid-name.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-invalid-name.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-invalid-name.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/stack-object-invalid-name.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-object-invalid-name.mir Thu Aug 13 18:10:16 2015<br>
@@ -20,11 +20,9 @@ frameInfo:<br>
stack:<br>
# CHECK: [[@LINE+1]]:20: alloca instruction named 'x' isn't defined in the function 'test'<br>
- { id: 0, name: x, offset: -12, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - 'MOV32mr %rsp, 1, _, -4, _, %edi'<br>
- - '%eax = MOV32rm %rsp, 1, _, -4, _'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ MOV32mr %rsp, 1, _, -4, _, %edi<br>
+ %eax = MOV32rm %rsp, 1, _, -4, _<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -23,13 +23,11 @@ frameInfo:<br>
maxAlignment: 4<br>
stack:<br>
- { id: 0, name: b, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
- # CHECK: [[@LINE+1]]:18: the name of the stack object '%stack.0' isn't 'x'<br>
- - 'MOV32mr %stack.0.x, 1, _, 0, _, %0'<br>
- - '%eax = COPY %0'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %0 = COPY %edi<br>
+ ; CHECK: [[@LINE+1]]:13: the name of the stack object '%stack.0' isn't 'x'<br>
+ MOV32mr %stack.0.x, 1, _, 0, _, %0<br>
+ %eax = COPY %0<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -29,20 +29,17 @@ fixedStack:<br>
stack:<br>
- { id: 0, name: b, size: 4, alignment: 4 }<br>
- { id: 1, size: 4, alignment: 4 }<br>
-body:<br>
- # CHECK: name: entry<br>
- # CHECK: instructions:<br>
- # CHECK-NEXT: - '%0 = MOV32rm %fixed-stack.0, 1, _, 0, _'<br>
- # CHECK-NEXT: - 'MOV32mr %stack.0.b, 1, _, 0, _, %0'<br>
- # CHECK-NEXT: - 'MOV32mi %stack.1, 1, _, 0, _, 2'<br>
- # CHECK-NEXT: - '%1 = MOV32rm %stack.0.b, 1, _, 0, _'<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%0 = MOV32rm %fixed-stack.0, 1, _, 0, _'<br>
- - 'MOV32mr %stack.0.b, 1, _, 0, _, %0'<br>
- - 'MOV32mi %stack.1, 1, _, 0, _, 2'<br>
- - '%1 = MOV32rm %stack.0, 1, _, 0, _'<br>
- - '%eax = COPY %1'<br>
- - 'RETL %eax'<br>
+body: |<br>
+ ; CHECK: bb.0.entry:<br>
+ ; CHECK-NEXT: %0 = MOV32rm %fixed-stack.0, 1, _, 0, _<br>
+ ; CHECK-NEXT: MOV32mr %stack.0.b, 1, _, 0, _, %0<br>
+ ; CHECK-NEXT: MOV32mi %stack.1, 1, _, 0, _, 2<br>
+ ; CHECK-NEXT: %1 = MOV32rm %stack.0.b, 1, _, 0, _<br>
+ bb.0.entry:<br>
+ %0 = MOV32rm %fixed-stack.0, 1, _, 0, _<br>
+ MOV32mr %stack.0.b, 1, _, 0, _, %0<br>
+ MOV32mi %stack.1, 1, _, 0, _, 2<br>
+ %1 = MOV32rm %stack.0, 1, _, 0, _<br>
+ %eax = COPY %1<br>
+ RETL %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -26,13 +26,12 @@ stack:<br>
- { id: 0, name: b, offset: -12, size: 4, alignment: 4 }<br>
# CHECK: [[@LINE+1]]:11: redefinition of stack object '%stack.0'<br>
- { id: 0, name: x, offset: -24, size: 8, alignment: 8 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - 'MOV32mr %rsp, 1, _, -4, _, killed %edi'<br>
- - 'MOV64mi32 %rsp, 1, _, -16, _, 2'<br>
- - '%eax = MOV32rm %rsp, 1, _, -4, _'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %edi<br>
+<br>
+ MOV32mr %rsp, 1, _, -4, _, killed %edi<br>
+ MOV64mi32 %rsp, 1, _, -16, _, 2<br>
+ %eax = MOV32rm %rsp, 1, _, -4, _<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir Thu Aug 13 18:10:16 2015<br>
@@ -28,12 +28,10 @@ stack:<br>
- { id: 0, name: b, offset: -12, size: 4, alignment: 4 }<br>
- { id: 1, name: x, offset: -24, size: 8, alignment: 8 }<br>
- { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - 'MOV32mr %rsp, 1, _, -4, _, %edi'<br>
- - 'MOV64mi32 %rsp, 1, _, -16, _, 2'<br>
- - '%eax = MOV32rm %rsp, 1, _, -4, _'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ MOV32mr %rsp, 1, _, -4, _, %edi<br>
+ MOV64mi32 %rsp, 1, _, -16, _, 2<br>
+ %eax = MOV32rm %rsp, 1, _, -4, _<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir Thu Aug 13 18:10:16 2015<br>
@@ -18,17 +18,15 @@ registers:<br>
- { id: 0, class: gr32 }<br>
- { id: 1, class: gr8 }<br>
- { id: 2, class: gr8 }<br>
-body:<br>
- - name: entry<br>
- id: 0<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- # CHECK: %0 = COPY %edi<br>
- # CHECK-NEXT: %1 = COPY %0:sub_8bit<br>
- - '%0 = COPY %edi'<br>
- - '%1 = COPY %0:sub_8bit'<br>
- - '%2 = AND8ri %1, 1, implicit-def %eflags'<br>
- - '%al = COPY %2'<br>
- - 'RETQ %al'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %edi<br>
+ ; CHECK: %0 = COPY %edi<br>
+ ; CHECK-NEXT: %1 = COPY %0:sub_8bit<br>
+ %0 = COPY %edi<br>
+ %1 = COPY %0:sub_8bit<br>
+ %2 = AND8ri %1, 1, implicit-def %eflags<br>
+ %al = COPY %2<br>
+ RETQ %al<br>
...<br>
<br>
<br>
Removed: llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-few-weights.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-few-weights.mir?rev=244981&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-few-weights.mir?rev=244981&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-few-weights.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-few-weights.mir (removed)<br>
@@ -1,41 +0,0 @@<br>
-# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
-<br>
---- |<br>
-<br>
- define i32 @foo(i32 %a) {<br>
- entry:<br>
- %0 = icmp sle i32 %a, 10<br>
- br i1 %0, label %less, label %exit<br>
-<br>
- less:<br>
- ret i32 0<br>
-<br>
- exit:<br>
- ret i32 %a<br>
- }<br>
-<br>
-...<br>
----<br>
-name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.less', '%bb.2.exit' ]<br>
-# CHECK: [[@LINE+1]]:23: too few successor weights, expected 2, have 1<br>
- weights: [ 16 ]<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - 'CMP32ri8 %edi, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.2.exit, implicit killed %eflags'<br>
- - id: 1<br>
- name: less<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def dead %eflags'<br>
- - 'RETQ killed %eax'<br>
- - id: 2<br>
- name: exit<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%eax = COPY killed %edi'<br>
- - 'RETQ killed %eax'<br>
-...<br>
<br>
Removed: llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-many-weights.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-many-weights.mir?rev=244981&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-many-weights.mir?rev=244981&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-many-weights.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-many-weights.mir (removed)<br>
@@ -1,41 +0,0 @@<br>
-# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
-<br>
---- |<br>
-<br>
- define i32 @foo(i32 %a) {<br>
- entry:<br>
- %0 = icmp sle i32 %a, 10<br>
- br i1 %0, label %less, label %exit<br>
-<br>
- less:<br>
- ret i32 0<br>
-<br>
- exit:<br>
- ret i32 %a<br>
- }<br>
-<br>
-...<br>
----<br>
-name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.less', '%bb.2.exit' ]<br>
-# CHECK: [[@LINE+1]]:28: too many successor weights, expected 2, have 3<br>
- weights: [ 16, 16, 16 ]<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - 'CMP32ri8 %edi, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.2.exit, implicit killed %eflags'<br>
- - id: 1<br>
- name: less<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def dead %eflags'<br>
- - 'RETQ killed %eax'<br>
- - id: 2<br>
- name: exit<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%eax = COPY killed %edi'<br>
- - 'RETQ killed %eax'<br>
-...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir Thu Aug 13 18:10:16 2015<br>
@@ -19,28 +19,24 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- # CHECK: name: entry<br>
- # CHECK: successors: [ '%bb.1.less', '%bb.2.exit' ]<br>
- # CHECK-NEXT: weights: [ 16, 32 ]<br>
- # CHECK: name: less<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.less', '%bb.2.exit' ]<br>
- weights: [ 16, 32 ]<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - 'CMP32ri8 %edi, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.2.exit, implicit killed %eflags'<br>
- - id: 1<br>
- name: less<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def dead %eflags'<br>
- - 'RETQ killed %eax'<br>
- - id: 2<br>
- name: exit<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%eax = COPY killed %edi'<br>
- - 'RETQ killed %eax'<br>
+body: |<br>
+ ; CHECK-LABEL: bb.0.entry:<br>
+ ; CHECK: successors: %bb.1.less(16), %bb.2.exit(32)<br>
+ ; CHECK-LABEL: bb.1.less:<br>
+ bb.0.entry:<br>
+ successors: %bb.1.less (16), %bb.2.exit(32)<br>
+ liveins: %edi<br>
+<br>
+ CMP32ri8 %edi, 10, implicit-def %eflags<br>
+ JG_1 %bb.2.exit, implicit killed %eflags<br>
+<br>
+ bb.1.less:<br>
+ %eax = MOV32r0 implicit-def dead %eflags<br>
+ RETQ killed %eax<br>
+<br>
+ bb.2.exit:<br>
+ liveins: %edi<br>
+<br>
+ %eax = COPY killed %edi<br>
+ RETQ killed %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir Thu Aug 13 18:10:16 2015<br>
@@ -30,51 +30,54 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- # CHECK: name: entry<br>
- # CHECK: successors: [ '%bb.1.less', '%bb.2.exit' ]<br>
- # CHECK: name: less<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.less', '%bb.2.exit' ]<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - 'CMP32ri8 %edi, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.2.exit, implicit killed %eflags'<br>
- - id: 1<br>
- name: less<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def dead %eflags'<br>
- - 'RETQ killed %eax'<br>
- - id: 2<br>
- name: exit<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%eax = COPY killed %edi'<br>
- - 'RETQ killed %eax'<br>
+body: |<br>
+ ; CHECK-LABEL: bb.0.entry:<br>
+ ; CHECK: successors: %bb.1.less, %bb.2.exit<br>
+ ; CHECK-LABEL: bb.1.less:<br>
+ bb.0.entry:<br>
+ successors: %bb.1.less, %bb.2.exit<br>
+ liveins: %edi<br>
+<br>
+ CMP32ri8 %edi, 10, implicit-def %eflags<br>
+ JG_1 %bb.2.exit, implicit killed %eflags<br>
+<br>
+ bb.1.less:<br>
+ %eax = MOV32r0 implicit-def dead %eflags<br>
+ RETQ killed %eax<br>
+<br>
+ bb.2.exit:<br>
+ liveins: %edi<br>
+<br>
+ %eax = COPY killed %edi<br>
+ RETQ killed %eax<br>
...<br>
---<br>
name: bar<br>
-body:<br>
- # CHECK: name: bar<br>
- # CHECK: name: entry<br>
- # CHECK: successors: [ '%bb.1', '%bb.2' ]<br>
- # CHECK: id: 1<br>
- # CHECK: id: 2<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1', '%bb.2' ]<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - 'CMP32ri8 %edi, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.2, implicit killed %eflags'<br>
- - id: 1<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def dead %eflags'<br>
- - 'RETQ killed %eax'<br>
- - id: 2<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%eax = COPY killed %edi'<br>
- - 'RETQ killed %eax'<br>
+body: |<br>
+ ; CHECK-LABEL: name: bar<br>
+ ; Verify that we can have multiple lists of successors that will be merged<br>
+ ; into one.<br>
+ ; CHECK-LABEL: bb.0.entry:<br>
+ ; CHECK: successors: %bb.1, %bb.2<br>
+ bb.0.entry:<br>
+ liveins: %edi<br>
+ successors: %bb.1<br>
+ successors: %bb.2<br>
+<br>
+ CMP32ri8 %edi, 10, implicit-def %eflags<br>
+ JG_1 %bb.2, implicit killed %eflags<br>
+<br>
+ ; Verify that we can have an empty list of successors.<br>
+ ; CHECK-LABEL: bb.1:<br>
+ ; CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags<br>
+ bb.1:<br>
+ successors:<br>
+ %eax = MOV32r0 implicit-def dead %eflags<br>
+ RETQ killed %eax<br>
+<br>
+ bb.2:<br>
+ liveins: %edi<br>
+<br>
+ %eax = COPY killed %edi<br>
+ RETQ killed %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/undef-register-flag.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undef-register-flag.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undef-register-flag.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/undef-register-flag.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/undef-register-flag.mir Thu Aug 13 18:10:16 2015<br>
@@ -21,22 +21,18 @@<br>
...<br>
---<br>
name: compute<br>
-body:<br>
- - id: 0<br>
- name: body<br>
- instructions:<br>
- - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ %eax = IMUL32rri8 %edi, 11, implicit-def %eflags<br>
+ RETQ %eax<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: - 'PUSH64r undef %rax<br>
- - 'PUSH64r undef %rax, implicit-def %rsp, implicit %rsp'<br>
- - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'<br>
- - '%rdx = POP64r implicit-def %rsp, implicit %rsp'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: PUSH64r undef %rax<br>
+ PUSH64r undef %rax, implicit-def %rsp, implicit %rsp<br>
+ CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax<br>
+ %rdx = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir Thu Aug 13 18:10:16 2015<br>
@@ -26,15 +26,13 @@ fixedStack:<br>
stack:<br>
- { id: 0, name: b, size: 4, alignment: 4 }<br>
- { id: 1, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:23: use of undefined fixed stack object '%fixed-stack.11'<br>
- - '%0 = MOV32rm %fixed-stack.11, 1, _, 0, _'<br>
- - 'MOV32mr %stack.0, 1, _, 0, _, %0'<br>
- - 'MOV32mi %stack.1, 1, _, 0, _, 2'<br>
- - '%1 = MOV32rm %stack.0, 1, _, 0, _'<br>
- - '%eax = COPY %1'<br>
- - 'RETL %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:18: use of undefined fixed stack object '%fixed-stack.11'<br>
+ %0 = MOV32rm %fixed-stack.11, 1, _, 0, _<br>
+ MOV32mr %stack.0, 1, _, 0, _, %0<br>
+ MOV32mi %stack.1, 1, _, 0, _, 2<br>
+ %1 = MOV32rm %stack.0, 1, _, 0, _<br>
+ %eax = COPY %1<br>
+ RETL %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-global-value.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-global-value.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-global-value.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-global-value.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-global-value.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,13 +16,11 @@<br>
...<br>
---<br>
name: inc<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:37: use of undefined global value '@2'<br>
- - '%rax = MOV64rm %rip, 1, _, @2, _'<br>
- - '%eax = MOV32rm %rax, 1, _, 0, _'<br>
- - '%eax = INC32r %eax'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:32: use of undefined global value '@2'<br>
+ %rax = MOV64rm %rip, 1, _, @2, _<br>
+ %eax = MOV32rm %rax, 1, _, 0, _<br>
+ %eax = INC32r %eax<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,18 +17,14 @@<br>
...<br>
---<br>
name: test<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1.block' ]<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:56: use of undefined IR block '%ir-block."block "'<br>
- - '%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block."block "), _'<br>
- - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'<br>
- - 'JMP64m %rip, 1, _, @addr, _'<br>
- - id: 1<br>
- name: block<br>
- addressTaken: true<br>
- instructions:<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1.block<br>
+ ; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block."block "'<br>
+ %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block."block "), _<br>
+ MOV64mr %rip, 1, _, @addr, _, killed %rax<br>
+ JMP64m %rip, 1, _, @addr, _<br>
+<br>
+ bb.1.block (address-taken):<br>
+ RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,17 +16,14 @@<br>
...<br>
---<br>
name: test<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.1' ]<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:56: use of undefined IR block '%ir-block.1'<br>
- - '%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.1), _'<br>
- - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'<br>
- - 'JMP64m %rip, 1, _, @addr, _'<br>
- - id: 1<br>
- addressTaken: true<br>
- instructions:<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1<br>
+ ; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block.1'<br>
+ %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.1), _<br>
+ MOV64mr %rip, 1, _, @addr, _, killed %rax<br>
+ JMP64m %rip, 1, _, @addr, _<br>
+<br>
+ bb.1 (address-taken):<br>
+ RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir Thu Aug 13 18:10:16 2015<br>
@@ -35,46 +35,39 @@ jumpTable:<br>
entries:<br>
- id: 0<br>
blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.2.def', '%bb.1.entry' ]<br>
- instructions:<br>
- - '%eax = MOV32rr %edi, implicit-def %rax'<br>
- - 'CMP32ri8 %edi, 3, implicit-def %eflags'<br>
- - 'JA_1 %bb.2.def, implicit %eflags'<br>
- - id: 1<br>
- name: entry<br>
- successors: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:36: use of undefined jump table '%jump-table.2'<br>
- - '%rcx = LEA64r %rip, 1, _, %jump-table.2, _'<br>
- - '%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _'<br>
- - '%rax = ADD64rr %rax, %rcx, implicit-def %eflags'<br>
- - 'JMP64r %rax'<br>
- - id: 2<br>
- name: def<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
- - id: 3<br>
- name: lbl1<br>
- instructions:<br>
- - '%eax = MOV32ri 1'<br>
- - 'RETQ %eax'<br>
- - id: 4<br>
- name: lbl2<br>
- instructions:<br>
- - '%eax = MOV32ri 2'<br>
- - 'RETQ %eax'<br>
- - id: 5<br>
- name: lbl3<br>
- instructions:<br>
- - '%eax = MOV32ri 4'<br>
- - 'RETQ %eax'<br>
- - id: 6<br>
- name: lbl4<br>
- instructions:<br>
- - '%eax = MOV32ri 8'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.2.def, %bb.1.entry<br>
+<br>
+ %eax = MOV32rr %edi, implicit-def %rax<br>
+ CMP32ri8 %edi, 3, implicit-def %eflags<br>
+ JA_1 %bb.2.def, implicit %eflags<br>
+<br>
+ bb.1.entry:<br>
+ successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4<br>
+ ; CHECK: [[@LINE+1]]:31: use of undefined jump table '%jump-table.2'<br>
+ %rcx = LEA64r %rip, 1, _, %jump-table.2, _<br>
+ %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _<br>
+ %rax = ADD64rr %rax, %rcx, implicit-def %eflags<br>
+ JMP64r %rax<br>
+<br>
+ bb.2.def:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+ RETQ %eax<br>
+<br>
+ bb.3.lbl1:<br>
+ %eax = MOV32ri 1<br>
+ RETQ %eax<br>
+<br>
+ bb.4.lbl2:<br>
+ %eax = MOV32ri 2<br>
+ RETQ %eax<br>
+<br>
+ bb.5.lbl3:<br>
+ %eax = MOV32ri 4<br>
+ RETQ %eax<br>
+<br>
+ bb.6.lbl4:<br>
+ %eax = MOV32ri 8<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-named-global-value.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-named-global-value.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-named-global-value.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-named-global-value.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-named-global-value.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,13 +16,11 @@<br>
...<br>
---<br>
name: inc<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:37: use of undefined global value '@GG'<br>
- - '%rax = MOV64rm %rip, 1, _, @GG, _'<br>
- - '%eax = MOV32rm %rax, 1, _, 0, _'<br>
- - '%eax = INC32r %eax'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:32: use of undefined global value '@GG'<br>
+ %rax = MOV64rm %rip, 1, _, @GG, _<br>
+ %eax = MOV32rm %rax, 1, _, 0, _<br>
+ %eax = INC32r %eax<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir Thu Aug 13 18:10:16 2015<br>
@@ -17,10 +17,8 @@ tracksRegLiveness: true<br>
registers:<br>
# CHECK: [[@LINE+1]]:20: use of undefined register class 'gr3200'<br>
- {id: 0, class: 'gr3200'}<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ RETQ %eax<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir Thu Aug 13 18:10:16 2015<br>
@@ -20,13 +20,11 @@ frameInfo:<br>
maxAlignment: 4<br>
stack:<br>
- { id: 0, name: b, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
- # CHECK: [[@LINE+1]]:18: use of undefined stack object '%stack.2'<br>
- - 'MOV32mr %stack.2, 1, _, 0, _, %0'<br>
- - '%eax = COPY %0'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %0 = COPY %edi<br>
+ ; CHECK: [[@LINE+1]]:13: use of undefined stack object '%stack.2'<br>
+ MOV32mr %stack.2, 1, _, 0, _, %0<br>
+ %eax = COPY %0<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir Thu Aug 13 18:10:16 2015<br>
@@ -14,13 +14,11 @@ name: test<br>
tracksRegLiveness: true<br>
liveins:<br>
- { reg: '%rdi' }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi' ]<br>
- instructions:<br>
-# CHECK: [[@LINE+1]]:65: use of undefined IR value '%ir.c'<br>
- - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.c)'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi<br>
+ ; CHECK: [[@LINE+1]]:60: use of undefined IR value '%ir.c'<br>
+ %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.c)<br>
+ RETQ %eax<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,13 +16,11 @@ isSSA: true<br>
tracksRegLiveness: true<br>
registers:<br>
- { id: 0, class: gr32 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
- # CHECK: [[@LINE+1]]:22: use of undefined virtual register '%10'<br>
- - '%eax = COPY %10'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %0 = COPY %edi<br>
+ ; CHECK: [[@LINE+1]]:17: use of undefined virtual register '%10'<br>
+ %eax = COPY %10<br>
+ RETQ %eax<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-instruction.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-instruction.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-instruction.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-instruction.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-instruction.mir Thu Aug 13 18:10:16 2015<br>
@@ -12,10 +12,8 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:8: unknown machine instruction name 'retJust0'<br>
- - retJust0<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:5: unknown machine instruction name 'retJust0'<br>
+ retJust0<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir Thu Aug 13 18:10:16 2015<br>
@@ -21,18 +21,16 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, _'<br>
- - 'CMP32ri8 %eax, 10, implicit-def %eflags'<br>
- # CHECK: [[@LINE+1]]:14: use of undefined machine basic block #4<br>
- - 'JG_1 %bb.4, implicit %eflags'<br>
- - id: 1<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - id: 2<br>
- instructions:<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %eax = MOV32rm %rdi, 1, _, 0, _<br>
+ CMP32ri8 %eax, 10, implicit-def %eflags<br>
+ ; CHECK: [[@LINE+1]]:10: use of undefined machine basic block #4<br>
+ JG_1 %bb.4, implicit %eflags<br>
+<br>
+ bb.1:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+<br>
+ bb.2:<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir Thu Aug 13 18:10:16 2015<br>
@@ -48,14 +48,12 @@ frameInfo:<br>
maxAlignment: 4<br>
stack:<br>
- { id: 0, name: x.addr, size: 4, alignment: 4 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
- # CHECK: [[@LINE+1]]:26: use of undefined metadata '!42'<br>
- - 'DBG_VALUE _, 0, !42, !13'<br>
- - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'<br>
- - '%eax = COPY %0'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %0 = COPY %edi<br>
+ ; CHECK: [[@LINE+1]]:21: use of undefined metadata '!42'<br>
+ DBG_VALUE _, 0, !42, !13<br>
+ MOV32mr %stack.0.x.addr, 1, _, 0, _, %0<br>
+ %eax = COPY %0<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir Thu Aug 13 18:10:16 2015<br>
@@ -20,20 +20,16 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - '%eax = MOV32rm %rdi, 1, _, 0, _'<br>
- - 'CMP32ri8 %eax, 10, implicit-def %eflags'<br>
- # CHECK: [[@LINE+1]]:14: the name of machine basic block #2 isn't 'hit'<br>
- - 'JG_1 %bb.2.hit, implicit %eflags'<br>
- - id: 1<br>
- name: less<br>
- instructions:<br>
- - '%eax = MOV32r0 implicit-def %eflags'<br>
- - id: 2<br>
- name: exit<br>
- instructions:<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %eax = MOV32rm %rdi, 1, _, 0, _<br>
+ CMP32ri8 %eax, 10, implicit-def %eflags<br>
+ ; CHECK: [[@LINE+1]]:10: the name of machine basic block #2 isn't 'hit'<br>
+ JG_1 %bb.2.hit, implicit %eflags<br>
+<br>
+ bb.1.less:<br>
+ %eax = MOV32r0 implicit-def %eflags<br>
+<br>
+ bb.2.exit:<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir Thu Aug 13 18:10:16 2015<br>
@@ -12,11 +12,9 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:9: unknown register name 'xax'<br>
- - '%xax = MOV32r0'<br>
- - 'RETQ %xax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:5: unknown register name 'xax'<br>
+ %xax = MOV32r0<br>
+ RETQ %xax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir Thu Aug 13 18:10:16 2015<br>
@@ -18,14 +18,12 @@ registers:<br>
- { id: 0, class: gr32 }<br>
- { id: 1, class: gr8 }<br>
- { id: 2, class: gr8 }<br>
-body:<br>
- - name: entry<br>
- id: 0<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
- # CHECK: [[@LINE+1]]:23: use of unknown subregister index 'bit8'<br>
- - '%1 = COPY %0:bit8'<br>
- - '%2 = AND8ri %1, 1, implicit-def %eflags'<br>
- - '%al = COPY %2'<br>
- - 'RETQ %al'<br>
+body: |<br>
+ bb.0.entry:<br>
+ %0 = COPY %edi<br>
+ ; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8'<br>
+ %1 = COPY %0:bit8<br>
+ %2 = AND8ri %1, 1, implicit-def %eflags<br>
+ %al = COPY %2<br>
+ RETQ %al<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/unrecognized-character.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unrecognized-character.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unrecognized-character.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/unrecognized-character.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/unrecognized-character.mir Thu Aug 13 18:10:16 2015<br>
@@ -10,10 +10,8 @@<br>
...<br>
---<br>
name: foo<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- # CHECK: [[@LINE+1]]:9: unexpected character '`'<br>
- - '` RETQ'<br>
+body: |<br>
+ bb.0.entry:<br>
+ ; CHECK: [[@LINE+1]]:5: unexpected character '`'<br>
+ ` RETQ<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/used-physical-register-info.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/used-physical-register-info.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/used-physical-register-info.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/used-physical-register-info.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/used-physical-register-info.mir Thu Aug 13 18:10:16 2015<br>
@@ -41,13 +41,12 @@ liveins:<br>
- { reg: '%edi' }<br>
frameInfo:<br>
stackSize: 8<br>
-body:<br>
- - id: 0<br>
- name: body<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ liveins: %edi<br>
+<br>
+ %eax = IMUL32rri8 %edi, 11, implicit-def %eflags<br>
+ RETQ %eax<br>
...<br>
---<br>
name: foo<br>
@@ -62,15 +61,14 @@ calleeSavedRegisters: [ '%bh', '%bl', '%<br>
'%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',<br>
'%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',<br>
'%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - 'PUSH64r %rax, implicit-def %rsp, implicit %rsp'<br>
- - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'<br>
- - '%rdx = POP64r implicit-def %rsp, implicit %rsp'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %edi<br>
+<br>
+ PUSH64r %rax, implicit-def %rsp, implicit %rsp<br>
+ CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax<br>
+ %rdx = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ %eax<br>
...<br>
---<br>
name: bar<br>
@@ -83,15 +81,14 @@ liveins:<br>
# CHECK-NEXT: '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',<br>
# CHECK-NEXT: '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',<br>
# CHECK-NEXT: '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - 'PUSH64r %rax, implicit-def %rsp, implicit %rsp'<br>
- - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'<br>
- - '%rdx = POP64r implicit-def %rsp, implicit %rsp'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %edi<br>
+<br>
+ PUSH64r %rax, implicit-def %rsp, implicit %rsp<br>
+ CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax<br>
+ %rdx = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ %eax<br>
...<br>
---<br>
name: empty<br>
@@ -101,13 +98,12 @@ liveins:<br>
# CHECK: name: empty<br>
# CHECK: calleeSavedRegisters: [ ]<br>
calleeSavedRegisters: [ ]<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - 'PUSH64r %rax, implicit-def %rsp, implicit %rsp'<br>
- - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'<br>
- - '%rdx = POP64r implicit-def %rsp, implicit %rsp'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %edi<br>
+<br>
+ PUSH64r %rax, implicit-def %rsp, implicit %rsp<br>
+ CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax<br>
+ %rdx = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -25,12 +25,10 @@ stack:<br>
- { id: 1, offset: -32, size: 8, alignment: 8 }<br>
# CHECK: [[@LINE+1]]:55: unknown key 'size'<br>
- { id: 2, type: variable-sized, offset: -32, size: 42, alignment: 1 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - 'MOV32mr %rsp, 1, _, -4, _, %edi'<br>
- - 'MOV64mi32 %rsp, 1, _, -16, _, 2'<br>
- - '%eax = MOV32rm %rsp, 1, _, -4, _'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ MOV32mr %rsp, 1, _, -4, _, %edi<br>
+ MOV64mi32 %rsp, 1, _, -16, _, 2<br>
+ %eax = MOV32rm %rsp, 1, _, -4, _<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir Thu Aug 13 18:10:16 2015<br>
@@ -31,12 +31,10 @@ stack:<br>
- { id: 0, offset: -20, size: 4, alignment: 4 }<br>
- { id: 1, offset: -32, size: 8, alignment: 8 }<br>
- { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- instructions:<br>
- - 'MOV32mr %rsp, 1, _, -4, _, %edi'<br>
- - 'MOV64mi32 %rsp, 1, _, -16, _, 2'<br>
- - '%eax = MOV32rm %rsp, 1, _, -4, _'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ MOV32mr %rsp, 1, _, -4, _, %edi<br>
+ MOV64mi32 %rsp, 1, _, -16, _, 2<br>
+ %eax = MOV32rm %rsp, 1, _, -4, _<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir Thu Aug 13 18:10:16 2015<br>
@@ -16,13 +16,12 @@ registers:<br>
- { id: 0, class: gr32 }<br>
# CHECK: [[@LINE+1]]:11: redefinition of virtual register '%0'<br>
- { id: 0, class: gr32 }<br>
-body:<br>
- - id: 0<br>
- name: body<br>
- liveins: [ '%edi' ]<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
- - '%eax = COPY %0'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.body:<br>
+ liveins: %edi<br>
+<br>
+ %0 = COPY %edi<br>
+ %eax = COPY %0<br>
+ RETQ %eax<br>
...<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir Thu Aug 13 18:10:16 2015<br>
@@ -41,31 +41,27 @@ registers:<br>
- { id: 0, class: gr32 }<br>
- { id: 1, class: gr32 }<br>
- { id: 2, class: gr32 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.2.exit', '%bb.1.less' ]<br>
- liveins: [ '%edi' ]<br>
- # CHECK: %0 = COPY %edi<br>
- # CHECK-NEXT: %1 = SUB32ri8 %0, 10<br>
- instructions:<br>
- - '%0 = COPY %edi'<br>
- - '%1 = SUB32ri8 %0, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.2.exit, implicit %eflags'<br>
- - 'JMP_1 %bb.1.less'<br>
- - id: 1<br>
- name: less<br>
- # CHECK: %2 = MOV32r0<br>
- # CHECK-NEXT: %eax = COPY %2<br>
- instructions:<br>
- - '%2 = MOV32r0 implicit-def %eflags'<br>
- - '%eax = COPY %2'<br>
- - 'RETQ %eax'<br>
- - id: 2<br>
- name: exit<br>
- instructions:<br>
- - '%eax = COPY %0'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.2.exit, %bb.1.less<br>
+ liveins: %edi<br>
+ ; CHECK: %0 = COPY %edi<br>
+ ; CHECK-NEXT: %1 = SUB32ri8 %0, 10<br>
+ %0 = COPY %edi<br>
+ %1 = SUB32ri8 %0, 10, implicit-def %eflags<br>
+ JG_1 %bb.2.exit, implicit %eflags<br>
+ JMP_1 %bb.1.less<br>
+<br>
+ bb.1.less:<br>
+ ; CHECK: %2 = MOV32r0<br>
+ ; CHECK-NEXT: %eax = COPY %2<br>
+ %2 = MOV32r0 implicit-def %eflags<br>
+ %eax = COPY %2<br>
+ RETQ %eax<br>
+<br>
+ bb.2.exit:<br>
+ %eax = COPY %0<br>
+ RETQ %eax<br>
...<br>
---<br>
name: foo<br>
@@ -80,30 +76,26 @@ registers:<br>
- { id: 2, class: gr32 }<br>
- { id: 0, class: gr32 }<br>
- { id: 10, class: gr32 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- successors: [ '%bb.2.exit', '%bb.1.less' ]<br>
- liveins: [ '%edi' ]<br>
- # CHECK: %0 = COPY %edi<br>
- # CHECK-NEXT: %1 = SUB32ri8 %0, 10<br>
- instructions:<br>
- - '%2 = COPY %edi'<br>
- - '%0 = SUB32ri8 %2, 10, implicit-def %eflags'<br>
- - 'JG_1 %bb.2.exit, implicit %eflags'<br>
- - 'JMP_1 %bb.1.less'<br>
- - id: 1<br>
- name: less<br>
- # CHECK: %2 = MOV32r0<br>
- # CHECK-NEXT: %eax = COPY %2<br>
- instructions:<br>
- - '%10 = MOV32r0 implicit-def %eflags'<br>
- - '%eax = COPY %10'<br>
- - 'RETQ %eax'<br>
- - id: 2<br>
- name: exit<br>
- # CHECK: %eax = COPY %0<br>
- instructions:<br>
- - '%eax = COPY %2'<br>
- - 'RETQ %eax'<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.2.exit, %bb.1.less<br>
+ liveins: %edi<br>
+ ; CHECK: %0 = COPY %edi<br>
+ ; CHECK-NEXT: %1 = SUB32ri8 %0, 10<br>
+ %2 = COPY %edi<br>
+ %0 = SUB32ri8 %2, 10, implicit-def %eflags<br>
+ JG_1 %bb.2.exit, implicit %eflags<br>
+ JMP_1 %bb.1.less<br>
+<br>
+ bb.1.less:<br>
+ ; CHECK: %2 = MOV32r0<br>
+ ; CHECK-NEXT: %eax = COPY %2<br>
+ %10 = MOV32r0 implicit-def %eflags<br>
+ %eax = COPY %10<br>
+ RETQ %eax<br>
+<br>
+ bb.2.exit:<br>
+ ; CHECK: %eax = COPY %0<br>
+ %eax = COPY %2<br>
+ RETQ %eax<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/expand-vr64-gr64-copy.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/expand-vr64-gr64-copy.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/expand-vr64-gr64-copy.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/expand-vr64-gr64-copy.mir (original)<br>
+++ llvm/trunk/test/CodeGen/X86/expand-vr64-gr64-copy.mir Thu Aug 13 18:10:16 2015<br>
@@ -18,20 +18,19 @@<br>
---<br>
name: test_pswapdsi<br>
tracksRegLiveness: true<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%xmm0' ]<br>
- instructions:<br>
- - '%xmm0 = PSHUFDri killed %xmm0, -24'<br>
- - 'MOVPQI2QImr %rsp, 1, _, -8, _, killed %xmm0'<br>
- - '%mm0 = PSWAPDrm %rsp, 1, _, -8, _'<br>
-# CHECK: %rax = MMX_MOVD64from64rr %mm0<br>
-# CHECK-NEXT: %mm0 = MMX_MOVD64to64rr %rax<br>
- - '%rax = COPY %mm0'<br>
- - '%mm0 = COPY %rax'<br>
- - 'MMX_MOVQ64mr %rsp, 1, _, -16, _, killed %mm0'<br>
- - '%xmm0 = MOVQI2PQIrm %rsp, 1, _, -16, _'<br>
- - '%xmm0 = PSHUFDri killed %xmm0, -44'<br>
- - 'RETQ %xmm0'<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %xmm0<br>
+<br>
+ %xmm0 = PSHUFDri killed %xmm0, -24<br>
+ MOVPQI2QImr %rsp, 1, _, -8, _, killed %xmm0<br>
+ %mm0 = PSWAPDrm %rsp, 1, _, -8, _<br>
+ ; CHECK: %rax = MMX_MOVD64from64rr %mm0<br>
+ ; CHECK-NEXT: %mm0 = MMX_MOVD64to64rr %rax<br>
+ %rax = COPY %mm0<br>
+ %mm0 = COPY %rax<br>
+ MMX_MOVQ64mr %rsp, 1, _, -16, _, killed %mm0<br>
+ %xmm0 = MOVQI2PQIrm %rsp, 1, _, -16, _<br>
+ %xmm0 = PSHUFDri killed %xmm0, -44<br>
+ RETQ %xmm0<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/patchpoint-verifiable.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/patchpoint-verifiable.mir?rev=244982&r1=244981&r2=244982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/patchpoint-verifiable.mir?rev=244982&r1=244981&r2=244982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/patchpoint-verifiable.mir (original)<br>
+++ llvm/trunk/test/CodeGen/X86/patchpoint-verifiable.mir Thu Aug 13 18:10:16 2015<br>
@@ -26,18 +26,17 @@ frameInfo:<br>
hasCalls: true<br>
fixedStack:<br>
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }<br>
-body:<br>
- - id: 0<br>
- name: entry<br>
- liveins: [ '%rdi', '%rsi', '%rbp' ]<br>
- instructions:<br>
- - 'frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp'<br>
- - CFI_INSTRUCTION .cfi_def_cfa_offset 16<br>
- - 'CFI_INSTRUCTION .cfi_offset %rbp, -16'<br>
- - '%rbp = frame-setup MOV64rr %rsp'<br>
- - 'CFI_INSTRUCTION .cfi_def_cfa_register %rbp'<br>
-# CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax<br>
- - 'PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax'<br>
- - '%rbp = POP64r implicit-def %rsp, implicit %rsp'<br>
- - RETQ<br>
+body: |<br>
+ bb.0.entry:<br>
+ liveins: %rdi, %rsi, %rbp<br>
+<br>
+ frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp<br>
+ CFI_INSTRUCTION .cfi_def_cfa_offset 16<br>
+ CFI_INSTRUCTION .cfi_offset %rbp, -16<br>
+ %rbp = frame-setup MOV64rr %rsp<br>
+ CFI_INSTRUCTION .cfi_def_cfa_register %rbp<br>
+ ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax<br>
+ PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax<br>
+ %rbp = POP64r implicit-def %rsp, implicit %rsp<br>
+ RETQ<br>
...<br>
<br>
<br>
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</blockquote></div><br></div>