<div dir="ltr"><br><div class="gmail_extra"><div class="gmail_quote">On Tue, Aug 11, 2015 at 5:06 AM, James Molloy via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: jamesm<br>
Date: Tue Aug 11 07:06:33 2015<br>
New Revision: 244594<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=244594&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=244594&view=rev</a><br>
Log:<br>
[AArch64] Replace the custom AArch64ISD::FMIN/MAX nodes with ISD::FMINNAN/MAXNAN<br>
<br>
NFCI. This just removes custom ISDNodes that are no longer needed.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h<br>
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=244594&r1=244593&r2=244594&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=244594&r1=244593&r2=244594&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Aug 11 07:06:33 2015<br>
@@ -679,6 +679,11 @@ void AArch64TargetLowering::addTypeForNE<br>
ISD::SABSDIFF, ISD::UABSDIFF})<br>
setOperationAction(Opcode, VT.getSimpleVT(), Legal);<br>
<br>
+ // F[MIN|MAX]NAN are available for all FP NEON types.<br>
+ if (VT.isFloatingPoint())<br>
+ for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN})<br>
+ setOperationAction(Opcode, VT.getSimpleVT(), Legal);<br>
+<br></blockquote><div><br></div><div>f16 shouldn't be Legal (the Expand default is fine, but Promote with the other f16 setOperationActions is better).</div><div><br></div><div>I guess this can't fire without D12015; when you land that, can you fix this and add an f{min,max}nan testcase to f16-instructions.ll (or elsewhere)?</div><div><br></div><div>Thanks!</div><div><br></div><div>-Ahmed</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
if (Subtarget->isLittleEndian()) {<br>
for (unsigned im = (unsigned)ISD::PRE_INC;<br>
im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {<br>
@@ -818,8 +823,6 @@ const char *AArch64TargetLowering::getTa<br>
case AArch64ISD::CCMN: return "AArch64ISD::CCMN";<br>
case AArch64ISD::FCCMP: return "AArch64ISD::FCCMP";<br>
case AArch64ISD::FCMP: return "AArch64ISD::FCMP";<br>
- case AArch64ISD::FMIN: return "AArch64ISD::FMIN";<br>
- case AArch64ISD::FMAX: return "AArch64ISD::FMAX";<br>
case AArch64ISD::DUP: return "AArch64ISD::DUP";<br>
case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";<br>
case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";<br>
@@ -8219,10 +8222,10 @@ static SDValue performIntrinsicCombine(S<br>
case Intrinsic::aarch64_neon_umaxv:<br>
return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);<br>
case Intrinsic::aarch64_neon_fmax:<br>
- return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),<br>
+ return DAG.getNode(ISD::FMAXNAN, SDLoc(N), N->getValueType(0),<br>
N->getOperand(1), N->getOperand(2));<br>
case Intrinsic::aarch64_neon_fmin:<br>
- return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),<br>
+ return DAG.getNode(ISD::FMINNAN, SDLoc(N), N->getValueType(0),<br>
N->getOperand(1), N->getOperand(2));<br>
case Intrinsic::aarch64_neon_sabd:<br>
return DAG.getNode(ISD::SABSDIFF, SDLoc(N), N->getValueType(0),<br>
@@ -9147,7 +9150,7 @@ static SDValue performSelectCCCombine(SD<br>
case ISD::SETLT:<br>
case ISD::SETLE:<br>
IsOrEqual = (CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE);<br>
- Opcode = IsReversed ? AArch64ISD::FMAX : AArch64ISD::FMIN;<br>
+ Opcode = IsReversed ? ISD::FMAXNAN : ISD::FMINNAN;<br>
break;<br>
<br>
case ISD::SETUGT:<br>
@@ -9158,7 +9161,7 @@ static SDValue performSelectCCCombine(SD<br>
case ISD::SETGT:<br>
case ISD::SETGE:<br>
IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE);<br>
- Opcode = IsReversed ? AArch64ISD::FMIN : AArch64ISD::FMAX;<br>
+ Opcode = IsReversed ? ISD::FMINNAN : ISD::FMAXNAN;<br>
break;<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=244594&r1=244593&r2=244594&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=244594&r1=244593&r2=244594&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h Tue Aug 11 07:06:33 2015<br>
@@ -66,10 +66,6 @@ enum NodeType : unsigned {<br>
// Floating point comparison<br>
FCMP,<br>
<br>
- // Floating point max and min instructions.<br>
- FMAX,<br>
- FMIN,<br>
-<br>
// Scalar extract<br>
EXTR,<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=244594&r1=244593&r2=244594&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=244594&r1=244593&r2=244594&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Tue Aug 11 07:06:33 2015<br>
@@ -182,9 +182,6 @@ def AArch64threadpointer : SDNode<"AArch<br>
<br>
def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;<br>
<br>
-def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;<br>
-def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;<br>
-<br>
def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;<br>
def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;<br>
def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;<br>
@@ -2506,18 +2503,18 @@ let SchedRW = [WriteFDiv] in {<br>
defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;<br>
}<br>
defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;<br>
-defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;<br>
+defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>;<br>
defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;<br>
-defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;<br>
+defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>;<br>
let SchedRW = [WriteFMul] in {<br>
defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;<br>
defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;<br>
}<br>
defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;<br>
<br>
-def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),<br>
+def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),<br>
(FMAXDrr FPR64:$Rn, FPR64:$Rm)>;<br>
-def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),<br>
+def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),<br>
(FMINDrr FPR64:$Rn, FPR64:$Rm)>;<br>
def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),<br>
(FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;<br>
@@ -2809,11 +2806,11 @@ defm FDIV : SIMDThreeSameVectorFP<1,0<br>
defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;<br>
defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;<br>
defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;<br>
-defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;<br>
+defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", fmaxnan>;<br>
defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;<br>
defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;<br>
defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;<br>
-defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;<br>
+defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", fminnan>;<br>
<br>
// NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the<br>
// instruction expects the addend first, while the fma intrinsic puts it last.<br>
<br>
<br>
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</blockquote></div><br></div></div>