<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head><meta http-equiv=Content-Type content="text/html; charset=us-ascii"><meta name=Generator content="Microsoft Word 15 (filtered medium)"><style><!--
/* Font Definitions */
@font-face
{font-family:Helvetica;
panose-1:2 11 6 4 2 2 2 2 2 4;}
@font-face
{font-family:"Cambria Math";
panose-1:2 4 5 3 5 4 6 3 2 4;}
@font-face
{font-family:Calibri;
panose-1:2 15 5 2 2 2 4 3 2 4;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0in;
margin-bottom:.0001pt;
font-size:12.0pt;
font-family:"Times New Roman",serif;}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:blue;
text-decoration:underline;}
a:visited, span.MsoHyperlinkFollowed
{mso-style-priority:99;
color:purple;
text-decoration:underline;}
span.apple-converted-space
{mso-style-name:apple-converted-space;}
span.EmailStyle18
{mso-style-type:personal-reply;
font-family:"Calibri",sans-serif;
color:#1F497D;}
.MsoChpDefault
{mso-style-type:export-only;
font-size:10.0pt;}
@page WordSection1
{size:8.5in 11.0in;
margin:1.0in 1.0in 1.0in 1.0in;}
div.WordSection1
{page:WordSection1;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1" />
</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Cool! Thanks for the quick response! Let me know if I can be of assistance..<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'> Quentin Colombet [mailto:qcolombet@apple.com] <br><b>Sent:</b> Friday, August 07, 2015 4:30 PM<br><b>To:</b> mcrosier@codeaurora.org<br><b>Cc:</b> llvm-commits@lists.llvm.org<br><b>Subject:</b> Re: [llvm] r231527 - [AArch64][LoadStoreOptimizer] Generate LDP + SXTW instead of LD[U]R + LD[U]RSW.<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Hi Chad,<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Nice catch.<o:p></o:p></p></div><div><p class=MsoNormal>There is indeed a potential bug here.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Looking if I can produce a test case to expose the problem.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Thanks,<o:p></o:p></p></div><div><p class=MsoNormal>-Quentin<o:p></o:p></p></div><div><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><p class=MsoNormal>On Aug 7, 2015, at 12:12 PM, Chad Rosier <<a href="mailto:mcrosier@codeaurora.org">mcrosier@codeaurora.org</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>+</span><a href="mailto:llvm-commits@lists.llvm.org"><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>llvm-commits@lists.llvm.org</span></a><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><br><br>Hi Quentin,<br>I was eyeballing this change and I'm concerned we're not properly tracking<br>what registers are being clobbered and used.<br><br>Inline comments below. Please let me know if I've missed something..<br><br> Chad<br><br>-----Original Message-----<br>From:<span class=apple-converted-space> </span></span><a href="mailto:llvm-commits-bounces@cs.uiuc.edu"><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>llvm-commits-bounces@cs.uiuc.edu</span></a><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><br>[</span><a href="mailto:llvm-commits-bounces@cs.uiuc.edu"><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>mailto:llvm-commits-bounces@cs.uiuc.edu</span></a><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>] On Behalf Of Quentin Colombet<br>Sent: Friday, March 06, 2015 5:42 PM<br>To:<span class=apple-converted-space> </span></span><a href="mailto:llvm-commits@cs.uiuc.edu"><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'>llvm-commits@cs.uiuc.edu</span></a><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><br>Subject: [llvm] r231527 - [AArch64][LoadStoreOptimizer] Generate LDP + SXTW<br>instead of LD[U]R + LD[U]RSW.<br><br>Author: qcolombet<br>Date: Fri Mar 6 16:42:10 2015<br>New Revision: 231527<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=231527&view=rev">http://llvm.org/viewvc/llvm-project?rev=231527&view=rev</a><br>Log:<br>[AArch64][LoadStoreOptimizer] Generate LDP + SXTW instead of LD[U]R +<br>LD[U]RSW.<br>Teach the load store optimizer how to sign extend a result of a load pair<br>when it helps creating more pairs.<br>The rational is that loads are more expensive than sign extensions, so if we<br>gather some in one instruction this is better!<br><br><<a href="rdar://problem/20072968">rdar://problem/20072968</a>><br><br>Modified:<br> llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp<br> llvm/trunk/test/CodeGen/AArch64/arm64-ldp.ll<br><br>Modified: llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp<br>URL:<br><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Loa">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Loa</a><br>dStoreOptimizer.cpp?rev=231527&r1=231526&r2=231527&view=diff<br>============================================================================<br>==<br>--- llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp (original)<br>+++ llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp Fri Mar<br>+++ 6 16:42:10 2015<br>@@ -63,16 +63,24 @@ struct AArch64LoadStoreOpt : public Mach<br> // If a matching instruction is found, MergeForward is set to true if the<br> // merge is to remove the first instruction and replace the second with<br> // a pair-wise insn, and false if the reverse is true.<br>+ // \p SExtIdx[out] gives the index of the result of the load pair<span class=apple-converted-space> </span><br>+ that // must be extended. The value of SExtIdx assumes that the<span class=apple-converted-space> </span><br>+ paired load // produces the value in this order: (I, returned<span class=apple-converted-space> </span><br>+ iterator), i.e., // -1 means no value has to be extended, 0 means I,<span class=apple-converted-space> </span><br>+ and 1 means the // returned iterator.<br> MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator<br>I,<br>- bool &MergeForward,<br>+ bool &MergeForward, int<span class=apple-converted-space> </span><br>+ &SExtIdx,<br> unsigned Limit);<br> // Merge the two instructions indicated into a single pair-wise<br>instruction.<br> // If MergeForward is true, erase the first instruction and fold its<br> // operation into the second. If false, the reverse. Return the<br>instruction<br> // following the first instruction (which may change during processing).<br>+ // \p SExtIdx index of the result that must be extended for a paired<br>load.<br>+ // -1 means none, 0 means I, and 1 means Paired.<br> MachineBasicBlock::iterator<br> mergePairedInsns(MachineBasicBlock::iterator I,<br>- MachineBasicBlock::iterator Paired, bool MergeForward);<br>+ MachineBasicBlock::iterator Paired, bool MergeForward,<br>+ int SExtIdx);<br><br> // Scan the instruction list to find a base register update that can<br> // be combined with the current instruction (a load or store) using @@<br>-181,6 +189,43 @@ int AArch64LoadStoreOpt::getMemSize(Mach<br> }<br>}<br><br>+static unsigned getMatchingNonSExtOpcode(unsigned Opc,<br>+ bool *IsValidLdStrOpc =<br>+nullptr) {<br>+ if (IsValidLdStrOpc)<br>+ *IsValidLdStrOpc = true;<br>+ switch (Opc) {<br>+ default:<br>+ if (IsValidLdStrOpc)<br>+ *IsValidLdStrOpc = false;<br>+ return UINT_MAX;<br>+ case AArch64::STRDui:<br>+ case AArch64::STURDi:<br>+ case AArch64::STRQui:<br>+ case AArch64::STURQi:<br>+ case AArch64::STRWui:<br>+ case AArch64::STURWi:<br>+ case AArch64::STRXui:<br>+ case AArch64::STURXi:<br>+ case AArch64::LDRDui:<br>+ case AArch64::LDURDi:<br>+ case AArch64::LDRQui:<br>+ case AArch64::LDURQi:<br>+ case AArch64::LDRWui:<br>+ case AArch64::LDURWi:<br>+ case AArch64::LDRXui:<br>+ case AArch64::LDURXi:<br>+ case AArch64::STRSui:<br>+ case AArch64::STURSi:<br>+ case AArch64::LDRSui:<br>+ case AArch64::LDURSi:<br>+ return Opc;<br>+ case AArch64::LDRSWui:<br>+ return AArch64::LDRWui;<br>+ case AArch64::LDURSWi:<br>+ return AArch64::LDURWi;<br>+ }<br>+}<br>+<br>static unsigned getMatchingPairOpcode(unsigned Opc) {<br> switch (Opc) {<br> default:<br>@@ -282,7 +327,7 @@ static unsigned getPostIndexedOpcode(uns<br>MachineBasicBlock::iterator<br>AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,<br> MachineBasicBlock::iterator Paired,<br>- bool MergeForward) {<br>+ bool MergeForward, int SExtIdx) {<br> MachineBasicBlock::iterator NextI = I;<br> ++NextI;<br> // If NextI is the second of the two instructions to be merged, we need<br>@@ -292,11 +337,13 @@ AArch64LoadStoreOpt::mergePairedInsns(Ma<br> if (NextI == Paired)<br> ++NextI;<br><br>- bool IsUnscaled = isUnscaledLdst(I->getOpcode());<br>+ unsigned Opc =<br>+ SExtIdx == -1 ? I->getOpcode() :<span class=apple-converted-space> </span><br>+ getMatchingNonSExtOpcode(I->getOpcode());<br>+ bool IsUnscaled = isUnscaledLdst(Opc);<br> int OffsetStride =<br> IsUnscaled && EnableAArch64UnscaledMemOp ? getMemSize(I) : 1;<br><br>- unsigned NewOpc = getMatchingPairOpcode(I->getOpcode());<br>+ unsigned NewOpc = getMatchingPairOpcode(Opc);<br> // Insert our new paired instruction after whichever of the paired<br> // instructions MergeForward indicates.<br> MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;<br>@@ -311,6 +358,11 @@ AArch64LoadStoreOpt::mergePairedInsns(Ma<br> Paired->getOperand(2).getImm() + OffsetStride) {<br> RtMI = Paired;<br> Rt2MI = I;<br>+ // Here we swapped the assumption made for SExtIdx.<br>+ // I.e., we turn ldp I, Paired into ldp Paired, I.<br>+ // Update the index accordingly.<br>+ if (SExtIdx != -1)<br>+ SExtIdx = (SExtIdx + 1) % 2;<br> } else {<br> RtMI = I;<br> Rt2MI = Paired;<br>@@ -337,8 +389,47 @@ AArch64LoadStoreOpt::mergePairedInsns(Ma<br> DEBUG(dbgs() << " ");<br> DEBUG(Paired->print(dbgs()));<br> DEBUG(dbgs() << " with instruction:\n ");<br>- DEBUG(((MachineInstr *)MIB)->print(dbgs()));<br>- DEBUG(dbgs() << "\n");<br>+<br>+ if (SExtIdx != -1) {<br>+ // Generate the sign extension for the proper result of the ldp.<br>+ // I.e., with X1, that would be:<br>+ // %W1<def> = KILL %W1, %X1<imp-def><br>+ // %X1<def> = SBFMXri %X1<kill>, 0, 31<br>+ MachineOperand &DstMO = MIB->getOperand(SExtIdx);<br>+ // Right now, DstMO has the extended register, since it comes from an<br>+ // extended opcode.<br>+ unsigned DstRegX = DstMO.getReg();<br>+ // Get the W variant of that register.<br>+ unsigned DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32);<br>+ // Update the result of LDP to use the W instead of the X variant.<br>+ DstMO.setReg(DstRegW);<br>+ DEBUG(((MachineInstr *)MIB)->print(dbgs()));<br>+ DEBUG(dbgs() << "\n");<br>+ // Make the machine verifier happy by providing a definition for<br>+ // the X register.<br>+ // Insert this definition right after the generated LDP, i.e., before<br>+ // InsertionPoint.<br>+ MachineInstrBuilder MIBKill =<br>+ BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),<br>+ TII->get(TargetOpcode::KILL), DstRegW)<br>+ .addReg(DstRegW)<br>+ .addReg(DstRegX, RegState::Define);<br>+ MIBKill->getOperand(2).setImplicit();<br>+ // Create the sign extension.<br>+ MachineInstrBuilder MIBSXTW =<br>+ BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),<br>+ TII->get(AArch64::SBFMXri), DstRegX)<br>+ .addReg(DstRegX)<br>+ .addImm(0)<br>+ .addImm(31);<br>+ (void)MIBSXTW;<br>+ DEBUG(dbgs() << " Extend operand:\n ");<br>+ DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs()));<br>+ DEBUG(dbgs() << "\n");<br>+ } else {<br>+ DEBUG(((MachineInstr *)MIB)->print(dbgs()));<br>+ DEBUG(dbgs() << "\n");<br>+ }<br><br> // Erase the old instructions.<br> I->eraseFromParent();<br>@@ -396,7 +487,8 @@ static int alignTo(int Num, int PowOf2) /// be combined<br>with the current instruction into a load/store pair.<br>MachineBasicBlock::iterator<br>AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,<br>- bool &MergeForward, unsigned Limit) {<br>+ bool &MergeForward, int &SExtIdx,<br>+ unsigned Limit) {<br> MachineBasicBlock::iterator E = I->getParent()->end();<br> MachineBasicBlock::iterator MBBI = I;<br> MachineInstr *FirstMI = I;<br>@@ -436,7 +528,19 @@ AArch64LoadStoreOpt::findMatchingInsn(Ma<br> // Now that we know this is a real instruction, count it.<br> ++Count;<br><br>- if (Opc == MI->getOpcode() && MI->getOperand(2).isImm()) {<br>+ bool CanMergeOpc = Opc == MI->getOpcode();<br>+ SExtIdx = -1;<br>+ if (!CanMergeOpc) {<br>+ bool IsValidLdStrOpc;<br>+ unsigned NonSExtOpc = getMatchingNonSExtOpcode(Opc,<br>&IsValidLdStrOpc);<br>+ if (!IsValidLdStrOpc)<br><br>I believe we need to add the below code on the continue path to ensure the<br>register defs/uses and memory operations are tracked correctly.<br><br> trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);<br> if (MI->mayLoadOrStore())<br> MemInsns.push_back(MI);<br><br>Alternatively, we could allow the control flow to fall thru to the logic at<br>the end of the for loop that takes care of the above logic but negating the<br>condtion. Something like..<br><br> if (IsValidLdStrOpc) {<br> // Opc will be the first instruction in the pair.<br> SExtIdx = NonSExtOpc == (unsigned)Opc ? 1 : 0;<br> CanMergeOpc = NonSExtOpc ==<br>getMatchingNonSExtOpcode(MI->getOpcode());<br> }<br><br>Please let me know your thoughts, Quentin. Again this is just something I<br>saw in passing and haven't proven it's actually a problem.<br><br>Chad<br><br>+ continue;<br>+ // Opc will be the first instruction in the pair.<br>+ SExtIdx = NonSExtOpc == (unsigned)Opc ? 1 : 0;<br>+ CanMergeOpc = NonSExtOpc ==<br>getMatchingNonSExtOpcode(MI->getOpcode());<br>+ }<br>+<br>+ if (CanMergeOpc && MI->getOperand(2).isImm()) {<br> // If we've found another instruction with the same opcode, check to<br>see<br> // if the base and offset are compatible with our starting<br>instruction.<br> // These instructions all have scaled immediate operands, so we just<br>@@ -823,13 +927,14 @@ bool AArch64LoadStoreOpt::optimizeBlock(<br> }<br> // Look ahead up to ScanLimit instructions for a pairable<br>instruction.<br> bool MergeForward = false;<br>+ int SExtIdx = -1;<br> MachineBasicBlock::iterator Paired =<br>- findMatchingInsn(MBBI, MergeForward, ScanLimit);<br>+ findMatchingInsn(MBBI, MergeForward, SExtIdx, ScanLimit);<br> if (Paired != E) {<br> // Merge the loads into a pair. Keeping the iterator straight is a<br> // pain, so we let the merge routine tell us what the next<br>instruction<br> // is after it's done mucking about.<br>- MBBI = mergePairedInsns(MBBI, Paired, MergeForward);<br>+ MBBI = mergePairedInsns(MBBI, Paired, MergeForward, SExtIdx);<br><br> Modified = true;<br> ++NumPairCreated;<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/arm64-ldp.ll<br>URL:<br><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ld">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ld</a><br>p.ll?rev=231527&r1=231526&r2=231527&view=diff<br>============================================================================<br>==<br>--- llvm/trunk/test/CodeGen/AArch64/arm64-ldp.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/arm64-ldp.ll Fri Mar 6 16:42:10<br>+++ 2015<br>@@ -24,6 +24,33 @@ define i64 @ldp_sext_int(i32* %p) nounwi<br> ret i64 %add<br>}<br><br>+; CHECK-LABEL: ldp_half_sext_res0_int:<br>+; CHECK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0]<br>+; CHECK: sxtw x[[DST1]], w[[DST1]]<br>+define i64 @ldp_half_sext_res0_int(i32* %p) nounwind {<br>+ %tmp = load i32, i32* %p, align 4<br>+ %add.ptr = getelementptr inbounds i32, i32* %p, i64 1<br>+ %tmp1 = load i32, i32* %add.ptr, align 4<br>+ %sexttmp = sext i32 %tmp to i64<br>+ %sexttmp1 = zext i32 %tmp1 to i64<br>+ %add = add nsw i64 %sexttmp1, %sexttmp<br>+ ret i64 %add<br>+}<br>+<br>+; CHECK-LABEL: ldp_half_sext_res1_int:<br>+; CHECK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0]<br>+; CHECK: sxtw x[[DST2]], w[[DST2]]<br>+define i64 @ldp_half_sext_res1_int(i32* %p) nounwind {<br>+ %tmp = load i32, i32* %p, align 4<br>+ %add.ptr = getelementptr inbounds i32, i32* %p, i64 1<br>+ %tmp1 = load i32, i32* %add.ptr, align 4<br>+ %sexttmp = zext i32 %tmp to i64<br>+ %sexttmp1 = sext i32 %tmp1 to i64<br>+ %add = add nsw i64 %sexttmp1, %sexttmp<br>+ ret i64 %add<br>+}<br>+<br>+<br>; CHECK: ldp_long<br>; CHECK: ldp<br>define i64 @ldp_long(i64* %p) nounwind { @@ -83,6 +110,39 @@ define i64<br>@ldur_sext_int(i32* %a) nounw<br> ret i64 %tmp3<br>}<br><br>+define i64 @ldur_half_sext_int_res0(i32* %a) nounwind { ; LDUR_CHK:<span class=apple-converted-space> </span><br>+ldur_half_sext_int_res0<br>+; LDUR_CHK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-8]<br>+; LDUR_CHK: sxtw x[[DST1]], w[[DST1]]<br>+; LDUR_CHK-NEXT: add x{{[0-9]+}}, x[[DST2]], x[[DST1]]<br>+; LDUR_CHK-NEXT: ret<br>+ %p1 = getelementptr inbounds i32, i32* %a, i32 -1<br>+ %tmp1 = load i32, i32* %p1, align 2<br>+ %p2 = getelementptr inbounds i32, i32* %a, i32 -2<br>+ %tmp2 = load i32, i32* %p2, align 2<br>+ %sexttmp1 = zext i32 %tmp1 to i64<br>+ %sexttmp2 = sext i32 %tmp2 to i64<br>+ %tmp3 = add i64 %sexttmp1, %sexttmp2<br>+ ret i64 %tmp3<br>+}<br>+<br>+define i64 @ldur_half_sext_int_res1(i32* %a) nounwind { ; LDUR_CHK:<span class=apple-converted-space> </span><br>+ldur_half_sext_int_res1<br>+; LDUR_CHK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-8]<br>+; LDUR_CHK: sxtw x[[DST2]], w[[DST2]]<br>+; LDUR_CHK-NEXT: add x{{[0-9]+}}, x[[DST2]], x[[DST1]]<br>+; LDUR_CHK-NEXT: ret<br>+ %p1 = getelementptr inbounds i32, i32* %a, i32 -1<br>+ %tmp1 = load i32, i32* %p1, align 2<br>+ %p2 = getelementptr inbounds i32, i32* %a, i32 -2<br>+ %tmp2 = load i32, i32* %p2, align 2<br>+ %sexttmp1 = sext i32 %tmp1 to i64<br>+ %sexttmp2 = zext i32 %tmp2 to i64<br>+ %tmp3 = add i64 %sexttmp1, %sexttmp2<br>+ ret i64 %tmp3<br>+}<br>+<br>+<br>define i64 @ldur_long(i64* %a) nounwind ssp { ; LDUR_CHK: ldur_long<br>; LDUR_CHK: ldp [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-16]<br>@@ -152,6 +212,40 @@ define i64 @pairUpBarelyInSext(i32* %a)<br> %tmp3 = add i64 %sexttmp1, %sexttmp2<br> ret i64 %tmp3<br>}<br>+<br>+define i64 @pairUpBarelyInHalfSextRes0(i32* %a) nounwind ssp { ;<br>+LDUR_CHK: pairUpBarelyInHalfSextRes0 ; LDUR_CHK-NOT: ldur<br>+; LDUR_CHK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-256]<br>+; LDUR_CHK: sxtw x[[DST1]], w[[DST1]]<br>+; LDUR_CHK-NEXT: add x{{[0-9]+}}, x[[DST2]], x[[DST1]]<br>+; LDUR_CHK-NEXT: ret<br>+ %p1 = getelementptr inbounds i32, i32* %a, i64 -63<br>+ %tmp1 = load i32, i32* %p1, align 2<br>+ %p2 = getelementptr inbounds i32, i32* %a, i64 -64<br>+ %tmp2 = load i32, i32* %p2, align 2<br>+ %sexttmp1 = zext i32 %tmp1 to i64<br>+ %sexttmp2 = sext i32 %tmp2 to i64<br>+ %tmp3 = add i64 %sexttmp1, %sexttmp2<br>+ ret i64 %tmp3<br>+}<br>+<br>+define i64 @pairUpBarelyInHalfSextRes1(i32* %a) nounwind ssp { ;<br>+LDUR_CHK: pairUpBarelyInHalfSextRes1 ; LDUR_CHK-NOT: ldur<br>+; LDUR_CHK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-256]<br>+; LDUR_CHK: sxtw x[[DST2]], w[[DST2]]<br>+; LDUR_CHK-NEXT: add x{{[0-9]+}}, x[[DST2]], x[[DST1]]<br>+; LDUR_CHK-NEXT: ret<br>+ %p1 = getelementptr inbounds i32, i32* %a, i64 -63<br>+ %tmp1 = load i32, i32* %p1, align 2<br>+ %p2 = getelementptr inbounds i32, i32* %a, i64 -64<br>+ %tmp2 = load i32, i32* %p2, align 2<br>+ %sexttmp1 = sext i32 %tmp1 to i64<br>+ %sexttmp2 = zext i32 %tmp2 to i64<br>+ %tmp3 = add i64 %sexttmp1, %sexttmp2<br>+ ret i64 %tmp3<br>+}<br><br>define i64 @pairUpBarelyOut(i64* %a) nounwind ssp { ; LDUR_CHK:<br>pairUpBarelyOut<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a></span><o:p></o:p></p></div></blockquote></div><p class=MsoNormal><o:p> </o:p></p></div></div></body></html>