<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Yup, will be part of the proper fix :)<div class=""><br class=""></div><div class="">—Juergen<br class=""><div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Aug 6, 2015, at 3:15 PM, Eric Christopher <<a href="mailto:echristo@gmail.com" class="">echristo@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Got a testcase for the revert? :)<div class=""><br class=""></div><div class="">-eric</div></div><br class=""><div class="gmail_quote"><div dir="ltr" class="">On Thu, Aug 6, 2015 at 3:14 PM Juergen Ributzka via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ributzka<br class="">
Date: Thu Aug 6 17:13:48 2015<br class="">
New Revision: 244287<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=244287&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=244287&view=rev</a><br class="">
Log:<br class="">
Revert "[AArch64][FastISel] Add more truncation tests." and "[AArch64][FastISel] Always use an AND instruction when truncating to non-legal types."<br class="">
<br class="">
This reverts commit r243198 and 243304.<br class="">
<br class="">
Turns out this wasn't the correct fix for this problem. It works only within<br class="">
FastISel, but fails when the truncate is selected by SDAG.<br class="">
<br class="">
Modified:<br class="">
llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp<br class="">
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll<br class="">
llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=244287&r1=244286&r2=244287&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=244287&r1=244286&r2=244287&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Thu Aug 6 17:13:48 2015<br class="">
@@ -3794,34 +3794,41 @@ bool AArch64FastISel::selectTrunc(const<br class="">
return false;<br class="">
bool SrcIsKill = hasTrivialKill(Op);<br class="">
<br class="">
- // If we're truncating from i64/i32 to a smaller non-legal type then generate<br class="">
- // an AND.<br class="">
- uint64_t Mask = 0;<br class="">
- switch (DestVT.SimpleTy) {<br class="">
- default:<br class="">
- // Trunc i64 to i32 is handled by the target-independent fast-isel.<br class="">
- return false;<br class="">
- case MVT::i1:<br class="">
- Mask = 0x1;<br class="">
- break;<br class="">
- case MVT::i8:<br class="">
- Mask = 0xff;<br class="">
- break;<br class="">
- case MVT::i16:<br class="">
- Mask = 0xffff;<br class="">
- break;<br class="">
- }<br class="">
+ // If we're truncating from i64 to a smaller non-legal type then generate an<br class="">
+ // AND. Otherwise, we know the high bits are undefined and a truncate only<br class="">
+ // generate a COPY. We cannot mark the source register also as result<br class="">
+ // register, because this can incorrectly transfer the kill flag onto the<br class="">
+ // source register.<br class="">
+ unsigned ResultReg;<br class="">
if (SrcVT == MVT::i64) {<br class="">
+ uint64_t Mask = 0;<br class="">
+ switch (DestVT.SimpleTy) {<br class="">
+ default:<br class="">
+ // Trunc i64 to i32 is handled by the target-independent fast-isel.<br class="">
+ return false;<br class="">
+ case MVT::i1:<br class="">
+ Mask = 0x1;<br class="">
+ break;<br class="">
+ case MVT::i8:<br class="">
+ Mask = 0xff;<br class="">
+ break;<br class="">
+ case MVT::i16:<br class="">
+ Mask = 0xffff;<br class="">
+ break;<br class="">
+ }<br class="">
// Issue an extract_subreg to get the lower 32-bits.<br class="">
- SrcReg = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,<br class="">
- AArch64::sub_32);<br class="">
- SrcIsKill = true;<br class="">
+ unsigned Reg32 = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,<br class="">
+ AArch64::sub_32);<br class="">
+ // Create the AND instruction which performs the actual truncation.<br class="">
+ ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);<br class="">
+ assert(ResultReg && "Unexpected AND instruction emission failure.");<br class="">
+ } else {<br class="">
+ ResultReg = createResultReg(&AArch64::GPR32RegClass);<br class="">
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,<br class="">
+ TII.get(TargetOpcode::COPY), ResultReg)<br class="">
+ .addReg(SrcReg, getKillRegState(SrcIsKill));<br class="">
}<br class="">
<br class="">
- // Create the AND instruction which performs the actual truncation.<br class="">
- unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, SrcIsKill, Mask);<br class="">
- assert(ResultReg && "Unexpected AND instruction emission failure.");<br class="">
-<br class="">
updateValueMap(I, ResultReg);<br class="">
return true;<br class="">
}<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll?rev=244287&r1=244286&r2=244287&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll?rev=244287&r1=244286&r2=244287&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll Thu Aug 6 17:13:48 2015<br class="">
@@ -363,8 +363,7 @@ entry:<br class="">
define i32 @i64_trunc_i32(i64 %a) nounwind ssp {<br class="">
entry:<br class="">
; CHECK-LABEL: i64_trunc_i32<br class="">
-; CHECK: mov [[REG:x[0-9]+]], x0<br class="">
-; CHECK-NEXT: mov x0, [[REG]]<br class="">
+; CHECK: mov x1, x0<br class="">
%conv = trunc i64 %a to i32<br class="">
ret i32 %conv<br class="">
}<br class="">
@@ -372,9 +371,9 @@ entry:<br class="">
define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {<br class="">
entry:<br class="">
; CHECK-LABEL: i64_trunc_i16<br class="">
-; CHECK: mov x[[REG:[0-9]+]], x0<br class="">
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0xffff<br class="">
-; CHECK-NEXT: uxth w0, [[REG2]]<br class="">
+; CHECK: mov x[[REG:[0-9]+]], x0<br class="">
+; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xffff<br class="">
+; CHECK: uxth w0, [[REG2]]<br class="">
%conv = trunc i64 %a to i16<br class="">
ret i16 %conv<br class="">
}<br class="">
@@ -382,9 +381,9 @@ entry:<br class="">
define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {<br class="">
entry:<br class="">
; CHECK-LABEL: i64_trunc_i8<br class="">
-; CHECK: mov x[[REG:[0-9]+]], x0<br class="">
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0xff<br class="">
-; CHECK-NEXT: uxtb w0, [[REG2]]<br class="">
+; CHECK: mov x[[REG:[0-9]+]], x0<br class="">
+; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xff<br class="">
+; CHECK: uxtb w0, [[REG2]]<br class="">
%conv = trunc i64 %a to i8<br class="">
ret i8 %conv<br class="">
}<br class="">
@@ -392,67 +391,13 @@ entry:<br class="">
define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {<br class="">
entry:<br class="">
; CHECK-LABEL: i64_trunc_i1<br class="">
-; CHECK: mov x[[REG:[0-9]+]], x0<br class="">
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0x1<br class="">
-; CHECK-NEXT: and w0, [[REG2]], #0x1<br class="">
+; CHECK: mov x[[REG:[0-9]+]], x0<br class="">
+; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0x1<br class="">
+; CHECK: and w0, [[REG2]], #0x1<br class="">
%conv = trunc i64 %a to i1<br class="">
ret i1 %conv<br class="">
}<br class="">
<br class="">
-define zeroext i16 @i32_trunc_i16(i32 %a) nounwind ssp {<br class="">
-entry:<br class="">
-; CHECK-LABEL: i32_trunc_i16<br class="">
-; CHECK: and [[REG:w[0-9]+]], w0, #0xffff<br class="">
-; CHECK-NEXT: uxth w0, [[REG]]<br class="">
- %conv = trunc i32 %a to i16<br class="">
- ret i16 %conv<br class="">
-}<br class="">
-<br class="">
-define zeroext i8 @i32_trunc_i8(i32 %a) nounwind ssp {<br class="">
-entry:<br class="">
-; CHECK-LABEL: i32_trunc_i8<br class="">
-; CHECK: and [[REG:w[0-9]+]], w0, #0xff<br class="">
-; CHECK-NEXT: uxtb w0, [[REG]]<br class="">
- %conv = trunc i32 %a to i8<br class="">
- ret i8 %conv<br class="">
-}<br class="">
-<br class="">
-define zeroext i1 @i32_trunc_i1(i32 %a) nounwind ssp {<br class="">
-entry:<br class="">
-; CHECK-LABEL: i32_trunc_i1<br class="">
-; CHECK: and [[REG:w[0-9]+]], w0, #0x1<br class="">
-; CHECK-NEXT: and w0, [[REG]], #0x1<br class="">
- %conv = trunc i32 %a to i1<br class="">
- ret i1 %conv<br class="">
-}<br class="">
-<br class="">
-define zeroext i8 @i16_trunc_i8(i16 zeroext %a) nounwind ssp {<br class="">
-entry:<br class="">
-; CHECK-LABEL: i16_trunc_i8<br class="">
-; CHECK: and [[REG:w[0-9]+]], w0, #0xff<br class="">
-; CHECK-NEXT: uxtb w0, [[REG]]<br class="">
- %conv = trunc i16 %a to i8<br class="">
- ret i8 %conv<br class="">
-}<br class="">
-<br class="">
-define zeroext i1 @i16_trunc_i1(i16 zeroext %a) nounwind ssp {<br class="">
-entry:<br class="">
-; CHECK-LABEL: i16_trunc_i1<br class="">
-; CHECK: and [[REG:w[0-9]+]], w0, #0x1<br class="">
-; CHECK-NEXT: and w0, [[REG]], #0x1<br class="">
- %conv = trunc i16 %a to i1<br class="">
- ret i1 %conv<br class="">
-}<br class="">
-<br class="">
-define zeroext i1 @i8_trunc_i1(i8 zeroext %a) nounwind ssp {<br class="">
-entry:<br class="">
-; CHECK-LABEL: i8_trunc_i1<br class="">
-; CHECK: and [[REG:w[0-9]+]], w0, #0x1<br class="">
-; CHECK-NEXT: and w0, [[REG]], #0x1<br class="">
- %conv = trunc i8 %a to i1<br class="">
- ret i1 %conv<br class="">
-}<br class="">
-<br class="">
; <a href="rdar://15101939" class="">rdar://15101939</a><br class="">
define void @stack_trunc() nounwind {<br class="">
; CHECK-LABEL: stack_trunc<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll?rev=244287&r1=244286&r2=244287&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll?rev=244287&r1=244286&r2=244287&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll Thu Aug 6 17:13:48 2015<br class="">
@@ -1,4 +1,4 @@<br class="">
-; RUN: llc %s -o - -O2 -verify-machineinstrs -fast-isel=true | FileCheck %s<br class="">
+; RUN: llc %s -o - -O0 -verify-machineinstrs -fast-isel=true | FileCheck %s<br class="">
<br class="">
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"<br class="">
target triple = "arm64-apple-ios8.0.0"<br class="">
@@ -7,7 +7,7 @@ target triple = "arm64-apple-ios8.0.0"<br class="">
; This was incorrect as %.mux isn't available in the last bb.<br class="">
<br class="">
; CHECK: sxtw [[REG:x[0-9]+]]<br class="">
-; CHECK: strh wzr, {{\[}}{{.*}}, [[REG]], lsl #1]<br class="">
+; CHECK: strh wzr, {{\[}}[[REG]], {{.*}}, lsl #1]<br class="">
<br class="">
; Function Attrs: nounwind optsize ssp<br class="">
define void @EdgeLoop(i32 %dir, i32 %edge, i32 %width, i16* %tmp89, i32 %tmp136, i16 %tmp144) #0 {<br class="">
<br class="">
<br class="">
_______________________________________________<br class="">
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</blockquote></div>
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