<div dir="ltr">Ah, sweet. :)<div><br></div><div>-eric</div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, Aug 6, 2015 at 3:16 PM Juergen Ributzka <<a href="mailto:juergen@apple.com">juergen@apple.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word">Yup, will be part of the proper fix :)<div><br></div><div></div></div><div style="word-wrap:break-word"><div>—Juergen</div></div><div style="word-wrap:break-word"><div><br><div><br><div><blockquote type="cite"><div>On Aug 6, 2015, at 3:15 PM, Eric Christopher <<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>> wrote:</div><br><div><div dir="ltr">Got a testcase for the revert? :)<div><br></div><div>-eric</div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, Aug 6, 2015 at 3:14 PM Juergen Ributzka via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ributzka<br>
Date: Thu Aug 6 17:13:48 2015<br>
New Revision: 244287<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=244287&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=244287&view=rev</a><br>
Log:<br>
Revert "[AArch64][FastISel] Add more truncation tests." and "[AArch64][FastISel] Always use an AND instruction when truncating to non-legal types."<br>
<br>
This reverts commit r243198 and 243304.<br>
<br>
Turns out this wasn't the correct fix for this problem. It works only within<br>
FastISel, but fails when the truncate is selected by SDAG.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp<br>
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll<br>
llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=244287&r1=244286&r2=244287&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=244287&r1=244286&r2=244287&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Thu Aug 6 17:13:48 2015<br>
@@ -3794,34 +3794,41 @@ bool AArch64FastISel::selectTrunc(const<br>
return false;<br>
bool SrcIsKill = hasTrivialKill(Op);<br>
<br>
- // If we're truncating from i64/i32 to a smaller non-legal type then generate<br>
- // an AND.<br>
- uint64_t Mask = 0;<br>
- switch (DestVT.SimpleTy) {<br>
- default:<br>
- // Trunc i64 to i32 is handled by the target-independent fast-isel.<br>
- return false;<br>
- case MVT::i1:<br>
- Mask = 0x1;<br>
- break;<br>
- case MVT::i8:<br>
- Mask = 0xff;<br>
- break;<br>
- case MVT::i16:<br>
- Mask = 0xffff;<br>
- break;<br>
- }<br>
+ // If we're truncating from i64 to a smaller non-legal type then generate an<br>
+ // AND. Otherwise, we know the high bits are undefined and a truncate only<br>
+ // generate a COPY. We cannot mark the source register also as result<br>
+ // register, because this can incorrectly transfer the kill flag onto the<br>
+ // source register.<br>
+ unsigned ResultReg;<br>
if (SrcVT == MVT::i64) {<br>
+ uint64_t Mask = 0;<br>
+ switch (DestVT.SimpleTy) {<br>
+ default:<br>
+ // Trunc i64 to i32 is handled by the target-independent fast-isel.<br>
+ return false;<br>
+ case MVT::i1:<br>
+ Mask = 0x1;<br>
+ break;<br>
+ case MVT::i8:<br>
+ Mask = 0xff;<br>
+ break;<br>
+ case MVT::i16:<br>
+ Mask = 0xffff;<br>
+ break;<br>
+ }<br>
// Issue an extract_subreg to get the lower 32-bits.<br>
- SrcReg = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,<br>
- AArch64::sub_32);<br>
- SrcIsKill = true;<br>
+ unsigned Reg32 = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,<br>
+ AArch64::sub_32);<br>
+ // Create the AND instruction which performs the actual truncation.<br>
+ ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);<br>
+ assert(ResultReg && "Unexpected AND instruction emission failure.");<br>
+ } else {<br>
+ ResultReg = createResultReg(&AArch64::GPR32RegClass);<br>
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,<br>
+ TII.get(TargetOpcode::COPY), ResultReg)<br>
+ .addReg(SrcReg, getKillRegState(SrcIsKill));<br>
}<br>
<br>
- // Create the AND instruction which performs the actual truncation.<br>
- unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, SrcIsKill, Mask);<br>
- assert(ResultReg && "Unexpected AND instruction emission failure.");<br>
-<br>
updateValueMap(I, ResultReg);<br>
return true;<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll?rev=244287&r1=244286&r2=244287&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll?rev=244287&r1=244286&r2=244287&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll Thu Aug 6 17:13:48 2015<br>
@@ -363,8 +363,7 @@ entry:<br>
define i32 @i64_trunc_i32(i64 %a) nounwind ssp {<br>
entry:<br>
; CHECK-LABEL: i64_trunc_i32<br>
-; CHECK: mov [[REG:x[0-9]+]], x0<br>
-; CHECK-NEXT: mov x0, [[REG]]<br>
+; CHECK: mov x1, x0<br>
%conv = trunc i64 %a to i32<br>
ret i32 %conv<br>
}<br>
@@ -372,9 +371,9 @@ entry:<br>
define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {<br>
entry:<br>
; CHECK-LABEL: i64_trunc_i16<br>
-; CHECK: mov x[[REG:[0-9]+]], x0<br>
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0xffff<br>
-; CHECK-NEXT: uxth w0, [[REG2]]<br>
+; CHECK: mov x[[REG:[0-9]+]], x0<br>
+; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xffff<br>
+; CHECK: uxth w0, [[REG2]]<br>
%conv = trunc i64 %a to i16<br>
ret i16 %conv<br>
}<br>
@@ -382,9 +381,9 @@ entry:<br>
define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {<br>
entry:<br>
; CHECK-LABEL: i64_trunc_i8<br>
-; CHECK: mov x[[REG:[0-9]+]], x0<br>
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0xff<br>
-; CHECK-NEXT: uxtb w0, [[REG2]]<br>
+; CHECK: mov x[[REG:[0-9]+]], x0<br>
+; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xff<br>
+; CHECK: uxtb w0, [[REG2]]<br>
%conv = trunc i64 %a to i8<br>
ret i8 %conv<br>
}<br>
@@ -392,67 +391,13 @@ entry:<br>
define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {<br>
entry:<br>
; CHECK-LABEL: i64_trunc_i1<br>
-; CHECK: mov x[[REG:[0-9]+]], x0<br>
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0x1<br>
-; CHECK-NEXT: and w0, [[REG2]], #0x1<br>
+; CHECK: mov x[[REG:[0-9]+]], x0<br>
+; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0x1<br>
+; CHECK: and w0, [[REG2]], #0x1<br>
%conv = trunc i64 %a to i1<br>
ret i1 %conv<br>
}<br>
<br>
-define zeroext i16 @i32_trunc_i16(i32 %a) nounwind ssp {<br>
-entry:<br>
-; CHECK-LABEL: i32_trunc_i16<br>
-; CHECK: and [[REG:w[0-9]+]], w0, #0xffff<br>
-; CHECK-NEXT: uxth w0, [[REG]]<br>
- %conv = trunc i32 %a to i16<br>
- ret i16 %conv<br>
-}<br>
-<br>
-define zeroext i8 @i32_trunc_i8(i32 %a) nounwind ssp {<br>
-entry:<br>
-; CHECK-LABEL: i32_trunc_i8<br>
-; CHECK: and [[REG:w[0-9]+]], w0, #0xff<br>
-; CHECK-NEXT: uxtb w0, [[REG]]<br>
- %conv = trunc i32 %a to i8<br>
- ret i8 %conv<br>
-}<br>
-<br>
-define zeroext i1 @i32_trunc_i1(i32 %a) nounwind ssp {<br>
-entry:<br>
-; CHECK-LABEL: i32_trunc_i1<br>
-; CHECK: and [[REG:w[0-9]+]], w0, #0x1<br>
-; CHECK-NEXT: and w0, [[REG]], #0x1<br>
- %conv = trunc i32 %a to i1<br>
- ret i1 %conv<br>
-}<br>
-<br>
-define zeroext i8 @i16_trunc_i8(i16 zeroext %a) nounwind ssp {<br>
-entry:<br>
-; CHECK-LABEL: i16_trunc_i8<br>
-; CHECK: and [[REG:w[0-9]+]], w0, #0xff<br>
-; CHECK-NEXT: uxtb w0, [[REG]]<br>
- %conv = trunc i16 %a to i8<br>
- ret i8 %conv<br>
-}<br>
-<br>
-define zeroext i1 @i16_trunc_i1(i16 zeroext %a) nounwind ssp {<br>
-entry:<br>
-; CHECK-LABEL: i16_trunc_i1<br>
-; CHECK: and [[REG:w[0-9]+]], w0, #0x1<br>
-; CHECK-NEXT: and w0, [[REG]], #0x1<br>
- %conv = trunc i16 %a to i1<br>
- ret i1 %conv<br>
-}<br>
-<br>
-define zeroext i1 @i8_trunc_i1(i8 zeroext %a) nounwind ssp {<br>
-entry:<br>
-; CHECK-LABEL: i8_trunc_i1<br>
-; CHECK: and [[REG:w[0-9]+]], w0, #0x1<br>
-; CHECK-NEXT: and w0, [[REG]], #0x1<br>
- %conv = trunc i8 %a to i1<br>
- ret i1 %conv<br>
-}<br>
-<br>
; <a>rdar://15101939</a><br>
define void @stack_trunc() nounwind {<br>
; CHECK-LABEL: stack_trunc<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll?rev=244287&r1=244286&r2=244287&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll?rev=244287&r1=244286&r2=244287&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll Thu Aug 6 17:13:48 2015<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc %s -o - -O2 -verify-machineinstrs -fast-isel=true | FileCheck %s<br>
+; RUN: llc %s -o - -O0 -verify-machineinstrs -fast-isel=true | FileCheck %s<br>
<br>
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"<br>
target triple = "arm64-apple-ios8.0.0"<br>
@@ -7,7 +7,7 @@ target triple = "arm64-apple-ios8.0.0"<br>
; This was incorrect as %.mux isn't available in the last bb.<br>
<br>
; CHECK: sxtw [[REG:x[0-9]+]]<br>
-; CHECK: strh wzr, {{\[}}{{.*}}, [[REG]], lsl #1]<br>
+; CHECK: strh wzr, {{\[}}[[REG]], {{.*}}, lsl #1]<br>
<br>
; Function Attrs: nounwind optsize ssp<br>
define void @EdgeLoop(i32 %dir, i32 %edge, i32 %width, i16* %tmp89, i32 %tmp136, i16 %tmp144) #0 {<br>
<br>
<br>
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</blockquote></div>
</div></blockquote></div><br></div></div></div></blockquote></div>