<div dir="ltr">My thinking is that for a given target, take AMDGPU for instance, the amount of memory used to store LiveIns could go up by an order of magnitude per MachineBasicBlock.<div><br></div><div>PL</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jul 31, 2015 at 11:20 AM, Puyan Lotfi <span dir="ltr"><<a href="mailto:puyan@puyan.org" target="_blank">puyan@puyan.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">I doubt this would work.<div>The original compile time fix was for targets with a large number of registers.</div><span class="HOEnZb"><font color="#888888"><div><br></div><div>PL</div></font></span></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jul 31, 2015 at 10:10 AM, Krzysztof Parzyszek <span dir="ltr"><<a href="mailto:kparzysz@codeaurora.org" target="_blank">kparzysz@codeaurora.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span>On 7/31/2015 11:02 AM, Puyan Lotfi wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
Originally I had added a patch to improve compile time in<br>
VirtRegRewriter, and me and Quentin had noticed that these LiveIns set<br>
in MachineBasicBlock<br>
we not actually in sorted order in all cases. We thought this could be a<br>
good way to maintain the ordering for the LiveIns set with low overhead<br>
since they were mostly sorted as a result of how they were being<br>
inserted into.<br>
</blockquote>
<br></span>
Can we use BitVector for physical vectors? They are pretty much constant in terms of read/write time. The only concern would be memory consumption, but even then only AMDGPU seems to have a considerable number of registers. Maybe some combination that uses BitVector for small numbers and something else otherwise would do the trick?<br>
<br>
AArch64GenRegisterInfo.inc: NUM_TARGET_REGS // 484<br>
AMDGPUGenRegisterInfo.inc: NUM_TARGET_REGS // 3418<br>
ARMGenRegisterInfo.inc: NUM_TARGET_REGS // 289<br>
BPFGenRegisterInfo.inc: NUM_TARGET_REGS // 13<br>
HexagonGenRegisterInfo.inc: NUM_TARGET_REGS // 78<br>
MipsGenRegisterInfo.inc: NUM_TARGET_REGS // 418<br>
MSP430GenRegisterInfo.inc: NUM_TARGET_REGS // 33<br>
NVPTXGenRegisterInfo.inc: NUM_TARGET_REGS // 86<br>
PPCGenRegisterInfo.inc: NUM_TARGET_REGS // 310<br>
SparcGenRegisterInfo.inc: NUM_TARGET_REGS // 153<br>
SystemZGenRegisterInfo.inc: NUM_TARGET_REGS // 162<br>
X86GenRegisterInfo.inc: NUM_TARGET_REGS // 246<br>
XCoreGenRegisterInfo.inc: NUM_TARGET_REGS // 17<span><br>
<br>
-Krzysztof<br>
<br>
<br>
-- <br>
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</div></div></blockquote></div><br></div>
</div></div></blockquote></div><br></div>