<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Hi Shahid,<div class=""><br class=""></div><div class="">Sorry for the delayed response, please see my answers inline:</div><div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Jul 22, 2015, at 1:54 AM, Shahid, Asghar-ahmad <<a href="mailto:Asghar-ahmad.Shahid@amd.com" class="">Asghar-ahmad.Shahid@amd.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Hi Mikhail,</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Thanks for the comments. Pls see the response inlined.</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Regards,</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Shahid</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">-----Original Message-----<br class="">From:<span class="Apple-converted-space"> </span><a href="mailto:llvm-commits-bounces@cs.uiuc.edu" class="">llvm-commits-bounces@cs.uiuc.edu</a><span class="Apple-converted-space"> </span>[mailto:llvm-commits-<br class=""><a href="mailto:bounces@cs.uiuc.edu" class="">bounces@cs.uiuc.edu</a>] On Behalf Of Mikhail Zolotukhin<br class="">Sent: Tuesday, July 21, 2015 12:02 AM<br class="">To: James Molloy<br class="">Cc:<span class="Apple-converted-space"> </span><a href="mailto:llvm-commits@cs.uiuc.edu" class="">llvm-commits@cs.uiuc.edu</a><br class="">Subject: Re: [llvm] r242409 - [Codegen] Add intrinsics 'absdiff' and<br class="">corresponding SDNodes for absolute difference operation<br class=""><br class=""><br class=""><blockquote type="cite" class="">On Jul 16, 2015, at 8:22 AM, James Molloy <<a href="mailto:James.Molloy@arm.com" class="">James.Molloy@arm.com</a>><br class=""></blockquote>wrote:<br class=""><blockquote type="cite" class=""><br class="">Author: jamesm<br class="">Date: Thu Jul 16 10:22:46 2015<br class="">New Revision: 242409<br class=""><br class="">URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject-3Frev-3D242409-26view-3Drev&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=yeshBOYSk1Kz2d_ThYMC7kqtuxvOnDPbeYv_SdXu3iM&e=" class="">http://llvm.org/viewvc/llvm-project?rev=242409&view=rev</a><br class="">Log:<br class="">[Codegen] Add intrinsics 'absdiff' and corresponding SDNodes for<br class="">absolute difference operation<br class=""><br class="">This adds new intrinsics "*absdiff" for absolute difference ops to facilitate<br class=""></blockquote>efficient code generation for "sum of absolute differences" operation.<br class=""><blockquote type="cite" class="">The patch also contains the introduction of corresponding SDNodes and<br class=""></blockquote>basic legalization support.Sanity of the generated code is tested on X86.<br class=""><blockquote type="cite" class=""><br class="">This is 1st of the three patches.<br class=""><br class="">Patch by Shahid Asghar-ahmad!<br class=""><br class="">Added:<br class=""> llvm/trunk/test/CodeGen/X86/absdiff_expand.ll<br class="">Modified:<br class=""> llvm/trunk/docs/LangRef.rst<br class=""> llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h<br class=""> llvm/trunk/include/llvm/IR/Intrinsics.td<br class=""> llvm/trunk/include/llvm/Target/TargetSelectionDAG.td<br class=""> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br class=""> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp<br class=""> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br class=""> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br class=""> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp<br class=""> llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp<br class=""><br class="">Modified: llvm/trunk/docs/LangRef.rst<br class="">URL:<br class=""><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_docs_LangRef.rst-3Frev-3D24&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=wyKLEjUVIem3PziHGjNnRUHID5G6vQB1RWOLdItDaWk&e=" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.rst?rev=24</a><br class="">2409&r1=242408&r2=242409&view=diff<br class=""><br class=""></blockquote>==========================================================<br class="">============<br class=""><blockquote type="cite" class="">========<br class="">--- llvm/trunk/docs/LangRef.rst (original)<br class="">+++ llvm/trunk/docs/LangRef.rst Thu Jul 16 10:22:46 2015<br class="">@@ -10328,6 +10328,65 @@ Examples:<br class=""><br class=""> %r2 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)<br class="">; yields float:r2 = (a * b) + c<br class=""><br class="">+<br class="">+'``llvm.uabsdiff.*``' and '``llvm.sabsdiff.*``' Intrinsics<br class=""><br class=""></blockquote>+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^<br class="">^<br class=""><blockquote type="cite" class="">+<br class="">+Syntax:<br class="">+"""""""<br class="">+This is an overloaded intrinsic. The loaded data is a vector of any integer<br class=""></blockquote>bit width.<br class=""><blockquote type="cite" class="">+<br class="">+.. code-block:: llvm<br class="">+<br class="">+ declare <4 x integer> @llvm.uabsdiff.v4i32(<4 x integer> %a, <4<br class="">+ x integer> %b)<br class="">+<br class="">+<br class="">+Overview:<br class="">+"""""""""<br class="">+<br class="">+The ``llvm.uabsdiff`` intrinsic returns a vector result of the<br class="">+absolute difference of the two operands, treating them both as unsigned<br class=""></blockquote>integers.<br class=""><blockquote type="cite" class="">+<br class="">+The ``llvm.sabsdiff`` intrinsic returns a vector result of the<br class="">+absolute difference of the two operands, treating them both as signed<br class=""></blockquote>integers.<br class=""><blockquote type="cite" class="">+<br class="">+.. note::<br class="">+<br class="">+ These intrinsics are primarily used during the code generation stage of<br class=""></blockquote>compilation.<br class=""><blockquote type="cite" class="">+ They are generated by compiler passes such as the Loop and SLP<br class=""></blockquote><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__vectorizers.it&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=4NGDyTG9Iw2_Dyd0zJJLwoAn-AEmbcVOnxgdpT1a3XU&e=" class="">vectorizers.it</a> is not<br class=""><blockquote type="cite" class="">+ recommended for users to create them manually.<br class="">+<br class="">+Arguments:<br class="">+""""""""""<br class="">+<br class="">+Both intrinsics take two integer of the same bitwidth.<br class="">+<br class="">+Semantics:<br class="">+""""""""""<br class="">+<br class="">+The expression::<br class="">+<br class="">+ call <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32> %a, <4 x i32> %b)<br class="">+<br class="">+is equivalent to::<br class="">+<br class="">+ %sub = sub <4 x i32> %a, %b<br class="">+ %ispos = icmp ugt <4 x i32> %sub, <i32 -1, i32 -1, i32 -1, i32<br class="">+ -1><br class=""></blockquote>Isn't it always 'false'?<br class=""></blockquote><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Oh yes, this will always be false as the comparison is 'unsigned'.</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Since the subtraction of two unsigned numbers can be a signed number, How about making this comparison as</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">"icmp sge <4 x i32> %sub, zeroinitializer”</span></div></blockquote>Sounds good to me.<br class=""><blockquote type="cite" class=""><div class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" class="">+ %neg = sub <4 x i32> zeroinitializer, %sub<br class="">+ %1 = select <4 x i1> %ispos, <4 x i32> %sub, <4 x i32> %neg<br class="">+<br class="">+Similarly the expression::<br class="">+<br class="">+ call <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32> %a, <4 x i32> %b)<br class="">+<br class="">+is equivalent to::<br class="">+<br class="">+ %sub = sub nsw <4 x i32> %a, %b<br class="">+ %ispos = icmp sgt <4 x i32> %sub, <i32 -1, i32 -1, i32 -1, i32<br class="">+ -1><br class=""></blockquote>Wouldn't it be more readable if we use "icmp sge <4 x i32> %sub,<br class="">zeroinitializer"?<br class=""></blockquote><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Yes, that will do.</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" class="">+ %neg = sub nsw <4 x i32> zeroinitializer, %sub<br class="">+ %1 = select <4 x i1> %ispos, <4 x i32> %sub, <4 x i32> %neg<br class="">+<br class="">+<br class="">Half Precision Floating Point Intrinsics<br class="">----------------------------------------<br class=""><br class=""><br class="">Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h<br class="">URL:<br class=""><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_include_llvm_CodeGen_IS&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=BTzdY1LktwU8sr3i8mqB2YxZYOC0JsLxJlQStyDA-po&e=" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/IS</a><br class="">DOpcodes.h?rev=242409&r1=242408&r2=242409&view=diff<br class=""><br class=""></blockquote>==========================================================<br class="">============<br class=""><blockquote type="cite" class="">========<br class="">--- llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h (original)<br class="">+++ llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Thu Jul 16 10:22:46<br class="">+++ 2015<br class="">@@ -334,6 +334,10 @@ namespace ISD {<br class=""> /// Byte Swap and Counting operators.<br class=""> BSWAP, CTTZ, CTLZ, CTPOP,<br class=""><br class="">+ /// [SU]ABSDIFF - Signed/Unsigned absolute difference of two input<br class=""></blockquote>integer<br class=""><blockquote type="cite" class="">+ /// vector. These nodes are generated from llvm.*absdiff* intrinsics.<br class="">+ SABSDIFF, UABSDIFF,<br class="">+<br class=""> /// Bit counting operators with an undefined result for zero inputs.<br class=""> CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,<br class=""><br class=""><br class="">Modified: llvm/trunk/include/llvm/IR/Intrinsics.td<br class="">URL:<br class=""><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_include_llvm_IR_Intrins&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=rVURCe5LhxOyJGe2cxaYTyWgdepcn2i6w8ARiTRLID0&e=" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/Intrins</a><br class="">ics.td?rev=242409&r1=242408&r2=242409&view=diff<br class=""><br class=""></blockquote>==========================================================<br class="">============<br class=""><blockquote type="cite" class="">========<br class="">--- llvm/trunk/include/llvm/IR/Intrinsics.td (original)<br class="">+++ llvm/trunk/include/llvm/IR/Intrinsics.td Thu Jul 16 10:22:46 2015<br class="">@@ -605,6 +605,12 @@ def int_convertuu : Intrinsic<[llvm_any def<br class="">int_clear_cache : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty],<br class=""> [], "llvm.clear_cache">;<br class=""><br class="">+// Calculate the Absolute Differences of the two input vectors.<br class="">+def int_sabsdiff : Intrinsic<[llvm_anyvector_ty],<br class="">+ [ LLVMMatchType<0>, LLVMMatchType<0> ],<br class="">+[IntrNoMem]>; def int_uabsdiff : Intrinsic<[llvm_anyvector_ty],<br class="">+ [ LLVMMatchType<0>, LLVMMatchType<0> ],<br class="">+[IntrNoMem]>;<br class="">+<br class="">//===-------------------------- Masked Intrinsics<br class="">-------------------------===// // def int_masked_store : Intrinsic<[],<br class="">[llvm_anyvector_ty, LLVMPointerTo<0>,<br class=""><br class="">Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td<br class="">URL:<br class=""><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_include_llvm_Target_Tar&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=bWh0DxXR-sAZO8KVQOHJOAh5tAj2-xWwJNRsGje7Fx4&e=" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Tar</a><br class="">getSelectionDAG.td?rev=242409&r1=242408&r2=242409&view=diff<br class=""><br class=""></blockquote>==========================================================<br class="">============<br class=""><blockquote type="cite" class="">========<br class="">--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)<br class="">+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Thu Jul 16<br class="">+++ 10:22:46 2015<br class="">@@ -386,6 +386,8 @@ def smax : SDNode<"ISD::SMAX"<br class="">def umin : SDNode<"ISD::UMIN" , SDTIntBinOp>;<br class="">def umax : SDNode<"ISD::UMAX" , SDTIntBinOp>;<br class=""><br class="">+def sabsdiff : SDNode<"ISD::SABSDIFF" , SDTIntBinOp>;<br class="">+def uabsdiff : SDNode<"ISD::UABSDIFF" , SDTIntBinOp>;<br class="">def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;<br class="">def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;<br class="">def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;<br class=""><br class="">Modified:<br class=""></blockquote>llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br class=""><blockquote type="cite" class="">URL:<br class=""><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_SelectionDA&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=3bcVziF_sqEaZSHKaO9qZ04bKzQaWpY5vQAJDLKIQqc&e=" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDA</a><br class=""><br class=""></blockquote>G/LegalizeIntegerTypes.cpp?rev=242409&r1=242408&r2=242409&view=diff<br class=""><blockquote type="cite" class=""><br class=""></blockquote>==========================================================<br class="">============<br class=""><blockquote type="cite" class="">========<br class="">--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br class="">(original)<br class="">+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Thu<br class="">+++ Jul 16 10:22:46 2015<br class="">@@ -146,6 +146,10 @@ void DAGTypeLegalizer::PromoteIntegerRes<br class=""> case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:<br class=""> Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N),<br class=""></blockquote>ResNo);<br class=""><blockquote type="cite" class=""> break;<br class="">+ case ISD::UABSDIFF:<br class="">+ case ISD::SABSDIFF:<br class="">+ Res = PromoteIntRes_SimpleIntBinOp(N);<br class="">+ break;<br class=""> }<br class=""><br class=""> // If the result is null then the sub-method took care of registering it.<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp<br class="">URL:<br class=""><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_SelectionDA&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=3bcVziF_sqEaZSHKaO9qZ04bKzQaWpY5vQAJDLKIQqc&e=" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDA</a><br class="">G/LegalizeVectorOps.cpp?rev=242409&r1=242408&r2=242409&view=diff<br class=""><br class=""></blockquote>==========================================================<br class="">============<br class=""><blockquote type="cite" class="">========<br class="">--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp<br class="">(original)<br class="">+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Thu Jul<br class="">+++ 16 10:22:46 2015<br class="">@@ -105,6 +105,7 @@ class VectorLegalizer {<br class=""> SDValue ExpandLoad(SDValue Op);<br class=""> SDValue ExpandStore(SDValue Op);<br class=""> SDValue ExpandFNEG(SDValue Op);<br class="">+ SDValue ExpandABSDIFF(SDValue Op);<br class=""><br class=""> /// \brief Implements vector promotion.<br class=""> ///<br class="">@@ -326,6 +327,8 @@ SDValue VectorLegalizer::LegalizeOp(SDVa<br class=""> case ISD::SMAX:<br class=""> case ISD::UMIN:<br class=""> case ISD::UMAX:<br class="">+ case ISD::UABSDIFF:<br class="">+ case ISD::SABSDIFF:<br class=""> QueryType = Node->getValueType(0);<br class=""> break;<br class=""> case ISD::FP_ROUND_INREG:<br class="">@@ -708,11 +711,36 @@ SDValue VectorLegalizer::Expand(SDValue<br class=""> return ExpandFNEG(Op);<br class=""> case ISD::SETCC:<br class=""> return UnrollVSETCC(Op);<br class="">+ case ISD::UABSDIFF:<br class="">+ case ISD::SABSDIFF:<br class="">+ return ExpandABSDIFF(Op);<br class=""> default:<br class=""> return DAG.UnrollVectorOp(Op.getNode());<br class=""> }<br class="">}<br class=""><br class="">+SDValue VectorLegalizer::ExpandABSDIFF(SDValue Op) {<br class="">+ SDLoc dl(Op);<br class="">+ SDValue Tmp1, Tmp2, Tmp3, Tmp4;<br class="">+ EVT VT = Op.getValueType();<br class="">+ SDNodeFlags Flags;<br class="">+ Flags.setNoSignedWrap(Op->getOpcode() == ISD::SABSDIFF);<br class="">+<br class="">+ Tmp2 = Op.getOperand(0);<br class="">+ Tmp3 = Op.getOperand(1);<br class="">+ Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp3, &Flags);<br class="">+ Tmp2 =<br class="">+ DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), Tmp1,<br class="">+&Flags);<br class="">+ Tmp4 = DAG.getNode(<br class="">+ ISD::SETCC, dl,<br class="">+ TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),<br class=""></blockquote>VT), Tmp2,<br class=""><blockquote type="cite" class="">+ DAG.getConstant(0, dl, VT),<br class="">+ DAG.getCondCode(Op->getOpcode() == ISD::SABSDIFF ? ISD::SETLT<br class="">+ :<br class="">+ISD::SETULT));<br class="">+ Tmp1 = DAG.getNode(ISD::VSELECT, dl, VT, Tmp4, Tmp1, Tmp2);<br class="">+ return Tmp1;<br class="">+}<br class="">+<br class="">SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {<br class=""> // Lower a select instruction where the condition is a scalar and the<br class=""> // operands are vectors. Lower this select to VSELECT and implement<br class="">it<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br class="">URL:<br class=""><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_SelectionDA&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=3bcVziF_sqEaZSHKaO9qZ04bKzQaWpY5vQAJDLKIQqc&e=" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDA</a><br class="">G/LegalizeVectorTypes.cpp?rev=242409&r1=242408&r2=242409&view=diff<br class=""><br class=""></blockquote>==========================================================<br class="">============<br class=""><blockquote type="cite" class="">========<br class="">--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br class="">(original)<br class="">+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu<br class="">+++ Jul 16 10:22:46 2015<br class="">@@ -678,6 +678,8 @@ void DAGTypeLegalizer::SplitVectorResult<br class=""> case ISD::SMAX:<br class=""> case ISD::UMIN:<br class=""> case ISD::UMAX:<br class="">+ case ISD::UABSDIFF:<br class="">+ case ISD::SABSDIFF:<br class=""> SplitVecRes_BinOp(N, Lo, Hi);<br class=""> break;<br class=""> case ISD::FMA:<br class=""><br class="">Modified:<br class=""></blockquote>llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br class=""><blockquote type="cite" class="">URL:<br class=""><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_SelectionDA&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=3bcVziF_sqEaZSHKaO9qZ04bKzQaWpY5vQAJDLKIQqc&e=" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDA</a><br class="">G/SelectionDAGBuilder.cpp?rev=242409&r1=242408&r2=242409&view=diff<br class=""><br class=""></blockquote>==========================================================<br class="">============<br class=""><blockquote type="cite" class="">========<br class="">--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br class="">(original)<br class="">+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu<br class="">+++ Jul 16 10:22:46 2015<br class="">@@ -4646,6 +4646,18 @@ SelectionDAGBuilder::visitIntrinsicCall(<br class=""> getValue(I.getArgOperand(0)).getValueType(),<br class=""> getValue(I.getArgOperand(0))));<br class=""> return nullptr;<br class="">+ case Intrinsic::uabsdiff:<br class="">+ setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,<br class="">+ getValue(I.getArgOperand(0)).getValueType(),<br class="">+ getValue(I.getArgOperand(0)),<br class="">+ getValue(I.getArgOperand(1))));<br class="">+ return nullptr;<br class="">+ case Intrinsic::sabsdiff:<br class="">+ setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,<br class="">+ getValue(I.getArgOperand(0)).getValueType(),<br class="">+ getValue(I.getArgOperand(0)),<br class="">+ getValue(I.getArgOperand(1))));<br class="">+ return nullptr;<br class=""> case Intrinsic::cttz: {<br class=""> SDValue Arg = getValue(I.getArgOperand(0));<br class=""> ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));<br class=""><br class="">Modified:<br class=""></blockquote>llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp<br class=""><blockquote type="cite" class="">URL:<br class=""><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_SelectionDA&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=3bcVziF_sqEaZSHKaO9qZ04bKzQaWpY5vQAJDLKIQqc&e=" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDA</a><br class=""><br class=""></blockquote>G/SelectionDAGDumper.cpp?rev=242409&r1=242408&r2=242409&view=diff<br class=""><blockquote type="cite" class=""><br class=""></blockquote>==========================================================<br class="">============<br class=""><blockquote type="cite" class="">========<br class="">--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp<br class="">(original)<br class="">+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp Thu<br class=""></blockquote>Jul<br class=""><blockquote type="cite" class="">+++ 16 10:22:46 2015<br class="">@@ -225,6 +225,8 @@ std::string SDNode::getOperationName(con<br class=""> case ISD::SHL_PARTS: return "shl_parts";<br class=""> case ISD::SRA_PARTS: return "sra_parts";<br class=""> case ISD::SRL_PARTS: return "srl_parts";<br class="">+ case ISD::UABSDIFF: return "uabsdiff";<br class="">+ case ISD::SABSDIFF: return "sabsdiff";<br class=""><br class=""> // Conversion operators.<br class=""> case ISD::SIGN_EXTEND: return "sign_extend";<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp<br class="">URL:<br class=""><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_TargetLower&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=8w9aFswvXCArZJ9Dtxp-1pjiow9y1YflCu3uOyA2Cfw&e=" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLower</a><br class="">ingBase.cpp?rev=242409&r1=242408&r2=242409&view=diff<br class=""><br class=""></blockquote>==========================================================<br class="">============<br class=""><blockquote type="cite" class="">========<br class="">--- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Thu Jul 16 10:22:46<br class="">+++ 2015<br class="">@@ -827,6 +827,8 @@ void TargetLoweringBase::initActions() {<br class=""> setOperationAction(ISD::USUBO, VT, Expand);<br class=""> setOperationAction(ISD::SMULO, VT, Expand);<br class=""> setOperationAction(ISD::UMULO, VT, Expand);<br class="">+ setOperationAction(ISD::UABSDIFF, VT, Expand);<br class="">+ setOperationAction(ISD::SABSDIFF, VT, Expand);<br class=""><br class=""> // These library functions default to expand.<br class=""> setOperationAction(ISD::FROUND, VT, Expand);<br class=""><br class="">Added: llvm/trunk/test/CodeGen/X86/absdiff_expand.ll<br class="">URL:<br class=""><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_absdif&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=YAq6rmuKu9-km64jVuBnIHMrUGPeeNgSnycsvXTDRk4&e=" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/absdif</a><br class="">f_expand.ll?rev=242409&view=auto<br class=""><br class=""></blockquote>==========================================================<br class="">============<br class=""><blockquote type="cite" class="">========<br class="">--- llvm/trunk/test/CodeGen/X86/absdiff_expand.ll (added)<br class="">+++ llvm/trunk/test/CodeGen/X86/absdiff_expand.ll Thu Jul 16 10:22:46<br class="">+++ 2015<br class="">@@ -0,0 +1,242 @@<br class="">+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s<br class="">+-check-prefix=CHECK<br class="">+<br class="">+declare <4 x i8> @llvm.uabsdiff.v4i8(<4 x i8>, <4 x i8>)<br class="">+<br class="">+define <4 x i8> @test_uabsdiff_v4i8_expand(<4 x i8> %a1, <4 x i8><br class="">+%a2) { ; CHECK-LABEL: test_uabsdiff_v4i8_expand<br class="">+; CHECK: psubd %xmm1, %xmm0<br class="">+; CHECK-NEXT: pxor %xmm1, %xmm1<br class="">+; CHECK-NEXT: psubd %xmm0, %xmm1<br class="">+; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}<br class="">+; CHECK-NEXT: movdqa %xmm1, %xmm3<br class="">+; CHECK-NEXT: pxor %xmm2, %xmm3<br class="">+; CHECK-NEXT: pcmpgtd %xmm3, %xmm2<br class="">+; CHECK-NEXT: pand %xmm2, %xmm0<br class="">+; CHECK-NEXT: pandn %xmm1, %xmm2<br class="">+; CHECK-NEXT: por %xmm2, %xmm0<br class="">+; CHECK-NEXT: retq<br class="">+<br class="">+ %1 = call <4 x i8> @llvm.uabsdiff.v4i8(<4 x i8> %a1, <4 x i8> %a2)<br class="">+ ret <4 x i8> %1<br class="">+}<br class="">+<br class="">+declare <4 x i8> @llvm.sabsdiff.v4i8(<4 x i8>, <4 x i8>)<br class="">+<br class="">+define <4 x i8> @test_sabsdiff_v4i8_expand(<4 x i8> %a1, <4 x i8><br class="">+%a2) { ; CHECK-LABEL: test_sabsdiff_v4i8_expand<br class="">+; CHECK: psubd %xmm1, %xmm0<br class="">+; CHECK-NEXT: pxor %xmm1, %xmm1<br class="">+; CHECK-NEXT: pxor %xmm2, %xmm2<br class="">+; CHECK-NEXT: psubd %xmm0, %xmm2<br class="">+; CHECK-NEXT: pcmpgtd %xmm2, %xmm1<br class="">+; CHECK-NEXT: pand %xmm1, %xmm0<br class="">+; CHECK-NEXT: pandn %xmm2, %xmm1<br class="">+; CHECK-NEXT: por %xmm1, %xmm0<br class="">+; CHECK-NEXT: retq<br class="">+<br class="">+ %1 = call <4 x i8> @llvm.sabsdiff.v4i8(<4 x i8> %a1, <4 x i8> %a2)<br class="">+ ret <4 x i8> %1<br class="">+}<br class="">+<br class="">+<br class="">+declare <8 x i8> @llvm.sabsdiff.v8i8(<8 x i8>, <8 x i8>)<br class="">+<br class="">+define <8 x i8> @test_sabsdiff_v8i8_expand(<8 x i8> %a1, <8 x i8><br class="">+%a2) { ; CHECK-LABEL: test_sabsdiff_v8i8_expand<br class="">+; CHECK: psubw %xmm1, %xmm0<br class="">+; CHECK-NEXT: pxor %xmm1, %xmm1<br class="">+; CHECK-NEXT: pxor %xmm2, %xmm2<br class="">+; CHECK-NEXT: psubw %xmm0, %xmm2<br class="">+; CHECK-NEXT: pcmpgtw %xmm2, %xmm1<br class="">+; CHECK-NEXT: pand %xmm1, %xmm0<br class="">+; CHECK-NEXT: pandn %xmm2, %xmm1<br class="">+; CHECK-NEXT: por %xmm1, %xmm0<br class="">+; CHECK-NEXT: retq<br class="">+ %1 = call <8 x i8> @llvm.sabsdiff.v8i8(<8 x i8> %a1, <8 x i8> %a2)<br class="">+ ret <8 x i8> %1<br class="">+}<br class="">+<br class="">+declare <16 x i8> @llvm.uabsdiff.v16i8(<16 x i8>, <16 x i8>)<br class="">+<br class="">+define <16 x i8> @test_uabsdiff_v16i8_expand(<16 x i8> %a1, <16 x i8><br class="">+%a2) { ; CHECK-LABEL: test_uabsdiff_v16i8_expand<br class="">+; CHECK: psubb %xmm1, %xmm0<br class="">+; CHECK-NEXT: pxor %xmm1, %xmm1<br class="">+; CHECK-NEXT: psubb %xmm0, %xmm1<br class="">+; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}<br class="">+; CHECK-NEXT: movdqa %xmm1, %xmm3<br class="">+; CHECK-NEXT: pxor %xmm2, %xmm3<br class="">+; CHECK-NEXT: pcmpgtb %xmm3, %xmm2<br class="">+; CHECK-NEXT: pand %xmm2, %xmm0<br class="">+; CHECK-NEXT: pandn %xmm1, %xmm2<br class="">+; CHECK-NEXT: por %xmm2, %xmm0<br class="">+; CHECK-NEXT: retq<br class="">+ %1 = call <16 x i8> @llvm.uabsdiff.v16i8(<16 x i8> %a1, <16 x i8><br class="">+%a2)<br class="">+ ret <16 x i8> %1<br class="">+}<br class="">+<br class="">+declare <8 x i16> @llvm.uabsdiff.v8i16(<8 x i16>, <8 x i16>)<br class="">+<br class="">+define <8 x i16> @test_uabsdiff_v8i16_expand(<8 x i16> %a1, <8 x i16><br class="">+%a2) { ; CHECK-LABEL: test_uabsdiff_v8i16_expand<br class="">+; CHECK: psubw %xmm1, %xmm0<br class="">+; CHECK-NEXT: pxor %xmm1, %xmm1<br class="">+; CHECK-NEXT: psubw %xmm0, %xmm1<br class="">+; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}<br class="">+; CHECK-NEXT: movdqa %xmm1, %xmm3<br class="">+; CHECK-NEXT: pxor %xmm2, %xmm3<br class="">+; CHECK-NEXT: pcmpgtw %xmm3, %xmm2<br class="">+; CHECK-NEXT: pand %xmm2, %xmm0<br class="">+; CHECK-NEXT: pandn %xmm1, %xmm2<br class="">+; CHECK-NEXT: por %xmm2, %xmm0<br class="">+; CHECK-NEXT: retq<br class="">+ %1 = call <8 x i16> @llvm.uabsdiff.v8i16(<8 x i16> %a1, <8 x i16><br class="">+%a2)<br class="">+ ret <8 x i16> %1<br class="">+}<br class="">+<br class="">+declare <8 x i16> @llvm.sabsdiff.v8i16(<8 x i16>, <8 x i16>)<br class="">+<br class="">+define <8 x i16> @test_sabsdiff_v8i16_expand(<8 x i16> %a1, <8 x i16><br class="">+%a2) { ; CHECK-LABEL: test_sabsdiff_v8i16_expand<br class="">+; CHECK: psubw %xmm1, %xmm0<br class="">+; CHECK-NEXT: pxor %xmm1, %xmm1<br class="">+; CHECK-NEXT: pxor %xmm2, %xmm2<br class="">+; CHECK-NEXT: psubw %xmm0, %xmm2<br class="">+; CHECK-NEXT: pcmpgtw %xmm2, %xmm1<br class="">+; CHECK-NEXT: pand %xmm1, %xmm0<br class="">+; CHECK-NEXT: pandn %xmm2, %xmm1<br class="">+; CHECK-NEXT: por %xmm1, %xmm0<br class="">+; CHECK-NEXT: retq<br class="">+ %1 = call <8 x i16> @llvm.sabsdiff.v8i16(<8 x i16> %a1, <8 x i16><br class="">+%a2)<br class="">+ ret <8 x i16> %1<br class="">+}<br class="">+<br class="">+declare <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32>, <4 x i32>)<br class="">+<br class="">+define <4 x i32> @test_sabsdiff_v4i32_expand(<4 x i32> %a1, <4 x i32><br class="">+%a2) { ; CHECK-LABEL: test_sabsdiff_v4i32_expand<br class="">+; CHECK: psubd %xmm1, %xmm0<br class="">+; CHECK-NEXT: pxor %xmm1, %xmm1<br class="">+; CHECK-NEXT: pxor %xmm2, %xmm2<br class="">+; CHECK-NEXT: psubd %xmm0, %xmm2<br class="">+; CHECK-NEXT: pcmpgtd %xmm2, %xmm1<br class="">+; CHECK-NEXT: pand %xmm1, %xmm0<br class="">+; CHECK-NEXT: pandn %xmm2, %xmm1<br class="">+; CHECK-NEXT: por %xmm1, %xmm0<br class="">+; CHECK-NEXT: retq<br class="">+ %1 = call <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32> %a1, <4 x i32><br class="">+%a2)<br class="">+ ret <4 x i32> %1<br class="">+}<br class="">+<br class="">+declare <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32>, <4 x i32>)<br class="">+<br class="">+define <4 x i32> @test_uabsdiff_v4i32_expand(<4 x i32> %a1, <4 x i32><br class="">+%a2) { ; CHECK-LABEL: test_uabsdiff_v4i32_expand<br class="">+; CHECK: psubd %xmm1, %xmm0<br class="">+; CHECK-NEXT: pxor %xmm1, %xmm1<br class="">+; CHECK-NEXT: psubd %xmm0, %xmm1<br class="">+; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}<br class="">+; CHECK-NEXT: movdqa %xmm1, %xmm3<br class="">+; CHECK-NEXT: pxor %xmm2, %xmm3<br class="">+; CHECK-NEXT: pcmpgtd %xmm3, %xmm2<br class="">+; CHECK-NEXT: pand %xmm2, %xmm0<br class="">+; CHECK-NEXT: pandn %xmm1, %xmm2<br class="">+; CHECK-NEXT: por %xmm2, %xmm0<br class="">+; CHECK-NEXT: retq<br class="">+ %1 = call <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32> %a1, <4 x i32><br class="">+%a2)<br class="">+ ret <4 x i32> %1<br class="">+}<br class="">+<br class="">+declare <2 x i32> @llvm.sabsdiff.v2i32(<2 x i32>, <2 x i32>)<br class="">+<br class="">+define <2 x i32> @test_sabsdiff_v2i32_expand(<2 x i32> %a1, <2 x i32><br class="">+%a2) { ; CHECK-LABEL: test_sabsdiff_v2i32_expand<br class="">+; CHECK: psubq %xmm1, %xmm0<br class="">+; CHECK-NEXT: pxor %xmm1, %xmm1<br class="">+; CHECK-NEXT: psubq %xmm0, %xmm1<br class="">+; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}<br class="">+; CHECK-NEXT: movdqa %xmm1, %xmm3<br class="">+; CHECK-NEXT: pxor %xmm2, %xmm3<br class="">+; CHECK-NEXT: movdqa %xmm2, %xmm4<br class="">+; CHECK-NEXT: pcmpgtd %xmm3, %xmm4<br class="">+; CHECK-NEXT: pshufd $160, %xmm4, %xmm5 # xmm5 =<br class=""></blockquote>xmm4[0,0,2,2]<br class=""><blockquote type="cite" class="">+; CHECK-NEXT: pcmpeqd %xmm2, %xmm3<br class="">+; CHECK-NEXT: pshufd $245, %xmm3, %xmm2 # xmm2 =<br class=""></blockquote>xmm3[1,1,3,3]<br class=""><blockquote type="cite" class="">+; CHECK-NEXT: pand %xmm5, %xmm2<br class="">+; CHECK-NEXT: pshufd $245, %xmm4, %xmm3 # xmm3 =<br class=""></blockquote>xmm4[1,1,3,3]<br class=""><blockquote type="cite" class="">+; CHECK-NEXT: por %xmm2, %xmm3<br class="">+; CHECK-NEXT: pand %xmm3, %xmm0<br class="">+; CHECK-NEXT: pandn %xmm1, %xmm3<br class="">+; CHECK-NEXT: por %xmm3, %xmm0<br class="">+; CHECK-NEXT: retq<br class="">+ %1 = call <2 x i32> @llvm.sabsdiff.v2i32(<2 x i32> %a1, <2 x i32><br class="">+%a2)<br class="">+ ret <2 x i32> %1<br class="">+}<br class="">+<br class="">+declare <2 x i64> @llvm.sabsdiff.v2i64(<2 x i64>, <2 x i64>)<br class="">+<br class="">+define <2 x i64> @test_sabsdiff_v2i64_expand(<2 x i64> %a1, <2 x i64><br class="">+%a2) { ; CHECK-LABEL: test_sabsdiff_v2i64_expand<br class="">+; CHECK: psubq %xmm1, %xmm0<br class="">+; CHECK-NEXT: pxor %xmm1, %xmm1<br class="">+; CHECK-NEXT: psubq %xmm0, %xmm1<br class="">+; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}<br class="">+; CHECK-NEXT: movdqa %xmm1, %xmm3<br class="">+; CHECK-NEXT: pxor %xmm2, %xmm3<br class="">+; CHECK-NEXT: movdqa %xmm2, %xmm4<br class="">+; CHECK-NEXT: pcmpgtd %xmm3, %xmm4<br class="">+; CHECK-NEXT: pshufd $160, %xmm4, %xmm5 # xmm5 =<br class=""></blockquote>xmm4[0,0,2,2]<br class=""><blockquote type="cite" class="">+; CHECK-NEXT: pcmpeqd %xmm2, %xmm3<br class="">+; CHECK-NEXT: pshufd $245, %xmm3, %xmm2 # xmm2 =<br class=""></blockquote>xmm3[1,1,3,3]<br class=""><blockquote type="cite" class="">+; CHECK-NEXT: pand %xmm5, %xmm2<br class="">+; CHECK-NEXT: pshufd $245, %xmm4, %xmm3 # xmm3 =<br class=""></blockquote>xmm4[1,1,3,3]<br class=""><blockquote type="cite" class="">+; CHECK-NEXT: por %xmm2, %xmm3<br class="">+; CHECK-NEXT: pand %xmm3, %xmm0<br class="">+; CHECK-NEXT: pandn %xmm1, %xmm3<br class="">+; CHECK-NEXT: por %xmm3, %xmm0<br class="">+; CHECK-NEXT: retq<br class="">+ %1 = call <2 x i64> @llvm.sabsdiff.v2i64(<2 x i64> %a1, <2 x i64><br class="">+%a2)<br class="">+ ret <2 x i64> %1<br class="">+}<br class="">+<br class="">+declare <16 x i32> @llvm.sabsdiff.v16i32(<16 x i32>, <16 x i32>)<br class="">+<br class="">+define <16 x i32> @test_sabsdiff_v16i32_expand(<16 x i32> %a1, <16 x<br class="">+i32> %a2) { ; CHECK-LABEL: test_sabsdiff_v16i32_expand<br class="">+; CHECK: psubd %xmm4, %xmm0<br class="">+; CHECK-NEXT: pxor %xmm8, %xmm8<br class="">+; CHECK-NEXT: pxor %xmm9, %xmm9<br class="">+; CHECK-NEXT: psubd %xmm0, %xmm9<br class="">+; CHECK-NEXT: pxor %xmm4, %xmm4<br class="">+; CHECK-NEXT: pcmpgtd %xmm9, %xmm4<br class="">+; CHECK-NEXT: pand %xmm4, %xmm0<br class="">+; CHECK-NEXT: pandn %xmm9, %xmm4<br class="">+; CHECK-NEXT: por %xmm4, %xmm0<br class="">+; CHECK-NEXT: psubd %xmm5, %xmm1<br class="">+; CHECK-NEXT: pxor %xmm4, %xmm4<br class="">+; CHECK-NEXT: psubd %xmm1, %xmm4<br class="">+; CHECK-NEXT: pxor %xmm5, %xmm5<br class="">+; CHECK-NEXT: pcmpgtd %xmm4, %xmm5<br class="">+; CHECK-NEXT: pand %xmm5, %xmm1<br class="">+; CHECK-NEXT: pandn %xmm4, %xmm5<br class="">+; CHECK-NEXT: por %xmm5, %xmm1<br class="">+; CHECK-NEXT: psubd %xmm6, %xmm2<br class="">+; CHECK-NEXT: pxor %xmm4, %xmm4<br class="">+; CHECK-NEXT: psubd %xmm2, %xmm4<br class="">+; CHECK-NEXT: pxor %xmm5, %xmm5<br class="">+; CHECK-NEXT: pcmpgtd %xmm4, %xmm5<br class="">+; CHECK-NEXT: pand %xmm5, %xmm2<br class="">+; CHECK-NEXT: pandn %xmm4, %xmm5<br class="">+; CHECK-NEXT: por %xmm5, %xmm2<br class="">+; CHECK-NEXT: psubd %xmm7, %xmm3<br class="">+; CHECK-NEXT: pxor %xmm4, %xmm4<br class="">+; CHECK-NEXT: psubd %xmm3, %xmm4<br class="">+; CHECK-NEXT: pcmpgtd %xmm4, %xmm8<br class="">+; CHECK-NEXT: pand %xmm8, %xmm3<br class="">+; CHECK-NEXT: pandn %xmm4, %xmm8<br class="">+; CHECK-NEXT: por %xmm8, %xmm3<br class="">+; CHECK-NEXT: req<br class=""></blockquote>The tests look very fragile, should we make them more relaxed in terms of<br class="">register names?<br class=""></blockquote><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Do you mean to use regular expression for register names?</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""></div></blockquote>That’s one aspect. However, it will fail if scheduling would order the instructions in some other way. I think we could use CHECK-DAG directives here to overcome this issue (see <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_docs_CommandGuide_FileCheck.html&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=DC9I7v41M5gXDQyF7vEbKDFeyj67RkErUFCMX8kWEoU&s=2lFjtMzeLmz7WAObVyjvuPxDgCs-PFInTml9jK8k0Ks&e=" class="">http://llvm.org/docs/CommandGuide/FileCheck.html</a>). You could find similar examples in test/CodeGen/X86/avx2-shift.ll and other tests.</div><div><br class=""></div><div>Thanks,</div><div>Michael<br class=""><blockquote type="cite" class=""><div class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" class="">+ %1 = call <16 x i32> @llvm.sabsdiff.v16i32(<16 x i32> %a1, <16 x<br class="">+i32> %a2)<br class="">+ ret <16 x i32> %1<br class="">+}<br class="">+<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@cs.uiuc.edu" class="">llvm-commits@cs.uiuc.edu</a><br class=""><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" class="">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br class=""></blockquote><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@cs.uiuc.edu" class="">llvm-commits@cs.uiuc.edu</a><br class=""><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" class="">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a></blockquote></div></blockquote></div><br class=""></div></body></html>