<div dir="ltr">Hi Bruno,<div><br></div><div>I've committed a test case for this commit in r243457.</div><div><br></div><div>Alex</div></div><div class="gmail_extra"><br><div class="gmail_quote">2015-07-14 13:09 GMT-07:00 Bruno Cardoso Lopes <span dir="ltr"><<a href="mailto:bruno.cardoso@gmail.com" target="_blank">bruno.cardoso@gmail.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: bruno<br>
Date: Tue Jul 14 15:09:34 2015<br>
New Revision: 242191<br>
<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject-3Frev-3D242191-26view-3Drev&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=6EnTJHaRAPNN3j3T9hnndP2iDdfglyNQH6is9b3r3Lg&s=cR8xf0mcYZUSadS-O_Qaj30H16P-OkcvV4kWNODmP6M&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=242191&view=rev</a><br>
Log:<br>
[MMX] Use the appropriate instructions for GR64 <-> VR64 copies.<br>
<br>
MOVSDto64rr and MOV64toSDrr are defined to convert between FR64 (%xmm)<br>
<-> GR64 registers, not VR64 (%mm) <-> GR64. This is wrong.<br>
<br>
I found this by inspection and could not find a suitable testcase for it<br>
since (1) we don't handle MMX bitcasts in Peephole optimizer as to<br>
generate COPYs that (2) could be expanded back to the appropriate x86<br>
instruction in ExpandPostRA.<br>
<br>
Switch to use the appropriate instructions: MMX_MOVD64from64rr and<br>
MMX_MOVD64to64rr here.<br>
<br>
Modified:<br>
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86InstrInfo.cpp-3Frev-3D242191-26r1-3D242190-26r2-3D242191-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=6EnTJHaRAPNN3j3T9hnndP2iDdfglyNQH6is9b3r3Lg&s=gSj3vU0MVNCpMs9zsF78pbXJ4LfEzfGY6Gg4RoP8pzw&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=242191&r1=242190&r2=242191&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Jul 14 15:09:34 2015<br>
@@ -3806,7 +3806,7 @@ static unsigned CopyToFromAsymmetricReg(<br>
                                                X86::MOVPQIto64rr);<br>
     if (X86::VR64RegClass.contains(SrcReg))<br>
       // Copy from a VR64 register to a GR64 register.<br>
-      return X86::MOVSDto64rr;<br>
+      return X86::MMX_MOVD64from64rr;<br>
   } else if (X86::GR64RegClass.contains(SrcReg)) {<br>
     // Copy from a GR64 register to a VR128 register.<br>
     if (X86::VR128XRegClass.contains(DestReg))<br>
@@ -3814,7 +3814,7 @@ static unsigned CopyToFromAsymmetricReg(<br>
                                                X86::MOV64toPQIrr);<br>
     // Copy from a GR64 register to a VR64 register.<br>
     if (X86::VR64RegClass.contains(DestReg))<br>
-      return X86::MOV64toSDrr;<br>
+      return X86::MMX_MOVD64to64rr;<br>
   }<br>
<br>
   // SrcReg(FR32) -> DestReg(GR32)<br>
<br>
<br>
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</blockquote></div><br></div>