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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">It seems that the feature was originally introduced to avoid the memory form of call instructions on Atom CPUs (including Silvermont).<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">But there’s nothing really special about memory-form calls. The same applies to memory-form pushes, for example.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">This is based on the following guidance from the x86 optimization manual:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">For Atom (Bonnell):<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">“For Intel Atom processors, minimize the presence of complex instructions requiring MSROM to take advantage the optimal decode bandwidth provided by the two
decode units.”<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">For Silvermont:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">“MSROM instructions should be avoided if possible. A good example is the memory form of PUSH and CALL. It will often be better to perform a load into a register
and then perform the register version of PUSH and CALL.”<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I’ve wanted to use MSROM explicitly to make cross-referencing with the manual easy, but, as I said, I’m not attached to that.<o:p></o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></a></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Regarding your other question in the commit – there are, of course, plenty of microcoded instructions (there’s a table in the optimization manual), but the
memory-form PUSHes and CALLs are probably the only ones that are both common and have faster alternative sequences. Off the top of my head, another one that has a faster alternative sequence is LEAVE, but we never generate it to begin with.
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> Michael<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Sean Silva [mailto:chisophugis@gmail.com]
<br>
<b>Sent:</b> Monday, July 27, 2015 03:51<br>
<b>To:</b> Kuperstein, Michael M<br>
<b>Cc:</b> llvm-commits@cs.uiuc.edu<br>
<b>Subject:</b> Re: [llvm] r243010 - [X86] Allow load folding into PUSH instructions<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal" style="line-height:115%"><o:p> </o:p></p>
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<p class="MsoNormal" style="line-height:115%"><o:p> </o:p></p>
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<p class="MsoNormal" style="line-height:115%">On Sun, Jul 26, 2015 at 12:11 AM, Kuperstein, Michael M <<a href="mailto:michael.m.kuperstein@intel.com" target="_blank">michael.m.kuperstein@intel.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Yes.</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I’m open to suggestions about the name, btw – I’m not at all attached to having “msrom” in it.</span><o:p></o:p></p>
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<p class="MsoNormal" style="line-height:115%"><o:p> </o:p></p>
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<p class="MsoNormal" style="line-height:115%">I've updated the comment to not use the acronym MSROM in r243256.<o:p></o:p></p>
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<p class="MsoNormal" style="line-height:115%"><o:p> </o:p></p>
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<p class="MsoNormal" style="line-height:115%">Do you have a better explanation of what subset of instructions this feature should really be guarding (now or in the future)?<o:p></o:p></p>
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<p class="MsoNormal" style="line-height:115%"><o:p> </o:p></p>
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<p class="MsoNormal" style="line-height:115%">-- Sean Silva<o:p></o:p></p>
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<p class="MsoNormal" style="line-height:115%"> <o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Michael</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><a name="14ec9382eaa86107__MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span></a><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Sean Silva [mailto:<a href="mailto:chisophugis@gmail.com" target="_blank">chisophugis@gmail.com</a>]
<br>
<b>Sent:</b> Friday, July 24, 2015 07:29<br>
<b>To:</b> Kuperstein, Michael M<br>
<b>Cc:</b> <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
<b>Subject:</b> Re: [llvm] r243010 - [X86] Allow load folding into PUSH instructions</span><o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p>
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<o:p></o:p></p>
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<o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;line-height:115%">
On Thu, Jul 23, 2015 at 5:23 AM, Michael Kuperstein <<a href="mailto:michael.m.kuperstein@intel.com" target="_blank">michael.m.kuperstein@intel.com</a>> wrote:<o:p></o:p></p>
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Author: mkuper<br>
Date: Thu Jul 23 07:23:45 2015<br>
New Revision: 243010<br>
<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject-3Frev-3D243010-26view-3Drev&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=OU98qDYM4aXzzHRpcXa-94JMHKLFFiIk5OMrauI7PWg&s=04aFYf2LDTgOmfZinDjYk98c70dPbgL-aKKW85FL4kE&e=" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=243010&view=rev</a><br>
Log:<br>
[X86] Allow load folding into PUSH instructions<br>
<br>
Adds pushes to the folding tables.<br>
This also required a fix to the TD definition, since the memory forms of<br>
the push instructions did not have the right mayLoad/mayStore flags.<br>
<br>
Differential Revision: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__reviews.llvm.org_D11340&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=OU98qDYM4aXzzHRpcXa-94JMHKLFFiIk5OMrauI7PWg&s=gDdJxV1jNUMTY1f5Sv7WM47K8smyMSRfFYaM05sxaE0&e=" target="_blank">http://reviews.llvm.org/D11340</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/fold-push.ll<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86.td<br>
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86.td<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86.td-3Frev-3D243010-26r1-3D243009-26r2-3D243010-26view-3Ddiff&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=OU98qDYM4aXzzHRpcXa-94JMHKLFFiIk5OMrauI7PWg&s=_Xlg5IoqWxXyVf8uZYHYj-SGgM-XPoEvnpoIAy_1uzA&e=" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=243010&r1=243009&r2=243010&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86.td Thu Jul 23 07:23:45 2015<br>
@@ -181,6 +181,11 @@ def FeatureSlowDivide64 : SubtargetFeatu<br>
def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",<br>
"PadShortFunctions", "true",<br>
"Pad short functions">;<br>
+// TODO: This feature ought to be renamed.<br>
+// What it really refers to are CPUs where instruction that cause MSROM<br>
+// lookups are expensive, so alternative sequences should be preferred.<o:p></o:p></p>
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<o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;line-height:115%">
What is "MSROM" in this context? Do you just mean that the instruction is microcoded?<o:p></o:p></p>
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<o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;line-height:115%">
-- Sean Silva<o:p></o:p></p>
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<o:p></o:p></p>
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<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-top:5.0pt;margin-right:0cm;margin-bottom:5.0pt">
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;line-height:115%">
+// The best examples of this are the memory forms of CALL and PUSH<br>
+// instructions, which should be avoided in favor of a MOV + register CALL/PUSH.<br>
def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",<br>
"CallRegIndirect", "true",<br>
"Call register indirect">;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86InstrInfo.cpp-3Frev-3D243010-26r1-3D243009-26r2-3D243010-26view-3Ddiff&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=OU98qDYM4aXzzHRpcXa-94JMHKLFFiIk5OMrauI7PWg&s=nfg1lWpWWHFT5AZndGfrGRVCA3xFATFX7HOcbjOEqwc&e=" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=243010&r1=243009&r2=243010&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Jul 23 07:23:45 2015<br>
@@ -332,6 +332,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br>
{ X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },<br>
{ X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },<br>
{ X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },<br>
+ { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },<br>
+ { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },<br>
+ { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },<br>
{ X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },<br>
{ X86::SETAr, X86::SETAm, TB_FOLDED_STORE },<br>
{ X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },<br>
@@ -4878,10 +4881,14 @@ MachineInstr *X86InstrInfo::foldMemoryOp<br>
bool isCallRegIndirect = Subtarget.callRegIndirect();<br>
bool isTwoAddrFold = false;<br>
<br>
- // For CPUs that favor the register form of a call,<br>
- // do not fold loads into calls.<br>
- if (isCallRegIndirect &&<br>
- (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r))<br>
+ // For CPUs that favor the register form of a call or push,<br>
+ // do not fold loads into calls or pushes, unless optimizing for size<br>
+ // aggressively.<br>
+ if (isCallRegIndirect &&<br>
+ !MF.getFunction()->hasFnAttribute(Attribute::MinSize) &&<br>
+ (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r ||<br>
+ MI->getOpcode() == X86::PUSH16r || MI->getOpcode() == X86::PUSH32r ||<br>
+ MI->getOpcode() == X86::PUSH64r))<br>
return nullptr;<br>
<br>
unsigned NumOps = MI->getDesc().getNumOperands();<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86InstrInfo.td-3Frev-3D243010-26r1-3D243009-26r2-3D243010-26view-3Ddiff&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=OU98qDYM4aXzzHRpcXa-94JMHKLFFiIk5OMrauI7PWg&s=08i84I5gpX1yIcnKqFLsOKNTRpVY2D_Q3uvOUYoT0II&e=" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=243010&r1=243009&r2=243010&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Jul 23 07:23:45 2015<br>
@@ -1022,12 +1022,8 @@ def PUSH32r : I<0x50, AddRegFrm, (outs)<br>
IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;<br>
def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],<br>
IIC_PUSH_REG>, OpSize16;<br>
-def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],<br>
- IIC_PUSH_MEM>, OpSize16;<br>
def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],<br>
IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;<br>
-def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],<br>
- IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;<br>
<br>
def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),<br>
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;<br>
@@ -1041,6 +1037,14 @@ def PUSHi32 : Ii32<0x68, RawFrm, (outs)<br>
"push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,<br>
Requires<[Not64BitMode]>;<br>
} // mayStore, SchedRW<br>
+<br>
+let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {<br>
+def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],<br>
+ IIC_PUSH_MEM>, OpSize16;<br>
+def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],<br>
+ IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;<br>
+} // mayLoad, mayStore, SchedRW<br>
+<br>
}<br>
<br>
let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,<br>
@@ -1073,9 +1077,11 @@ def PUSH64r : I<0x50, AddRegFrm, (outs)<br>
IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;<br>
def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],<br>
IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;<br>
+} // mayStore, SchedRW<br>
+let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {<br>
def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],<br>
IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;<br>
-} // mayStore, SchedRW<br>
+} // mayLoad, mayStore, SchedRW<br>
}<br>
<br>
let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/fold-push.ll<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_fold-2Dpush.ll-3Frev-3D243010-26view-3Dauto&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=OU98qDYM4aXzzHRpcXa-94JMHKLFFiIk5OMrauI7PWg&s=n7BgZfEk_0924AKAcbZPnwh9B8FX6c6hM41kx1JayAA&e=" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-push.ll?rev=243010&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/fold-push.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/fold-push.ll Thu Jul 23 07:23:45 2015<br>
@@ -0,0 +1,40 @@<br>
+; RUN: llc < %s -mtriple=i686-windows | FileCheck %s -check-prefix=CHECK -check-prefix=NORMAL<br>
+; RUN: llc < %s -mtriple=i686-windows -mattr=call-reg-indirect | FileCheck %s -check-prefix=CHECK -check-prefix=SLM<br>
+<br>
+declare void @foo(i32 %r)<br>
+<br>
+define void @test(i32 %a, i32 %b) optsize {<br>
+; CHECK-LABEL: test:<br>
+; CHECK: movl [[EAX:%e..]], (%esp)<br>
+; CHECK-NEXT: pushl [[EAX]]<br>
+; CHECK-NEXT: calll<br>
+; CHECK-NEXT: addl $4, %esp<br>
+; CHECK: nop<br>
+; NORMAL: pushl (%esp)<br>
+; SLM: movl (%esp), [[RELOAD:%e..]]<br>
+; SLM-NEXT: pushl [[RELOAD]]<br>
+; CHECK: calll<br>
+; CHECK-NEXT: addl $4, %esp<br>
+ %c = add i32 %a, %b<br>
+ call void @foo(i32 %c)<br>
+ call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di}"()<br>
+ call void @foo(i32 %c)<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_min(i32 %a, i32 %b) minsize {<br>
+; CHECK-LABEL: test_min:<br>
+; CHECK: movl [[EAX:%e..]], (%esp)<br>
+; CHECK-NEXT: pushl [[EAX]]<br>
+; CHECK-NEXT: calll<br>
+; CHECK-NEXT: addl $4, %esp<br>
+; CHECK: nop<br>
+; CHECK: pushl (%esp)<br>
+; CHECK: calll<br>
+; CHECK-NEXT: addl $4, %esp<br>
+ %c = add i32 %a, %b<br>
+ call void @foo(i32 %c)<br>
+ call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di}"()<br>
+ call void @foo(i32 %c)<br>
+ ret void<br>
+}<br>
<br>
<br>
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